 @@ -1,14 +1,14 @@
-/*	$NetBSD: mips_fpu.c,v 1.15 2017/05/07 05:45:07 skrll Exp $	*/
+/*	$NetBSD: mips_fpu.c,v 1.16 2021/05/11 14:41:08 simonb Exp $	*/
 /*-
  * Copyright (c) 2010 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Matt Thomas of 3am Software Foundry.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
 @@ -20,27 +20,27 @@
  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: mips_fpu.c,v 1.15 2017/05/07 05:45:07 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: mips_fpu.c,v 1.16 2021/05/11 14:41:08 simonb Exp $");
 #include <sys/param.h>
 #include <sys/mutex.h>
 #include <sys/condvar.h>
 #include <sys/cpu.h>
 #include <sys/proc.h>
 #include <sys/lwp.h>
 #include <sys/pcu.h>
 #include <mips/locore.h>
 #include <mips/regnum.h>
 #include <mips/pcb.h>
 @@ -69,27 +69,27 @@ fpu_load(void)
 void
 fpu_save(lwp_t *l)
+{
 	pcu_save(&mips_fpu_ops, l);
+}
 bool
 fpu_used_p(const lwp_t *l)
+{
 	return pcu_valid_p(&mips_fpu_ops, l);
+}
-void
+static void
 mips_fpu_state_save(lwp_t *l)
+{
 	struct trapframe * const tf = l->l_md.md_utf;
 #ifndef __mips_soft_float
 	struct pcb * const pcb = lwp_getpcb(l);
 	mips_fpreg_t * const fp = pcb->pcb_fpregs.r_regs;
 #endif
 	uint32_t status, fpcsr;
 	/*
 	 * Don't do anything if the FPU is already off.
 	 */
 	if ((tf->tf_regs[_R_SR] & MIPS_SR_COP_1_BIT) == 0)
 @@ -196,27 +196,27 @@ mips_fpu_state_save(lwp_t *l)
 			"swc1	$f28, (28*%d1)(%0)	;"
 			"swc1	$f29, (29*%d1)(%0)	;"
 			"swc1	$f30, (30*%d1)(%0)	;"
 			"swc1	$f31, (31*%d1)(%0)	;"
 		".set reorder" :: "r"(fp), "i"(4));
+	}
 #endif
 	/*
 	 * stop COP1
 	 */
 	__asm volatile ("mtc0 %0, $%1" :: "r"(status), "n"(MIPS_COP_0_STATUS));
+}
-void
+static void
 mips_fpu_state_load(lwp_t *l, u_int flags)
+{
 	struct trapframe * const tf = l->l_md.md_utf;
 	struct pcb * const pcb = lwp_getpcb(l);
 #ifndef __mips_soft_float
 	mips_fpreg_t * const fp = pcb->pcb_fpregs.r_regs;
 #endif
 	uint32_t status;
 	uint32_t fpcsr;
 	l->l_cpu->ci_ev_fpu_loads.ev_count++;
 	/*
 @@ -340,18 +340,18 @@ mips_fpu_state_load(lwp_t *l, u_int flag
 	 */
 	__asm volatile(
 		".set noreorder"	"\n\t"
 		".set noat"		"\n\t"
 		"ctc1	%0, $31"	"\n\t"
 		"nop"			"\n\t"	/* XXX: Hack */
 		"mtc0	%1, $%2"	"\n\t"
 		".set at"		"\n\t"
 		".set reorder"		"\n\t"
 	    ::	"r"(fpcsr &~ MIPS_FPU_EXCEPTION_BITS), "r"(status),
 		"n"(MIPS_COP_0_STATUS));
+}
-void
+static void
 mips_fpu_state_release(lwp_t *l)
+{
 	l->l_md.md_utf->tf_regs[_R_SR] &= ~MIPS_SR_COP_1_BIT;
+}