Sun May 23 11:49:45 2021 UTC ()
xhci(4): Draft suspend/resume.

Work almost entirely done and tested by maya@ based on xhci 1.2 spec;
tidied up and tweaked by me.

Not sure about issuing Stop Endpoint commands or ensuring the Command
Ring is in the Stopped or Idle state, but this seems to work as is,
so it's already an improvement over what we had before which was no
xhci suspend/resume at all.

In particular, it's not clear to us:

- if we don't have any pending USB activity whether we need to issue
  the Stop Endpoints or quiesce the command ring; but

- if we do have any pending USB activity whether issuing Stop
  Endpoint is enough or whether we also need to do anything to
  synchronize with other software logic to quiesce it too.


(riastradh)
diff -r1.138 -r1.139 src/sys/dev/usb/xhci.c
diff -r1.18 -r1.19 src/sys/dev/usb/xhcireg.h
diff -r1.17 -r1.18 src/sys/dev/usb/xhcivar.h
cvs diff -r1.138 -r1.139 src/sys/dev/usb/xhci.c (switch to unified diff)

--- src/sys/dev/usb/xhci.c 2021/01/05 18:00:21 1.138
+++ src/sys/dev/usb/xhci.c 2021/05/23 11:49:45 1.139
@@ -1,1774 +1,2113 @@ @@ -1,1774 +1,2113 @@
1/* $NetBSD: xhci.c,v 1.138 2021/01/05 18:00:21 skrll Exp $ */ 1/* $NetBSD: xhci.c,v 1.139 2021/05/23 11:49:45 riastradh Exp $ */
2 2
3/* 3/*
4 * Copyright (c) 2013 Jonathan A. Kollasch 4 * Copyright (c) 2013 Jonathan A. Kollasch
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * Redistribution and use in source and binary forms, with or without 7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions 8 * modification, are permitted provided that the following conditions
9 * are met: 9 * are met:
10 * 1. Redistributions of source code must retain the above copyright 10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer. 11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright 12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the 13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution. 14 * documentation and/or other materials provided with the distribution.
15 * 15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */ 27 */
28 28
29/* 29/*
30 * USB rev 2.0 and rev 3.1 specification 30 * USB rev 2.0 and rev 3.1 specification
31 * http://www.usb.org/developers/docs/ 31 * http://www.usb.org/developers/docs/
32 * xHCI rev 1.1 specification 32 * xHCI rev 1.1 specification
33 * http://www.intel.com/technology/usb/spec.htm 33 * http://www.intel.com/technology/usb/spec.htm
34 */ 34 */
35 35
36#include <sys/cdefs.h> 36#include <sys/cdefs.h>
37__KERNEL_RCSID(0, "$NetBSD: xhci.c,v 1.138 2021/01/05 18:00:21 skrll Exp $"); 37__KERNEL_RCSID(0, "$NetBSD: xhci.c,v 1.139 2021/05/23 11:49:45 riastradh Exp $");
38 38
39#ifdef _KERNEL_OPT 39#ifdef _KERNEL_OPT
40#include "opt_usb.h" 40#include "opt_usb.h"
41#endif 41#endif
42 42
43#include <sys/param.h> 43#include <sys/param.h>
44#include <sys/systm.h> 44#include <sys/systm.h>
45#include <sys/kernel.h> 45#include <sys/kernel.h>
46#include <sys/kmem.h> 46#include <sys/kmem.h>
47#include <sys/device.h> 47#include <sys/device.h>
48#include <sys/select.h> 48#include <sys/select.h>
49#include <sys/proc.h> 49#include <sys/proc.h>
50#include <sys/queue.h> 50#include <sys/queue.h>
51#include <sys/mutex.h> 51#include <sys/mutex.h>
52#include <sys/condvar.h> 52#include <sys/condvar.h>
53#include <sys/bus.h> 53#include <sys/bus.h>
54#include <sys/cpu.h> 54#include <sys/cpu.h>
55#include <sys/sysctl.h> 55#include <sys/sysctl.h>
56 56
57#include <machine/endian.h> 57#include <machine/endian.h>
58 58
59#include <dev/usb/usb.h> 59#include <dev/usb/usb.h>
60#include <dev/usb/usbdi.h> 60#include <dev/usb/usbdi.h>
61#include <dev/usb/usbdivar.h> 61#include <dev/usb/usbdivar.h>
62#include <dev/usb/usbdi_util.h> 62#include <dev/usb/usbdi_util.h>
63#include <dev/usb/usbhist.h> 63#include <dev/usb/usbhist.h>
64#include <dev/usb/usb_mem.h> 64#include <dev/usb/usb_mem.h>
65#include <dev/usb/usb_quirks.h> 65#include <dev/usb/usb_quirks.h>
66 66
67#include <dev/usb/xhcireg.h> 67#include <dev/usb/xhcireg.h>
68#include <dev/usb/xhcivar.h> 68#include <dev/usb/xhcivar.h>
69#include <dev/usb/usbroothub.h> 69#include <dev/usb/usbroothub.h>
70 70
71 71
72#ifdef USB_DEBUG 72#ifdef USB_DEBUG
73#ifndef XHCI_DEBUG 73#ifndef XHCI_DEBUG
74#define xhcidebug 0 74#define xhcidebug 0
75#else /* !XHCI_DEBUG */ 75#else /* !XHCI_DEBUG */
76#define HEXDUMP(a, b, c) \ 76#define HEXDUMP(a, b, c) \
77 do { \ 77 do { \
78 if (xhcidebug > 0) \ 78 if (xhcidebug > 0) \
79 hexdump(printf, a, b, c); \ 79 hexdump(printf, a, b, c); \
80 } while (/*CONSTCOND*/0) 80 } while (/*CONSTCOND*/0)
81static int xhcidebug = 0; 81static int xhcidebug = 0;
82 82
83SYSCTL_SETUP(sysctl_hw_xhci_setup, "sysctl hw.xhci setup") 83SYSCTL_SETUP(sysctl_hw_xhci_setup, "sysctl hw.xhci setup")
84{ 84{
85 int err; 85 int err;
86 const struct sysctlnode *rnode; 86 const struct sysctlnode *rnode;
87 const struct sysctlnode *cnode; 87 const struct sysctlnode *cnode;
88 88
89 err = sysctl_createv(clog, 0, NULL, &rnode, 89 err = sysctl_createv(clog, 0, NULL, &rnode,
90 CTLFLAG_PERMANENT, CTLTYPE_NODE, "xhci", 90 CTLFLAG_PERMANENT, CTLTYPE_NODE, "xhci",
91 SYSCTL_DESCR("xhci global controls"), 91 SYSCTL_DESCR("xhci global controls"),
92 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 92 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL);
93 93
94 if (err) 94 if (err)
95 goto fail; 95 goto fail;
96 96
97 /* control debugging printfs */ 97 /* control debugging printfs */
98 err = sysctl_createv(clog, 0, &rnode, &cnode, 98 err = sysctl_createv(clog, 0, &rnode, &cnode,
99 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 99 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT,
100 "debug", SYSCTL_DESCR("Enable debugging output"), 100 "debug", SYSCTL_DESCR("Enable debugging output"),
101 NULL, 0, &xhcidebug, sizeof(xhcidebug), CTL_CREATE, CTL_EOL); 101 NULL, 0, &xhcidebug, sizeof(xhcidebug), CTL_CREATE, CTL_EOL);
102 if (err) 102 if (err)
103 goto fail; 103 goto fail;
104 104
105 return; 105 return;
106fail: 106fail:
107 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 107 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err);
108} 108}
109 109
110#endif /* !XHCI_DEBUG */ 110#endif /* !XHCI_DEBUG */
111#endif /* USB_DEBUG */ 111#endif /* USB_DEBUG */
112 112
113#ifndef HEXDUMP 113#ifndef HEXDUMP
114#define HEXDUMP(a, b, c) 114#define HEXDUMP(a, b, c)
115#endif 115#endif
116 116
117#define DPRINTF(FMT,A,B,C,D) USBHIST_LOG(xhcidebug,FMT,A,B,C,D) 117#define DPRINTF(FMT,A,B,C,D) USBHIST_LOG(xhcidebug,FMT,A,B,C,D)
118#define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(xhcidebug,N,FMT,A,B,C,D) 118#define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(xhcidebug,N,FMT,A,B,C,D)
119#define XHCIHIST_FUNC() USBHIST_FUNC() 119#define XHCIHIST_FUNC() USBHIST_FUNC()
120#define XHCIHIST_CALLED(name) USBHIST_CALLED(xhcidebug) 120#define XHCIHIST_CALLED(name) USBHIST_CALLED(xhcidebug)
121#define XHCIHIST_CALLARGS(FMT,A,B,C,D) \ 121#define XHCIHIST_CALLARGS(FMT,A,B,C,D) \
122 USBHIST_CALLARGS(xhcidebug,FMT,A,B,C,D) 122 USBHIST_CALLARGS(xhcidebug,FMT,A,B,C,D)
123 123
124#define XHCI_DCI_SLOT 0 124#define XHCI_DCI_SLOT 0
125#define XHCI_DCI_EP_CONTROL 1 125#define XHCI_DCI_EP_CONTROL 1
126 126
127#define XHCI_ICI_INPUT_CONTROL 0 127#define XHCI_ICI_INPUT_CONTROL 0
128 128
129struct xhci_pipe { 129struct xhci_pipe {
130 struct usbd_pipe xp_pipe; 130 struct usbd_pipe xp_pipe;
131 struct usb_task xp_async_task; 131 struct usb_task xp_async_task;
132 int16_t xp_isoc_next; /* next frame */ 132 int16_t xp_isoc_next; /* next frame */
133 uint8_t xp_maxb; /* max burst */ 133 uint8_t xp_maxb; /* max burst */
134 uint8_t xp_mult; 134 uint8_t xp_mult;
135}; 135};
136 136
137#define XHCI_COMMAND_RING_TRBS 256 137#define XHCI_COMMAND_RING_TRBS 256
138#define XHCI_EVENT_RING_TRBS 256 138#define XHCI_EVENT_RING_TRBS 256
139#define XHCI_EVENT_RING_SEGMENTS 1 139#define XHCI_EVENT_RING_SEGMENTS 1
140#define XHCI_TRB_3_ED_BIT XHCI_TRB_3_ISP_BIT 140#define XHCI_TRB_3_ED_BIT XHCI_TRB_3_ISP_BIT
141 141
142static usbd_status xhci_open(struct usbd_pipe *); 142static usbd_status xhci_open(struct usbd_pipe *);
143static void xhci_close_pipe(struct usbd_pipe *); 143static void xhci_close_pipe(struct usbd_pipe *);
144static int xhci_intr1(struct xhci_softc * const); 144static int xhci_intr1(struct xhci_softc * const);
145static void xhci_softintr(void *); 145static void xhci_softintr(void *);
146static void xhci_poll(struct usbd_bus *); 146static void xhci_poll(struct usbd_bus *);
147static struct usbd_xfer *xhci_allocx(struct usbd_bus *, unsigned int); 147static struct usbd_xfer *xhci_allocx(struct usbd_bus *, unsigned int);
148static void xhci_freex(struct usbd_bus *, struct usbd_xfer *); 148static void xhci_freex(struct usbd_bus *, struct usbd_xfer *);
149static void xhci_abortx(struct usbd_xfer *); 149static void xhci_abortx(struct usbd_xfer *);
150static bool xhci_dying(struct usbd_bus *); 150static bool xhci_dying(struct usbd_bus *);
151static void xhci_get_lock(struct usbd_bus *, kmutex_t **); 151static void xhci_get_lock(struct usbd_bus *, kmutex_t **);
152static usbd_status xhci_new_device(device_t, struct usbd_bus *, int, int, int, 152static usbd_status xhci_new_device(device_t, struct usbd_bus *, int, int, int,
153 struct usbd_port *); 153 struct usbd_port *);
154static int xhci_roothub_ctrl(struct usbd_bus *, usb_device_request_t *, 154static int xhci_roothub_ctrl(struct usbd_bus *, usb_device_request_t *,
155 void *, int); 155 void *, int);
156 156
157static usbd_status xhci_configure_endpoint(struct usbd_pipe *); 157static usbd_status xhci_configure_endpoint(struct usbd_pipe *);
158//static usbd_status xhci_unconfigure_endpoint(struct usbd_pipe *); 158//static usbd_status xhci_unconfigure_endpoint(struct usbd_pipe *);
159static usbd_status xhci_reset_endpoint(struct usbd_pipe *); 159static usbd_status xhci_reset_endpoint(struct usbd_pipe *);
160static usbd_status xhci_stop_endpoint(struct usbd_pipe *); 160static usbd_status xhci_stop_endpoint(struct usbd_pipe *);
161 161
162static void xhci_host_dequeue(struct xhci_ring * const); 162static void xhci_host_dequeue(struct xhci_ring * const);
163static usbd_status xhci_set_dequeue(struct usbd_pipe *); 163static usbd_status xhci_set_dequeue(struct usbd_pipe *);
164 164
165static usbd_status xhci_do_command(struct xhci_softc * const, 165static usbd_status xhci_do_command(struct xhci_softc * const,
166 struct xhci_soft_trb * const, int); 166 struct xhci_soft_trb * const, int);
167static usbd_status xhci_do_command_locked(struct xhci_softc * const, 167static usbd_status xhci_do_command_locked(struct xhci_softc * const,
168 struct xhci_soft_trb * const, int); 168 struct xhci_soft_trb * const, int);
169static usbd_status xhci_init_slot(struct usbd_device *, uint32_t); 169static usbd_status xhci_init_slot(struct usbd_device *, uint32_t);
170static void xhci_free_slot(struct xhci_softc *, struct xhci_slot *); 170static void xhci_free_slot(struct xhci_softc *, struct xhci_slot *);
171static usbd_status xhci_set_address(struct usbd_device *, uint32_t, bool); 171static usbd_status xhci_set_address(struct usbd_device *, uint32_t, bool);
172static usbd_status xhci_enable_slot(struct xhci_softc * const, 172static usbd_status xhci_enable_slot(struct xhci_softc * const,
173 uint8_t * const); 173 uint8_t * const);
174static usbd_status xhci_disable_slot(struct xhci_softc * const, uint8_t); 174static usbd_status xhci_disable_slot(struct xhci_softc * const, uint8_t);
175static usbd_status xhci_address_device(struct xhci_softc * const, 175static usbd_status xhci_address_device(struct xhci_softc * const,
176 uint64_t, uint8_t, bool); 176 uint64_t, uint8_t, bool);
177static void xhci_set_dcba(struct xhci_softc * const, uint64_t, int); 177static void xhci_set_dcba(struct xhci_softc * const, uint64_t, int);
178static usbd_status xhci_update_ep0_mps(struct xhci_softc * const, 178static usbd_status xhci_update_ep0_mps(struct xhci_softc * const,
179 struct xhci_slot * const, u_int); 179 struct xhci_slot * const, u_int);
180static usbd_status xhci_ring_init(struct xhci_softc * const, 180static usbd_status xhci_ring_init(struct xhci_softc * const,
181 struct xhci_ring **, size_t, size_t); 181 struct xhci_ring **, size_t, size_t);
182static void xhci_ring_free(struct xhci_softc * const, 182static void xhci_ring_free(struct xhci_softc * const,
183 struct xhci_ring ** const); 183 struct xhci_ring ** const);
184 184
185static void xhci_setup_ctx(struct usbd_pipe *); 185static void xhci_setup_ctx(struct usbd_pipe *);
186static void xhci_setup_route(struct usbd_pipe *, uint32_t *); 186static void xhci_setup_route(struct usbd_pipe *, uint32_t *);
187static void xhci_setup_tthub(struct usbd_pipe *, uint32_t *); 187static void xhci_setup_tthub(struct usbd_pipe *, uint32_t *);
188static void xhci_setup_maxburst(struct usbd_pipe *, uint32_t *); 188static void xhci_setup_maxburst(struct usbd_pipe *, uint32_t *);
189static uint32_t xhci_bival2ival(uint32_t, uint32_t); 189static uint32_t xhci_bival2ival(uint32_t, uint32_t);
190 190
191static void xhci_noop(struct usbd_pipe *); 191static void xhci_noop(struct usbd_pipe *);
192 192
193static usbd_status xhci_root_intr_transfer(struct usbd_xfer *); 193static usbd_status xhci_root_intr_transfer(struct usbd_xfer *);
194static usbd_status xhci_root_intr_start(struct usbd_xfer *); 194static usbd_status xhci_root_intr_start(struct usbd_xfer *);
195static void xhci_root_intr_abort(struct usbd_xfer *); 195static void xhci_root_intr_abort(struct usbd_xfer *);
196static void xhci_root_intr_close(struct usbd_pipe *); 196static void xhci_root_intr_close(struct usbd_pipe *);
197static void xhci_root_intr_done(struct usbd_xfer *); 197static void xhci_root_intr_done(struct usbd_xfer *);
198 198
199static usbd_status xhci_device_ctrl_transfer(struct usbd_xfer *); 199static usbd_status xhci_device_ctrl_transfer(struct usbd_xfer *);
200static usbd_status xhci_device_ctrl_start(struct usbd_xfer *); 200static usbd_status xhci_device_ctrl_start(struct usbd_xfer *);
201static void xhci_device_ctrl_abort(struct usbd_xfer *); 201static void xhci_device_ctrl_abort(struct usbd_xfer *);
202static void xhci_device_ctrl_close(struct usbd_pipe *); 202static void xhci_device_ctrl_close(struct usbd_pipe *);
203static void xhci_device_ctrl_done(struct usbd_xfer *); 203static void xhci_device_ctrl_done(struct usbd_xfer *);
204 204
205static usbd_status xhci_device_isoc_transfer(struct usbd_xfer *); 205static usbd_status xhci_device_isoc_transfer(struct usbd_xfer *);
206static usbd_status xhci_device_isoc_enter(struct usbd_xfer *); 206static usbd_status xhci_device_isoc_enter(struct usbd_xfer *);
207static void xhci_device_isoc_abort(struct usbd_xfer *); 207static void xhci_device_isoc_abort(struct usbd_xfer *);
208static void xhci_device_isoc_close(struct usbd_pipe *); 208static void xhci_device_isoc_close(struct usbd_pipe *);
209static void xhci_device_isoc_done(struct usbd_xfer *); 209static void xhci_device_isoc_done(struct usbd_xfer *);
210 210
211static usbd_status xhci_device_intr_transfer(struct usbd_xfer *); 211static usbd_status xhci_device_intr_transfer(struct usbd_xfer *);
212static usbd_status xhci_device_intr_start(struct usbd_xfer *); 212static usbd_status xhci_device_intr_start(struct usbd_xfer *);
213static void xhci_device_intr_abort(struct usbd_xfer *); 213static void xhci_device_intr_abort(struct usbd_xfer *);
214static void xhci_device_intr_close(struct usbd_pipe *); 214static void xhci_device_intr_close(struct usbd_pipe *);
215static void xhci_device_intr_done(struct usbd_xfer *); 215static void xhci_device_intr_done(struct usbd_xfer *);
216 216
217static usbd_status xhci_device_bulk_transfer(struct usbd_xfer *); 217static usbd_status xhci_device_bulk_transfer(struct usbd_xfer *);
218static usbd_status xhci_device_bulk_start(struct usbd_xfer *); 218static usbd_status xhci_device_bulk_start(struct usbd_xfer *);
219static void xhci_device_bulk_abort(struct usbd_xfer *); 219static void xhci_device_bulk_abort(struct usbd_xfer *);
220static void xhci_device_bulk_close(struct usbd_pipe *); 220static void xhci_device_bulk_close(struct usbd_pipe *);
221static void xhci_device_bulk_done(struct usbd_xfer *); 221static void xhci_device_bulk_done(struct usbd_xfer *);
222 222
223static const struct usbd_bus_methods xhci_bus_methods = { 223static const struct usbd_bus_methods xhci_bus_methods = {
224 .ubm_open = xhci_open, 224 .ubm_open = xhci_open,
225 .ubm_softint = xhci_softintr, 225 .ubm_softint = xhci_softintr,
226 .ubm_dopoll = xhci_poll, 226 .ubm_dopoll = xhci_poll,
227 .ubm_allocx = xhci_allocx, 227 .ubm_allocx = xhci_allocx,
228 .ubm_freex = xhci_freex, 228 .ubm_freex = xhci_freex,
229 .ubm_abortx = xhci_abortx, 229 .ubm_abortx = xhci_abortx,
230 .ubm_dying = xhci_dying, 230 .ubm_dying = xhci_dying,
231 .ubm_getlock = xhci_get_lock, 231 .ubm_getlock = xhci_get_lock,
232 .ubm_newdev = xhci_new_device, 232 .ubm_newdev = xhci_new_device,
233 .ubm_rhctrl = xhci_roothub_ctrl, 233 .ubm_rhctrl = xhci_roothub_ctrl,
234}; 234};
235 235
236static const struct usbd_pipe_methods xhci_root_intr_methods = { 236static const struct usbd_pipe_methods xhci_root_intr_methods = {
237 .upm_transfer = xhci_root_intr_transfer, 237 .upm_transfer = xhci_root_intr_transfer,
238 .upm_start = xhci_root_intr_start, 238 .upm_start = xhci_root_intr_start,
239 .upm_abort = xhci_root_intr_abort, 239 .upm_abort = xhci_root_intr_abort,
240 .upm_close = xhci_root_intr_close, 240 .upm_close = xhci_root_intr_close,
241 .upm_cleartoggle = xhci_noop, 241 .upm_cleartoggle = xhci_noop,
242 .upm_done = xhci_root_intr_done, 242 .upm_done = xhci_root_intr_done,
243}; 243};
244 244
245 245
246static const struct usbd_pipe_methods xhci_device_ctrl_methods = { 246static const struct usbd_pipe_methods xhci_device_ctrl_methods = {
247 .upm_transfer = xhci_device_ctrl_transfer, 247 .upm_transfer = xhci_device_ctrl_transfer,
248 .upm_start = xhci_device_ctrl_start, 248 .upm_start = xhci_device_ctrl_start,
249 .upm_abort = xhci_device_ctrl_abort, 249 .upm_abort = xhci_device_ctrl_abort,
250 .upm_close = xhci_device_ctrl_close, 250 .upm_close = xhci_device_ctrl_close,
251 .upm_cleartoggle = xhci_noop, 251 .upm_cleartoggle = xhci_noop,
252 .upm_done = xhci_device_ctrl_done, 252 .upm_done = xhci_device_ctrl_done,
253}; 253};
254 254
255static const struct usbd_pipe_methods xhci_device_isoc_methods = { 255static const struct usbd_pipe_methods xhci_device_isoc_methods = {
256 .upm_transfer = xhci_device_isoc_transfer, 256 .upm_transfer = xhci_device_isoc_transfer,
257 .upm_abort = xhci_device_isoc_abort, 257 .upm_abort = xhci_device_isoc_abort,
258 .upm_close = xhci_device_isoc_close, 258 .upm_close = xhci_device_isoc_close,
259 .upm_cleartoggle = xhci_noop, 259 .upm_cleartoggle = xhci_noop,
260 .upm_done = xhci_device_isoc_done, 260 .upm_done = xhci_device_isoc_done,
261}; 261};
262 262
263static const struct usbd_pipe_methods xhci_device_bulk_methods = { 263static const struct usbd_pipe_methods xhci_device_bulk_methods = {
264 .upm_transfer = xhci_device_bulk_transfer, 264 .upm_transfer = xhci_device_bulk_transfer,
265 .upm_start = xhci_device_bulk_start, 265 .upm_start = xhci_device_bulk_start,
266 .upm_abort = xhci_device_bulk_abort, 266 .upm_abort = xhci_device_bulk_abort,
267 .upm_close = xhci_device_bulk_close, 267 .upm_close = xhci_device_bulk_close,
268 .upm_cleartoggle = xhci_noop, 268 .upm_cleartoggle = xhci_noop,
269 .upm_done = xhci_device_bulk_done, 269 .upm_done = xhci_device_bulk_done,
270}; 270};
271 271
272static const struct usbd_pipe_methods xhci_device_intr_methods = { 272static const struct usbd_pipe_methods xhci_device_intr_methods = {
273 .upm_transfer = xhci_device_intr_transfer, 273 .upm_transfer = xhci_device_intr_transfer,
274 .upm_start = xhci_device_intr_start, 274 .upm_start = xhci_device_intr_start,
275 .upm_abort = xhci_device_intr_abort, 275 .upm_abort = xhci_device_intr_abort,
276 .upm_close = xhci_device_intr_close, 276 .upm_close = xhci_device_intr_close,
277 .upm_cleartoggle = xhci_noop, 277 .upm_cleartoggle = xhci_noop,
278 .upm_done = xhci_device_intr_done, 278 .upm_done = xhci_device_intr_done,
279}; 279};
280 280
281static inline uint32_t 281static inline uint32_t
282xhci_read_1(const struct xhci_softc * const sc, bus_size_t offset) 282xhci_read_1(const struct xhci_softc * const sc, bus_size_t offset)
283{ 283{
284 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 284 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset);
285} 285}
286 286
287static inline uint32_t 287static inline uint32_t
288xhci_read_2(const struct xhci_softc * const sc, bus_size_t offset) 288xhci_read_2(const struct xhci_softc * const sc, bus_size_t offset)
289{ 289{
290 return bus_space_read_2(sc->sc_iot, sc->sc_ioh, offset); 290 return bus_space_read_2(sc->sc_iot, sc->sc_ioh, offset);
291} 291}
292 292
293static inline uint32_t 293static inline uint32_t
294xhci_read_4(const struct xhci_softc * const sc, bus_size_t offset) 294xhci_read_4(const struct xhci_softc * const sc, bus_size_t offset)
295{ 295{
296 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, offset); 296 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, offset);
297} 297}
298 298
299static inline void 299static inline void
300xhci_write_1(const struct xhci_softc * const sc, bus_size_t offset, 300xhci_write_1(const struct xhci_softc * const sc, bus_size_t offset,
301 uint32_t value) 301 uint32_t value)
302{ 302{
303 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, value); 303 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, value);
304} 304}
305 305
306#if 0 /* unused */ 306#if 0 /* unused */
307static inline void 307static inline void
308xhci_write_4(const struct xhci_softc * const sc, bus_size_t offset, 308xhci_write_4(const struct xhci_softc * const sc, bus_size_t offset,
309 uint32_t value) 309 uint32_t value)
310{ 310{
311 bus_space_write_4(sc->sc_iot, sc->sc_ioh, offset, value); 311 bus_space_write_4(sc->sc_iot, sc->sc_ioh, offset, value);
312} 312}
313#endif /* unused */ 313#endif /* unused */
314 314
315static inline void 315static inline void
316xhci_barrier(const struct xhci_softc * const sc, int flags) 316xhci_barrier(const struct xhci_softc * const sc, int flags)
317{ 317{
318 bus_space_barrier(sc->sc_iot, sc->sc_ioh, 0, sc->sc_ios, flags); 318 bus_space_barrier(sc->sc_iot, sc->sc_ioh, 0, sc->sc_ios, flags);
319} 319}
320 320
321static inline uint32_t 321static inline uint32_t
322xhci_cap_read_4(const struct xhci_softc * const sc, bus_size_t offset) 322xhci_cap_read_4(const struct xhci_softc * const sc, bus_size_t offset)
323{ 323{
324 return bus_space_read_4(sc->sc_iot, sc->sc_cbh, offset); 324 return bus_space_read_4(sc->sc_iot, sc->sc_cbh, offset);
325} 325}
326 326
327static inline uint32_t 327static inline uint32_t
328xhci_op_read_4(const struct xhci_softc * const sc, bus_size_t offset) 328xhci_op_read_4(const struct xhci_softc * const sc, bus_size_t offset)
329{ 329{
330 return bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 330 return bus_space_read_4(sc->sc_iot, sc->sc_obh, offset);
331} 331}
332 332
333static inline void 333static inline void
334xhci_op_write_4(const struct xhci_softc * const sc, bus_size_t offset, 334xhci_op_write_4(const struct xhci_softc * const sc, bus_size_t offset,
335 uint32_t value) 335 uint32_t value)
336{ 336{
337 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 337 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value);
338} 338}
339 339
340static inline uint64_t 340static inline uint64_t
341xhci_op_read_8(const struct xhci_softc * const sc, bus_size_t offset) 341xhci_op_read_8(const struct xhci_softc * const sc, bus_size_t offset)
342{ 342{
343 uint64_t value; 343 uint64_t value;
344 344
345 if (XHCI_HCC_AC64(sc->sc_hcc)) { 345 if (XHCI_HCC_AC64(sc->sc_hcc)) {
346#ifdef XHCI_USE_BUS_SPACE_8 346#ifdef XHCI_USE_BUS_SPACE_8
347 value = bus_space_read_8(sc->sc_iot, sc->sc_obh, offset); 347 value = bus_space_read_8(sc->sc_iot, sc->sc_obh, offset);
348#else 348#else
349 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 349 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset);
350 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_obh, 350 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_obh,
351 offset + 4) << 32; 351 offset + 4) << 32;
352#endif 352#endif
353 } else { 353 } else {
354 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 354 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset);
355 } 355 }
356 356
357 return value; 357 return value;
358} 358}
359 359
360static inline void 360static inline void
361xhci_op_write_8(const struct xhci_softc * const sc, bus_size_t offset, 361xhci_op_write_8(const struct xhci_softc * const sc, bus_size_t offset,
362 uint64_t value) 362 uint64_t value)
363{ 363{
364 if (XHCI_HCC_AC64(sc->sc_hcc)) { 364 if (XHCI_HCC_AC64(sc->sc_hcc)) {
365#ifdef XHCI_USE_BUS_SPACE_8 365#ifdef XHCI_USE_BUS_SPACE_8
366 bus_space_write_8(sc->sc_iot, sc->sc_obh, offset, value); 366 bus_space_write_8(sc->sc_iot, sc->sc_obh, offset, value);
367#else 367#else
368 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 0, 368 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 0,
369 (value >> 0) & 0xffffffff); 369 (value >> 0) & 0xffffffff);
370 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 4, 370 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 4,
371 (value >> 32) & 0xffffffff); 371 (value >> 32) & 0xffffffff);
372#endif 372#endif
373 } else { 373 } else {
374 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 374 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value);
375 } 375 }
376} 376}
377 377
378static inline uint32_t 378static inline uint32_t
379xhci_rt_read_4(const struct xhci_softc * const sc, bus_size_t offset) 379xhci_rt_read_4(const struct xhci_softc * const sc, bus_size_t offset)
380{ 380{
381 return bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 381 return bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset);
382} 382}
383 383
384static inline void 384static inline void
385xhci_rt_write_4(const struct xhci_softc * const sc, bus_size_t offset, 385xhci_rt_write_4(const struct xhci_softc * const sc, bus_size_t offset,
386 uint32_t value) 386 uint32_t value)
387{ 387{
388 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 388 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value);
389} 389}
390 390
391#if 0 /* unused */ 
392static inline uint64_t 391static inline uint64_t
393xhci_rt_read_8(const struct xhci_softc * const sc, bus_size_t offset) 392xhci_rt_read_8(const struct xhci_softc * const sc, bus_size_t offset)
394{ 393{
395 uint64_t value; 394 uint64_t value;
396 395
397 if (XHCI_HCC_AC64(sc->sc_hcc)) { 396 if (XHCI_HCC_AC64(sc->sc_hcc)) {
398#ifdef XHCI_USE_BUS_SPACE_8 397#ifdef XHCI_USE_BUS_SPACE_8
399 value = bus_space_read_8(sc->sc_iot, sc->sc_rbh, offset); 398 value = bus_space_read_8(sc->sc_iot, sc->sc_rbh, offset);
400#else 399#else
401 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 400 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset);
402 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_rbh, 401 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_rbh,
403 offset + 4) << 32; 402 offset + 4) << 32;
404#endif 403#endif
405 } else { 404 } else {
406 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 405 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset);
407 } 406 }
408 407
409 return value; 408 return value;
410} 409}
411#endif /* unused */ 
412 410
413static inline void 411static inline void
414xhci_rt_write_8(const struct xhci_softc * const sc, bus_size_t offset, 412xhci_rt_write_8(const struct xhci_softc * const sc, bus_size_t offset,
415 uint64_t value) 413 uint64_t value)
416{ 414{
417 if (XHCI_HCC_AC64(sc->sc_hcc)) { 415 if (XHCI_HCC_AC64(sc->sc_hcc)) {
418#ifdef XHCI_USE_BUS_SPACE_8 416#ifdef XHCI_USE_BUS_SPACE_8
419 bus_space_write_8(sc->sc_iot, sc->sc_rbh, offset, value); 417 bus_space_write_8(sc->sc_iot, sc->sc_rbh, offset, value);
420#else 418#else
421 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 0, 419 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 0,
422 (value >> 0) & 0xffffffff); 420 (value >> 0) & 0xffffffff);
423 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 4, 421 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 4,
424 (value >> 32) & 0xffffffff); 422 (value >> 32) & 0xffffffff);
425#endif 423#endif
426 } else { 424 } else {
427 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 425 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value);
428 } 426 }
429} 427}
430 428
431#if 0 /* unused */ 429#if 0 /* unused */
432static inline uint32_t 430static inline uint32_t
433xhci_db_read_4(const struct xhci_softc * const sc, bus_size_t offset) 431xhci_db_read_4(const struct xhci_softc * const sc, bus_size_t offset)
434{ 432{
435 return bus_space_read_4(sc->sc_iot, sc->sc_dbh, offset); 433 return bus_space_read_4(sc->sc_iot, sc->sc_dbh, offset);
436} 434}
437#endif /* unused */ 435#endif /* unused */
438 436
439static inline void 437static inline void
440xhci_db_write_4(const struct xhci_softc * const sc, bus_size_t offset, 438xhci_db_write_4(const struct xhci_softc * const sc, bus_size_t offset,
441 uint32_t value) 439 uint32_t value)
442{ 440{
443 bus_space_write_4(sc->sc_iot, sc->sc_dbh, offset, value); 441 bus_space_write_4(sc->sc_iot, sc->sc_dbh, offset, value);
444} 442}
445 443
446/* --- */ 444/* --- */
447 445
448static inline uint8_t 446static inline uint8_t
449xhci_ep_get_type(usb_endpoint_descriptor_t * const ed) 447xhci_ep_get_type(usb_endpoint_descriptor_t * const ed)
450{ 448{
451 u_int eptype = 0; 449 u_int eptype = 0;
452 450
453 switch (UE_GET_XFERTYPE(ed->bmAttributes)) { 451 switch (UE_GET_XFERTYPE(ed->bmAttributes)) {
454 case UE_CONTROL: 452 case UE_CONTROL:
455 eptype = 0x0; 453 eptype = 0x0;
456 break; 454 break;
457 case UE_ISOCHRONOUS: 455 case UE_ISOCHRONOUS:
458 eptype = 0x1; 456 eptype = 0x1;
459 break; 457 break;
460 case UE_BULK: 458 case UE_BULK:
461 eptype = 0x2; 459 eptype = 0x2;
462 break; 460 break;
463 case UE_INTERRUPT: 461 case UE_INTERRUPT:
464 eptype = 0x3; 462 eptype = 0x3;
465 break; 463 break;
466 } 464 }
467 465
468 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 466 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) ||
469 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 467 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN))
470 return eptype | 0x4; 468 return eptype | 0x4;
471 else 469 else
472 return eptype; 470 return eptype;
473} 471}
474 472
475static u_int 473static u_int
476xhci_ep_get_dci(usb_endpoint_descriptor_t * const ed) 474xhci_ep_get_dci(usb_endpoint_descriptor_t * const ed)
477{ 475{
478 /* xHCI 1.0 section 4.5.1 */ 476 /* xHCI 1.0 section 4.5.1 */
479 u_int epaddr = UE_GET_ADDR(ed->bEndpointAddress); 477 u_int epaddr = UE_GET_ADDR(ed->bEndpointAddress);
480 u_int in = 0; 478 u_int in = 0;
481 479
482 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 480 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) ||
483 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 481 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN))
484 in = 1; 482 in = 1;
485 483
486 return epaddr * 2 + in; 484 return epaddr * 2 + in;
487} 485}
488 486
489static inline u_int 487static inline u_int
490xhci_dci_to_ici(const u_int i) 488xhci_dci_to_ici(const u_int i)
491{ 489{
492 return i + 1; 490 return i + 1;
493} 491}
494 492
495static inline void * 493static inline void *
496xhci_slot_get_dcv(struct xhci_softc * const sc, struct xhci_slot * const xs, 494xhci_slot_get_dcv(struct xhci_softc * const sc, struct xhci_slot * const xs,
497 const u_int dci) 495 const u_int dci)
498{ 496{
499 return KERNADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 497 return KERNADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci);
500} 498}
501 499
502#if 0 /* unused */ 500#if 0 /* unused */
503static inline bus_addr_t 501static inline bus_addr_t
504xhci_slot_get_dcp(struct xhci_softc * const sc, struct xhci_slot * const xs, 502xhci_slot_get_dcp(struct xhci_softc * const sc, struct xhci_slot * const xs,
505 const u_int dci) 503 const u_int dci)
506{ 504{
507 return DMAADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 505 return DMAADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci);
508} 506}
509#endif /* unused */ 507#endif /* unused */
510 508
511static inline void * 509static inline void *
512xhci_slot_get_icv(struct xhci_softc * const sc, struct xhci_slot * const xs, 510xhci_slot_get_icv(struct xhci_softc * const sc, struct xhci_slot * const xs,
513 const u_int ici) 511 const u_int ici)
514{ 512{
515 return KERNADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 513 return KERNADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici);
516} 514}
517 515
518static inline bus_addr_t 516static inline bus_addr_t
519xhci_slot_get_icp(struct xhci_softc * const sc, struct xhci_slot * const xs, 517xhci_slot_get_icp(struct xhci_softc * const sc, struct xhci_slot * const xs,
520 const u_int ici) 518 const u_int ici)
521{ 519{
522 return DMAADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 520 return DMAADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici);
523} 521}
524 522
525static inline struct xhci_trb * 523static inline struct xhci_trb *
526xhci_ring_trbv(struct xhci_ring * const xr, u_int idx) 524xhci_ring_trbv(struct xhci_ring * const xr, u_int idx)
527{ 525{
528 return KERNADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 526 return KERNADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx);
529} 527}
530 528
531static inline bus_addr_t 529static inline bus_addr_t
532xhci_ring_trbp(struct xhci_ring * const xr, u_int idx) 530xhci_ring_trbp(struct xhci_ring * const xr, u_int idx)
533{ 531{
534 return DMAADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 532 return DMAADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx);
535} 533}
536 534
537static inline void 535static inline void
538xhci_xfer_put_trb(struct xhci_xfer * const xx, u_int idx, 536xhci_xfer_put_trb(struct xhci_xfer * const xx, u_int idx,
539 uint64_t parameter, uint32_t status, uint32_t control) 537 uint64_t parameter, uint32_t status, uint32_t control)
540{ 538{
541 KASSERTMSG(idx < xx->xx_ntrb, "idx=%u xx_ntrb=%u", idx, xx->xx_ntrb); 539 KASSERTMSG(idx < xx->xx_ntrb, "idx=%u xx_ntrb=%u", idx, xx->xx_ntrb);
542 xx->xx_trb[idx].trb_0 = parameter; 540 xx->xx_trb[idx].trb_0 = parameter;
543 xx->xx_trb[idx].trb_2 = status; 541 xx->xx_trb[idx].trb_2 = status;
544 xx->xx_trb[idx].trb_3 = control; 542 xx->xx_trb[idx].trb_3 = control;
545} 543}
546 544
547static inline void 545static inline void
548xhci_trb_put(struct xhci_trb * const trb, uint64_t parameter, uint32_t status, 546xhci_trb_put(struct xhci_trb * const trb, uint64_t parameter, uint32_t status,
549 uint32_t control) 547 uint32_t control)
550{ 548{
551 trb->trb_0 = htole64(parameter); 549 trb->trb_0 = htole64(parameter);
552 trb->trb_2 = htole32(status); 550 trb->trb_2 = htole32(status);
553 trb->trb_3 = htole32(control); 551 trb->trb_3 = htole32(control);
554} 552}
555 553
556static int 554static int
557xhci_trb_get_idx(struct xhci_ring *xr, uint64_t trb_0, int *idx) 555xhci_trb_get_idx(struct xhci_ring *xr, uint64_t trb_0, int *idx)
558{ 556{
559 /* base address of TRBs */ 557 /* base address of TRBs */
560 bus_addr_t trbp = xhci_ring_trbp(xr, 0); 558 bus_addr_t trbp = xhci_ring_trbp(xr, 0);
561 559
562 /* trb_0 range sanity check */ 560 /* trb_0 range sanity check */
563 if (trb_0 == 0 || trb_0 < trbp || 561 if (trb_0 == 0 || trb_0 < trbp ||
564 (trb_0 - trbp) % sizeof(struct xhci_trb) != 0 || 562 (trb_0 - trbp) % sizeof(struct xhci_trb) != 0 ||
565 (trb_0 - trbp) / sizeof(struct xhci_trb) >= xr->xr_ntrb) { 563 (trb_0 - trbp) / sizeof(struct xhci_trb) >= xr->xr_ntrb) {
566 return 1; 564 return 1;
567 } 565 }
568 *idx = (trb_0 - trbp) / sizeof(struct xhci_trb); 566 *idx = (trb_0 - trbp) / sizeof(struct xhci_trb);
569 return 0; 567 return 0;
570} 568}
571 569
572static unsigned int 570static unsigned int
573xhci_get_epstate(struct xhci_softc * const sc, struct xhci_slot * const xs, 571xhci_get_epstate(struct xhci_softc * const sc, struct xhci_slot * const xs,
574 u_int dci) 572 u_int dci)
575{ 573{
576 uint32_t *cp; 574 uint32_t *cp;
577 575
578 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 576 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD);
579 cp = xhci_slot_get_dcv(sc, xs, dci); 577 cp = xhci_slot_get_dcv(sc, xs, dci);
580 return XHCI_EPCTX_0_EPSTATE_GET(le32toh(cp[0])); 578 return XHCI_EPCTX_0_EPSTATE_GET(le32toh(cp[0]));
581} 579}
582 580
583static inline unsigned int 581static inline unsigned int
584xhci_ctlrport2bus(struct xhci_softc * const sc, unsigned int ctlrport) 582xhci_ctlrport2bus(struct xhci_softc * const sc, unsigned int ctlrport)
585{ 583{
586 const unsigned int port = ctlrport - 1; 584 const unsigned int port = ctlrport - 1;
587 const uint8_t bit = __BIT(port % NBBY); 585 const uint8_t bit = __BIT(port % NBBY);
588 586
589 return __SHIFTOUT(sc->sc_ctlrportbus[port / NBBY], bit); 587 return __SHIFTOUT(sc->sc_ctlrportbus[port / NBBY], bit);
590} 588}
591 589
592/* 590/*
593 * Return the roothub port for a controller port. Both are 1..n. 591 * Return the roothub port for a controller port. Both are 1..n.
594 */ 592 */
595static inline unsigned int 593static inline unsigned int
596xhci_ctlrport2rhport(struct xhci_softc * const sc, unsigned int ctrlport) 594xhci_ctlrport2rhport(struct xhci_softc * const sc, unsigned int ctrlport)
597{ 595{
598 596
599 return sc->sc_ctlrportmap[ctrlport - 1]; 597 return sc->sc_ctlrportmap[ctrlport - 1];
600} 598}
601 599
602/* 600/*
603 * Return the controller port for a bus roothub port. Both are 1..n. 601 * Return the controller port for a bus roothub port. Both are 1..n.
604 */ 602 */
605static inline unsigned int 603static inline unsigned int
606xhci_rhport2ctlrport(struct xhci_softc * const sc, unsigned int bn, 604xhci_rhport2ctlrport(struct xhci_softc * const sc, unsigned int bn,
607 unsigned int rhport) 605 unsigned int rhport)
608{ 606{
609 607
610 return sc->sc_rhportmap[bn][rhport - 1]; 608 return sc->sc_rhportmap[bn][rhport - 1];
611} 609}
612 610
613/* --- */ 611/* --- */
614 612
615void 613void
616xhci_childdet(device_t self, device_t child) 614xhci_childdet(device_t self, device_t child)
617{ 615{
618 struct xhci_softc * const sc = device_private(self); 616 struct xhci_softc * const sc = device_private(self);
619 617
620 KASSERT((sc->sc_child == child) || (sc->sc_child2 == child)); 618 KASSERT((sc->sc_child == child) || (sc->sc_child2 == child));
621 if (child == sc->sc_child2) 619 if (child == sc->sc_child2)
622 sc->sc_child2 = NULL; 620 sc->sc_child2 = NULL;
623 else if (child == sc->sc_child) 621 else if (child == sc->sc_child)
624 sc->sc_child = NULL; 622 sc->sc_child = NULL;
625} 623}
626 624
627int 625int
628xhci_detach(struct xhci_softc *sc, int flags) 626xhci_detach(struct xhci_softc *sc, int flags)
629{ 627{
630 int rv = 0; 628 int rv = 0;
631 629
632 if (sc->sc_child2 != NULL) { 630 if (sc->sc_child2 != NULL) {
633 rv = config_detach(sc->sc_child2, flags); 631 rv = config_detach(sc->sc_child2, flags);
634 if (rv != 0) 632 if (rv != 0)
635 return rv; 633 return rv;
636 KASSERT(sc->sc_child2 == NULL); 634 KASSERT(sc->sc_child2 == NULL);
637 } 635 }
638 636
639 if (sc->sc_child != NULL) { 637 if (sc->sc_child != NULL) {
640 rv = config_detach(sc->sc_child, flags); 638 rv = config_detach(sc->sc_child, flags);
641 if (rv != 0) 639 if (rv != 0)
642 return rv; 640 return rv;
643 KASSERT(sc->sc_child == NULL); 641 KASSERT(sc->sc_child == NULL);
644 } 642 }
645 643
646 /* XXX unconfigure/free slots */ 644 /* XXX unconfigure/free slots */
647 645
648 /* verify: */ 646 /* verify: */
649 xhci_rt_write_4(sc, XHCI_IMAN(0), 0); 647 xhci_rt_write_4(sc, XHCI_IMAN(0), 0);
650 xhci_op_write_4(sc, XHCI_USBCMD, 0); 648 xhci_op_write_4(sc, XHCI_USBCMD, 0);
651 /* do we need to wait for stop? */ 649 /* do we need to wait for stop? */
652 650
653 xhci_op_write_8(sc, XHCI_CRCR, 0); 651 xhci_op_write_8(sc, XHCI_CRCR, 0);
654 xhci_ring_free(sc, &sc->sc_cr); 652 xhci_ring_free(sc, &sc->sc_cr);
655 cv_destroy(&sc->sc_command_cv); 653 cv_destroy(&sc->sc_command_cv);
656 cv_destroy(&sc->sc_cmdbusy_cv); 654 cv_destroy(&sc->sc_cmdbusy_cv);
657 655
658 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), 0); 656 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), 0);
659 xhci_rt_write_8(sc, XHCI_ERSTBA(0), 0); 657 xhci_rt_write_8(sc, XHCI_ERSTBA(0), 0);
660 xhci_rt_write_8(sc, XHCI_ERDP(0), 0 | XHCI_ERDP_BUSY); 658 xhci_rt_write_8(sc, XHCI_ERDP(0), 0 | XHCI_ERDP_BUSY);
661 xhci_ring_free(sc, &sc->sc_er); 659 xhci_ring_free(sc, &sc->sc_er);
662 660
663 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 661 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma);
664 662
665 xhci_op_write_8(sc, XHCI_DCBAAP, 0); 663 xhci_op_write_8(sc, XHCI_DCBAAP, 0);
666 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 664 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma);
667 665
668 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * sc->sc_maxslots); 666 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * sc->sc_maxslots);
669 667
670 kmem_free(sc->sc_ctlrportbus, 668 kmem_free(sc->sc_ctlrportbus,
671 howmany(sc->sc_maxports * sizeof(uint8_t), NBBY)); 669 howmany(sc->sc_maxports * sizeof(uint8_t), NBBY));
672 kmem_free(sc->sc_ctlrportmap, sc->sc_maxports * sizeof(int)); 670 kmem_free(sc->sc_ctlrportmap, sc->sc_maxports * sizeof(int));
673 671
674 for (size_t j = 0; j < __arraycount(sc->sc_rhportmap); j++) { 672 for (size_t j = 0; j < __arraycount(sc->sc_rhportmap); j++) {
675 kmem_free(sc->sc_rhportmap[j], sc->sc_maxports * sizeof(int)); 673 kmem_free(sc->sc_rhportmap[j], sc->sc_maxports * sizeof(int));
676 } 674 }
677 675
678 mutex_destroy(&sc->sc_lock); 676 mutex_destroy(&sc->sc_lock);
679 mutex_destroy(&sc->sc_intr_lock); 677 mutex_destroy(&sc->sc_intr_lock);
680 678
681 pool_cache_destroy(sc->sc_xferpool); 679 pool_cache_destroy(sc->sc_xferpool);
682 680
683 return rv; 681 return rv;
684} 682}
685 683
686int 684int
687xhci_activate(device_t self, enum devact act) 685xhci_activate(device_t self, enum devact act)
688{ 686{
689 struct xhci_softc * const sc = device_private(self); 687 struct xhci_softc * const sc = device_private(self);
690 688
691 switch (act) { 689 switch (act) {
692 case DVACT_DEACTIVATE: 690 case DVACT_DEACTIVATE:
693 sc->sc_dying = true; 691 sc->sc_dying = true;
694 return 0; 692 return 0;
695 default: 693 default:
696 return EOPNOTSUPP; 694 return EOPNOTSUPP;
697 } 695 }
698} 696}
699 697
700bool 698bool
701xhci_suspend(device_t dv, const pmf_qual_t *qual) 699xhci_suspend(device_t self, const pmf_qual_t *qual)
702{ 700{
703 return false; 701 struct xhci_softc * const sc = device_private(self);
 702 size_t i, j, bn;
 703 int port;
 704 uint32_t v;
 705
 706 XHCIHIST_FUNC(); XHCIHIST_CALLED();
 707
 708 /*
 709 * First, suspend all the ports:
 710 *
 711 * xHCI Requirements Specification 1.2, May 2019, Sec. 4.15:
 712 * Suspend-Resume, pp. 276-283
 713 * https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/extensible-host-controler-interface-usb-xhci.pdf#page=276
 714 */
 715 for (bn = 0; bn < 2; bn++) {
 716 for (i = 1; i <= sc->sc_rhportcount[bn]; i++) {
 717 /* 4.15.1: Port Suspend. */
 718 port = XHCI_PORTSC(xhci_rhport2ctlrport(sc, bn, i));
 719
 720 /*
 721 * `System software places individual ports
 722 * into suspend mode by writing a ``3'' into
 723 * the appropriate PORTSC register Port Link
 724 * State (PLS) field (refer to Section 5.4.8).
 725 * Software should only set the PLS field to
 726 * ``3'' when the port is in the Enabled
 727 * state.'
 728 *
 729 * `Software should not attempt to suspend a
 730 * port unless the port reports that it is in
 731 * the enabled (PED = ``1''; PLS < ``3'')
 732 * state (refer to Section 5.4.8 for more
 733 * information about PED and PLS).'
 734 */
 735 v = xhci_op_read_4(sc, port);
 736 if (((v & XHCI_PS_PED) == 0) ||
 737 XHCI_PS_PLS_GET(v) >= XHCI_PS_PLS_U3)
 738 continue;
 739 v &= ~(XHCI_PS_PLS_MASK | XHCI_PS_CLEAR);
 740 v |= XHCI_PS_LWS | XHCI_PS_PLS_SET(XHCI_PS_PLS_SETU3);
 741 xhci_op_write_4(sc, port, v);
 742
 743 /*
 744 * `When the PLS field is written with U3
 745 * (``3''), the status of the PLS bit will not
 746 * change to the target U state U3 until the
 747 * suspend signaling has completed to the
 748 * attached device (which may be as long as
 749 * 10ms.).'
 750 *
 751 * `Software is required to wait for U3
 752 * transitions to complete before it puts the
 753 * xHC into a low power state, and before
 754 * resuming the port.'
 755 *
 756 * XXX Take advantage of the technique to
 757 * reduce polling on host controllers that
 758 * support the U3C capability.
 759 */
 760 for (j = 0; j < XHCI_WAIT_PLS_U3; j++) {
 761 v = xhci_op_read_4(sc, port);
 762 if (XHCI_PS_PLS_GET(v) == XHCI_PS_PLS_U3)
 763 break;
 764 usb_delay_ms(&sc->sc_bus, 1);
 765 }
 766 if (j == XHCI_WAIT_PLS_U3) {
 767 device_printf(self,
 768 "suspend timeout on bus %zu port %zu\n",
 769 bn, i);
 770 return false;
 771 }
 772 }
 773 }
 774
 775 /*
 776 * xHCI Requirements Specification 1.2, May 2019, Sec. 4.23.2:
 777 * xHCI Power Management, p. 342
 778 * https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/extensible-host-controler-interface-usb-xhci.pdf#page=342
 779 */
 780
 781 /*
 782 * `1. Stop all USB activity by issuing Stop Endpoint Commands
 783 * for Busy endpoints in the Running state. If the Force
 784 * Save Context Capability (FSC = ``0'') is not supported,
 785 * then Stop Endpoint Commands shall be issued for all Idle
 786 * endpoints in the Running state as well. The Stop
 787 * Endpoint Command causes the xHC to update the respective
 788 * Endpoint or Stream Contexts in system memory, e.g. the
 789 * TR Dequeue Pointer, DCS, etc. fields. Refer to
 790 * Implementation Note "0".'
 791 *
 792 * XXX Not entirely sure if this is necessary for us; also it
 793 * probably has to happen before suspending the ports.
 794 */
 795
 796 /*
 797 * `2. Ensure that the Command Ring is in the Stopped state
 798 * (CRR = ``0'') or Idle (i.e. the Command Transfer Ring is
 799 * empty), and all Command Completion Events associated
 800 * with them have been received.'
 801 *
 802 * XXX
 803 */
 804
 805 /* `3. Stop the controller by setting Run/Stop (R/S) = ``0''.' */
 806 xhci_op_write_4(sc, XHCI_USBCMD,
 807 xhci_op_read_4(sc, XHCI_USBCMD) & ~XHCI_CMD_RS);
 808
 809 /*
 810 * `4. Read the Operational Runtime, and VTIO registers in the
 811 * following order: USBCMD, DNCTRL, DCBAAP, CONFIG, ERSTSZ,
 812 * ERSTBA, ERDP, IMAN, IMOD, and VTIO and save their
 813 * state.'
 814 *
 815 * (We don't use VTIO here (XXX for now?).)
 816 */
 817 sc->sc_regs.usbcmd = xhci_op_read_4(sc, XHCI_USBCMD);
 818 sc->sc_regs.dnctrl = xhci_op_read_4(sc, XHCI_DNCTRL);
 819 sc->sc_regs.dcbaap = xhci_op_read_8(sc, XHCI_DCBAAP);
 820 sc->sc_regs.config = xhci_op_read_4(sc, XHCI_CONFIG);
 821 sc->sc_regs.erstsz0 = xhci_rt_read_4(sc, XHCI_ERSTSZ(0));
 822 sc->sc_regs.erstba0 = xhci_rt_read_8(sc, XHCI_ERSTBA(0));
 823 sc->sc_regs.erdp0 = xhci_rt_read_8(sc, XHCI_ERDP(0));
 824 sc->sc_regs.iman0 = xhci_rt_read_4(sc, XHCI_IMAN(0));
 825 sc->sc_regs.imod0 = xhci_rt_read_4(sc, XHCI_IMOD(0));
 826
 827 /*
 828 * `5. Set the Controller Save State (CSS) flag in the USBCMD
 829 * register (5.4.1)...'
 830 */
 831 xhci_op_write_4(sc, XHCI_USBCMD,
 832 xhci_op_read_4(sc, XHCI_USBCMD) | XHCI_CMD_CSS);
 833
 834 /*
 835 * `...and wait for the Save State Status (SSS) flag in the
 836 * USBSTS register (5.4.2) to transition to ``0''.'
 837 */
 838 for (i = 0; i < XHCI_WAIT_SSS; i++) {
 839 if ((xhci_op_read_4(sc, XHCI_USBSTS) & XHCI_STS_SSS) == 0)
 840 break;
 841 usb_delay_ms(&sc->sc_bus, 1);
 842 }
 843 if (i >= XHCI_WAIT_SSS) {
 844 device_printf(self, "suspend timeout, USBSTS.SSS\n");
 845 /*
 846 * Just optimistically go on and check SRE anyway --
 847 * what's the worst that could happen?
 848 */
 849 }
 850
 851 /*
 852 * `Note: After a Save or Restore operation completes, the
 853 * Save/Restore Error (SRE) flag in the USBSTS register should
 854 * be checked to ensure that the operation completed
 855 * successfully.'
 856 */
 857 if (xhci_op_read_4(sc, XHCI_USBSTS) & XHCI_STS_SRE) {
 858 device_printf(self, "suspend error, USBSTS.SRE\n");
 859 return false;
 860 }
 861
 862 return true;
704} 863}
705 864
706bool 865bool
707xhci_resume(device_t dv, const pmf_qual_t *qual) 866xhci_resume(device_t self, const pmf_qual_t *qual)
708{ 867{
709 return false; 868 struct xhci_softc * const sc = device_private(self);
 869 size_t i, j, bn, dci;
 870 int port;
 871 uint32_t v;
 872
 873 XHCIHIST_FUNC(); XHCIHIST_CALLED();
 874
 875 /*
 876 * xHCI Requirements Specification 1.2, May 2019, Sec. 4.23.2:
 877 * xHCI Power Management, p. 343
 878 * https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/extensible-host-controler-interface-usb-xhci.pdf#page=343
 879 */
 880
 881 /*
 882 * `4. Restore the Operational Runtime, and VTIO registers with
 883 * their previously saved state in the following order:
 884 * DNCTRL, DCBAAP, CONFIG, ERSTSZ, ERSTBA, ERDP, IMAN,
 885 * IMOD, and VTIO.'
 886 *
 887 * (We don't use VTIO here (for now?).)
 888 */
 889 xhci_op_write_4(sc, XHCI_USBCMD, sc->sc_regs.usbcmd);
 890 xhci_op_write_4(sc, XHCI_DNCTRL, sc->sc_regs.dnctrl);
 891 xhci_op_write_8(sc, XHCI_DCBAAP, sc->sc_regs.dcbaap);
 892 xhci_op_write_4(sc, XHCI_CONFIG, sc->sc_regs.config);
 893 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), sc->sc_regs.erstsz0);
 894 xhci_rt_write_8(sc, XHCI_ERSTBA(0), sc->sc_regs.erstba0);
 895 xhci_rt_write_8(sc, XHCI_ERDP(0), sc->sc_regs.erdp0);
 896 xhci_rt_write_4(sc, XHCI_IMAN(0), sc->sc_regs.iman0);
 897 xhci_rt_write_4(sc, XHCI_IMOD(0), sc->sc_regs.imod0);
 898
 899 memset(&sc->sc_regs, 0, sizeof(sc->sc_regs)); /* paranoia */
 900
 901 /*
 902 * `5. Set the Controller Restore State (CRS) flag in the
 903 * USBCMD register (5.4.1) to ``1''...'
 904 */
 905 xhci_op_write_4(sc, XHCI_USBCMD,
 906 xhci_op_read_4(sc, XHCI_USBCMD) | XHCI_CMD_CRS);
 907
 908 /*
 909 * `...and wait for the Restore State Status (RSS) in the
 910 * USBSTS register (5.4.2) to transition to ``0''.'
 911 */
 912 for (i = 0; i < XHCI_WAIT_RSS; i++) {
 913 if ((xhci_op_read_4(sc, XHCI_USBSTS) & XHCI_STS_RSS) == 0)
 914 break;
 915 usb_delay_ms(&sc->sc_bus, 1);
 916 }
 917 if (i >= XHCI_WAIT_RSS) {
 918 device_printf(self, "suspend timeout, USBSTS.RSS\n");
 919 return false;
 920 }
 921
 922 /*
 923 * `6. Reinitialize the Command Ring, i.e. so its Cycle bits
 924 * are consistent with the RCS values to be written to the
 925 * CRCR.'
 926 *
 927 * XXX Hope just zeroing it is good enough!
 928 */
 929 xhci_host_dequeue(sc->sc_cr);
 930
 931 /*
 932 * `7. Write the CRCR with the address and RCS value of the
 933 * reinitialized Command Ring. Note that this write will
 934 * cause the Command Ring to restart at the address
 935 * specified by the CRCR.'
 936 */
 937 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(sc->sc_cr, 0) |
 938 sc->sc_cr->xr_cs);
 939
 940 /*
 941 * `8. Enable the controller by setting Run/Stop (R/S) =
 942 * ``1''.'
 943 */
 944 xhci_op_write_4(sc, XHCI_USBCMD,
 945 xhci_op_read_4(sc, XHCI_USBCMD) | XHCI_CMD_RS);
 946
 947 /*
 948 * `9. Software shall walk the USB topology and initialize each
 949 * of the xHC PORTSC, PORTPMSC, and PORTLI registers, and
 950 * external hub ports attached to USB devices.'
 951 *
 952 * This follows the procedure in 4.15 `Suspend-Resume', 4.15.2
 953 * `Port Resume', 4.15.2.1 `Host Initiated'.
 954 *
 955 * XXX We should maybe batch up initiating the state
 956 * transitions, and then wait for them to complete all at once.
 957 */
 958 for (bn = 0; bn < 2; bn++) {
 959 for (i = 1; i <= sc->sc_rhportcount[bn]; i++) {
 960 port = XHCI_PORTSC(xhci_rhport2ctlrport(sc, bn, i));
 961
 962 /* `When a port is in the U3 state: ...' */
 963 v = xhci_op_read_4(sc, port);
 964 if (XHCI_PS_PLS_GET(v) != XHCI_PS_PLS_U3)
 965 continue;
 966
 967 /*
 968 * `For a USB2 protocol port, software shall
 969 * write a ``15'' (Resume) to the PLS field to
 970 * initiate resume signaling. The port shall
 971 * transition to the Resume substate and the
 972 * xHC shall transmit the resume signaling
 973 * within 1ms (T_URSM). Software shall ensure
 974 * that resume is signaled for at least 20ms
 975 * (T_DRSMDN). Software shall start timing
 976 * T_DRSMDN from the write of ``15'' (Resume)
 977 * to PLS.'
 978 */
 979 if (bn == 1) {
 980 KASSERT(sc->sc_bus2.ub_revision == USBREV_2_0);
 981 v &= ~(XHCI_PS_PLS_MASK | XHCI_PS_CLEAR);
 982 v |= XHCI_PS_LWS;
 983 v |= XHCI_PS_PLS_SET(XHCI_PS_PLS_SETRESUME);
 984 xhci_op_write_4(sc, port, v);
 985 usb_delay_ms(&sc->sc_bus, 20);
 986 } else {
 987 KASSERT(sc->sc_bus.ub_revision > USBREV_2_0);
 988 }
 989
 990 /*
 991 * `For a USB3 protocol port [and a USB2
 992 * protocol port after transitioning to
 993 * Resume], software shall write a ``0'' (U0)
 994 * to the PLS field...'
 995 */
 996 v = xhci_op_read_4(sc, port);
 997 v &= ~(XHCI_PS_PLS_MASK | XHCI_PS_CLEAR);
 998 v |= XHCI_PS_LWS | XHCI_PS_PLS_SET(XHCI_PS_PLS_SETU0);
 999 xhci_op_write_4(sc, port, v);
 1000
 1001 for (j = 0; j < XHCI_WAIT_PLS_U0; j++) {
 1002 v = xhci_op_read_4(sc, port);
 1003 if (XHCI_PS_PLS_GET(v) == XHCI_PS_PLS_U0)
 1004 break;
 1005 usb_delay_ms(&sc->sc_bus, 1);
 1006 }
 1007 if (j == XHCI_WAIT_PLS_U0) {
 1008 device_printf(self,
 1009 "resume timeout on bus %zu port %zu\n",
 1010 bn, i);
 1011 return false;
 1012 }
 1013 }
 1014 }
 1015
 1016 /*
 1017 * `10. Restart each of the previously Running endpoints by
 1018 * ringing their doorbells.'
 1019 */
 1020 for (i = 0; i < sc->sc_maxslots; i++) {
 1021 struct xhci_slot *xs = &sc->sc_slots[i];
 1022
 1023 /* Skip if the slot is not in use. */
 1024 if (xs->xs_idx == 0)
 1025 continue;
 1026
 1027 for (dci = XHCI_DCI_SLOT; dci <= XHCI_MAX_DCI; dci++) {
 1028 /* Skip if the endpoint is not Running. */
 1029 if (xhci_get_epstate(sc, xs, dci) !=
 1030 XHCI_EPSTATE_RUNNING)
 1031 continue;
 1032
 1033 /* Ring the doorbell. */
 1034 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci);
 1035 }
 1036 }
 1037
 1038 /*
 1039 * `Note: After a Save or Restore operation completes, the
 1040 * Save/Restore Error (SRE) flag in the USBSTS register should
 1041 * be checked to ensure that the operation completed
 1042 * successfully.'
 1043 */
 1044 if (xhci_op_read_4(sc, XHCI_USBSTS) & XHCI_STS_SRE) {
 1045 device_printf(self, "resume error, USBSTS.SRE\n");
 1046 return false;
 1047 }
 1048
 1049 return true;
710} 1050}
711 1051
712bool 1052bool
713xhci_shutdown(device_t self, int flags) 1053xhci_shutdown(device_t self, int flags)
714{ 1054{
715 return false; 1055 return false;
716} 1056}
717 1057
718static int 1058static int
719xhci_hc_reset(struct xhci_softc * const sc) 1059xhci_hc_reset(struct xhci_softc * const sc)
720{ 1060{
721 uint32_t usbcmd, usbsts; 1061 uint32_t usbcmd, usbsts;
722 int i; 1062 int i;
723 1063
724 /* Check controller not ready */ 1064 /* Check controller not ready */
725 for (i = 0; i < XHCI_WAIT_CNR; i++) { 1065 for (i = 0; i < XHCI_WAIT_CNR; i++) {
726 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1066 usbsts = xhci_op_read_4(sc, XHCI_USBSTS);
727 if ((usbsts & XHCI_STS_CNR) == 0) 1067 if ((usbsts & XHCI_STS_CNR) == 0)
728 break; 1068 break;
729 usb_delay_ms(&sc->sc_bus, 1); 1069 usb_delay_ms(&sc->sc_bus, 1);
730 } 1070 }
731 if (i >= XHCI_WAIT_CNR) { 1071 if (i >= XHCI_WAIT_CNR) {
732 aprint_error_dev(sc->sc_dev, "controller not ready timeout\n"); 1072 aprint_error_dev(sc->sc_dev, "controller not ready timeout\n");
733 return EIO; 1073 return EIO;
734 } 1074 }
735 1075
736 /* Halt controller */ 1076 /* Halt controller */
737 usbcmd = 0; 1077 usbcmd = 0;
738 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 1078 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd);
739 usb_delay_ms(&sc->sc_bus, 1); 1079 usb_delay_ms(&sc->sc_bus, 1);
740 1080
741 /* Reset controller */ 1081 /* Reset controller */
742 usbcmd = XHCI_CMD_HCRST; 1082 usbcmd = XHCI_CMD_HCRST;
743 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 1083 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd);
744 for (i = 0; i < XHCI_WAIT_HCRST; i++) { 1084 for (i = 0; i < XHCI_WAIT_HCRST; i++) {
745 /* 1085 /*
746 * Wait 1ms first. Existing Intel xHCI requies 1ms delay to 1086 * Wait 1ms first. Existing Intel xHCI requies 1ms delay to
747 * prevent system hang (Errata). 1087 * prevent system hang (Errata).
748 */ 1088 */
749 usb_delay_ms(&sc->sc_bus, 1); 1089 usb_delay_ms(&sc->sc_bus, 1);
750 usbcmd = xhci_op_read_4(sc, XHCI_USBCMD); 1090 usbcmd = xhci_op_read_4(sc, XHCI_USBCMD);
751 if ((usbcmd & XHCI_CMD_HCRST) == 0) 1091 if ((usbcmd & XHCI_CMD_HCRST) == 0)
752 break; 1092 break;
753 } 1093 }
754 if (i >= XHCI_WAIT_HCRST) { 1094 if (i >= XHCI_WAIT_HCRST) {
755 aprint_error_dev(sc->sc_dev, "host controller reset timeout\n"); 1095 aprint_error_dev(sc->sc_dev, "host controller reset timeout\n");
756 return EIO; 1096 return EIO;
757 } 1097 }
758 1098
759 /* Check controller not ready */ 1099 /* Check controller not ready */
760 for (i = 0; i < XHCI_WAIT_CNR; i++) { 1100 for (i = 0; i < XHCI_WAIT_CNR; i++) {
761 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1101 usbsts = xhci_op_read_4(sc, XHCI_USBSTS);
762 if ((usbsts & XHCI_STS_CNR) == 0) 1102 if ((usbsts & XHCI_STS_CNR) == 0)
763 break; 1103 break;
764 usb_delay_ms(&sc->sc_bus, 1); 1104 usb_delay_ms(&sc->sc_bus, 1);
765 } 1105 }
766 if (i >= XHCI_WAIT_CNR) { 1106 if (i >= XHCI_WAIT_CNR) {
767 aprint_error_dev(sc->sc_dev, 1107 aprint_error_dev(sc->sc_dev,
768 "controller not ready timeout after reset\n"); 1108 "controller not ready timeout after reset\n");
769 return EIO; 1109 return EIO;
770 } 1110 }
771 1111
772 return 0; 1112 return 0;
773} 1113}
774 1114
775 
776/* 7.2 xHCI Support Protocol Capability */ 1115/* 7.2 xHCI Support Protocol Capability */
777static void 1116static void
778xhci_id_protocols(struct xhci_softc *sc, bus_size_t ecp) 1117xhci_id_protocols(struct xhci_softc *sc, bus_size_t ecp)
779{ 1118{
780 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1119 XHCIHIST_FUNC(); XHCIHIST_CALLED();
781 1120
782 /* XXX Cache this lot */ 1121 /* XXX Cache this lot */
783 1122
784 const uint32_t w0 = xhci_read_4(sc, ecp); 1123 const uint32_t w0 = xhci_read_4(sc, ecp);
785 const uint32_t w4 = xhci_read_4(sc, ecp + 4); 1124 const uint32_t w4 = xhci_read_4(sc, ecp + 4);
786 const uint32_t w8 = xhci_read_4(sc, ecp + 8); 1125 const uint32_t w8 = xhci_read_4(sc, ecp + 8);
787 const uint32_t wc = xhci_read_4(sc, ecp + 0xc); 1126 const uint32_t wc = xhci_read_4(sc, ecp + 0xc);
788 1127
789 aprint_debug_dev(sc->sc_dev, 1128 aprint_debug_dev(sc->sc_dev,
790 " SP: 0x%08x 0x%08x 0x%08x 0x%08x\n", w0, w4, w8, wc); 1129 " SP: 0x%08x 0x%08x 0x%08x 0x%08x\n", w0, w4, w8, wc);
791 1130
792 if (w4 != XHCI_XECP_USBID) 1131 if (w4 != XHCI_XECP_USBID)
793 return; 1132 return;
794 1133
795 const int major = XHCI_XECP_SP_W0_MAJOR(w0); 1134 const int major = XHCI_XECP_SP_W0_MAJOR(w0);
796 const int minor = XHCI_XECP_SP_W0_MINOR(w0); 1135 const int minor = XHCI_XECP_SP_W0_MINOR(w0);
797 const uint8_t cpo = XHCI_XECP_SP_W8_CPO(w8); 1136 const uint8_t cpo = XHCI_XECP_SP_W8_CPO(w8);
798 const uint8_t cpc = XHCI_XECP_SP_W8_CPC(w8); 1137 const uint8_t cpc = XHCI_XECP_SP_W8_CPC(w8);
799 1138
800 const uint16_t mm = __SHIFTOUT(w0, __BITS(31, 16)); 1139 const uint16_t mm = __SHIFTOUT(w0, __BITS(31, 16));
801 switch (mm) { 1140 switch (mm) {
802 case 0x0200: 1141 case 0x0200:
803 case 0x0300: 1142 case 0x0300:
804 case 0x0301: 1143 case 0x0301:
805 case 0x0310: 1144 case 0x0310:
806 aprint_debug_dev(sc->sc_dev, " %s ports %d - %d\n", 1145 aprint_debug_dev(sc->sc_dev, " %s ports %d - %d\n",
807 major == 3 ? "ss" : "hs", cpo, cpo + cpc -1); 1146 major == 3 ? "ss" : "hs", cpo, cpo + cpc -1);
808 break; 1147 break;
809 default: 1148 default:
810 aprint_error_dev(sc->sc_dev, " unknown major/minor (%d/%d)\n", 1149 aprint_error_dev(sc->sc_dev, " unknown major/minor (%d/%d)\n",
811 major, minor); 1150 major, minor);
812 return; 1151 return;
813 } 1152 }
814 1153
815 const size_t bus = (major == 3) ? 0 : 1; 1154 const size_t bus = (major == 3) ? 0 : 1;
816 1155
817 /* Index arrays with 0..n-1 where ports are numbered 1..n */ 1156 /* Index arrays with 0..n-1 where ports are numbered 1..n */
818 for (size_t cp = cpo - 1; cp < cpo + cpc - 1; cp++) { 1157 for (size_t cp = cpo - 1; cp < cpo + cpc - 1; cp++) {
819 if (sc->sc_ctlrportmap[cp] != 0) { 1158 if (sc->sc_ctlrportmap[cp] != 0) {
820 aprint_error_dev(sc->sc_dev, "controller port %zu " 1159 aprint_error_dev(sc->sc_dev, "controller port %zu "
821 "already assigned", cp); 1160 "already assigned", cp);
822 continue; 1161 continue;
823 } 1162 }
824 1163
825 sc->sc_ctlrportbus[cp / NBBY] |= 1164 sc->sc_ctlrportbus[cp / NBBY] |=
826 bus == 0 ? 0 : __BIT(cp % NBBY); 1165 bus == 0 ? 0 : __BIT(cp % NBBY);
827 1166
828 const size_t rhp = sc->sc_rhportcount[bus]++; 1167 const size_t rhp = sc->sc_rhportcount[bus]++;
829 1168
830 KASSERTMSG(sc->sc_rhportmap[bus][rhp] == 0, 1169 KASSERTMSG(sc->sc_rhportmap[bus][rhp] == 0,
831 "bus %zu rhp %zu is %d", bus, rhp, 1170 "bus %zu rhp %zu is %d", bus, rhp,
832 sc->sc_rhportmap[bus][rhp]); 1171 sc->sc_rhportmap[bus][rhp]);
833 1172
834 sc->sc_rhportmap[bus][rhp] = cp + 1; 1173 sc->sc_rhportmap[bus][rhp] = cp + 1;
835 sc->sc_ctlrportmap[cp] = rhp + 1; 1174 sc->sc_ctlrportmap[cp] = rhp + 1;
836 } 1175 }
837} 1176}
838 1177
839/* Process extended capabilities */ 1178/* Process extended capabilities */
840static void 1179static void
841xhci_ecp(struct xhci_softc *sc) 1180xhci_ecp(struct xhci_softc *sc)
842{ 1181{
843 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1182 XHCIHIST_FUNC(); XHCIHIST_CALLED();
844 1183
845 bus_size_t ecp = XHCI_HCC_XECP(sc->sc_hcc) * 4; 1184 bus_size_t ecp = XHCI_HCC_XECP(sc->sc_hcc) * 4;
846 while (ecp != 0) { 1185 while (ecp != 0) {
847 uint32_t ecr = xhci_read_4(sc, ecp); 1186 uint32_t ecr = xhci_read_4(sc, ecp);
848 aprint_debug_dev(sc->sc_dev, "ECR: 0x%08x\n", ecr); 1187 aprint_debug_dev(sc->sc_dev, "ECR: 0x%08x\n", ecr);
849 switch (XHCI_XECP_ID(ecr)) { 1188 switch (XHCI_XECP_ID(ecr)) {
850 case XHCI_ID_PROTOCOLS: { 1189 case XHCI_ID_PROTOCOLS: {
851 xhci_id_protocols(sc, ecp); 1190 xhci_id_protocols(sc, ecp);
852 break; 1191 break;
853 } 1192 }
854 case XHCI_ID_USB_LEGACY: { 1193 case XHCI_ID_USB_LEGACY: {
855 uint8_t bios_sem; 1194 uint8_t bios_sem;
856 1195
857 /* Take host controller ownership from BIOS */ 1196 /* Take host controller ownership from BIOS */
858 bios_sem = xhci_read_1(sc, ecp + XHCI_XECP_BIOS_SEM); 1197 bios_sem = xhci_read_1(sc, ecp + XHCI_XECP_BIOS_SEM);
859 if (bios_sem) { 1198 if (bios_sem) {
860 /* sets xHCI to be owned by OS */ 1199 /* sets xHCI to be owned by OS */
861 xhci_write_1(sc, ecp + XHCI_XECP_OS_SEM, 1); 1200 xhci_write_1(sc, ecp + XHCI_XECP_OS_SEM, 1);
862 aprint_debug_dev(sc->sc_dev, 1201 aprint_debug_dev(sc->sc_dev,
863 "waiting for BIOS to give up control\n"); 1202 "waiting for BIOS to give up control\n");
864 for (int i = 0; i < 5000; i++) { 1203 for (int i = 0; i < 5000; i++) {
865 bios_sem = xhci_read_1(sc, ecp + 1204 bios_sem = xhci_read_1(sc, ecp +
866 XHCI_XECP_BIOS_SEM); 1205 XHCI_XECP_BIOS_SEM);
867 if (bios_sem == 0) 1206 if (bios_sem == 0)
868 break; 1207 break;
869 DELAY(1000); 1208 DELAY(1000);
870 } 1209 }
871 if (bios_sem) { 1210 if (bios_sem) {
872 aprint_error_dev(sc->sc_dev, 1211 aprint_error_dev(sc->sc_dev,
873 "timed out waiting for BIOS\n"); 1212 "timed out waiting for BIOS\n");
874 } 1213 }
875 } 1214 }
876 break; 1215 break;
877 } 1216 }
878 default: 1217 default:
879 break; 1218 break;
880 } 1219 }
881 ecr = xhci_read_4(sc, ecp); 1220 ecr = xhci_read_4(sc, ecp);
882 if (XHCI_XECP_NEXT(ecr) == 0) { 1221 if (XHCI_XECP_NEXT(ecr) == 0) {
883 ecp = 0; 1222 ecp = 0;
884 } else { 1223 } else {
885 ecp += XHCI_XECP_NEXT(ecr) * 4; 1224 ecp += XHCI_XECP_NEXT(ecr) * 4;
886 } 1225 }
887 } 1226 }
888} 1227}
889 1228
890#define XHCI_HCCPREV1_BITS \ 1229#define XHCI_HCCPREV1_BITS \
891 "\177\020" /* New bitmask */ \ 1230 "\177\020" /* New bitmask */ \
892 "f\020\020XECP\0" \ 1231 "f\020\020XECP\0" \
893 "f\014\4MAXPSA\0" \ 1232 "f\014\4MAXPSA\0" \
894 "b\013CFC\0" \ 1233 "b\013CFC\0" \
895 "b\012SEC\0" \ 1234 "b\012SEC\0" \
896 "b\011SBD\0" \ 1235 "b\011SBD\0" \
897 "b\010FSE\0" \ 1236 "b\010FSE\0" \
898 "b\7NSS\0" \ 1237 "b\7NSS\0" \
899 "b\6LTC\0" \ 1238 "b\6LTC\0" \
900 "b\5LHRC\0" \ 1239 "b\5LHRC\0" \
901 "b\4PIND\0" \ 1240 "b\4PIND\0" \
902 "b\3PPC\0" \ 1241 "b\3PPC\0" \
903 "b\2CZC\0" \ 1242 "b\2CZC\0" \
904 "b\1BNC\0" \ 1243 "b\1BNC\0" \
905 "b\0AC64\0" \ 1244 "b\0AC64\0" \
906 "\0" 1245 "\0"
907#define XHCI_HCCV1_x_BITS \ 1246#define XHCI_HCCV1_x_BITS \
908 "\177\020" /* New bitmask */ \ 1247 "\177\020" /* New bitmask */ \
909 "f\020\020XECP\0" \ 1248 "f\020\020XECP\0" \
910 "f\014\4MAXPSA\0" \ 1249 "f\014\4MAXPSA\0" \
911 "b\013CFC\0" \ 1250 "b\013CFC\0" \
912 "b\012SEC\0" \ 1251 "b\012SEC\0" \
913 "b\011SPC\0" \ 1252 "b\011SPC\0" \
914 "b\010PAE\0" \ 1253 "b\010PAE\0" \
915 "b\7NSS\0" \ 1254 "b\7NSS\0" \
916 "b\6LTC\0" \ 1255 "b\6LTC\0" \
917 "b\5LHRC\0" \ 1256 "b\5LHRC\0" \
918 "b\4PIND\0" \ 1257 "b\4PIND\0" \
919 "b\3PPC\0" \ 1258 "b\3PPC\0" \
920 "b\2CSZ\0" \ 1259 "b\2CSZ\0" \
921 "b\1BNC\0" \ 1260 "b\1BNC\0" \
922 "b\0AC64\0" \ 1261 "b\0AC64\0" \
923 "\0" 1262 "\0"
924 1263
925#define XHCI_HCC2_BITS \ 1264#define XHCI_HCC2_BITS \
926 "\177\020" /* New bitmask */ \ 1265 "\177\020" /* New bitmask */ \
927 "b\7ETC_TSC\0" \ 1266 "b\7ETC_TSC\0" \
928 "b\6ETC\0" \ 1267 "b\6ETC\0" \
929 "b\5CIC\0" \ 1268 "b\5CIC\0" \
930 "b\4LEC\0" \ 1269 "b\4LEC\0" \
931 "b\3CTC\0" \ 1270 "b\3CTC\0" \
932 "b\2FSC\0" \ 1271 "b\2FSC\0" \
933 "b\1CMC\0" \ 1272 "b\1CMC\0" \
934 "b\0U3C\0" \ 1273 "b\0U3C\0" \
935 "\0" 1274 "\0"
936 1275
937void 1276void
938xhci_start(struct xhci_softc *sc) 1277xhci_start(struct xhci_softc *sc)
939{ 1278{
940 xhci_rt_write_4(sc, XHCI_IMAN(0), XHCI_IMAN_INTR_ENA); 1279 xhci_rt_write_4(sc, XHCI_IMAN(0), XHCI_IMAN_INTR_ENA);
941 if ((sc->sc_quirks & XHCI_QUIRK_INTEL) != 0) 1280 if ((sc->sc_quirks & XHCI_QUIRK_INTEL) != 0)
942 /* Intel xhci needs interrupt rate moderated. */ 1281 /* Intel xhci needs interrupt rate moderated. */
943 xhci_rt_write_4(sc, XHCI_IMOD(0), XHCI_IMOD_DEFAULT_LP); 1282 xhci_rt_write_4(sc, XHCI_IMOD(0), XHCI_IMOD_DEFAULT_LP);
944 else 1283 else
945 xhci_rt_write_4(sc, XHCI_IMOD(0), 0); 1284 xhci_rt_write_4(sc, XHCI_IMOD(0), 0);
946 aprint_debug_dev(sc->sc_dev, "current IMOD %u\n", 1285 aprint_debug_dev(sc->sc_dev, "current IMOD %u\n",
947 xhci_rt_read_4(sc, XHCI_IMOD(0))); 1286 xhci_rt_read_4(sc, XHCI_IMOD(0)));
948 1287
949 /* Go! */ 1288 /* Go! */
950 xhci_op_write_4(sc, XHCI_USBCMD, XHCI_CMD_INTE|XHCI_CMD_RS); 1289 xhci_op_write_4(sc, XHCI_USBCMD, XHCI_CMD_INTE|XHCI_CMD_RS);
951 aprint_debug_dev(sc->sc_dev, "USBCMD 0x%08"PRIx32"\n", 1290 aprint_debug_dev(sc->sc_dev, "USBCMD 0x%08"PRIx32"\n",
952 xhci_op_read_4(sc, XHCI_USBCMD)); 1291 xhci_op_read_4(sc, XHCI_USBCMD));
953} 1292}
954 1293
955int 1294int
956xhci_init(struct xhci_softc *sc) 1295xhci_init(struct xhci_softc *sc)
957{ 1296{
958 bus_size_t bsz; 1297 bus_size_t bsz;
959 uint32_t hcs1, hcs2, hcs3, dboff, rtsoff; 1298 uint32_t hcs1, hcs2, hcs3, dboff, rtsoff;
960 uint32_t pagesize, config; 1299 uint32_t pagesize, config;
961 int i = 0; 1300 int i = 0;
962 uint16_t hciversion; 1301 uint16_t hciversion;
963 uint8_t caplength; 1302 uint8_t caplength;
964 1303
965 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1304 XHCIHIST_FUNC(); XHCIHIST_CALLED();
966 1305
967 /* Set up the bus struct for the usb 3 and usb 2 buses */ 1306 /* Set up the bus struct for the usb 3 and usb 2 buses */
968 sc->sc_bus.ub_methods = &xhci_bus_methods; 1307 sc->sc_bus.ub_methods = &xhci_bus_methods;
969 sc->sc_bus.ub_pipesize = sizeof(struct xhci_pipe); 1308 sc->sc_bus.ub_pipesize = sizeof(struct xhci_pipe);
970 sc->sc_bus.ub_usedma = true; 1309 sc->sc_bus.ub_usedma = true;
971 sc->sc_bus.ub_hcpriv = sc; 1310 sc->sc_bus.ub_hcpriv = sc;
972 1311
973 sc->sc_bus2.ub_methods = &xhci_bus_methods; 1312 sc->sc_bus2.ub_methods = &xhci_bus_methods;
974 sc->sc_bus2.ub_pipesize = sizeof(struct xhci_pipe); 1313 sc->sc_bus2.ub_pipesize = sizeof(struct xhci_pipe);
975 sc->sc_bus2.ub_revision = USBREV_2_0; 1314 sc->sc_bus2.ub_revision = USBREV_2_0;
976 sc->sc_bus2.ub_usedma = true; 1315 sc->sc_bus2.ub_usedma = true;
977 sc->sc_bus2.ub_hcpriv = sc; 1316 sc->sc_bus2.ub_hcpriv = sc;
978 sc->sc_bus2.ub_dmatag = sc->sc_bus.ub_dmatag; 1317 sc->sc_bus2.ub_dmatag = sc->sc_bus.ub_dmatag;
979 1318
980 caplength = xhci_read_1(sc, XHCI_CAPLENGTH); 1319 caplength = xhci_read_1(sc, XHCI_CAPLENGTH);
981 hciversion = xhci_read_2(sc, XHCI_HCIVERSION); 1320 hciversion = xhci_read_2(sc, XHCI_HCIVERSION);
982 1321
983 if (hciversion < XHCI_HCIVERSION_0_96 || 1322 if (hciversion < XHCI_HCIVERSION_0_96 ||
984 hciversion >= 0x0200) { 1323 hciversion >= 0x0200) {
985 aprint_normal_dev(sc->sc_dev, 1324 aprint_normal_dev(sc->sc_dev,
986 "xHCI version %x.%x not known to be supported\n", 1325 "xHCI version %x.%x not known to be supported\n",
987 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 1326 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff);
988 } else { 1327 } else {
989 aprint_verbose_dev(sc->sc_dev, "xHCI version %x.%x\n", 1328 aprint_verbose_dev(sc->sc_dev, "xHCI version %x.%x\n",
990 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 1329 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff);
991 } 1330 }
992 1331
993 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 0, caplength, 1332 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 0, caplength,
994 &sc->sc_cbh) != 0) { 1333 &sc->sc_cbh) != 0) {
995 aprint_error_dev(sc->sc_dev, "capability subregion failure\n"); 1334 aprint_error_dev(sc->sc_dev, "capability subregion failure\n");
996 return ENOMEM; 1335 return ENOMEM;
997 } 1336 }
998 1337
999 hcs1 = xhci_cap_read_4(sc, XHCI_HCSPARAMS1); 1338 hcs1 = xhci_cap_read_4(sc, XHCI_HCSPARAMS1);
1000 sc->sc_maxslots = XHCI_HCS1_MAXSLOTS(hcs1); 1339 sc->sc_maxslots = XHCI_HCS1_MAXSLOTS(hcs1);
1001 sc->sc_maxintrs = XHCI_HCS1_MAXINTRS(hcs1); 1340 sc->sc_maxintrs = XHCI_HCS1_MAXINTRS(hcs1);
1002 sc->sc_maxports = XHCI_HCS1_MAXPORTS(hcs1); 1341 sc->sc_maxports = XHCI_HCS1_MAXPORTS(hcs1);
1003 hcs2 = xhci_cap_read_4(sc, XHCI_HCSPARAMS2); 1342 hcs2 = xhci_cap_read_4(sc, XHCI_HCSPARAMS2);
1004 hcs3 = xhci_cap_read_4(sc, XHCI_HCSPARAMS3); 1343 hcs3 = xhci_cap_read_4(sc, XHCI_HCSPARAMS3);
1005 aprint_debug_dev(sc->sc_dev, 1344 aprint_debug_dev(sc->sc_dev,
1006 "hcs1=%"PRIx32" hcs2=%"PRIx32" hcs3=%"PRIx32"\n", hcs1, hcs2, hcs3); 1345 "hcs1=%"PRIx32" hcs2=%"PRIx32" hcs3=%"PRIx32"\n", hcs1, hcs2, hcs3);
1007 1346
1008 sc->sc_hcc = xhci_cap_read_4(sc, XHCI_HCCPARAMS); 1347 sc->sc_hcc = xhci_cap_read_4(sc, XHCI_HCCPARAMS);
1009 sc->sc_ctxsz = XHCI_HCC_CSZ(sc->sc_hcc) ? 64 : 32; 1348 sc->sc_ctxsz = XHCI_HCC_CSZ(sc->sc_hcc) ? 64 : 32;
1010 1349
1011 char sbuf[128]; 1350 char sbuf[128];
1012 if (hciversion < XHCI_HCIVERSION_1_0) 1351 if (hciversion < XHCI_HCIVERSION_1_0)
1013 snprintb(sbuf, sizeof(sbuf), XHCI_HCCPREV1_BITS, sc->sc_hcc); 1352 snprintb(sbuf, sizeof(sbuf), XHCI_HCCPREV1_BITS, sc->sc_hcc);
1014 else 1353 else
1015 snprintb(sbuf, sizeof(sbuf), XHCI_HCCV1_x_BITS, sc->sc_hcc); 1354 snprintb(sbuf, sizeof(sbuf), XHCI_HCCV1_x_BITS, sc->sc_hcc);
1016 aprint_debug_dev(sc->sc_dev, "hcc=%s\n", sbuf); 1355 aprint_debug_dev(sc->sc_dev, "hcc=%s\n", sbuf);
1017 aprint_debug_dev(sc->sc_dev, "xECP %" __PRIxBITS "\n", 1356 aprint_debug_dev(sc->sc_dev, "xECP %" __PRIxBITS "\n",
1018 XHCI_HCC_XECP(sc->sc_hcc) * 4); 1357 XHCI_HCC_XECP(sc->sc_hcc) * 4);
1019 if (hciversion >= XHCI_HCIVERSION_1_1) { 1358 if (hciversion >= XHCI_HCIVERSION_1_1) {
1020 sc->sc_hcc2 = xhci_cap_read_4(sc, XHCI_HCCPARAMS2); 1359 sc->sc_hcc2 = xhci_cap_read_4(sc, XHCI_HCCPARAMS2);
1021 snprintb(sbuf, sizeof(sbuf), XHCI_HCC2_BITS, sc->sc_hcc2); 1360 snprintb(sbuf, sizeof(sbuf), XHCI_HCC2_BITS, sc->sc_hcc2);
1022 aprint_debug_dev(sc->sc_dev, "hcc2=%s\n", sbuf); 1361 aprint_debug_dev(sc->sc_dev, "hcc2=%s\n", sbuf);
1023 } 1362 }
1024 1363
1025 /* default all ports to bus 0, i.e. usb 3 */ 1364 /* default all ports to bus 0, i.e. usb 3 */
1026 sc->sc_ctlrportbus = kmem_zalloc( 1365 sc->sc_ctlrportbus = kmem_zalloc(
1027 howmany(sc->sc_maxports * sizeof(uint8_t), NBBY), KM_SLEEP); 1366 howmany(sc->sc_maxports * sizeof(uint8_t), NBBY), KM_SLEEP);
1028 sc->sc_ctlrportmap = kmem_zalloc(sc->sc_maxports * sizeof(int), KM_SLEEP); 1367 sc->sc_ctlrportmap = kmem_zalloc(sc->sc_maxports * sizeof(int), KM_SLEEP);
1029 1368
1030 /* controller port to bus roothub port map */ 1369 /* controller port to bus roothub port map */
1031 for (size_t j = 0; j < __arraycount(sc->sc_rhportmap); j++) { 1370 for (size_t j = 0; j < __arraycount(sc->sc_rhportmap); j++) {
1032 sc->sc_rhportmap[j] = kmem_zalloc(sc->sc_maxports * sizeof(int), KM_SLEEP); 1371 sc->sc_rhportmap[j] = kmem_zalloc(sc->sc_maxports * sizeof(int), KM_SLEEP);
1033 } 1372 }
1034 1373
1035 /* 1374 /*
1036 * Process all Extended Capabilities 1375 * Process all Extended Capabilities
1037 */ 1376 */
1038 xhci_ecp(sc); 1377 xhci_ecp(sc);
1039 1378
1040 bsz = XHCI_PORTSC(sc->sc_maxports); 1379 bsz = XHCI_PORTSC(sc->sc_maxports);
1041 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, caplength, bsz, 1380 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, caplength, bsz,
1042 &sc->sc_obh) != 0) { 1381 &sc->sc_obh) != 0) {
1043 aprint_error_dev(sc->sc_dev, "operational subregion failure\n"); 1382 aprint_error_dev(sc->sc_dev, "operational subregion failure\n");
1044 return ENOMEM; 1383 return ENOMEM;
1045 } 1384 }
1046 1385
1047 dboff = xhci_cap_read_4(sc, XHCI_DBOFF); 1386 dboff = xhci_cap_read_4(sc, XHCI_DBOFF);
1048 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, dboff, 1387 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, dboff,
1049 sc->sc_maxslots * 4, &sc->sc_dbh) != 0) { 1388 sc->sc_maxslots * 4, &sc->sc_dbh) != 0) {
1050 aprint_error_dev(sc->sc_dev, "doorbell subregion failure\n"); 1389 aprint_error_dev(sc->sc_dev, "doorbell subregion failure\n");
1051 return ENOMEM; 1390 return ENOMEM;
1052 } 1391 }
1053 1392
1054 rtsoff = xhci_cap_read_4(sc, XHCI_RTSOFF); 1393 rtsoff = xhci_cap_read_4(sc, XHCI_RTSOFF);
1055 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, rtsoff, 1394 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, rtsoff,
1056 sc->sc_maxintrs * 0x20, &sc->sc_rbh) != 0) { 1395 sc->sc_maxintrs * 0x20, &sc->sc_rbh) != 0) {
1057 aprint_error_dev(sc->sc_dev, "runtime subregion failure\n"); 1396 aprint_error_dev(sc->sc_dev, "runtime subregion failure\n");
1058 return ENOMEM; 1397 return ENOMEM;
1059 } 1398 }
1060 1399
1061 int rv; 1400 int rv;
1062 rv = xhci_hc_reset(sc); 1401 rv = xhci_hc_reset(sc);
1063 if (rv != 0) { 1402 if (rv != 0) {
1064 return rv; 1403 return rv;
1065 } 1404 }
1066 1405
1067 if (sc->sc_vendor_init) 1406 if (sc->sc_vendor_init)
1068 sc->sc_vendor_init(sc); 1407 sc->sc_vendor_init(sc);
1069 1408
1070 pagesize = xhci_op_read_4(sc, XHCI_PAGESIZE); 1409 pagesize = xhci_op_read_4(sc, XHCI_PAGESIZE);
1071 aprint_debug_dev(sc->sc_dev, "PAGESIZE 0x%08x\n", pagesize); 1410 aprint_debug_dev(sc->sc_dev, "PAGESIZE 0x%08x\n", pagesize);
1072 pagesize = ffs(pagesize); 1411 pagesize = ffs(pagesize);
1073 if (pagesize == 0) { 1412 if (pagesize == 0) {
1074 aprint_error_dev(sc->sc_dev, "pagesize is 0\n"); 1413 aprint_error_dev(sc->sc_dev, "pagesize is 0\n");
1075 return EIO; 1414 return EIO;
1076 } 1415 }
1077 sc->sc_pgsz = 1 << (12 + (pagesize - 1)); 1416 sc->sc_pgsz = 1 << (12 + (pagesize - 1));
1078 aprint_debug_dev(sc->sc_dev, "sc_pgsz 0x%08x\n", (uint32_t)sc->sc_pgsz); 1417 aprint_debug_dev(sc->sc_dev, "sc_pgsz 0x%08x\n", (uint32_t)sc->sc_pgsz);
1079 aprint_debug_dev(sc->sc_dev, "sc_maxslots 0x%08x\n", 1418 aprint_debug_dev(sc->sc_dev, "sc_maxslots 0x%08x\n",
1080 (uint32_t)sc->sc_maxslots); 1419 (uint32_t)sc->sc_maxslots);
1081 aprint_debug_dev(sc->sc_dev, "sc_maxports %d\n", sc->sc_maxports); 1420 aprint_debug_dev(sc->sc_dev, "sc_maxports %d\n", sc->sc_maxports);
1082 1421
1083 int err; 1422 int err;
1084 sc->sc_maxspbuf = XHCI_HCS2_MAXSPBUF(hcs2); 1423 sc->sc_maxspbuf = XHCI_HCS2_MAXSPBUF(hcs2);
1085 aprint_debug_dev(sc->sc_dev, "sc_maxspbuf %d\n", sc->sc_maxspbuf); 1424 aprint_debug_dev(sc->sc_dev, "sc_maxspbuf %d\n", sc->sc_maxspbuf);
1086 if (sc->sc_maxspbuf != 0) { 1425 if (sc->sc_maxspbuf != 0) {
1087 err = usb_allocmem(&sc->sc_bus, 1426 err = usb_allocmem(&sc->sc_bus,
1088 sizeof(uint64_t) * sc->sc_maxspbuf, sizeof(uint64_t), 1427 sizeof(uint64_t) * sc->sc_maxspbuf, sizeof(uint64_t),
1089 USBMALLOC_COHERENT | USBMALLOC_ZERO, 1428 USBMALLOC_COHERENT | USBMALLOC_ZERO,
1090 &sc->sc_spbufarray_dma); 1429 &sc->sc_spbufarray_dma);
1091 if (err) { 1430 if (err) {
1092 aprint_error_dev(sc->sc_dev, 1431 aprint_error_dev(sc->sc_dev,
1093 "spbufarray init fail, err %d\n", err); 1432 "spbufarray init fail, err %d\n", err);
1094 return ENOMEM; 1433 return ENOMEM;
1095 } 1434 }
1096 1435
1097 sc->sc_spbuf_dma = kmem_zalloc(sizeof(*sc->sc_spbuf_dma) * 1436 sc->sc_spbuf_dma = kmem_zalloc(sizeof(*sc->sc_spbuf_dma) *
1098 sc->sc_maxspbuf, KM_SLEEP); 1437 sc->sc_maxspbuf, KM_SLEEP);
1099 uint64_t *spbufarray = KERNADDR(&sc->sc_spbufarray_dma, 0); 1438 uint64_t *spbufarray = KERNADDR(&sc->sc_spbufarray_dma, 0);
1100 for (i = 0; i < sc->sc_maxspbuf; i++) { 1439 for (i = 0; i < sc->sc_maxspbuf; i++) {
1101 usb_dma_t * const dma = &sc->sc_spbuf_dma[i]; 1440 usb_dma_t * const dma = &sc->sc_spbuf_dma[i];
1102 /* allocate contexts */ 1441 /* allocate contexts */
1103 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, 1442 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz,
1104 sc->sc_pgsz, USBMALLOC_COHERENT | USBMALLOC_ZERO, 1443 sc->sc_pgsz, USBMALLOC_COHERENT | USBMALLOC_ZERO,
1105 dma); 1444 dma);
1106 if (err) { 1445 if (err) {
1107 aprint_error_dev(sc->sc_dev, 1446 aprint_error_dev(sc->sc_dev,
1108 "spbufarray_dma init fail, err %d\n", err); 1447 "spbufarray_dma init fail, err %d\n", err);
1109 rv = ENOMEM; 1448 rv = ENOMEM;
1110 goto bad1; 1449 goto bad1;
1111 } 1450 }
1112 spbufarray[i] = htole64(DMAADDR(dma, 0)); 1451 spbufarray[i] = htole64(DMAADDR(dma, 0));
1113 usb_syncmem(dma, 0, sc->sc_pgsz, 1452 usb_syncmem(dma, 0, sc->sc_pgsz,
1114 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1453 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1115 } 1454 }
1116 1455
1117 usb_syncmem(&sc->sc_spbufarray_dma, 0, 1456 usb_syncmem(&sc->sc_spbufarray_dma, 0,
1118 sizeof(uint64_t) * sc->sc_maxspbuf, BUS_DMASYNC_PREWRITE); 1457 sizeof(uint64_t) * sc->sc_maxspbuf, BUS_DMASYNC_PREWRITE);
1119 } 1458 }
1120 1459
1121 config = xhci_op_read_4(sc, XHCI_CONFIG); 1460 config = xhci_op_read_4(sc, XHCI_CONFIG);
1122 config &= ~0xFF; 1461 config &= ~0xFF;
1123 config |= sc->sc_maxslots & 0xFF; 1462 config |= sc->sc_maxslots & 0xFF;
1124 xhci_op_write_4(sc, XHCI_CONFIG, config); 1463 xhci_op_write_4(sc, XHCI_CONFIG, config);
1125 1464
1126 err = xhci_ring_init(sc, &sc->sc_cr, XHCI_COMMAND_RING_TRBS, 1465 err = xhci_ring_init(sc, &sc->sc_cr, XHCI_COMMAND_RING_TRBS,
1127 XHCI_COMMAND_RING_SEGMENTS_ALIGN); 1466 XHCI_COMMAND_RING_SEGMENTS_ALIGN);
1128 if (err) { 1467 if (err) {
1129 aprint_error_dev(sc->sc_dev, "command ring init fail, err %d\n", 1468 aprint_error_dev(sc->sc_dev, "command ring init fail, err %d\n",
1130 err); 1469 err);
1131 rv = ENOMEM; 1470 rv = ENOMEM;
1132 goto bad1; 1471 goto bad1;
1133 } 1472 }
1134 1473
1135 err = xhci_ring_init(sc, &sc->sc_er, XHCI_EVENT_RING_TRBS, 1474 err = xhci_ring_init(sc, &sc->sc_er, XHCI_EVENT_RING_TRBS,
1136 XHCI_EVENT_RING_SEGMENTS_ALIGN); 1475 XHCI_EVENT_RING_SEGMENTS_ALIGN);
1137 if (err) { 1476 if (err) {
1138 aprint_error_dev(sc->sc_dev, "event ring init fail, err %d\n", 1477 aprint_error_dev(sc->sc_dev, "event ring init fail, err %d\n",
1139 err); 1478 err);
1140 rv = ENOMEM; 1479 rv = ENOMEM;
1141 goto bad2; 1480 goto bad2;
1142 } 1481 }
1143 1482
1144 usb_dma_t *dma; 1483 usb_dma_t *dma;
1145 size_t size; 1484 size_t size;
1146 size_t align; 1485 size_t align;
1147 1486
1148 dma = &sc->sc_eventst_dma; 1487 dma = &sc->sc_eventst_dma;
1149 size = roundup2(XHCI_EVENT_RING_SEGMENTS * XHCI_ERSTE_SIZE, 1488 size = roundup2(XHCI_EVENT_RING_SEGMENTS * XHCI_ERSTE_SIZE,
1150 XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN); 1489 XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN);
1151 KASSERTMSG(size <= (512 * 1024), "eventst size %zu too large", size); 1490 KASSERTMSG(size <= (512 * 1024), "eventst size %zu too large", size);
1152 align = XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN; 1491 align = XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN;
1153 err = usb_allocmem(&sc->sc_bus, size, align, 1492 err = usb_allocmem(&sc->sc_bus, size, align,
1154 USBMALLOC_COHERENT | USBMALLOC_ZERO, dma); 1493 USBMALLOC_COHERENT | USBMALLOC_ZERO, dma);
1155 if (err) { 1494 if (err) {
1156 aprint_error_dev(sc->sc_dev, "eventst init fail, err %d\n", 1495 aprint_error_dev(sc->sc_dev, "eventst init fail, err %d\n",
1157 err); 1496 err);
1158 rv = ENOMEM; 1497 rv = ENOMEM;
1159 goto bad3; 1498 goto bad3;
1160 } 1499 }
1161 1500
1162 aprint_debug_dev(sc->sc_dev, "eventst: 0x%016jx %p %zx\n", 1501 aprint_debug_dev(sc->sc_dev, "eventst: 0x%016jx %p %zx\n",
1163 (uintmax_t)DMAADDR(&sc->sc_eventst_dma, 0), 1502 (uintmax_t)DMAADDR(&sc->sc_eventst_dma, 0),
1164 KERNADDR(&sc->sc_eventst_dma, 0), 1503 KERNADDR(&sc->sc_eventst_dma, 0),
1165 sc->sc_eventst_dma.udma_block->size); 1504 sc->sc_eventst_dma.udma_block->size);
1166 1505
1167 dma = &sc->sc_dcbaa_dma; 1506 dma = &sc->sc_dcbaa_dma;
1168 size = (1 + sc->sc_maxslots) * sizeof(uint64_t); 1507 size = (1 + sc->sc_maxslots) * sizeof(uint64_t);
1169 KASSERTMSG(size <= 2048, "dcbaa size %zu too large", size); 1508 KASSERTMSG(size <= 2048, "dcbaa size %zu too large", size);
1170 align = XHCI_DEVICE_CONTEXT_BASE_ADDRESS_ARRAY_ALIGN; 1509 align = XHCI_DEVICE_CONTEXT_BASE_ADDRESS_ARRAY_ALIGN;
1171 err = usb_allocmem(&sc->sc_bus, size, align, 1510 err = usb_allocmem(&sc->sc_bus, size, align,
1172 USBMALLOC_COHERENT | USBMALLOC_ZERO, dma); 1511 USBMALLOC_COHERENT | USBMALLOC_ZERO, dma);
1173 if (err) { 1512 if (err) {
1174 aprint_error_dev(sc->sc_dev, "dcbaa init fail, err %d\n", err); 1513 aprint_error_dev(sc->sc_dev, "dcbaa init fail, err %d\n", err);
1175 rv = ENOMEM; 1514 rv = ENOMEM;
1176 goto bad4; 1515 goto bad4;
1177 } 1516 }
1178 aprint_debug_dev(sc->sc_dev, "dcbaa: 0x%016jx %p %zx\n", 1517 aprint_debug_dev(sc->sc_dev, "dcbaa: 0x%016jx %p %zx\n",
1179 (uintmax_t)DMAADDR(&sc->sc_dcbaa_dma, 0), 1518 (uintmax_t)DMAADDR(&sc->sc_dcbaa_dma, 0),
1180 KERNADDR(&sc->sc_dcbaa_dma, 0), 1519 KERNADDR(&sc->sc_dcbaa_dma, 0),
1181 sc->sc_dcbaa_dma.udma_block->size); 1520 sc->sc_dcbaa_dma.udma_block->size);
1182 1521
1183 if (sc->sc_maxspbuf != 0) { 1522 if (sc->sc_maxspbuf != 0) {
1184 /* 1523 /*
1185 * DCBA entry 0 hold the scratchbuf array pointer. 1524 * DCBA entry 0 hold the scratchbuf array pointer.
1186 */ 1525 */
1187 *(uint64_t *)KERNADDR(dma, 0) = 1526 *(uint64_t *)KERNADDR(dma, 0) =
1188 htole64(DMAADDR(&sc->sc_spbufarray_dma, 0)); 1527 htole64(DMAADDR(&sc->sc_spbufarray_dma, 0));
1189 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 1528 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE);
1190 } 1529 }
1191 1530
1192 sc->sc_slots = kmem_zalloc(sizeof(*sc->sc_slots) * sc->sc_maxslots, 1531 sc->sc_slots = kmem_zalloc(sizeof(*sc->sc_slots) * sc->sc_maxslots,
1193 KM_SLEEP); 1532 KM_SLEEP);
1194 if (sc->sc_slots == NULL) { 1533 if (sc->sc_slots == NULL) {
1195 aprint_error_dev(sc->sc_dev, "slots init fail, err %d\n", err); 1534 aprint_error_dev(sc->sc_dev, "slots init fail, err %d\n", err);
1196 rv = ENOMEM; 1535 rv = ENOMEM;
1197 goto bad; 1536 goto bad;
1198 } 1537 }
1199 1538
1200 sc->sc_xferpool = pool_cache_init(sizeof(struct xhci_xfer), 0, 0, 0, 1539 sc->sc_xferpool = pool_cache_init(sizeof(struct xhci_xfer), 0, 0, 0,
1201 "xhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 1540 "xhcixfer", NULL, IPL_USB, NULL, NULL, NULL);
1202 if (sc->sc_xferpool == NULL) { 1541 if (sc->sc_xferpool == NULL) {
1203 aprint_error_dev(sc->sc_dev, "pool_cache init fail, err %d\n", 1542 aprint_error_dev(sc->sc_dev, "pool_cache init fail, err %d\n",
1204 err); 1543 err);
1205 rv = ENOMEM; 1544 rv = ENOMEM;
1206 goto bad; 1545 goto bad;
1207 } 1546 }
1208 1547
1209 cv_init(&sc->sc_command_cv, "xhcicmd"); 1548 cv_init(&sc->sc_command_cv, "xhcicmd");
1210 cv_init(&sc->sc_cmdbusy_cv, "xhcicmdq"); 1549 cv_init(&sc->sc_cmdbusy_cv, "xhcicmdq");
1211 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 1550 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB);
1212 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 1551 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB);
1213 1552
1214 struct xhci_erste *erst; 1553 struct xhci_erste *erst;
1215 erst = KERNADDR(&sc->sc_eventst_dma, 0); 1554 erst = KERNADDR(&sc->sc_eventst_dma, 0);
1216 erst[0].erste_0 = htole64(xhci_ring_trbp(sc->sc_er, 0)); 1555 erst[0].erste_0 = htole64(xhci_ring_trbp(sc->sc_er, 0));
1217 erst[0].erste_2 = htole32(sc->sc_er->xr_ntrb); 1556 erst[0].erste_2 = htole32(sc->sc_er->xr_ntrb);
1218 erst[0].erste_3 = htole32(0); 1557 erst[0].erste_3 = htole32(0);
1219 usb_syncmem(&sc->sc_eventst_dma, 0, 1558 usb_syncmem(&sc->sc_eventst_dma, 0,
1220 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS, BUS_DMASYNC_PREWRITE); 1559 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS, BUS_DMASYNC_PREWRITE);
1221 1560
1222 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), XHCI_EVENT_RING_SEGMENTS); 1561 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), XHCI_EVENT_RING_SEGMENTS);
1223 xhci_rt_write_8(sc, XHCI_ERSTBA(0), DMAADDR(&sc->sc_eventst_dma, 0)); 1562 xhci_rt_write_8(sc, XHCI_ERSTBA(0), DMAADDR(&sc->sc_eventst_dma, 0));
1224 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(sc->sc_er, 0) | 1563 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(sc->sc_er, 0) |
1225 XHCI_ERDP_BUSY); 1564 XHCI_ERDP_BUSY);
1226 1565
1227 xhci_op_write_8(sc, XHCI_DCBAAP, DMAADDR(&sc->sc_dcbaa_dma, 0)); 1566 xhci_op_write_8(sc, XHCI_DCBAAP, DMAADDR(&sc->sc_dcbaa_dma, 0));
1228 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(sc->sc_cr, 0) | 1567 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(sc->sc_cr, 0) |
1229 sc->sc_cr->xr_cs); 1568 sc->sc_cr->xr_cs);
1230 1569
1231 xhci_barrier(sc, BUS_SPACE_BARRIER_WRITE); 1570 xhci_barrier(sc, BUS_SPACE_BARRIER_WRITE);
1232 1571
1233 HEXDUMP("eventst", KERNADDR(&sc->sc_eventst_dma, 0), 1572 HEXDUMP("eventst", KERNADDR(&sc->sc_eventst_dma, 0),
1234 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS); 1573 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS);
1235 1574
1236 if ((sc->sc_quirks & XHCI_DEFERRED_START) == 0) 1575 if ((sc->sc_quirks & XHCI_DEFERRED_START) == 0)
1237 xhci_start(sc); 1576 xhci_start(sc);
1238 1577
1239 return 0; 1578 return 0;
1240 1579
1241 bad: 1580 bad:
1242 if (sc->sc_xferpool) { 1581 if (sc->sc_xferpool) {
1243 pool_cache_destroy(sc->sc_xferpool); 1582 pool_cache_destroy(sc->sc_xferpool);
1244 sc->sc_xferpool = NULL; 1583 sc->sc_xferpool = NULL;
1245 } 1584 }
1246 1585
1247 if (sc->sc_slots) { 1586 if (sc->sc_slots) {
1248 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * 1587 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) *
1249 sc->sc_maxslots); 1588 sc->sc_maxslots);
1250 sc->sc_slots = NULL; 1589 sc->sc_slots = NULL;
1251 } 1590 }
1252 1591
1253 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 1592 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma);
1254 bad4: 1593 bad4:
1255 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 1594 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma);
1256 bad3: 1595 bad3:
1257 xhci_ring_free(sc, &sc->sc_er); 1596 xhci_ring_free(sc, &sc->sc_er);
1258 bad2: 1597 bad2:
1259 xhci_ring_free(sc, &sc->sc_cr); 1598 xhci_ring_free(sc, &sc->sc_cr);
1260 i = sc->sc_maxspbuf; 1599 i = sc->sc_maxspbuf;
1261 bad1: 1600 bad1:
1262 for (int j = 0; j < i; j++) 1601 for (int j = 0; j < i; j++)
1263 usb_freemem(&sc->sc_bus, &sc->sc_spbuf_dma[j]); 1602 usb_freemem(&sc->sc_bus, &sc->sc_spbuf_dma[j]);
1264 usb_freemem(&sc->sc_bus, &sc->sc_spbufarray_dma); 1603 usb_freemem(&sc->sc_bus, &sc->sc_spbufarray_dma);
1265 1604
1266 return rv; 1605 return rv;
1267} 1606}
1268 1607
1269static inline bool 1608static inline bool
1270xhci_polling_p(struct xhci_softc * const sc) 1609xhci_polling_p(struct xhci_softc * const sc)
1271{ 1610{
1272 return sc->sc_bus.ub_usepolling || sc->sc_bus2.ub_usepolling; 1611 return sc->sc_bus.ub_usepolling || sc->sc_bus2.ub_usepolling;
1273} 1612}
1274 1613
1275int 1614int
1276xhci_intr(void *v) 1615xhci_intr(void *v)
1277{ 1616{
1278 struct xhci_softc * const sc = v; 1617 struct xhci_softc * const sc = v;
1279 int ret = 0; 1618 int ret = 0;
1280 1619
1281 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1620 XHCIHIST_FUNC(); XHCIHIST_CALLED();
1282 1621
1283 if (sc == NULL) 1622 if (sc == NULL)
1284 return 0; 1623 return 0;
1285 1624
1286 mutex_spin_enter(&sc->sc_intr_lock); 1625 mutex_spin_enter(&sc->sc_intr_lock);
1287 1626
1288 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1627 if (sc->sc_dying || !device_has_power(sc->sc_dev))
1289 goto done; 1628 goto done;
1290 1629
1291 /* If we get an interrupt while polling, then just ignore it. */ 1630 /* If we get an interrupt while polling, then just ignore it. */
1292 if (xhci_polling_p(sc)) { 1631 if (xhci_polling_p(sc)) {
1293#ifdef DIAGNOSTIC 1632#ifdef DIAGNOSTIC
1294 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1633 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0);
1295#endif 1634#endif
1296 goto done; 1635 goto done;
1297 } 1636 }
1298 1637
1299 ret = xhci_intr1(sc); 1638 ret = xhci_intr1(sc);
1300 if (ret) { 1639 if (ret) {
1301 KASSERT(sc->sc_child || sc->sc_child2); 1640 KASSERT(sc->sc_child || sc->sc_child2);
1302 1641
1303 /* 1642 /*
1304 * One of child busses could be already detached. It doesn't 1643 * One of child busses could be already detached. It doesn't
1305 * matter on which of the two the softintr is scheduled. 1644 * matter on which of the two the softintr is scheduled.
1306 */ 1645 */
1307 if (sc->sc_child) 1646 if (sc->sc_child)
1308 usb_schedsoftintr(&sc->sc_bus); 1647 usb_schedsoftintr(&sc->sc_bus);
1309 else 1648 else
1310 usb_schedsoftintr(&sc->sc_bus2); 1649 usb_schedsoftintr(&sc->sc_bus2);
1311 } 1650 }
1312done: 1651done:
1313 mutex_spin_exit(&sc->sc_intr_lock); 1652 mutex_spin_exit(&sc->sc_intr_lock);
1314 return ret; 1653 return ret;
1315} 1654}
1316 1655
1317int 1656int
1318xhci_intr1(struct xhci_softc * const sc) 1657xhci_intr1(struct xhci_softc * const sc)
1319{ 1658{
1320 uint32_t usbsts; 1659 uint32_t usbsts;
1321 uint32_t iman; 1660 uint32_t iman;
1322 1661
1323 XHCIHIST_FUNC(); 1662 XHCIHIST_FUNC();
1324 1663
1325 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1664 usbsts = xhci_op_read_4(sc, XHCI_USBSTS);
1326 XHCIHIST_CALLARGS("USBSTS 0x%08jx", usbsts, 0, 0, 0); 1665 XHCIHIST_CALLARGS("USBSTS 0x%08jx", usbsts, 0, 0, 0);
1327 if ((usbsts & (XHCI_STS_HSE | XHCI_STS_EINT | XHCI_STS_PCD | 1666 if ((usbsts & (XHCI_STS_HSE | XHCI_STS_EINT | XHCI_STS_PCD |
1328 XHCI_STS_HCE)) == 0) { 1667 XHCI_STS_HCE)) == 0) {
1329 DPRINTFN(16, "ignored intr not for %jd", 1668 DPRINTFN(16, "ignored intr not for %jd",
1330 device_unit(sc->sc_dev), 0, 0, 0); 1669 device_unit(sc->sc_dev), 0, 0, 0);
1331 return 0; 1670 return 0;
1332 } 1671 }
1333 1672
1334 /* 1673 /*
1335 * Clear EINT and other transient flags, to not misenterpret 1674 * Clear EINT and other transient flags, to not misenterpret
1336 * next shared interrupt. Also, to avoid race, EINT must be cleared 1675 * next shared interrupt. Also, to avoid race, EINT must be cleared
1337 * before XHCI_IMAN_INTR_PEND is cleared. 1676 * before XHCI_IMAN_INTR_PEND is cleared.
1338 */ 1677 */
1339 xhci_op_write_4(sc, XHCI_USBSTS, usbsts & XHCI_STS_RSVDP0); 1678 xhci_op_write_4(sc, XHCI_USBSTS, usbsts & XHCI_STS_RSVDP0);
1340 1679
1341#ifdef XHCI_DEBUG 1680#ifdef XHCI_DEBUG
1342 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1681 usbsts = xhci_op_read_4(sc, XHCI_USBSTS);
1343 DPRINTFN(16, "USBSTS 0x%08jx", usbsts, 0, 0, 0); 1682 DPRINTFN(16, "USBSTS 0x%08jx", usbsts, 0, 0, 0);
1344#endif 1683#endif
1345 1684
1346 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1685 iman = xhci_rt_read_4(sc, XHCI_IMAN(0));
1347 DPRINTFN(16, "IMAN0 0x%08jx", iman, 0, 0, 0); 1686 DPRINTFN(16, "IMAN0 0x%08jx", iman, 0, 0, 0);
1348 iman |= XHCI_IMAN_INTR_PEND; 1687 iman |= XHCI_IMAN_INTR_PEND;
1349 xhci_rt_write_4(sc, XHCI_IMAN(0), iman); 1688 xhci_rt_write_4(sc, XHCI_IMAN(0), iman);
1350 1689
1351#ifdef XHCI_DEBUG 1690#ifdef XHCI_DEBUG
1352 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1691 iman = xhci_rt_read_4(sc, XHCI_IMAN(0));
1353 DPRINTFN(16, "IMAN0 0x%08jx", iman, 0, 0, 0); 1692 DPRINTFN(16, "IMAN0 0x%08jx", iman, 0, 0, 0);
1354 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1693 usbsts = xhci_op_read_4(sc, XHCI_USBSTS);
1355 DPRINTFN(16, "USBSTS 0x%08jx", usbsts, 0, 0, 0); 1694 DPRINTFN(16, "USBSTS 0x%08jx", usbsts, 0, 0, 0);
1356#endif 1695#endif
1357 1696
1358 return 1; 1697 return 1;
1359} 1698}
1360 1699
1361/* 1700/*
1362 * 3 port speed types used in USB stack 1701 * 3 port speed types used in USB stack
1363 * 1702 *
1364 * usbdi speed 1703 * usbdi speed
1365 * definition: USB_SPEED_* in usb.h 1704 * definition: USB_SPEED_* in usb.h
1366 * They are used in struct usbd_device in USB stack. 1705 * They are used in struct usbd_device in USB stack.
1367 * ioctl interface uses these values too. 1706 * ioctl interface uses these values too.
1368 * port_status speed 1707 * port_status speed
1369 * definition: UPS_*_SPEED in usb.h 1708 * definition: UPS_*_SPEED in usb.h
1370 * They are used in usb_port_status_t and valid only for USB 2.0. 1709 * They are used in usb_port_status_t and valid only for USB 2.0.
1371 * Speed value is always 0 for Super Speed or more, and dwExtPortStatus 1710 * Speed value is always 0 for Super Speed or more, and dwExtPortStatus
1372 * of usb_port_status_ext_t indicates port speed. 1711 * of usb_port_status_ext_t indicates port speed.
1373 * Note that some 3.0 values overlap with 2.0 values. 1712 * Note that some 3.0 values overlap with 2.0 values.
1374 * (e.g. 0x200 means UPS_POER_POWER_SS in SS and 1713 * (e.g. 0x200 means UPS_POER_POWER_SS in SS and
1375 * means UPS_LOW_SPEED in HS.) 1714 * means UPS_LOW_SPEED in HS.)
1376 * port status returned from hub also uses these values. 1715 * port status returned from hub also uses these values.
1377 * On NetBSD UPS_OTHER_SPEED indicates port speed is super speed 1716 * On NetBSD UPS_OTHER_SPEED indicates port speed is super speed
1378 * or more. 1717 * or more.
1379 * xspeed: 1718 * xspeed:
1380 * definition: Protocol Speed ID (PSI) (xHCI 1.1 7.2.1) 1719 * definition: Protocol Speed ID (PSI) (xHCI 1.1 7.2.1)
1381 * They are used in only slot context and PORTSC reg of xhci. 1720 * They are used in only slot context and PORTSC reg of xhci.
1382 * The difference between usbdi speed and xspeed is 1721 * The difference between usbdi speed and xspeed is
1383 * that FS and LS values are swapped. 1722 * that FS and LS values are swapped.
1384 */ 1723 */
1385 1724
1386/* convert usbdi speed to xspeed */ 1725/* convert usbdi speed to xspeed */
1387static int 1726static int
1388xhci_speed2xspeed(int speed) 1727xhci_speed2xspeed(int speed)
1389{ 1728{
1390 switch (speed) { 1729 switch (speed) {
1391 case USB_SPEED_LOW: return 2; 1730 case USB_SPEED_LOW: return 2;
1392 case USB_SPEED_FULL: return 1; 1731 case USB_SPEED_FULL: return 1;
1393 default: return speed; 1732 default: return speed;
1394 } 1733 }
1395} 1734}
1396 1735
1397#if 0 1736#if 0
1398/* convert xspeed to usbdi speed */ 1737/* convert xspeed to usbdi speed */
1399static int 1738static int
1400xhci_xspeed2speed(int xspeed) 1739xhci_xspeed2speed(int xspeed)
1401{ 1740{
1402 switch (xspeed) { 1741 switch (xspeed) {
1403 case 1: return USB_SPEED_FULL; 1742 case 1: return USB_SPEED_FULL;
1404 case 2: return USB_SPEED_LOW; 1743 case 2: return USB_SPEED_LOW;
1405 default: return xspeed; 1744 default: return xspeed;
1406 } 1745 }
1407} 1746}
1408#endif 1747#endif
1409 1748
1410/* convert xspeed to port status speed */ 1749/* convert xspeed to port status speed */
1411static int 1750static int
1412xhci_xspeed2psspeed(int xspeed) 1751xhci_xspeed2psspeed(int xspeed)
1413{ 1752{
1414 switch (xspeed) { 1753 switch (xspeed) {
1415 case 0: return 0; 1754 case 0: return 0;
1416 case 1: return UPS_FULL_SPEED; 1755 case 1: return UPS_FULL_SPEED;
1417 case 2: return UPS_LOW_SPEED; 1756 case 2: return UPS_LOW_SPEED;
1418 case 3: return UPS_HIGH_SPEED; 1757 case 3: return UPS_HIGH_SPEED;
1419 default: return UPS_OTHER_SPEED; 1758 default: return UPS_OTHER_SPEED;
1420 } 1759 }
1421} 1760}
1422 1761
1423/* 1762/*
1424 * Construct input contexts and issue TRB to open pipe. 1763 * Construct input contexts and issue TRB to open pipe.
1425 */ 1764 */
1426static usbd_status 1765static usbd_status
1427xhci_configure_endpoint(struct usbd_pipe *pipe) 1766xhci_configure_endpoint(struct usbd_pipe *pipe)
1428{ 1767{
1429 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1768 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe);
1430 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1769 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv;
1431#ifdef USB_DEBUG 1770#ifdef USB_DEBUG
1432 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1771 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc);
1433#endif 1772#endif
1434 struct xhci_soft_trb trb; 1773 struct xhci_soft_trb trb;
1435 usbd_status err; 1774 usbd_status err;
1436 1775
1437 XHCIHIST_FUNC(); 1776 XHCIHIST_FUNC();
1438 XHCIHIST_CALLARGS("slot %ju dci %ju epaddr 0x%02jx attr 0x%02jx", 1777 XHCIHIST_CALLARGS("slot %ju dci %ju epaddr 0x%02jx attr 0x%02jx",
1439 xs->xs_idx, dci, pipe->up_endpoint->ue_edesc->bEndpointAddress, 1778 xs->xs_idx, dci, pipe->up_endpoint->ue_edesc->bEndpointAddress,
1440 pipe->up_endpoint->ue_edesc->bmAttributes); 1779 pipe->up_endpoint->ue_edesc->bmAttributes);
1441 1780
1442 /* XXX ensure input context is available? */ 1781 /* XXX ensure input context is available? */
1443 1782
1444 memset(xhci_slot_get_icv(sc, xs, 0), 0, sc->sc_pgsz); 1783 memset(xhci_slot_get_icv(sc, xs, 0), 0, sc->sc_pgsz);
1445 1784
1446 /* set up context */ 1785 /* set up context */
1447 xhci_setup_ctx(pipe); 1786 xhci_setup_ctx(pipe);
1448 1787
1449 HEXDUMP("input control context", xhci_slot_get_icv(sc, xs, 0), 1788 HEXDUMP("input control context", xhci_slot_get_icv(sc, xs, 0),
1450 sc->sc_ctxsz * 1); 1789 sc->sc_ctxsz * 1);
1451 HEXDUMP("input endpoint context", xhci_slot_get_icv(sc, xs, 1790 HEXDUMP("input endpoint context", xhci_slot_get_icv(sc, xs,
1452 xhci_dci_to_ici(dci)), sc->sc_ctxsz * 1); 1791 xhci_dci_to_ici(dci)), sc->sc_ctxsz * 1);
1453 1792
1454 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1793 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0);
1455 trb.trb_2 = 0; 1794 trb.trb_2 = 0;
1456 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1795 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) |
1457 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1796 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP);
1458 1797
1459 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1798 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT);
1460 1799
1461 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1800 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD);
1462 HEXDUMP("output context", xhci_slot_get_dcv(sc, xs, dci), 1801 HEXDUMP("output context", xhci_slot_get_dcv(sc, xs, dci),
1463 sc->sc_ctxsz * 1); 1802 sc->sc_ctxsz * 1);
1464 1803
1465 return err; 1804 return err;
1466} 1805}
1467 1806
1468#if 0 1807#if 0
1469static usbd_status 1808static usbd_status
1470xhci_unconfigure_endpoint(struct usbd_pipe *pipe) 1809xhci_unconfigure_endpoint(struct usbd_pipe *pipe)
1471{ 1810{
1472#ifdef USB_DEBUG 1811#ifdef USB_DEBUG
1473 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1812 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv;
1474#endif 1813#endif
1475 1814
1476 XHCIHIST_FUNC(); 1815 XHCIHIST_FUNC();
1477 XHCIHIST_CALLARGS("slot %ju", xs->xs_idx, 0, 0, 0); 1816 XHCIHIST_CALLARGS("slot %ju", xs->xs_idx, 0, 0, 0);
1478 1817
1479 return USBD_NORMAL_COMPLETION; 1818 return USBD_NORMAL_COMPLETION;
1480} 1819}
1481#endif 1820#endif
1482 1821
1483/* 4.6.8, 6.4.3.7 */ 1822/* 4.6.8, 6.4.3.7 */
1484static usbd_status 1823static usbd_status
1485xhci_reset_endpoint_locked(struct usbd_pipe *pipe) 1824xhci_reset_endpoint_locked(struct usbd_pipe *pipe)
1486{ 1825{
1487 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1826 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe);
1488 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1827 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv;
1489 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1828 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc);
1490 struct xhci_soft_trb trb; 1829 struct xhci_soft_trb trb;
1491 usbd_status err; 1830 usbd_status err;
1492 1831
1493 XHCIHIST_FUNC(); 1832 XHCIHIST_FUNC();
1494 XHCIHIST_CALLARGS("slot %ju dci %ju", xs->xs_idx, dci, 0, 0); 1833 XHCIHIST_CALLARGS("slot %ju dci %ju", xs->xs_idx, dci, 0, 0);
1495 1834
1496 KASSERT(mutex_owned(&sc->sc_lock)); 1835 KASSERT(mutex_owned(&sc->sc_lock));
1497 1836
1498 trb.trb_0 = 0; 1837 trb.trb_0 = 0;
1499 trb.trb_2 = 0; 1838 trb.trb_2 = 0;
1500 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1839 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) |
1501 XHCI_TRB_3_EP_SET(dci) | 1840 XHCI_TRB_3_EP_SET(dci) |
1502 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP); 1841 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP);
1503 1842
1504 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1843 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT);
1505 1844
1506 return err; 1845 return err;
1507} 1846}
1508 1847
1509static usbd_status 1848static usbd_status
1510xhci_reset_endpoint(struct usbd_pipe *pipe) 1849xhci_reset_endpoint(struct usbd_pipe *pipe)
1511{ 1850{
1512 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1851 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe);
1513 1852
1514 mutex_enter(&sc->sc_lock); 1853 mutex_enter(&sc->sc_lock);
1515 usbd_status ret = xhci_reset_endpoint_locked(pipe); 1854 usbd_status ret = xhci_reset_endpoint_locked(pipe);
1516 mutex_exit(&sc->sc_lock); 1855 mutex_exit(&sc->sc_lock);
1517 1856
1518 return ret; 1857 return ret;
1519} 1858}
1520 1859
1521/* 1860/*
1522 * 4.6.9, 6.4.3.8 1861 * 4.6.9, 6.4.3.8
1523 * Stop execution of TDs on xfer ring. 1862 * Stop execution of TDs on xfer ring.
1524 * Should be called with sc_lock held. 1863 * Should be called with sc_lock held.
1525 */ 1864 */
1526static usbd_status 1865static usbd_status
1527xhci_stop_endpoint(struct usbd_pipe *pipe) 1866xhci_stop_endpoint(struct usbd_pipe *pipe)
1528{ 1867{
1529 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1868 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe);
1530 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1869 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv;
1531 struct xhci_soft_trb trb; 1870 struct xhci_soft_trb trb;
1532 usbd_status err; 1871 usbd_status err;
1533 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1872 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc);
1534 1873
1535 XHCIHIST_FUNC(); 1874 XHCIHIST_FUNC();
1536 XHCIHIST_CALLARGS("slot %ju dci %ju", xs->xs_idx, dci, 0, 0); 1875 XHCIHIST_CALLARGS("slot %ju dci %ju", xs->xs_idx, dci, 0, 0);
1537 1876
1538 KASSERT(mutex_owned(&sc->sc_lock)); 1877 KASSERT(mutex_owned(&sc->sc_lock));
1539 1878
1540 trb.trb_0 = 0; 1879 trb.trb_0 = 0;
1541 trb.trb_2 = 0; 1880 trb.trb_2 = 0;
1542 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1881 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) |
1543 XHCI_TRB_3_EP_SET(dci) | 1882 XHCI_TRB_3_EP_SET(dci) |
1544 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP); 1883 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP);
1545 1884
1546 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1885 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT);
1547 1886
1548 return err; 1887 return err;
1549} 1888}
1550 1889
1551/* 1890/*
1552 * Set TR Dequeue Pointer. 1891 * Set TR Dequeue Pointer.
1553 * xHCI 1.1 4.6.10 6.4.3.9 1892 * xHCI 1.1 4.6.10 6.4.3.9
1554 * Purge all of the TRBs on ring and reinitialize ring. 1893 * Purge all of the TRBs on ring and reinitialize ring.
1555 * Set TR dequeue Pointr to 0 and Cycle State to 1. 1894 * Set TR dequeue Pointr to 0 and Cycle State to 1.
1556 * EPSTATE of endpoint must be ERROR or STOPPED, otherwise CONTEXT_STATE 1895 * EPSTATE of endpoint must be ERROR or STOPPED, otherwise CONTEXT_STATE
1557 * error will be generated. 1896 * error will be generated.
1558 */ 1897 */
1559static usbd_status 1898static usbd_status
1560xhci_set_dequeue_locked(struct usbd_pipe *pipe) 1899xhci_set_dequeue_locked(struct usbd_pipe *pipe)
1561{ 1900{
1562 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1901 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe);
1563 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1902 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv;
1564 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1903 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc);
1565 struct xhci_ring * const xr = xs->xs_xr[dci]; 1904 struct xhci_ring * const xr = xs->xs_xr[dci];
1566 struct xhci_soft_trb trb; 1905 struct xhci_soft_trb trb;
1567 usbd_status err; 1906 usbd_status err;
1568 1907
1569 XHCIHIST_FUNC(); 1908 XHCIHIST_FUNC();
1570 XHCIHIST_CALLARGS("slot %ju dci %ju", xs->xs_idx, dci, 0, 0); 1909 XHCIHIST_CALLARGS("slot %ju dci %ju", xs->xs_idx, dci, 0, 0);
1571 1910
1572 KASSERT(mutex_owned(&sc->sc_lock)); 1911 KASSERT(mutex_owned(&sc->sc_lock));
1573 KASSERT(xr != NULL); 1912 KASSERT(xr != NULL);
1574 1913
1575 xhci_host_dequeue(xr); 1914 xhci_host_dequeue(xr);
1576 1915
1577 /* set DCS */ 1916 /* set DCS */
1578 trb.trb_0 = xhci_ring_trbp(xr, 0) | 1; /* XXX */ 1917 trb.trb_0 = xhci_ring_trbp(xr, 0) | 1; /* XXX */
1579 trb.trb_2 = 0; 1918 trb.trb_2 = 0;
1580 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1919 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) |
1581 XHCI_TRB_3_EP_SET(dci) | 1920 XHCI_TRB_3_EP_SET(dci) |
1582 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE); 1921 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE);
1583 1922
1584 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1923 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT);
1585 1924
1586 return err; 1925 return err;
1587} 1926}
1588 1927
1589static usbd_status 1928static usbd_status
1590xhci_set_dequeue(struct usbd_pipe *pipe) 1929xhci_set_dequeue(struct usbd_pipe *pipe)
1591{ 1930{
1592 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1931 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe);
1593 1932
1594 mutex_enter(&sc->sc_lock); 1933 mutex_enter(&sc->sc_lock);
1595 usbd_status ret = xhci_set_dequeue_locked(pipe); 1934 usbd_status ret = xhci_set_dequeue_locked(pipe);
1596 mutex_exit(&sc->sc_lock); 1935 mutex_exit(&sc->sc_lock);
1597 1936
1598 return ret; 1937 return ret;
1599} 1938}
1600 1939
1601/* 1940/*
1602 * Open new pipe: called from usbd_setup_pipe_flags. 1941 * Open new pipe: called from usbd_setup_pipe_flags.
1603 * Fills methods of pipe. 1942 * Fills methods of pipe.
1604 * If pipe is not for ep0, calls configure_endpoint. 1943 * If pipe is not for ep0, calls configure_endpoint.
1605 */ 1944 */
1606static usbd_status 1945static usbd_status
1607xhci_open(struct usbd_pipe *pipe) 1946xhci_open(struct usbd_pipe *pipe)
1608{ 1947{
1609 struct usbd_device * const dev = pipe->up_dev; 1948 struct usbd_device * const dev = pipe->up_dev;
1610 struct xhci_pipe * const xpipe = (struct xhci_pipe *)pipe; 1949 struct xhci_pipe * const xpipe = (struct xhci_pipe *)pipe;
1611 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 1950 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus);
1612 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1951 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv;
1613 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1952 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc;
1614 const u_int dci = xhci_ep_get_dci(ed); 1953 const u_int dci = xhci_ep_get_dci(ed);
1615 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1954 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes);
1616 usbd_status err; 1955 usbd_status err;
1617 1956
1618 XHCIHIST_FUNC(); 1957 XHCIHIST_FUNC();
1619 XHCIHIST_CALLARGS("addr %jd depth %jd port %jd speed %jd", dev->ud_addr, 1958 XHCIHIST_CALLARGS("addr %jd depth %jd port %jd speed %jd", dev->ud_addr,
1620 dev->ud_depth, dev->ud_powersrc->up_portno, dev->ud_speed); 1959 dev->ud_depth, dev->ud_powersrc->up_portno, dev->ud_speed);
1621 DPRINTFN(1, " dci %ju type 0x%02jx epaddr 0x%02jx attr 0x%02jx", 1960 DPRINTFN(1, " dci %ju type 0x%02jx epaddr 0x%02jx attr 0x%02jx",
1622 xhci_ep_get_dci(ed), ed->bDescriptorType, ed->bEndpointAddress, 1961 xhci_ep_get_dci(ed), ed->bDescriptorType, ed->bEndpointAddress,
1623 ed->bmAttributes); 1962 ed->bmAttributes);
1624 DPRINTFN(1, " mps %ju ival %ju", UGETW(ed->wMaxPacketSize), 1963 DPRINTFN(1, " mps %ju ival %ju", UGETW(ed->wMaxPacketSize),
1625 ed->bInterval, 0, 0); 1964 ed->bInterval, 0, 0);
1626 1965
1627 if (sc->sc_dying) 1966 if (sc->sc_dying)
1628 return USBD_IOERROR; 1967 return USBD_IOERROR;
1629 1968
1630 /* Root Hub */ 1969 /* Root Hub */
1631 if (dev->ud_depth == 0 && dev->ud_powersrc->up_portno == 0) { 1970 if (dev->ud_depth == 0 && dev->ud_powersrc->up_portno == 0) {
1632 switch (ed->bEndpointAddress) { 1971 switch (ed->bEndpointAddress) {
1633 case USB_CONTROL_ENDPOINT: 1972 case USB_CONTROL_ENDPOINT:
1634 pipe->up_methods = &roothub_ctrl_methods; 1973 pipe->up_methods = &roothub_ctrl_methods;
1635 break; 1974 break;
1636 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1975 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT:
1637 pipe->up_methods = &xhci_root_intr_methods; 1976 pipe->up_methods = &xhci_root_intr_methods;
1638 break; 1977 break;
1639 default: 1978 default:
1640 pipe->up_methods = NULL; 1979 pipe->up_methods = NULL;
1641 DPRINTFN(0, "bad bEndpointAddress 0x%02jx", 1980 DPRINTFN(0, "bad bEndpointAddress 0x%02jx",
1642 ed->bEndpointAddress, 0, 0, 0); 1981 ed->bEndpointAddress, 0, 0, 0);
1643 return USBD_INVAL; 1982 return USBD_INVAL;
1644 } 1983 }
1645 return USBD_NORMAL_COMPLETION; 1984 return USBD_NORMAL_COMPLETION;
1646 } 1985 }
1647 1986
1648 switch (xfertype) { 1987 switch (xfertype) {
1649 case UE_CONTROL: 1988 case UE_CONTROL:
1650 pipe->up_methods = &xhci_device_ctrl_methods; 1989 pipe->up_methods = &xhci_device_ctrl_methods;
1651 break; 1990 break;
1652 case UE_ISOCHRONOUS: 1991 case UE_ISOCHRONOUS:
1653 pipe->up_methods = &xhci_device_isoc_methods; 1992 pipe->up_methods = &xhci_device_isoc_methods;
1654 pipe->up_serialise = false; 1993 pipe->up_serialise = false;
1655 xpipe->xp_isoc_next = -1; 1994 xpipe->xp_isoc_next = -1;
1656 break; 1995 break;
1657 case UE_BULK: 1996 case UE_BULK:
1658 pipe->up_methods = &xhci_device_bulk_methods; 1997 pipe->up_methods = &xhci_device_bulk_methods;
1659 break; 1998 break;
1660 case UE_INTERRUPT: 1999 case UE_INTERRUPT:
1661 pipe->up_methods = &xhci_device_intr_methods; 2000 pipe->up_methods = &xhci_device_intr_methods;
1662 break; 2001 break;
1663 default: 2002 default:
1664 return USBD_IOERROR; 2003 return USBD_IOERROR;
1665 break; 2004 break;
1666 } 2005 }
1667 2006
1668 KASSERT(xs != NULL); 2007 KASSERT(xs != NULL);
1669 KASSERT(xs->xs_xr[dci] == NULL); 2008 KASSERT(xs->xs_xr[dci] == NULL);
1670 2009
1671 /* allocate transfer ring */ 2010 /* allocate transfer ring */
1672 err = xhci_ring_init(sc, &xs->xs_xr[dci], XHCI_TRANSFER_RING_TRBS, 2011 err = xhci_ring_init(sc, &xs->xs_xr[dci], XHCI_TRANSFER_RING_TRBS,
1673 XHCI_TRB_ALIGN); 2012 XHCI_TRB_ALIGN);
1674 if (err) { 2013 if (err) {
1675 DPRINTFN(1, "ring alloc failed %jd", err, 0, 0, 0); 2014 DPRINTFN(1, "ring alloc failed %jd", err, 0, 0, 0);
1676 return err; 2015 return err;
1677 } 2016 }
1678 2017
1679 if (ed->bEndpointAddress != USB_CONTROL_ENDPOINT) 2018 if (ed->bEndpointAddress != USB_CONTROL_ENDPOINT)
1680 return xhci_configure_endpoint(pipe); 2019 return xhci_configure_endpoint(pipe);
1681 2020
1682 return USBD_NORMAL_COMPLETION; 2021 return USBD_NORMAL_COMPLETION;
1683} 2022}
1684 2023
1685/* 2024/*
1686 * Closes pipe, called from usbd_kill_pipe via close methods. 2025 * Closes pipe, called from usbd_kill_pipe via close methods.
1687 * If the endpoint to be closed is ep0, disable_slot. 2026 * If the endpoint to be closed is ep0, disable_slot.
1688 * Should be called with sc_lock held. 2027 * Should be called with sc_lock held.
1689 */ 2028 */
1690static void 2029static void
1691xhci_close_pipe(struct usbd_pipe *pipe) 2030xhci_close_pipe(struct usbd_pipe *pipe)
1692{ 2031{
1693 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 2032 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe);
1694 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 2033 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv;
1695 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 2034 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc;
1696 const u_int dci = xhci_ep_get_dci(ed); 2035 const u_int dci = xhci_ep_get_dci(ed);
1697 struct xhci_soft_trb trb; 2036 struct xhci_soft_trb trb;
1698 uint32_t *cp; 2037 uint32_t *cp;
1699 2038
1700 XHCIHIST_FUNC(); 2039 XHCIHIST_FUNC();
1701 2040
1702 if (sc->sc_dying) 2041 if (sc->sc_dying)
1703 return; 2042 return;
1704 2043
1705 /* xs is uninitialized before xhci_init_slot */ 2044 /* xs is uninitialized before xhci_init_slot */
1706 if (xs == NULL || xs->xs_idx == 0) 2045 if (xs == NULL || xs->xs_idx == 0)
1707 return; 2046 return;
1708 2047
1709 XHCIHIST_CALLARGS("pipe %#jx slot %ju dci %ju", 2048 XHCIHIST_CALLARGS("pipe %#jx slot %ju dci %ju",
1710 (uintptr_t)pipe, xs->xs_idx, dci, 0); 2049 (uintptr_t)pipe, xs->xs_idx, dci, 0);
1711 2050
1712 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 2051 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx");
1713 KASSERT(mutex_owned(&sc->sc_lock)); 2052 KASSERT(mutex_owned(&sc->sc_lock));
1714 2053
1715 if (pipe->up_dev->ud_depth == 0) 2054 if (pipe->up_dev->ud_depth == 0)
1716 return; 2055 return;
1717 2056
1718 if (dci == XHCI_DCI_EP_CONTROL) { 2057 if (dci == XHCI_DCI_EP_CONTROL) {
1719 DPRINTFN(4, "closing ep0", 0, 0, 0, 0); 2058 DPRINTFN(4, "closing ep0", 0, 0, 0, 0);
1720 /* This frees all rings */ 2059 /* This frees all rings */
1721 xhci_disable_slot(sc, xs->xs_idx); 2060 xhci_disable_slot(sc, xs->xs_idx);
1722 return; 2061 return;
1723 } 2062 }
1724 2063
1725 if (xhci_get_epstate(sc, xs, dci) != XHCI_EPSTATE_STOPPED) 2064 if (xhci_get_epstate(sc, xs, dci) != XHCI_EPSTATE_STOPPED)
1726 (void)xhci_stop_endpoint(pipe); 2065 (void)xhci_stop_endpoint(pipe);
1727 2066
1728 /* 2067 /*
1729 * set appropriate bit to be dropped. 2068 * set appropriate bit to be dropped.
1730 * don't set DC bit to 1, otherwise all endpoints 2069 * don't set DC bit to 1, otherwise all endpoints
1731 * would be deconfigured. 2070 * would be deconfigured.
1732 */ 2071 */
1733 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2072 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL);
1734 cp[0] = htole32(XHCI_INCTX_0_DROP_MASK(dci)); 2073 cp[0] = htole32(XHCI_INCTX_0_DROP_MASK(dci));
1735 cp[1] = htole32(0); 2074 cp[1] = htole32(0);
1736 2075
1737 /* XXX should be most significant one, not dci? */ 2076 /* XXX should be most significant one, not dci? */
1738 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 2077 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT));
1739 cp[0] = htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 2078 cp[0] = htole32(XHCI_SCTX_0_CTX_NUM_SET(dci));
1740 2079
1741 /* configure ep context performs an implicit dequeue */ 2080 /* configure ep context performs an implicit dequeue */
1742 xhci_host_dequeue(xs->xs_xr[dci]); 2081 xhci_host_dequeue(xs->xs_xr[dci]);
1743 2082
1744 /* sync input contexts before they are read from memory */ 2083 /* sync input contexts before they are read from memory */
1745 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2084 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE);
1746 2085
1747 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 2086 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0);
1748 trb.trb_2 = 0; 2087 trb.trb_2 = 0;
1749 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 2088 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) |
1750 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 2089 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP);
1751 2090
1752 (void)xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 2091 (void)xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT);
1753 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 2092 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD);
1754 2093
1755 xhci_ring_free(sc, &xs->xs_xr[dci]); 2094 xhci_ring_free(sc, &xs->xs_xr[dci]);
1756} 2095}
1757 2096
1758/* 2097/*
1759 * Abort transfer. 2098 * Abort transfer.
1760 * Should be called with sc_lock held. 2099 * Should be called with sc_lock held.
1761 */ 2100 */
1762static void 2101static void
1763xhci_abortx(struct usbd_xfer *xfer) 2102xhci_abortx(struct usbd_xfer *xfer)
1764{ 2103{
1765 XHCIHIST_FUNC(); 2104 XHCIHIST_FUNC();
1766 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 2105 struct xhci_softc * const sc = XHCI_XFER2SC(xfer);
1767 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 2106 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv;
1768 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 2107 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc);
1769 2108
1770 XHCIHIST_CALLARGS("xfer %#jx pipe %#jx", 2109 XHCIHIST_CALLARGS("xfer %#jx pipe %#jx",
1771 (uintptr_t)xfer, (uintptr_t)xfer->ux_pipe, 0, 0); 2110 (uintptr_t)xfer, (uintptr_t)xfer->ux_pipe, 0, 0);
1772 2111
1773 KASSERT(mutex_owned(&sc->sc_lock)); 2112 KASSERT(mutex_owned(&sc->sc_lock));
1774 ASSERT_SLEEPABLE(); 2113 ASSERT_SLEEPABLE();
cvs diff -r1.18 -r1.19 src/sys/dev/usb/xhcireg.h (switch to unified diff)

--- src/sys/dev/usb/xhcireg.h 2020/06/06 08:56:30 1.18
+++ src/sys/dev/usb/xhcireg.h 2021/05/23 11:49:45 1.19
@@ -1,663 +1,667 @@ @@ -1,663 +1,667 @@
1/* $NetBSD: xhcireg.h,v 1.18 2020/06/06 08:56:30 skrll Exp $ */ 1/* $NetBSD: xhcireg.h,v 1.19 2021/05/23 11:49:45 riastradh Exp $ */
2 2
3/*- 3/*-
4 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved. 4 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved.
5 * 5 *
6 * Redistribution and use in source and binary forms, with or without 6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions 7 * modification, are permitted provided that the following conditions
8 * are met: 8 * are met:
9 * 1. Redistributions of source code must retain the above copyright 9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer. 10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright 11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the 12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution. 13 * documentation and/or other materials provided with the distribution.
14 * 14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE. 25 * SUCH DAMAGE.
26 */ 26 */
27 27
28#ifndef _DEV_USB_XHCIREG_H_ 28#ifndef _DEV_USB_XHCIREG_H_
29#define _DEV_USB_XHCIREG_H_ 29#define _DEV_USB_XHCIREG_H_
30 30
31/* XHCI PCI config registers */ 31/* XHCI PCI config registers */
32#define PCI_CBMEM 0x10 /* configuration base MEM */ 32#define PCI_CBMEM 0x10 /* configuration base MEM */
33#define PCI_INTERFACE_XHCI 0x30 33#define PCI_INTERFACE_XHCI 0x30
34 34
35#define PCI_USBREV 0x60 /* RO USB protocol revision */ 35#define PCI_USBREV 0x60 /* RO USB protocol revision */
36#define PCI_USBREV_MASK 0xFF 36#define PCI_USBREV_MASK 0xFF
37#define PCI_USBREV_3_0 0x30 /* USB 3.0 */ 37#define PCI_USBREV_3_0 0x30 /* USB 3.0 */
38#define PCI_USBREV_3_1 0x31 /* USB 3.1 */ 38#define PCI_USBREV_3_1 0x31 /* USB 3.1 */
39 39
40#define PCI_XHCI_FLADJ 0x61 /* RW frame length adjust */ 40#define PCI_XHCI_FLADJ 0x61 /* RW frame length adjust */
41 41
42#define PCI_XHCI_INTEL_XUSB2PR 0xd0 /* Intel USB2 Port Routing */ 42#define PCI_XHCI_INTEL_XUSB2PR 0xd0 /* Intel USB2 Port Routing */
43#define PCI_XHCI_INTEL_USB2PRM 0xd4 /* Intel USB2 Port Routing Mask */ 43#define PCI_XHCI_INTEL_USB2PRM 0xd4 /* Intel USB2 Port Routing Mask */
44#define PCI_XHCI_INTEL_USB3_PSSEN 0xd8 /* Intel USB3 Port SuperSpeed Enable */ 44#define PCI_XHCI_INTEL_USB3_PSSEN 0xd8 /* Intel USB3 Port SuperSpeed Enable */
45#define PCI_XHCI_INTEL_USB3PRM 0xdc /* Intel USB3 Port Routing Mask */ 45#define PCI_XHCI_INTEL_USB3PRM 0xdc /* Intel USB3 Port Routing Mask */
46 46
47/* XHCI capability registers */ 47/* XHCI capability registers */
48#define XHCI_CAPLENGTH 0x00 /* RO capability - 1 byte */ 48#define XHCI_CAPLENGTH 0x00 /* RO capability - 1 byte */
49#define XHCI_HCIVERSION 0x02 /* RO version - 2 bytes */ 49#define XHCI_HCIVERSION 0x02 /* RO version - 2 bytes */
50#define XHCI_HCIVERSION_0_9 0x0090 /* xHCI version 0.9 */ 50#define XHCI_HCIVERSION_0_9 0x0090 /* xHCI version 0.9 */
51#define XHCI_HCIVERSION_0_96 0x0096 /* xHCI version 0.96 */ 51#define XHCI_HCIVERSION_0_96 0x0096 /* xHCI version 0.96 */
52#define XHCI_HCIVERSION_1_0 0x0100 /* xHCI version 1.0 */ 52#define XHCI_HCIVERSION_1_0 0x0100 /* xHCI version 1.0 */
53#define XHCI_HCIVERSION_1_1 0x0110 /* xHCI version 1.1 */ 53#define XHCI_HCIVERSION_1_1 0x0110 /* xHCI version 1.1 */
54#define XHCI_HCIVERSION_1_2 0x0120 /* xHCI version 1.2 */ 54#define XHCI_HCIVERSION_1_2 0x0120 /* xHCI version 1.2 */
55 55
56#define XHCI_HCSPARAMS1 0x04 /* RO structual parameters 1 */ 56#define XHCI_HCSPARAMS1 0x04 /* RO structual parameters 1 */
57#define XHCI_HCS1_MAXSLOTS_MASK __BITS(7, 0) 57#define XHCI_HCS1_MAXSLOTS_MASK __BITS(7, 0)
58#define XHCI_HCS1_MAXSLOTS(x) __SHIFTOUT((x), XHCI_HCS1_MAXSLOTS_MASK) 58#define XHCI_HCS1_MAXSLOTS(x) __SHIFTOUT((x), XHCI_HCS1_MAXSLOTS_MASK)
59#define XHCI_HCS1_MAXINTRS_MASK __BITS(18, 8) 59#define XHCI_HCS1_MAXINTRS_MASK __BITS(18, 8)
60#define XHCI_HCS1_MAXINTRS(x) __SHIFTOUT((x), XHCI_HCS1_MAXINTRS_MASK) 60#define XHCI_HCS1_MAXINTRS(x) __SHIFTOUT((x), XHCI_HCS1_MAXINTRS_MASK)
61#define XHCI_HCS1_MAXPORTS_MASK __BITS(31, 24) 61#define XHCI_HCS1_MAXPORTS_MASK __BITS(31, 24)
62#define XHCI_HCS1_MAXPORTS(x) __SHIFTOUT((x), XHCI_HCS1_MAXPORTS_MASK) 62#define XHCI_HCS1_MAXPORTS(x) __SHIFTOUT((x), XHCI_HCS1_MAXPORTS_MASK)
63 63
64#define XHCI_HCSPARAMS2 0x08 /* RO structual parameters 2 */ 64#define XHCI_HCSPARAMS2 0x08 /* RO structual parameters 2 */
65#define XHCI_HCS2_IST_MASK __BITS(3, 0) 65#define XHCI_HCS2_IST_MASK __BITS(3, 0)
66#define XHCI_HCS2_IST(x) __SHIFTOUT((x), XHCI_HCS2_IST_MASK) 66#define XHCI_HCS2_IST(x) __SHIFTOUT((x), XHCI_HCS2_IST_MASK)
67#define XHCI_HCS2_ERSTMAX_MASK __BITS(7, 4) 67#define XHCI_HCS2_ERSTMAX_MASK __BITS(7, 4)
68#define XHCI_HCS2_ERSTMAX(x) __SHIFTOUT((x), XHCI_HCS2_ERSTMAX_MASK) 68#define XHCI_HCS2_ERSTMAX(x) __SHIFTOUT((x), XHCI_HCS2_ERSTMAX_MASK)
69#define XHCI_HCS2_SPBUFHI_MASK __BITS(25, 21) 69#define XHCI_HCS2_SPBUFHI_MASK __BITS(25, 21)
70#define XHCI_HCS2_SPR_MASK __BIT(26) 70#define XHCI_HCS2_SPR_MASK __BIT(26)
71#define XHCI_HCS2_SPR(x) __SHIFTOUT((x), XHCI_HCS2_SPR_MASK) 71#define XHCI_HCS2_SPR(x) __SHIFTOUT((x), XHCI_HCS2_SPR_MASK)
72#define XHCI_HCS2_SPBUFLO_MASK __BITS(31, 27) 72#define XHCI_HCS2_SPBUFLO_MASK __BITS(31, 27)
73#define XHCI_HCS2_MAXSPBUF(x) \ 73#define XHCI_HCS2_MAXSPBUF(x) \
74 (__SHIFTOUT((x), XHCI_HCS2_SPBUFHI_MASK) << 5) | \ 74 (__SHIFTOUT((x), XHCI_HCS2_SPBUFHI_MASK) << 5) | \
75 (__SHIFTOUT((x), XHCI_HCS2_SPBUFLO_MASK)) 75 (__SHIFTOUT((x), XHCI_HCS2_SPBUFLO_MASK))
76 76
77#define XHCI_HCSPARAMS3 0x0c /* RO structual parameters 3 */ 77#define XHCI_HCSPARAMS3 0x0c /* RO structual parameters 3 */
78#define XHCI_HCS3_U1_DEL_MASK __BITS(7, 0) 78#define XHCI_HCS3_U1_DEL_MASK __BITS(7, 0)
79#define XHCI_HCS3_U1_DEL(x) __SHIFTOUT((x), XHCI_HCS3_U1_DEL_MASK) 79#define XHCI_HCS3_U1_DEL(x) __SHIFTOUT((x), XHCI_HCS3_U1_DEL_MASK)
80#define XHCI_HCS3_U2_DEL_MASK __BITS(15, 8) 80#define XHCI_HCS3_U2_DEL_MASK __BITS(15, 8)
81#define XHCI_HCS3_U2_DEL(x) __SHIFTOUT((x), XHCI_HCS3_U2_DEL_MASK) 81#define XHCI_HCS3_U2_DEL(x) __SHIFTOUT((x), XHCI_HCS3_U2_DEL_MASK)
82 82
83#define XHCI_HCCPARAMS 0x10 /* RO capability parameters */ 83#define XHCI_HCCPARAMS 0x10 /* RO capability parameters */
84#define XHCI_HCC_AC64(x) __SHIFTOUT((x), __BIT(0)) /* 64-bit capable */ 84#define XHCI_HCC_AC64(x) __SHIFTOUT((x), __BIT(0)) /* 64-bit capable */
85#define XHCI_HCC_BNC(x) __SHIFTOUT((x), __BIT(1)) /* BW negotiation */ 85#define XHCI_HCC_BNC(x) __SHIFTOUT((x), __BIT(1)) /* BW negotiation */
86#define XHCI_HCC_CSZ(x) __SHIFTOUT((x), __BIT(2)) /* context size */ 86#define XHCI_HCC_CSZ(x) __SHIFTOUT((x), __BIT(2)) /* context size */
87#define XHCI_HCC_PPC(x) __SHIFTOUT((x), __BIT(3)) /* port power control */ 87#define XHCI_HCC_PPC(x) __SHIFTOUT((x), __BIT(3)) /* port power control */
88#define XHCI_HCC_PIND(x) __SHIFTOUT((x), __BIT(4)) /* port indicators */ 88#define XHCI_HCC_PIND(x) __SHIFTOUT((x), __BIT(4)) /* port indicators */
89#define XHCI_HCC_LHRC(x) __SHIFTOUT((x), __BIT(5)) /* light HC reset */ 89#define XHCI_HCC_LHRC(x) __SHIFTOUT((x), __BIT(5)) /* light HC reset */
90#define XHCI_HCC_LTC(x) __SHIFTOUT((x), __BIT(6)) /* latency tolerance msg */ 90#define XHCI_HCC_LTC(x) __SHIFTOUT((x), __BIT(6)) /* latency tolerance msg */
91#define XHCI_HCC_NSS(x) __SHIFTOUT((x), __BIT(7)) /* no secondary sid */ 91#define XHCI_HCC_NSS(x) __SHIFTOUT((x), __BIT(7)) /* no secondary sid */
92#define XHCI_HCC_PAE(x) __SHIFTOUT((x), __BIT(8)) /* Parse All Event Data */ 92#define XHCI_HCC_PAE(x) __SHIFTOUT((x), __BIT(8)) /* Parse All Event Data */
93#define XHCI_HCC_SPC(x) __SHIFTOUT((x), __BIT(9)) /* Short packet */ 93#define XHCI_HCC_SPC(x) __SHIFTOUT((x), __BIT(9)) /* Short packet */
94#define XHCI_HCC_SEC(x) __SHIFTOUT((x), __BIT(10)) /* Stopped EDTLA */ 94#define XHCI_HCC_SEC(x) __SHIFTOUT((x), __BIT(10)) /* Stopped EDTLA */
95#define XHCI_HCC_CFC(x) __SHIFTOUT((x), __BIT(11)) /* Configuous Frame ID */ 95#define XHCI_HCC_CFC(x) __SHIFTOUT((x), __BIT(11)) /* Configuous Frame ID */
96#define XHCI_HCC_MAXPSASIZE_MASK __BITS(15, 12) /* max pri. stream array size */ 96#define XHCI_HCC_MAXPSASIZE_MASK __BITS(15, 12) /* max pri. stream array size */
97#define XHCI_HCC_MAXPSASIZE(x) __SHIFTOUT((x), XHCI_HCC_MAXPSASIZE_MASK) 97#define XHCI_HCC_MAXPSASIZE(x) __SHIFTOUT((x), XHCI_HCC_MAXPSASIZE_MASK)
98#define XHCI_HCC_XECP_MASK __BITS(31, 16) /* extended capabilities pointer */ 98#define XHCI_HCC_XECP_MASK __BITS(31, 16) /* extended capabilities pointer */
99#define XHCI_HCC_XECP(x) __SHIFTOUT((x), XHCI_HCC_XECP_MASK) 99#define XHCI_HCC_XECP(x) __SHIFTOUT((x), XHCI_HCC_XECP_MASK)
100 100
101#define XHCI_DBOFF 0x14 /* RO doorbell offset */ 101#define XHCI_DBOFF 0x14 /* RO doorbell offset */
102#define XHCI_RTSOFF 0x18 /* RO runtime register space offset */ 102#define XHCI_RTSOFF 0x18 /* RO runtime register space offset */
103#define XHCI_HCCPARAMS2 0x1c /* RO capability parameters 2 */ 103#define XHCI_HCCPARAMS2 0x1c /* RO capability parameters 2 */
104#define XHCI_HCC2_U3C(x) __SHIFTOUT((x), __BIT(0)) /* U3 Entry capable */ 104#define XHCI_HCC2_U3C(x) __SHIFTOUT((x), __BIT(0)) /* U3 Entry capable */
105#define XHCI_HCC2_CMC(x) __SHIFTOUT((x), __BIT(1)) /* CEC MaxExLatTooLg */ 105#define XHCI_HCC2_CMC(x) __SHIFTOUT((x), __BIT(1)) /* CEC MaxExLatTooLg */
106#define XHCI_HCC2_FSC(x) __SHIFTOUT((x), __BIT(2)) /* Foce Save Context */ 106#define XHCI_HCC2_FSC(x) __SHIFTOUT((x), __BIT(2)) /* Foce Save Context */
107#define XHCI_HCC2_CTC(x) __SHIFTOUT((x), __BIT(3)) /* Compliance Transc */ 107#define XHCI_HCC2_CTC(x) __SHIFTOUT((x), __BIT(3)) /* Compliance Transc */
108#define XHCI_HCC2_LEC(x) __SHIFTOUT((x), __BIT(4)) /* Large ESIT Paylod */ 108#define XHCI_HCC2_LEC(x) __SHIFTOUT((x), __BIT(4)) /* Large ESIT Paylod */
109#define XHCI_HCC2_CIC(x) __SHIFTOUT((x), __BIT(5)) /* Configuration Inf */ 109#define XHCI_HCC2_CIC(x) __SHIFTOUT((x), __BIT(5)) /* Configuration Inf */
110#define XHCI_HCC2_ETC(x) __SHIFTOUT((x), __BIT(6)) /* Extended TBC */ 110#define XHCI_HCC2_ETC(x) __SHIFTOUT((x), __BIT(6)) /* Extended TBC */
111#define XHCI_HCC2_ETC_TSC(x) __SHIFTOUT((x), __BIT(7)) /* ExtTBC TRB Status */ 111#define XHCI_HCC2_ETC_TSC(x) __SHIFTOUT((x), __BIT(7)) /* ExtTBC TRB Status */
112#define XHCI_HCC2_GSC(x) __SHIFTOUT((x), __BIT(8)) /* Get/Set Extended Property */ 112#define XHCI_HCC2_GSC(x) __SHIFTOUT((x), __BIT(8)) /* Get/Set Extended Property */
113#define XHCI_HCC2_VTC(x) __SHIFTOUT((x), __BIT(9)) /* Virt. Based Trust */ 113#define XHCI_HCC2_VTC(x) __SHIFTOUT((x), __BIT(9)) /* Virt. Based Trust */
114 114
115#define XHCI_VTIOSOFF 0x20 /* RO Virtualization Base Trusted IO Offset */ 115#define XHCI_VTIOSOFF 0x20 /* RO Virtualization Base Trusted IO Offset */
116 116
117/* XHCI operational registers. Offset given by XHCI_CAPLENGTH register */ 117/* XHCI operational registers. Offset given by XHCI_CAPLENGTH register */
118#define XHCI_USBCMD 0x00 /* XHCI command */ 118#define XHCI_USBCMD 0x00 /* XHCI command */
119#define XHCI_CMD_RS __BIT(0) /* RW Run/Stop */ 119#define XHCI_CMD_RS __BIT(0) /* RW Run/Stop */
120#define XHCI_CMD_HCRST __BIT(1) /* RW Host Controller Reset */ 120#define XHCI_CMD_HCRST __BIT(1) /* RW Host Controller Reset */
121#define XHCI_CMD_INTE __BIT(2) /* RW Interrupter Enable */ 121#define XHCI_CMD_INTE __BIT(2) /* RW Interrupter Enable */
122#define XHCI_CMD_HSEE __BIT(3) /* RW Host System Error Enable */ 122#define XHCI_CMD_HSEE __BIT(3) /* RW Host System Error Enable */
123#define XHCI_CMD_LHCRST __BIT(7) /* RO/RW Light Host Controller Reset */ 123#define XHCI_CMD_LHCRST __BIT(7) /* RO/RW Light Host Controller Reset */
124#define XHCI_CMD_CSS __BIT(8) /* RW Controller Save State */ 124#define XHCI_CMD_CSS __BIT(8) /* RW Controller Save State */
125#define XHCI_CMD_CRS __BIT(9) /* RW Controller Restore State */ 125#define XHCI_CMD_CRS __BIT(9) /* RW Controller Restore State */
126#define XHCI_CMD_EWE __BIT(10) /* RW Enable Wrap Event */ 126#define XHCI_CMD_EWE __BIT(10) /* RW Enable Wrap Event */
127#define XHCI_CMD_EU3S __BIT(11) /* RW Enable U3 MFINDEX Stop */ 127#define XHCI_CMD_EU3S __BIT(11) /* RW Enable U3 MFINDEX Stop */
128#define XHCI_CMD_CME __BIT(13) /* RW CEM Enable */ 128#define XHCI_CMD_CME __BIT(13) /* RW CEM Enable */
129#define XHCI_CMD_ETE __BIT(14) /* RW Extended TBC Enable */ 129#define XHCI_CMD_ETE __BIT(14) /* RW Extended TBC Enable */
130#define XHCI_CMD_TSC_EN __BIT(15) /* RW Extended TBC TRB Status Enable */ 130#define XHCI_CMD_TSC_EN __BIT(15) /* RW Extended TBC TRB Status Enable */
131#define XHCI_CMD_VTIOE __BIT(16) /* RW VTIO Enable */ 131#define XHCI_CMD_VTIOE __BIT(16) /* RW VTIO Enable */
132 132
133#define XHCI_WAIT_CNR 100 /* in 1ms */ 133#define XHCI_WAIT_CNR 100 /* in 1ms */
134#define XHCI_WAIT_HCRST 100 /* in 1ms */ 134#define XHCI_WAIT_HCRST 100 /* in 1ms */
 135#define XHCI_WAIT_RSS 100 /* in 1ms */
 136#define XHCI_WAIT_SSS 100 /* in 1ms */
 137#define XHCI_WAIT_PLS_U0 100 /* in 1ms */
 138#define XHCI_WAIT_PLS_U3 10 /* in 1ms */
135 139
136#define XHCI_USBSTS 0x04 /* XHCI status */ 140#define XHCI_USBSTS 0x04 /* XHCI status */
137#define XHCI_STS_HCH __BIT(0) /* RO - Host Controller Halted */ 141#define XHCI_STS_HCH __BIT(0) /* RO - Host Controller Halted */
138#define XHCI_STS_RSVDZ0 __BIT(1) /* RsvdZ - 1:1 */ 142#define XHCI_STS_RSVDZ0 __BIT(1) /* RsvdZ - 1:1 */
139#define XHCI_STS_HSE __BIT(2) /* RW - Host System Error */ 143#define XHCI_STS_HSE __BIT(2) /* RW - Host System Error */
140#define XHCI_STS_EINT __BIT(3) /* RW - Event Interrupt */ 144#define XHCI_STS_EINT __BIT(3) /* RW - Event Interrupt */
141#define XHCI_STS_PCD __BIT(4) /* RW - Port Change Detect */ 145#define XHCI_STS_PCD __BIT(4) /* RW - Port Change Detect */
142#define XHCI_STS_RSVDZ1 __BITS(7, 5) /* RsvdZ - 7:5 */ 146#define XHCI_STS_RSVDZ1 __BITS(7, 5) /* RsvdZ - 7:5 */
143#define XHCI_STS_SSS __BIT(8) /* RO - Save State Status */ 147#define XHCI_STS_SSS __BIT(8) /* RO - Save State Status */
144#define XHCI_STS_RSS __BIT(9) /* RO - Restore State Status */ 148#define XHCI_STS_RSS __BIT(9) /* RO - Restore State Status */
145#define XHCI_STS_SRE __BIT(10) /* RW - Save/Restore Error */ 149#define XHCI_STS_SRE __BIT(10) /* RW - Save/Restore Error */
146#define XHCI_STS_CNR __BIT(11) /* RO - Controller Not Ready */ 150#define XHCI_STS_CNR __BIT(11) /* RO - Controller Not Ready */
147#define XHCI_STS_HCE __BIT(12) /* RO - Host Controller Error */ 151#define XHCI_STS_HCE __BIT(12) /* RO - Host Controller Error */
148#define XHCI_STS_RSVDP0 __BITS(13, 31) /* RsvdP - 31:13 */ 152#define XHCI_STS_RSVDP0 __BITS(13, 31) /* RsvdP - 31:13 */
149 153
150#define XHCI_PAGESIZE 0x08 /* XHCI page size mask */ 154#define XHCI_PAGESIZE 0x08 /* XHCI page size mask */
151#define XHCI_PAGESIZE_4K __BIT(0) /* 4K Page Size */ 155#define XHCI_PAGESIZE_4K __BIT(0) /* 4K Page Size */
152#define XHCI_PAGESIZE_8K __BIT(1) /* 8K Page Size */ 156#define XHCI_PAGESIZE_8K __BIT(1) /* 8K Page Size */
153#define XHCI_PAGESIZE_16K __BIT(2) /* 16K Page Size */ 157#define XHCI_PAGESIZE_16K __BIT(2) /* 16K Page Size */
154#define XHCI_PAGESIZE_32K __BIT(3) /* 32K Page Size */ 158#define XHCI_PAGESIZE_32K __BIT(3) /* 32K Page Size */
155#define XHCI_PAGESIZE_64K __BIT(4) /* 64K Page Size */ 159#define XHCI_PAGESIZE_64K __BIT(4) /* 64K Page Size */
156#define XHCI_PAGESIZE_128K __BIT(5) /* 128K Page Size */ 160#define XHCI_PAGESIZE_128K __BIT(5) /* 128K Page Size */
157#define XHCI_PAGESIZE_256K __BIT(6) /* 256K Page Size */ 161#define XHCI_PAGESIZE_256K __BIT(6) /* 256K Page Size */
158#define XHCI_PAGESIZE_512K __BIT(7) /* 512K Page Size */ 162#define XHCI_PAGESIZE_512K __BIT(7) /* 512K Page Size */
159#define XHCI_PAGESIZE_1M __BIT(8) /* 1M Page Size */ 163#define XHCI_PAGESIZE_1M __BIT(8) /* 1M Page Size */
160#define XHCI_PAGESIZE_2M __BIT(9) /* 2M Page Size */ 164#define XHCI_PAGESIZE_2M __BIT(9) /* 2M Page Size */
161/* ... extends to 128M */ 165/* ... extends to 128M */
162 166
163#define XHCI_DNCTRL 0x14 /* XHCI device notification control */ 167#define XHCI_DNCTRL 0x14 /* XHCI device notification control */
164#define XHCI_DNCTRL_MASK(n) __BIT((n)) 168#define XHCI_DNCTRL_MASK(n) __BIT((n))
165 169
166/* 5.4.5 Command Ring Control Register */ 170/* 5.4.5 Command Ring Control Register */
167#define XHCI_CRCR 0x18 /* XHCI command ring control */ 171#define XHCI_CRCR 0x18 /* XHCI command ring control */
168#define XHCI_CRCR_LO_RCS __BIT(0) /* RW - consumer cycle state */ 172#define XHCI_CRCR_LO_RCS __BIT(0) /* RW - consumer cycle state */
169#define XHCI_CRCR_LO_CS __BIT(1) /* RW - command stop */ 173#define XHCI_CRCR_LO_CS __BIT(1) /* RW - command stop */
170#define XHCI_CRCR_LO_CA __BIT(2) /* RW - command abort */ 174#define XHCI_CRCR_LO_CA __BIT(2) /* RW - command abort */
171#define XHCI_CRCR_LO_CRR __BIT(3) /* RW - command ring running */ 175#define XHCI_CRCR_LO_CRR __BIT(3) /* RW - command ring running */
172#define XHCI_CRCR_LO_MASK __BITS(31, 6) 176#define XHCI_CRCR_LO_MASK __BITS(31, 6)
173 177
174#define XHCI_CRCR_HI 0x1c /* XHCI command ring control */ 178#define XHCI_CRCR_HI 0x1c /* XHCI command ring control */
175 179
176/* 5.4.6 Device Context Base Address Array Pointer Registers */ 180/* 5.4.6 Device Context Base Address Array Pointer Registers */
177#define XHCI_DCBAAP 0x30 /* XHCI dev context BA pointer */ 181#define XHCI_DCBAAP 0x30 /* XHCI dev context BA pointer */
178#define XHCI_DCBAAP_HI 0x34 /* XHCI dev context BA pointer */ 182#define XHCI_DCBAAP_HI 0x34 /* XHCI dev context BA pointer */
179 183
180/* 5.4.7 Configure Register */ 184/* 5.4.7 Configure Register */
181#define XHCI_CONFIG 0x38 185#define XHCI_CONFIG 0x38
182#define XHCI_CONFIG_SLOTS_MASK __BITS(7, 0) /* RW - number of device slots enabled */ 186#define XHCI_CONFIG_SLOTS_MASK __BITS(7, 0) /* RW - number of device slots enabled */
183#define XHCI_CONFIG_U3E __BIT(8) /* RW - U3 Entry Enable */ 187#define XHCI_CONFIG_U3E __BIT(8) /* RW - U3 Entry Enable */
184#define XHCI_CONFIG_CIE __BIT(9) /* RW - Configuration Information Enable */ 188#define XHCI_CONFIG_CIE __BIT(9) /* RW - Configuration Information Enable */
185 189
186/* 5.4.8 XHCI port status registers */ 190/* 5.4.8 XHCI port status registers */
187#define XHCI_PORTSC(n) (0x3f0 + (0x10 * (n))) /* XHCI port status */ 191#define XHCI_PORTSC(n) (0x3f0 + (0x10 * (n))) /* XHCI port status */
188#define XHCI_PS_CCS __BIT(0) /* RO - current connect status */ 192#define XHCI_PS_CCS __BIT(0) /* RO - current connect status */
189#define XHCI_PS_PED __BIT(1) /* RW - port enabled / disabled */ 193#define XHCI_PS_PED __BIT(1) /* RW - port enabled / disabled */
190#define XHCI_PS_OCA __BIT(3) /* RO - over current active */ 194#define XHCI_PS_OCA __BIT(3) /* RO - over current active */
191#define XHCI_PS_PR __BIT(4) /* RW - port reset */ 195#define XHCI_PS_PR __BIT(4) /* RW - port reset */
192#define XHCI_PS_PLS_MASK __BITS(8, 5) /* RW - port link state */ 196#define XHCI_PS_PLS_MASK __BITS(8, 5) /* RW - port link state */
193#define XHCI_PS_PLS_GET(x) __SHIFTOUT((x), XHCI_PS_PLS_MASK) /* RW - port link state */ 197#define XHCI_PS_PLS_GET(x) __SHIFTOUT((x), XHCI_PS_PLS_MASK) /* RW - port link state */
194#define XHCI_PS_PLS_SET(x) __SHIFTIN((x), XHCI_PS_PLS_MASK) /* RW - port link state */ 198#define XHCI_PS_PLS_SET(x) __SHIFTIN((x), XHCI_PS_PLS_MASK) /* RW - port link state */
195 199
196#define XHCI_PS_PLS_SETU0 0 200#define XHCI_PS_PLS_SETU0 0
197#define XHCI_PS_PLS_SETU2 2 201#define XHCI_PS_PLS_SETU2 2
198#define XHCI_PS_PLS_SETU3 3 202#define XHCI_PS_PLS_SETU3 3
199#define XHCI_PS_PLS_SETDISC 5 203#define XHCI_PS_PLS_SETDISC 5
200#define XHCI_PS_PLS_SETCOMP 10 204#define XHCI_PS_PLS_SETCOMP 10
201#define XHCI_PS_PLS_SETRESUME 15 205#define XHCI_PS_PLS_SETRESUME 15
202 206
203#define XHCI_PS_PLS_U0 0 207#define XHCI_PS_PLS_U0 0
204#define XHCI_PS_PLS_U1 1 208#define XHCI_PS_PLS_U1 1
205#define XHCI_PS_PLS_U2 2 209#define XHCI_PS_PLS_U2 2
206#define XHCI_PS_PLS_U3 3 210#define XHCI_PS_PLS_U3 3
207#define XHCI_PS_PLS_DISABLED 4 211#define XHCI_PS_PLS_DISABLED 4
208#define XHCI_PS_PLS_RXDETECT 5 212#define XHCI_PS_PLS_RXDETECT 5
209#define XHCI_PS_PLS_INACTIVE 6 213#define XHCI_PS_PLS_INACTIVE 6
210#define XHCI_PS_PLS_POLLING 7 214#define XHCI_PS_PLS_POLLING 7
211#define XHCI_PS_PLS_RECOVERY 8 215#define XHCI_PS_PLS_RECOVERY 8
212#define XHCI_PS_PLS_HOTRESET 9 216#define XHCI_PS_PLS_HOTRESET 9
213#define XHCI_PS_PLS_COMPLIANCE 10 217#define XHCI_PS_PLS_COMPLIANCE 10
214#define XHCI_PS_PLS_TEST 11 218#define XHCI_PS_PLS_TEST 11
215#define XHCI_PS_PLS_RESUME 15 219#define XHCI_PS_PLS_RESUME 15
216 220
217#define XHCI_PS_PP __BIT(9) /* RW - port power */ 221#define XHCI_PS_PP __BIT(9) /* RW - port power */
218#define XHCI_PS_SPEED_MASK __BITS(13, 10) /* RO - port speed */ 222#define XHCI_PS_SPEED_MASK __BITS(13, 10) /* RO - port speed */
219#define XHCI_PS_SPEED_GET(x) __SHIFTOUT((x), XHCI_PS_SPEED_MASK) 223#define XHCI_PS_SPEED_GET(x) __SHIFTOUT((x), XHCI_PS_SPEED_MASK)
220#define XHCI_PS_SPEED_FS 1 224#define XHCI_PS_SPEED_FS 1
221#define XHCI_PS_SPEED_LS 2 225#define XHCI_PS_SPEED_LS 2
222#define XHCI_PS_SPEED_HS 3 226#define XHCI_PS_SPEED_HS 3
223#define XHCI_PS_SPEED_SS 4 227#define XHCI_PS_SPEED_SS 4
224#define XHCI_PS_PIC_MASK __BITS(15, 14) /* RW - port indicator */ 228#define XHCI_PS_PIC_MASK __BITS(15, 14) /* RW - port indicator */
225#define XHCI_PS_PIC_GET(x) __SHIFTOUT((x), XHCI_PS_PIC_MASK) 229#define XHCI_PS_PIC_GET(x) __SHIFTOUT((x), XHCI_PS_PIC_MASK)
226#define XHCI_PS_PIC_SET(x) __SHIFTIN((x), XHCI_PS_PIC_MASK) 230#define XHCI_PS_PIC_SET(x) __SHIFTIN((x), XHCI_PS_PIC_MASK)
227#define XHCI_PS_LWS __BIT(16) /* RW - port link state write strobe */ 231#define XHCI_PS_LWS __BIT(16) /* RW - port link state write strobe */
228#define XHCI_PS_CSC __BIT(17) /* RW - connect status change */ 232#define XHCI_PS_CSC __BIT(17) /* RW - connect status change */
229#define XHCI_PS_PEC __BIT(18) /* RW - port enable/disable change */ 233#define XHCI_PS_PEC __BIT(18) /* RW - port enable/disable change */
230#define XHCI_PS_WRC __BIT(19) /* RW - warm port reset change */ 234#define XHCI_PS_WRC __BIT(19) /* RW - warm port reset change */
231#define XHCI_PS_OCC __BIT(20) /* RW - over-current change */ 235#define XHCI_PS_OCC __BIT(20) /* RW - over-current change */
232#define XHCI_PS_PRC __BIT(21) /* RW - port reset change */ 236#define XHCI_PS_PRC __BIT(21) /* RW - port reset change */
233#define XHCI_PS_PLC __BIT(22) /* RW - port link state change */ 237#define XHCI_PS_PLC __BIT(22) /* RW - port link state change */
234#define XHCI_PS_CEC __BIT(23) /* RW - config error change */ 238#define XHCI_PS_CEC __BIT(23) /* RW - config error change */
235#define XHCI_PS_CAS __BIT(24) /* RO - cold attach status */ 239#define XHCI_PS_CAS __BIT(24) /* RO - cold attach status */
236#define XHCI_PS_WCE __BIT(25) /* RW - wake on connect enable */ 240#define XHCI_PS_WCE __BIT(25) /* RW - wake on connect enable */
237#define XHCI_PS_WDE __BIT(26) /* RW - wake on disconnect enable */ 241#define XHCI_PS_WDE __BIT(26) /* RW - wake on disconnect enable */
238#define XHCI_PS_WOE __BIT(27) /* RW - wake on over-current enable */ 242#define XHCI_PS_WOE __BIT(27) /* RW - wake on over-current enable */
239#define XHCI_PS_DR __BIT(30) /* RO - device removable */ 243#define XHCI_PS_DR __BIT(30) /* RO - device removable */
240#define XHCI_PS_WPR __BIT(31) /* RW - warm port reset */ 244#define XHCI_PS_WPR __BIT(31) /* RW - warm port reset */
241#define XHCI_PS_CLEAR 0x80FF01FFU /* command bits */ 245#define XHCI_PS_CLEAR 0x80FF01FFU /* command bits */
242 246
243/* 5.4.9 Port PM Status and Control Register */ 247/* 5.4.9 Port PM Status and Control Register */
244#define XHCI_PORTPMSC(n) (0x3f4 + (0x10 * (n))) /* XHCI status and control */ 248#define XHCI_PORTPMSC(n) (0x3f4 + (0x10 * (n))) /* XHCI status and control */
245/* 5.4.9.1 */ 249/* 5.4.9.1 */
246#define XHCI_PM3_U1TO_MASK __BITS(7, 0) /* RW - U1 timeout */ 250#define XHCI_PM3_U1TO_MASK __BITS(7, 0) /* RW - U1 timeout */
247#define XHCI_PM3_U1TO_GET(x) __SHIFTOUT((x), XHCI_PM3_U1TO_MASK) 251#define XHCI_PM3_U1TO_GET(x) __SHIFTOUT((x), XHCI_PM3_U1TO_MASK)
248#define XHCI_PM3_U1TO_SET(x) __SHIFTIN((x), XHCI_PM3_U1TO_MASK) 252#define XHCI_PM3_U1TO_SET(x) __SHIFTIN((x), XHCI_PM3_U1TO_MASK)
249#define XHCI_PM3_U2TO_MASK __BITS(15, 8) /* RW - U2 timeout */ 253#define XHCI_PM3_U2TO_MASK __BITS(15, 8) /* RW - U2 timeout */
250#define XHCI_PM3_U2TO_GET(x) __SHIFTOUT((x), XHCI_PM3_U2TO_MASK) 254#define XHCI_PM3_U2TO_GET(x) __SHIFTOUT((x), XHCI_PM3_U2TO_MASK)
251#define XHCI_PM3_U2TO_SET(x) __SHIFTIN((x), XHCI_PM3_U2TO_MASK) 255#define XHCI_PM3_U2TO_SET(x) __SHIFTIN((x), XHCI_PM3_U2TO_MASK)
252#define XHCI_PM3_FLA __BIT(16) /* RW - Force Link PM Accept */ 256#define XHCI_PM3_FLA __BIT(16) /* RW - Force Link PM Accept */
253 257
254/* 5.4.9.2 */ 258/* 5.4.9.2 */
255#define XHCI_PM2_L1S_MASK __BITS(2, 0) /* RO - L1 status */ 259#define XHCI_PM2_L1S_MASK __BITS(2, 0) /* RO - L1 status */
256#define XHCI_PM2_L1S_GET(x) __SHIFTOUT((x), XHCI_PM2_L1S_MASK) 260#define XHCI_PM2_L1S_GET(x) __SHIFTOUT((x), XHCI_PM2_L1S_MASK)
257#define XHCI_PM2_RWE __BIT(3) /* RW - remote wakup enable */ 261#define XHCI_PM2_RWE __BIT(3) /* RW - remote wakup enable */
258#define XHCI_PM2_BESL_MASK __BITS(7, 4) /* RW - Best Effort Service Latency */ 262#define XHCI_PM2_BESL_MASK __BITS(7, 4) /* RW - Best Effort Service Latency */
259#define XHCI_PM2_BESL_GET(x) __SHIFTOUT((x), XHCI_PM2_BESL_MASK) 263#define XHCI_PM2_BESL_GET(x) __SHIFTOUT((x), XHCI_PM2_BESL_MASK)
260#define XHCI_PM2_BESL_SET(x) __SHIFTIN((x), XHCI_PM2_BESL_MASK) 264#define XHCI_PM2_BESL_SET(x) __SHIFTIN((x), XHCI_PM2_BESL_MASK)
261#define XHCI_PM2_L1SLOT_MASK __BITS(15, 8) /* RW - L1 device slot */ 265#define XHCI_PM2_L1SLOT_MASK __BITS(15, 8) /* RW - L1 device slot */
262#define XHCI_PM2_L1SLOT_GET(x) __SHIFTOUT((x), XHCI_PM2_L1SLOT_MASK) 266#define XHCI_PM2_L1SLOT_GET(x) __SHIFTOUT((x), XHCI_PM2_L1SLOT_MASK)
263#define XHCI_PM2_L1SLOT_SET(x) __SHIFTIN((x), XHCI_PM2_L1SLOT_MASK) 267#define XHCI_PM2_L1SLOT_SET(x) __SHIFTIN((x), XHCI_PM2_L1SLOT_MASK)
264#define XHCI_PM2_HLE __BIT(16) /* RW - hardware LPM enable */ 268#define XHCI_PM2_HLE __BIT(16) /* RW - hardware LPM enable */
265#define XHCI_PM2_PTC_MASK __BITS(31, 28) /* RW - port test control */ 269#define XHCI_PM2_PTC_MASK __BITS(31, 28) /* RW - port test control */
266#define XHCI_PM2_PTC_GET(x) __SHIFTOUT((x), XHCI_PM2_PTC_MASK) 270#define XHCI_PM2_PTC_GET(x) __SHIFTOUT((x), XHCI_PM2_PTC_MASK)
267#define XHCI_PM2_PTC_SET(x) __SHIFTOUT((x), XHCI_PM2_PTC_MASK) 271#define XHCI_PM2_PTC_SET(x) __SHIFTOUT((x), XHCI_PM2_PTC_MASK)
268 272
269/* 5.4.10 Port Link Info Register */ 273/* 5.4.10 Port Link Info Register */
270#define XHCI_PORTLI(n) (0x3f8 + (0x10 * (n))) /* XHCI port link info */ 274#define XHCI_PORTLI(n) (0x3f8 + (0x10 * (n))) /* XHCI port link info */
271/* 5.4.10.1 */ 275/* 5.4.10.1 */
272#define XHCI_PLI3_ERR_MASK __BITS(15, 0) /* RW - port link errors */ 276#define XHCI_PLI3_ERR_MASK __BITS(15, 0) /* RW - port link errors */
273#define XHCI_PLI3_ERR_GET(x) __SHIFTOUT((x), XHCI_PLI3_ERR_MASK) 277#define XHCI_PLI3_ERR_GET(x) __SHIFTOUT((x), XHCI_PLI3_ERR_MASK)
274#define XHCI_PLI3_RLC_MASK __BITS(19, 16) /* RO - Rx Lane Count */ 278#define XHCI_PLI3_RLC_MASK __BITS(19, 16) /* RO - Rx Lane Count */
275#define XHCI_PLI3_RLC_GET __SHIFTOUT((x), XHCI_PLI3_RLC_MASK) 279#define XHCI_PLI3_RLC_GET __SHIFTOUT((x), XHCI_PLI3_RLC_MASK)
276#define XHCI_PLI3_TLC_MASK __BITS(23, 20) /* RO - Tx Lane Count */ 280#define XHCI_PLI3_TLC_MASK __BITS(23, 20) /* RO - Tx Lane Count */
277#define XHCI_PLI3_TLC_GET __SHIFTOUT((x), XHCI_PLI3_TLC_MASK) 281#define XHCI_PLI3_TLC_GET __SHIFTOUT((x), XHCI_PLI3_TLC_MASK)
278 282
279/* 5.4.11 */ 283/* 5.4.11 */
280#define XHCI_PORTHLPMC(n) (0x3fc + (0x10 * (n))) /* XHCI port hardware LPM control */ 284#define XHCI_PORTHLPMC(n) (0x3fc + (0x10 * (n))) /* XHCI port hardware LPM control */
281/* 5.4.11.1 */ 285/* 5.4.11.1 */
282#define XHCI_PLMC3_LSEC_MASK __BITS(15, 0) /* RW - Link Soft Error Count */ 286#define XHCI_PLMC3_LSEC_MASK __BITS(15, 0) /* RW - Link Soft Error Count */
283#define XHCI_PLMC3_LSEC_GET(x) __SHIFTOUT((x), XHCI_PLMC3_LSEC_MASK) 287#define XHCI_PLMC3_LSEC_GET(x) __SHIFTOUT((x), XHCI_PLMC3_LSEC_MASK)
284 288
285/* 5.5.1 */ 289/* 5.5.1 */
286/* XHCI runtime registers. Offset given by XHCI_CAPLENGTH + XHCI_RTSOFF registers */ 290/* XHCI runtime registers. Offset given by XHCI_CAPLENGTH + XHCI_RTSOFF registers */
287#define XHCI_MFINDEX 0x0000 291#define XHCI_MFINDEX 0x0000
288#define XHCI_MFINDEX_MASK __BITS(13, 0) /* RO - microframe index */ 292#define XHCI_MFINDEX_MASK __BITS(13, 0) /* RO - microframe index */
289#define XHCI_MFINDEX_GET(x) __SHIFTOUT((x), XHCI_MFINDEX_MASK) 293#define XHCI_MFINDEX_GET(x) __SHIFTOUT((x), XHCI_MFINDEX_MASK)
290 294
291/* 5.5.2 Interrupter Register set */ 295/* 5.5.2 Interrupter Register set */
292/* 5.5.2.1 interrupt management */ 296/* 5.5.2.1 interrupt management */
293#define XHCI_IMAN(n) (0x0020 + (0x20 * (n))) 297#define XHCI_IMAN(n) (0x0020 + (0x20 * (n)))
294#define XHCI_IMAN_INTR_PEND __BIT(0) /* RW - interrupt pending */ 298#define XHCI_IMAN_INTR_PEND __BIT(0) /* RW - interrupt pending */
295#define XHCI_IMAN_INTR_ENA __BIT(1) /* RW - interrupt enable */ 299#define XHCI_IMAN_INTR_ENA __BIT(1) /* RW - interrupt enable */
296 300
297/* 5.5.2.2 Interrupter Moderation */ 301/* 5.5.2.2 Interrupter Moderation */
298#define XHCI_IMOD(n) (0x0024 + (0x20 * (n))) /* XHCI interrupt moderation */ 302#define XHCI_IMOD(n) (0x0024 + (0x20 * (n))) /* XHCI interrupt moderation */
299#define XHCI_IMOD_IVAL_MASK __BITS(15,0) /* 250ns unit */ 303#define XHCI_IMOD_IVAL_MASK __BITS(15,0) /* 250ns unit */
300#define XHCI_IMOD_IVAL_GET(x) __SHIFTOUT((x), XHCI_IMOD_IVAL_MASK) 304#define XHCI_IMOD_IVAL_GET(x) __SHIFTOUT((x), XHCI_IMOD_IVAL_MASK)
301#define XHCI_IMOD_IVAL_SET(x) __SHIFTIN((x), XHCI_IMOD_IVAL_MASK) 305#define XHCI_IMOD_IVAL_SET(x) __SHIFTIN((x), XHCI_IMOD_IVAL_MASK)
302#define XHCI_IMOD_ICNT_MASK __BITS(31, 16) /* 250ns unit */ 306#define XHCI_IMOD_ICNT_MASK __BITS(31, 16) /* 250ns unit */
303#define XHCI_IMOD_ICNT_GET(x) __SHIFTOUT((x), XHCI_IMOD_ICNT_MASK) 307#define XHCI_IMOD_ICNT_GET(x) __SHIFTOUT((x), XHCI_IMOD_ICNT_MASK)
304#define XHCI_IMOD_ICNT_SET(x) __SHIFTIN((x), XHCI_IMOD_ICNT_MASK) 308#define XHCI_IMOD_ICNT_SET(x) __SHIFTIN((x), XHCI_IMOD_ICNT_MASK)
305#define XHCI_IMOD_DEFAULT 0x000001F4U /* 8000 IRQ/second */ 309#define XHCI_IMOD_DEFAULT 0x000001F4U /* 8000 IRQ/second */
306#define XHCI_IMOD_DEFAULT_LP 0x000003E8U /* 4000 IRQ/sec for LynxPoint */ 310#define XHCI_IMOD_DEFAULT_LP 0x000003E8U /* 4000 IRQ/sec for LynxPoint */
307 311
308/* 5.5.2.3 Event Ring */ 312/* 5.5.2.3 Event Ring */
309/* 5.5.2.3.1 Event Ring Segment Table Size */ 313/* 5.5.2.3.1 Event Ring Segment Table Size */
310#define XHCI_ERSTSZ(n) (0x0028 + (0x20 * (n))) 314#define XHCI_ERSTSZ(n) (0x0028 + (0x20 * (n)))
311#define XHCI_ERSTS_MASK __BITS(15, 0) /* Event Ring Segment Table Size */ 315#define XHCI_ERSTS_MASK __BITS(15, 0) /* Event Ring Segment Table Size */
312#define XHCI_ERSTS_GET(x) __SHIFTOUT((x), XHCI_ERSTS_MASK) 316#define XHCI_ERSTS_GET(x) __SHIFTOUT((x), XHCI_ERSTS_MASK)
313#define XHCI_ERSTS_SET(x) __SHIFTIN((x), XHCI_ERSTS_MASK) 317#define XHCI_ERSTS_SET(x) __SHIFTIN((x), XHCI_ERSTS_MASK)
314 318
315/* 5.5.2.3.2 Event Ring Segment Table Base Address Register */ 319/* 5.5.2.3.2 Event Ring Segment Table Base Address Register */
316#define XHCI_ERSTBA(n) (0x0030 + (0x20 * (n))) 320#define XHCI_ERSTBA(n) (0x0030 + (0x20 * (n)))
317#define XHCI_ERSTBA_MASK __BIT(31,6) /* RW - segment base address (low) */ 321#define XHCI_ERSTBA_MASK __BIT(31,6) /* RW - segment base address (low) */
318#define XHCI_ERSTBA_HI(n) (0x0034 + (0x20 * (n))) 322#define XHCI_ERSTBA_HI(n) (0x0034 + (0x20 * (n)))
319 323
320/* 5.5.2.3.3 Event Ring Dequeue Pointer */ 324/* 5.5.2.3.3 Event Ring Dequeue Pointer */
321#define XHCI_ERDP(n) (0x0038 + (0x20 * (n))) 325#define XHCI_ERDP(n) (0x0038 + (0x20 * (n)))
322#define XHCI_ERDP_DESI_MASK __BITS(2,0) /* RO - dequeue segment index */ 326#define XHCI_ERDP_DESI_MASK __BITS(2,0) /* RO - dequeue segment index */
323#define XHCI_ERDP_GET_DESI(x) __SHIFTOUT(x), XHCI_ERDP_DESI_MASK) 327#define XHCI_ERDP_GET_DESI(x) __SHIFTOUT(x), XHCI_ERDP_DESI_MASK)
324#define XHCI_ERDP_BUSY __BIT(3) /* RW - event handler busy */ 328#define XHCI_ERDP_BUSY __BIT(3) /* RW - event handler busy */
325#define XHCI_ERDP_PTRLO_MASK __BIT(31,4) /* RW - dequeue pointer (low) */ 329#define XHCI_ERDP_PTRLO_MASK __BIT(31,4) /* RW - dequeue pointer (low) */
326#define XHCI_ERDP_HI(n) (0x003C + (0x20 * (n))) 330#define XHCI_ERDP_HI(n) (0x003C + (0x20 * (n)))
327 331
328/* 5.6 XHCI doorbell registers. Offset given by XHCI_CAPLENGTH + XHCI_DBOFF registers */ 332/* 5.6 XHCI doorbell registers. Offset given by XHCI_CAPLENGTH + XHCI_DBOFF registers */
329#define XHCI_DOORBELL(n) (0x0000 + (4 * (n))) 333#define XHCI_DOORBELL(n) (0x0000 + (4 * (n)))
330#define XHCI_DB_TARGET_MASK __BITS(7, 0) /* RW - doorbell target */ 334#define XHCI_DB_TARGET_MASK __BITS(7, 0) /* RW - doorbell target */
331#define XHCI_DB_TARGET_GET(x) __SHIFTOUT((x), XHCI_DB_TARGET_MASK) 335#define XHCI_DB_TARGET_GET(x) __SHIFTOUT((x), XHCI_DB_TARGET_MASK)
332#define XHCI_DB_TARGET_SET(x) __SHIFTIN((x), XHCI_DB_TARGET_MASK) 336#define XHCI_DB_TARGET_SET(x) __SHIFTIN((x), XHCI_DB_TARGET_MASK)
333#define XHCI_DB_SID_MASK __BITS(31, 16) /* RW - doorbell stream ID */ 337#define XHCI_DB_SID_MASK __BITS(31, 16) /* RW - doorbell stream ID */
334#define XHCI_DB_SID_GET(x) __SHIFTOUT((x), XHCI_DB_SID_MASK) 338#define XHCI_DB_SID_GET(x) __SHIFTOUT((x), XHCI_DB_SID_MASK)
335#define XHCI_DB_SID_SET(x) __SHIFTIN((x), XHCI_DB_SID_MASK) 339#define XHCI_DB_SID_SET(x) __SHIFTIN((x), XHCI_DB_SID_MASK)
336 340
337/* 7 xHCI Extendeded capabilities */ 341/* 7 xHCI Extendeded capabilities */
338#define XHCI_XECP_ID_MASK __BITS(7, 0) 342#define XHCI_XECP_ID_MASK __BITS(7, 0)
339#define XHCI_XECP_ID(x) __SHIFTOUT((x), XHCI_XECP_ID_MASK) 343#define XHCI_XECP_ID(x) __SHIFTOUT((x), XHCI_XECP_ID_MASK)
340#define XHCI_XECP_NEXT_MASK __BITS(15, 8) 344#define XHCI_XECP_NEXT_MASK __BITS(15, 8)
341#define XHCI_XECP_NEXT(x) __SHIFTOUT((x), XHCI_XECP_NEXT_MASK) 345#define XHCI_XECP_NEXT(x) __SHIFTOUT((x), XHCI_XECP_NEXT_MASK)
342 346
343/* XHCI extended capability ID's */ 347/* XHCI extended capability ID's */
344#define XHCI_ID_USB_LEGACY 0x0001 /* USB Legacy Support */ 348#define XHCI_ID_USB_LEGACY 0x0001 /* USB Legacy Support */
345#define XHCI_XECP_USBLEGSUP 0x0000 /* Legacy Support Capability Reg */ 349#define XHCI_XECP_USBLEGSUP 0x0000 /* Legacy Support Capability Reg */
346#define XHCI_XECP_USBLEGCTLSTS 0x0004 /* Legacy Support Ctrl & Status Reg */ 350#define XHCI_XECP_USBLEGCTLSTS 0x0004 /* Legacy Support Ctrl & Status Reg */
347#define XHCI_ID_PROTOCOLS 0x0002 /* Supported Protocol */ 351#define XHCI_ID_PROTOCOLS 0x0002 /* Supported Protocol */
348#define XHCI_ID_POWER_MGMT 0x0003 /* Extended Power Management */ 352#define XHCI_ID_POWER_MGMT 0x0003 /* Extended Power Management */
349#define XHCI_ID_VIRTUALIZATION 0x0004 /* I/O Virtualization */ 353#define XHCI_ID_VIRTUALIZATION 0x0004 /* I/O Virtualization */
350#define XHCI_ID_MSG_IRQ 0x0005 /* Message Interrupt */ 354#define XHCI_ID_MSG_IRQ 0x0005 /* Message Interrupt */
351#define XHCI_ID_USB_LOCAL_MEM 0x0006 /* Local Memory */ 355#define XHCI_ID_USB_LOCAL_MEM 0x0006 /* Local Memory */
352#define XHCI_ID_USB_DEBUG 0x000A /* USB Debug Capability */ 356#define XHCI_ID_USB_DEBUG 0x000A /* USB Debug Capability */
353#define XHCI_ID_XMSG_IRQ 0x0011 /* Extended Message Interrupt */ 357#define XHCI_ID_XMSG_IRQ 0x0011 /* Extended Message Interrupt */
354 358
355/* 7.1 xHCI legacy support */ 359/* 7.1 xHCI legacy support */
356#define XHCI_XECP_BIOS_SEM 0x0002 360#define XHCI_XECP_BIOS_SEM 0x0002
357#define XHCI_XECP_OS_SEM 0x0003 361#define XHCI_XECP_OS_SEM 0x0003
358 362
359/* 7.2 xHCI Supported Protocol Capability */ 363/* 7.2 xHCI Supported Protocol Capability */
360#define XHCI_XECP_USBID 0x20425355 364#define XHCI_XECP_USBID 0x20425355
361 365
362#define XHCI_XECP_SP_W0_MINOR_MASK __BITS(23, 16) 366#define XHCI_XECP_SP_W0_MINOR_MASK __BITS(23, 16)
363#define XHCI_XECP_SP_W0_MINOR(x) __SHIFTOUT((x), XHCI_XECP_SP_W0_MINOR_MASK) 367#define XHCI_XECP_SP_W0_MINOR(x) __SHIFTOUT((x), XHCI_XECP_SP_W0_MINOR_MASK)
364#define XHCI_XECP_SP_W0_MAJOR_MASK __BITS(31, 24) 368#define XHCI_XECP_SP_W0_MAJOR_MASK __BITS(31, 24)
365#define XHCI_XECP_SP_W0_MAJOR(x) __SHIFTOUT((x), XHCI_XECP_SP_W0_MAJOR_MASK) 369#define XHCI_XECP_SP_W0_MAJOR(x) __SHIFTOUT((x), XHCI_XECP_SP_W0_MAJOR_MASK)
366 370
367#define XHCI_XECP_SP_W8_CPO_MASK __BITS(7, 0) 371#define XHCI_XECP_SP_W8_CPO_MASK __BITS(7, 0)
368#define XHCI_XECP_SP_W8_CPO(x) __SHIFTOUT((x), XHCI_XECP_SP_W8_CPO_MASK) 372#define XHCI_XECP_SP_W8_CPO(x) __SHIFTOUT((x), XHCI_XECP_SP_W8_CPO_MASK)
369#define XHCI_XECP_SP_W8_CPC_MASK __BITS(15, 8) 373#define XHCI_XECP_SP_W8_CPC_MASK __BITS(15, 8)
370#define XHCI_XECP_SP_W8_CPC(x) __SHIFTOUT((x), XHCI_XECP_SP_W8_CPC_MASK) 374#define XHCI_XECP_SP_W8_CPC(x) __SHIFTOUT((x), XHCI_XECP_SP_W8_CPC_MASK)
371#define XHCI_XECP_SP_W8_PD_MASK __BITS(27, 16) 375#define XHCI_XECP_SP_W8_PD_MASK __BITS(27, 16)
372#define XHCI_XECP_SP_W8_PD(x) __SHIFTOUT((x), XHCI_XECP_SP_W8_PD_MASK) 376#define XHCI_XECP_SP_W8_PD(x) __SHIFTOUT((x), XHCI_XECP_SP_W8_PD_MASK)
373#define XHCI_XECP_SP_W8_PSIC_MASK __BITS(31, 28) 377#define XHCI_XECP_SP_W8_PSIC_MASK __BITS(31, 28)
374#define XHCI_XECP_SP_W8_PSIC(x) __SHIFTOUT((x), XHCI_XECP_SP_W8_PSIC_MASK) 378#define XHCI_XECP_SP_W8_PSIC(x) __SHIFTOUT((x), XHCI_XECP_SP_W8_PSIC_MASK)
375 379
376#define XHCI_PAGE_SIZE(sc) ((sc)->sc_pgsz) 380#define XHCI_PAGE_SIZE(sc) ((sc)->sc_pgsz)
377 381
378/* Chapter 6, Table 49 */ 382/* Chapter 6, Table 49 */
379#define XHCI_DEVICE_CONTEXT_BASE_ADDRESS_ARRAY_ALIGN 64 383#define XHCI_DEVICE_CONTEXT_BASE_ADDRESS_ARRAY_ALIGN 64
380#define XHCI_DEVICE_CONTEXT_ALIGN 64 384#define XHCI_DEVICE_CONTEXT_ALIGN 64
381#define XHCI_INPUT_CONTROL_CONTEXT_ALIGN 64 385#define XHCI_INPUT_CONTROL_CONTEXT_ALIGN 64
382#define XHCI_SLOT_CONTEXT_ALIGN 32 386#define XHCI_SLOT_CONTEXT_ALIGN 32
383#define XHCI_ENDPOINT_CONTEXT_ALIGN 32 387#define XHCI_ENDPOINT_CONTEXT_ALIGN 32
384#define XHCI_STREAM_CONTEXT_ALIGN 16 388#define XHCI_STREAM_CONTEXT_ALIGN 16
385#define XHCI_STREAM_ARRAY_ALIGN 16 389#define XHCI_STREAM_ARRAY_ALIGN 16
386#define XHCI_TRANSFER_RING_SEGMENTS_ALIGN 16 390#define XHCI_TRANSFER_RING_SEGMENTS_ALIGN 16
387#define XHCI_COMMAND_RING_SEGMENTS_ALIGN 64 391#define XHCI_COMMAND_RING_SEGMENTS_ALIGN 64
388#define XHCI_EVENT_RING_SEGMENTS_ALIGN 64 392#define XHCI_EVENT_RING_SEGMENTS_ALIGN 64
389#define XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN 64 393#define XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN 64
390#define XHCI_SCRATCHPAD_BUFFER_ARRAY_ALIGN 64 394#define XHCI_SCRATCHPAD_BUFFER_ARRAY_ALIGN 64
391#define XHCI_SCRATCHPAD_BUFFERS_ALIGN XHCI_PAGE_SIZE 395#define XHCI_SCRATCHPAD_BUFFERS_ALIGN XHCI_PAGE_SIZE
392 396
393#define XHCI_ERSTE_ALIGN 16 397#define XHCI_ERSTE_ALIGN 16
394#define XHCI_TRB_ALIGN 16 398#define XHCI_TRB_ALIGN 16
395 399
396struct xhci_trb { 400struct xhci_trb {
397 uint64_t trb_0; 401 uint64_t trb_0;
398 uint32_t trb_2; 402 uint32_t trb_2;
399#define XHCI_TRB_2_ERROR_MASK __BITS(31, 24) 403#define XHCI_TRB_2_ERROR_MASK __BITS(31, 24)
400#define XHCI_TRB_2_ERROR_GET(x) __SHIFTOUT((x), XHCI_TRB_2_ERROR_MASK) 404#define XHCI_TRB_2_ERROR_GET(x) __SHIFTOUT((x), XHCI_TRB_2_ERROR_MASK)
401#define XHCI_TRB_2_ERROR_SET(x) __SHIFTIN((x), XHCI_TRB_2_ERROR_MASK) 405#define XHCI_TRB_2_ERROR_SET(x) __SHIFTIN((x), XHCI_TRB_2_ERROR_MASK)
402 406
403#define XHCI_TRB_2_TDSZ_MASK __BITS(21, 17) /* TD Size */ 407#define XHCI_TRB_2_TDSZ_MASK __BITS(21, 17) /* TD Size */
404#define XHCI_TRB_2_TDSZ_GET(x) __SHIFTOUT((x), XHCI_TRB_2_TDSZ_MASK) 408#define XHCI_TRB_2_TDSZ_GET(x) __SHIFTOUT((x), XHCI_TRB_2_TDSZ_MASK)
405#define XHCI_TRB_2_TDSZ_SET(x) __SHIFTIN((x), XHCI_TRB_2_TDSZ_MASK) 409#define XHCI_TRB_2_TDSZ_SET(x) __SHIFTIN((x), XHCI_TRB_2_TDSZ_MASK)
406#define XHCI_TRB_2_REM_MASK __BITS(23, 0) 410#define XHCI_TRB_2_REM_MASK __BITS(23, 0)
407#define XHCI_TRB_2_REM_GET(x) __SHIFTOUT((x), XHCI_TRB_2_REM_MASK) 411#define XHCI_TRB_2_REM_GET(x) __SHIFTOUT((x), XHCI_TRB_2_REM_MASK)
408#define XHCI_TRB_2_REM_SET(x) __SHIFTIN((x), XHCI_TRB_2_REM_MASK) 412#define XHCI_TRB_2_REM_SET(x) __SHIFTIN((x), XHCI_TRB_2_REM_MASK)
409 413
410#define XHCI_TRB_2_BYTES_MASK __BITS(16, 0) 414#define XHCI_TRB_2_BYTES_MASK __BITS(16, 0)
411#define XHCI_TRB_2_BYTES_GET(x) __SHIFTOUT((x), XHCI_TRB_2_BYTES_MASK) 415#define XHCI_TRB_2_BYTES_GET(x) __SHIFTOUT((x), XHCI_TRB_2_BYTES_MASK)
412#define XHCI_TRB_2_BYTES_SET(x) __SHIFTIN((x), XHCI_TRB_2_BYTES_MASK) 416#define XHCI_TRB_2_BYTES_SET(x) __SHIFTIN((x), XHCI_TRB_2_BYTES_MASK)
413#define XHCI_TRB_2_IRQ_MASK __BITS(31, 22) 417#define XHCI_TRB_2_IRQ_MASK __BITS(31, 22)
414#define XHCI_TRB_2_IRQ_GET(x) __SHIFTOUT((x), XHCI_TRB_2_IRQ_MASK) 418#define XHCI_TRB_2_IRQ_GET(x) __SHIFTOUT((x), XHCI_TRB_2_IRQ_MASK)
415#define XHCI_TRB_2_IRQ_SET(x) __SHIFTIN((x), XHCI_TRB_2_IRQ_MASK) 419#define XHCI_TRB_2_IRQ_SET(x) __SHIFTIN((x), XHCI_TRB_2_IRQ_MASK)
416#define XHCI_TRB_2_STREAM_MASK __BITS(31, 16) 420#define XHCI_TRB_2_STREAM_MASK __BITS(31, 16)
417#define XHCI_TRB_2_STREAM_GET(x) __SHIFTOUT((x), XHCI_TRB_2_STREAM_MASK) 421#define XHCI_TRB_2_STREAM_GET(x) __SHIFTOUT((x), XHCI_TRB_2_STREAM_MASK)
418#define XHCI_TRB_2_STREAM_SET(x) __SHIFTIN((x), XHCI_TRB_2_STREAM_MASK) 422#define XHCI_TRB_2_STREAM_SET(x) __SHIFTIN((x), XHCI_TRB_2_STREAM_MASK)
419 uint32_t trb_3; 423 uint32_t trb_3;
420#define XHCI_TRB_3_TYPE_MASK __BITS(15, 10) 424#define XHCI_TRB_3_TYPE_MASK __BITS(15, 10)
421#define XHCI_TRB_3_TYPE_GET(x) __SHIFTOUT((x), XHCI_TRB_3_TYPE_MASK) 425#define XHCI_TRB_3_TYPE_GET(x) __SHIFTOUT((x), XHCI_TRB_3_TYPE_MASK)
422#define XHCI_TRB_3_TYPE_SET(x) __SHIFTIN((x), XHCI_TRB_3_TYPE_MASK) 426#define XHCI_TRB_3_TYPE_SET(x) __SHIFTIN((x), XHCI_TRB_3_TYPE_MASK)
423#define XHCI_TRB_3_CYCLE_BIT __BIT(0) 427#define XHCI_TRB_3_CYCLE_BIT __BIT(0)
424#define XHCI_TRB_3_TC_BIT __BIT(1) /* command ring only */ 428#define XHCI_TRB_3_TC_BIT __BIT(1) /* command ring only */
425#define XHCI_TRB_3_ENT_BIT __BIT(1) /* transfer ring only */ 429#define XHCI_TRB_3_ENT_BIT __BIT(1) /* transfer ring only */
426#define XHCI_TRB_3_ISP_BIT __BIT(2) 430#define XHCI_TRB_3_ISP_BIT __BIT(2)
427#define XHCI_TRB_3_NSNOOP_BIT __BIT(3) 431#define XHCI_TRB_3_NSNOOP_BIT __BIT(3)
428#define XHCI_TRB_3_CHAIN_BIT __BIT(4) 432#define XHCI_TRB_3_CHAIN_BIT __BIT(4)
429#define XHCI_TRB_3_IOC_BIT __BIT(5) 433#define XHCI_TRB_3_IOC_BIT __BIT(5)
430#define XHCI_TRB_3_IDT_BIT __BIT(6) 434#define XHCI_TRB_3_IDT_BIT __BIT(6)
431#define XHCI_TRB_3_TBC_MASK __BITS(8, 7) 435#define XHCI_TRB_3_TBC_MASK __BITS(8, 7)
432#define XHCI_TRB_3_TBC_GET(x) __SHIFTOUT((x), XHCI_TRB_3_TBC_MASK) 436#define XHCI_TRB_3_TBC_GET(x) __SHIFTOUT((x), XHCI_TRB_3_TBC_MASK)
433#define XHCI_TRB_3_TBC_SET(x) __SHIFTIN((x), XHCI_TRB_3_TBC_MASK) 437#define XHCI_TRB_3_TBC_SET(x) __SHIFTIN((x), XHCI_TRB_3_TBC_MASK)
434#define XHCI_TRB_3_BEI_BIT __BIT(9) 438#define XHCI_TRB_3_BEI_BIT __BIT(9)
435#define XHCI_TRB_3_DCEP_BIT __BIT(9) 439#define XHCI_TRB_3_DCEP_BIT __BIT(9)
436#define XHCI_TRB_3_PRSV_BIT __BIT(9) 440#define XHCI_TRB_3_PRSV_BIT __BIT(9)
437#define XHCI_TRB_3_BSR_BIT __BIT(9) 441#define XHCI_TRB_3_BSR_BIT __BIT(9)
438 442
439#define XHCI_TRB_3_TRT_MASK __BITS(17, 16) 443#define XHCI_TRB_3_TRT_MASK __BITS(17, 16)
440#define XHCI_TRB_3_TRT_NONE __SHIFTIN(0U, XHCI_TRB_3_TRT_MASK) 444#define XHCI_TRB_3_TRT_NONE __SHIFTIN(0U, XHCI_TRB_3_TRT_MASK)
441#define XHCI_TRB_3_TRT_OUT __SHIFTIN(2U, XHCI_TRB_3_TRT_MASK) 445#define XHCI_TRB_3_TRT_OUT __SHIFTIN(2U, XHCI_TRB_3_TRT_MASK)
442#define XHCI_TRB_3_TRT_IN __SHIFTIN(3U, XHCI_TRB_3_TRT_MASK) 446#define XHCI_TRB_3_TRT_IN __SHIFTIN(3U, XHCI_TRB_3_TRT_MASK)
443#define XHCI_TRB_3_DIR_IN __BIT(16) 447#define XHCI_TRB_3_DIR_IN __BIT(16)
444#define XHCI_TRB_3_TLBPC_MASK __BITS(19, 16) 448#define XHCI_TRB_3_TLBPC_MASK __BITS(19, 16)
445#define XHCI_TRB_3_TLBPC_GET(x) __SHIFTOUT((x), XHCI_TRB_3_TLBPC_MASK) 449#define XHCI_TRB_3_TLBPC_GET(x) __SHIFTOUT((x), XHCI_TRB_3_TLBPC_MASK)
446#define XHCI_TRB_3_TLBPC_SET(x) __SHIFTIN((x), XHCI_TRB_3_TLBPC_MASK) 450#define XHCI_TRB_3_TLBPC_SET(x) __SHIFTIN((x), XHCI_TRB_3_TLBPC_MASK)
447#define XHCI_TRB_3_EP_MASK __BITS(20, 16) 451#define XHCI_TRB_3_EP_MASK __BITS(20, 16)
448#define XHCI_TRB_3_EP_GET(x) __SHIFTOUT((x), XHCI_TRB_3_EP_MASK) 452#define XHCI_TRB_3_EP_GET(x) __SHIFTOUT((x), XHCI_TRB_3_EP_MASK)
449#define XHCI_TRB_3_EP_SET(x) __SHIFTIN((x), XHCI_TRB_3_EP_MASK) 453#define XHCI_TRB_3_EP_SET(x) __SHIFTIN((x), XHCI_TRB_3_EP_MASK)
450#define XHCI_TRB_3_FRID_MASK __BITS(30, 20) 454#define XHCI_TRB_3_FRID_MASK __BITS(30, 20)
451#define XHCI_TRB_3_FRID_GET(x) __SHIFTOUT((x), XHCI_TRB_3_FRID_MASK) 455#define XHCI_TRB_3_FRID_GET(x) __SHIFTOUT((x), XHCI_TRB_3_FRID_MASK)
452#define XHCI_TRB_3_FRID_SET(x) __SHIFTIN((x), XHCI_TRB_3_FRID_MASK) 456#define XHCI_TRB_3_FRID_SET(x) __SHIFTIN((x), XHCI_TRB_3_FRID_MASK)
453#define XHCI_TRB_3_ISO_SIA_BIT __BIT(31) 457#define XHCI_TRB_3_ISO_SIA_BIT __BIT(31)
454#define XHCI_TRB_3_SUSP_EP_BIT __BIT(23) 458#define XHCI_TRB_3_SUSP_EP_BIT __BIT(23)
455#define XHCI_TRB_3_VFID_MASK __BITS(23, 16) 459#define XHCI_TRB_3_VFID_MASK __BITS(23, 16)
456#define XHCI_TRB_3_VFID_GET(x) __SHIFTOUT((x), XHCI_TRB_3_VFID_MASK) 460#define XHCI_TRB_3_VFID_GET(x) __SHIFTOUT((x), XHCI_TRB_3_VFID_MASK)
457#define XHCI_TRB_3_VFID_SET(x) __SHIFTIN((x), XHCI_TRB_3_VFID_MASK) 461#define XHCI_TRB_3_VFID_SET(x) __SHIFTIN((x), XHCI_TRB_3_VFID_MASK)
458#define XHCI_TRB_3_SLOT_MASK __BITS(31, 24) 462#define XHCI_TRB_3_SLOT_MASK __BITS(31, 24)
459#define XHCI_TRB_3_SLOT_GET(x) __SHIFTOUT((x), XHCI_TRB_3_SLOT_MASK) 463#define XHCI_TRB_3_SLOT_GET(x) __SHIFTOUT((x), XHCI_TRB_3_SLOT_MASK)
460#define XHCI_TRB_3_SLOT_SET(x) __SHIFTIN((x), XHCI_TRB_3_SLOT_MASK) 464#define XHCI_TRB_3_SLOT_SET(x) __SHIFTIN((x), XHCI_TRB_3_SLOT_MASK)
461 465
462 /* Commands */ 466 /* Commands */
463#define XHCI_TRB_TYPE_RESERVED 0x00 467#define XHCI_TRB_TYPE_RESERVED 0x00
464#define XHCI_TRB_TYPE_NORMAL 0x01 468#define XHCI_TRB_TYPE_NORMAL 0x01
465#define XHCI_TRB_TYPE_SETUP_STAGE 0x02 469#define XHCI_TRB_TYPE_SETUP_STAGE 0x02
466#define XHCI_TRB_TYPE_DATA_STAGE 0x03 470#define XHCI_TRB_TYPE_DATA_STAGE 0x03
467#define XHCI_TRB_TYPE_STATUS_STAGE 0x04 471#define XHCI_TRB_TYPE_STATUS_STAGE 0x04
468#define XHCI_TRB_TYPE_ISOCH 0x05 472#define XHCI_TRB_TYPE_ISOCH 0x05
469#define XHCI_TRB_TYPE_LINK 0x06 473#define XHCI_TRB_TYPE_LINK 0x06
470#define XHCI_TRB_TYPE_EVENT_DATA 0x07 474#define XHCI_TRB_TYPE_EVENT_DATA 0x07
471#define XHCI_TRB_TYPE_NOOP 0x08 475#define XHCI_TRB_TYPE_NOOP 0x08
472#define XHCI_TRB_TYPE_ENABLE_SLOT 0x09 476#define XHCI_TRB_TYPE_ENABLE_SLOT 0x09
473#define XHCI_TRB_TYPE_DISABLE_SLOT 0x0A 477#define XHCI_TRB_TYPE_DISABLE_SLOT 0x0A
474#define XHCI_TRB_TYPE_ADDRESS_DEVICE 0x0B 478#define XHCI_TRB_TYPE_ADDRESS_DEVICE 0x0B
475#define XHCI_TRB_TYPE_CONFIGURE_EP 0x0C 479#define XHCI_TRB_TYPE_CONFIGURE_EP 0x0C
476#define XHCI_TRB_TYPE_EVALUATE_CTX 0x0D 480#define XHCI_TRB_TYPE_EVALUATE_CTX 0x0D
477#define XHCI_TRB_TYPE_RESET_EP 0x0E 481#define XHCI_TRB_TYPE_RESET_EP 0x0E
478#define XHCI_TRB_TYPE_STOP_EP 0x0F 482#define XHCI_TRB_TYPE_STOP_EP 0x0F
479#define XHCI_TRB_TYPE_SET_TR_DEQUEUE 0x10 483#define XHCI_TRB_TYPE_SET_TR_DEQUEUE 0x10
480#define XHCI_TRB_TYPE_RESET_DEVICE 0x11 484#define XHCI_TRB_TYPE_RESET_DEVICE 0x11
481#define XHCI_TRB_TYPE_FORCE_EVENT 0x12 485#define XHCI_TRB_TYPE_FORCE_EVENT 0x12
482#define XHCI_TRB_TYPE_NEGOTIATE_BW 0x13 486#define XHCI_TRB_TYPE_NEGOTIATE_BW 0x13
483#define XHCI_TRB_TYPE_SET_LATENCY_TOL 0x14 487#define XHCI_TRB_TYPE_SET_LATENCY_TOL 0x14
484#define XHCI_TRB_TYPE_GET_PORT_BW 0x15 488#define XHCI_TRB_TYPE_GET_PORT_BW 0x15
485#define XHCI_TRB_TYPE_FORCE_HEADER 0x16 489#define XHCI_TRB_TYPE_FORCE_HEADER 0x16
486#define XHCI_TRB_TYPE_NOOP_CMD 0x17 490#define XHCI_TRB_TYPE_NOOP_CMD 0x17
487 491
488 /* Events */ 492 /* Events */
489#define XHCI_TRB_EVENT_TRANSFER 0x20 493#define XHCI_TRB_EVENT_TRANSFER 0x20
490#define XHCI_TRB_EVENT_CMD_COMPLETE 0x21 494#define XHCI_TRB_EVENT_CMD_COMPLETE 0x21
491#define XHCI_TRB_EVENT_PORT_STS_CHANGE 0x22 495#define XHCI_TRB_EVENT_PORT_STS_CHANGE 0x22
492#define XHCI_TRB_EVENT_BW_REQUEST 0x23 496#define XHCI_TRB_EVENT_BW_REQUEST 0x23
493#define XHCI_TRB_EVENT_DOORBELL 0x24 497#define XHCI_TRB_EVENT_DOORBELL 0x24
494#define XHCI_TRB_EVENT_HOST_CTRL 0x25 498#define XHCI_TRB_EVENT_HOST_CTRL 0x25
495#define XHCI_TRB_EVENT_DEVICE_NOTIFY 0x26 499#define XHCI_TRB_EVENT_DEVICE_NOTIFY 0x26
496#define XHCI_TRB_EVENT_MFINDEX_WRAP 0x27 500#define XHCI_TRB_EVENT_MFINDEX_WRAP 0x27
497 501
498 /* Error codes */ 502 /* Error codes */
499#define XHCI_TRB_ERROR_INVALID 0x00 503#define XHCI_TRB_ERROR_INVALID 0x00
500#define XHCI_TRB_ERROR_SUCCESS 0x01 504#define XHCI_TRB_ERROR_SUCCESS 0x01
501#define XHCI_TRB_ERROR_DATA_BUF 0x02 505#define XHCI_TRB_ERROR_DATA_BUF 0x02
502#define XHCI_TRB_ERROR_BABBLE 0x03 506#define XHCI_TRB_ERROR_BABBLE 0x03
503#define XHCI_TRB_ERROR_XACT 0x04 507#define XHCI_TRB_ERROR_XACT 0x04
504#define XHCI_TRB_ERROR_TRB 0x05 508#define XHCI_TRB_ERROR_TRB 0x05
505#define XHCI_TRB_ERROR_STALL 0x06 509#define XHCI_TRB_ERROR_STALL 0x06
506#define XHCI_TRB_ERROR_RESOURCE 0x07 510#define XHCI_TRB_ERROR_RESOURCE 0x07
507#define XHCI_TRB_ERROR_BANDWIDTH 0x08 511#define XHCI_TRB_ERROR_BANDWIDTH 0x08
508#define XHCI_TRB_ERROR_NO_SLOTS 0x09 512#define XHCI_TRB_ERROR_NO_SLOTS 0x09
509#define XHCI_TRB_ERROR_STREAM_TYPE 0x0A 513#define XHCI_TRB_ERROR_STREAM_TYPE 0x0A
510#define XHCI_TRB_ERROR_SLOT_NOT_ON 0x0B 514#define XHCI_TRB_ERROR_SLOT_NOT_ON 0x0B
511#define XHCI_TRB_ERROR_ENDP_NOT_ON 0x0C 515#define XHCI_TRB_ERROR_ENDP_NOT_ON 0x0C
512#define XHCI_TRB_ERROR_SHORT_PKT 0x0D 516#define XHCI_TRB_ERROR_SHORT_PKT 0x0D
513#define XHCI_TRB_ERROR_RING_UNDERRUN 0x0E 517#define XHCI_TRB_ERROR_RING_UNDERRUN 0x0E
514#define XHCI_TRB_ERROR_RING_OVERRUN 0x0F 518#define XHCI_TRB_ERROR_RING_OVERRUN 0x0F
515#define XHCI_TRB_ERROR_VF_RING_FULL 0x10 519#define XHCI_TRB_ERROR_VF_RING_FULL 0x10
516#define XHCI_TRB_ERROR_PARAMETER 0x11 520#define XHCI_TRB_ERROR_PARAMETER 0x11
517#define XHCI_TRB_ERROR_BW_OVERRUN 0x12 521#define XHCI_TRB_ERROR_BW_OVERRUN 0x12
518#define XHCI_TRB_ERROR_CONTEXT_STATE 0x13 522#define XHCI_TRB_ERROR_CONTEXT_STATE 0x13
519#define XHCI_TRB_ERROR_NO_PING_RESP 0x14 523#define XHCI_TRB_ERROR_NO_PING_RESP 0x14
520#define XHCI_TRB_ERROR_EV_RING_FULL 0x15 524#define XHCI_TRB_ERROR_EV_RING_FULL 0x15
521#define XHCI_TRB_ERROR_INCOMPAT_DEV 0x16 525#define XHCI_TRB_ERROR_INCOMPAT_DEV 0x16
522#define XHCI_TRB_ERROR_MISSED_SERVICE 0x17 526#define XHCI_TRB_ERROR_MISSED_SERVICE 0x17
523#define XHCI_TRB_ERROR_CMD_RING_STOP 0x18 527#define XHCI_TRB_ERROR_CMD_RING_STOP 0x18
524#define XHCI_TRB_ERROR_CMD_ABORTED 0x19 528#define XHCI_TRB_ERROR_CMD_ABORTED 0x19
525#define XHCI_TRB_ERROR_STOPPED 0x1A 529#define XHCI_TRB_ERROR_STOPPED 0x1A
526#define XHCI_TRB_ERROR_LENGTH 0x1B 530#define XHCI_TRB_ERROR_LENGTH 0x1B
527#define XHCI_TRB_ERROR_STOPPED_SHORT 0x1C 531#define XHCI_TRB_ERROR_STOPPED_SHORT 0x1C
528#define XHCI_TRB_ERROR_BAD_MELAT 0x1D 532#define XHCI_TRB_ERROR_BAD_MELAT 0x1D
529#define XHCI_TRB_ERROR_ISOC_OVERRUN 0x1F 533#define XHCI_TRB_ERROR_ISOC_OVERRUN 0x1F
530#define XHCI_TRB_ERROR_EVENT_LOST 0x20 534#define XHCI_TRB_ERROR_EVENT_LOST 0x20
531#define XHCI_TRB_ERROR_UNDEFINED 0x21 535#define XHCI_TRB_ERROR_UNDEFINED 0x21
532#define XHCI_TRB_ERROR_INVALID_SID 0x22 536#define XHCI_TRB_ERROR_INVALID_SID 0x22
533#define XHCI_TRB_ERROR_SEC_BW 0x23 537#define XHCI_TRB_ERROR_SEC_BW 0x23
534#define XHCI_TRB_ERROR_SPLIT_XACT 0x24 538#define XHCI_TRB_ERROR_SPLIT_XACT 0x24
535} __packed __aligned(XHCI_TRB_ALIGN); 539} __packed __aligned(XHCI_TRB_ALIGN);
536#define XHCI_TRB_SIZE sizeof(struct xhci_trb) 540#define XHCI_TRB_SIZE sizeof(struct xhci_trb)
537 541
538/* 542/*
539 * 6.2.2 Slot context 543 * 6.2.2 Slot context
540 */ 544 */
541#define XHCI_SCTX_0_ROUTE_MASK __BITS(19, 0) 545#define XHCI_SCTX_0_ROUTE_MASK __BITS(19, 0)
542#define XHCI_SCTX_0_ROUTE_GET(x) __SHIFTOUT((x), XHCI_SCTX_0_ROUTE_MASK) 546#define XHCI_SCTX_0_ROUTE_GET(x) __SHIFTOUT((x), XHCI_SCTX_0_ROUTE_MASK)
543#define XHCI_SCTX_0_ROUTE_SET(x) __SHIFTIN((x), XHCI_SCTX_0_ROUTE_MASK) 547#define XHCI_SCTX_0_ROUTE_SET(x) __SHIFTIN((x), XHCI_SCTX_0_ROUTE_MASK)
544#define XHCI_SCTX_0_SPEED_MASK __BITS(23, 20) 548#define XHCI_SCTX_0_SPEED_MASK __BITS(23, 20)
545#define XHCI_SCTX_0_SPEED_GET(x) __SHIFTOUT((x), XHCI_SCTX_0_SPEED_MASK) 549#define XHCI_SCTX_0_SPEED_GET(x) __SHIFTOUT((x), XHCI_SCTX_0_SPEED_MASK)
546#define XHCI_SCTX_0_SPEED_SET(x) __SHIFTIN((x), XHCI_SCTX_0_SPEED_MASK) 550#define XHCI_SCTX_0_SPEED_SET(x) __SHIFTIN((x), XHCI_SCTX_0_SPEED_MASK)
547#define XHCI_SCTX_0_MTT_MASK __BIT(25) 551#define XHCI_SCTX_0_MTT_MASK __BIT(25)
548#define XHCI_SCTX_0_MTT_SET(x) __SHIFTIN((x), XHCI_SCTX_0_MTT_MASK) 552#define XHCI_SCTX_0_MTT_SET(x) __SHIFTIN((x), XHCI_SCTX_0_MTT_MASK)
549#define XHCI_SCTX_0_MTT_GET(x) __SHIFTOUT((x), XHCI_SCTX_0_MTT_MASK) 553#define XHCI_SCTX_0_MTT_GET(x) __SHIFTOUT((x), XHCI_SCTX_0_MTT_MASK)
550#define XHCI_SCTX_0_HUB_MASK __BIT(26) 554#define XHCI_SCTX_0_HUB_MASK __BIT(26)
551#define XHCI_SCTX_0_HUB_SET(x) __SHIFTIN((x), XHCI_SCTX_0_HUB_MASK) 555#define XHCI_SCTX_0_HUB_SET(x) __SHIFTIN((x), XHCI_SCTX_0_HUB_MASK)
552#define XHCI_SCTX_0_HUB_GET(x) __SHIFTOUT((x), XHCI_SCTX_0_HUB_MASK) 556#define XHCI_SCTX_0_HUB_GET(x) __SHIFTOUT((x), XHCI_SCTX_0_HUB_MASK)
553#define XHCI_SCTX_0_CTX_NUM_MASK __BITS(31, 27) 557#define XHCI_SCTX_0_CTX_NUM_MASK __BITS(31, 27)
554#define XHCI_SCTX_0_CTX_NUM_SET(x) __SHIFTIN((x), XHCI_SCTX_0_CTX_NUM_MASK) 558#define XHCI_SCTX_0_CTX_NUM_SET(x) __SHIFTIN((x), XHCI_SCTX_0_CTX_NUM_MASK)
555#define XHCI_SCTX_0_CTX_NUM_GET(x) __SHIFTOUT((x), XHCI_SCTX_0_CTX_NUM_MASK) 559#define XHCI_SCTX_0_CTX_NUM_GET(x) __SHIFTOUT((x), XHCI_SCTX_0_CTX_NUM_MASK)
556 560
557#define XHCI_SCTX_1_MAX_EL_MASK __BITS(15, 0) 561#define XHCI_SCTX_1_MAX_EL_MASK __BITS(15, 0)
558#define XHCI_SCTX_1_MAX_EL_SET(x) __SHIFTIN((x), XHCI_SCTX_1_MAX_EL_MASK) 562#define XHCI_SCTX_1_MAX_EL_SET(x) __SHIFTIN((x), XHCI_SCTX_1_MAX_EL_MASK)
559#define XHCI_SCTX_1_MAX_EL_GET(x) __SHIFTOUT((x), XHCI_SCTX_1_MAX_EL_MASK) 563#define XHCI_SCTX_1_MAX_EL_GET(x) __SHIFTOUT((x), XHCI_SCTX_1_MAX_EL_MASK)
560#define XHCI_SCTX_1_RH_PORT_MASK __BITS(23, 16) 564#define XHCI_SCTX_1_RH_PORT_MASK __BITS(23, 16)
561#define XHCI_SCTX_1_RH_PORT_SET(x) __SHIFTIN((x), XHCI_SCTX_1_RH_PORT_MASK) 565#define XHCI_SCTX_1_RH_PORT_SET(x) __SHIFTIN((x), XHCI_SCTX_1_RH_PORT_MASK)
562#define XHCI_SCTX_1_RH_PORT_GET(x) __SHIFTOUT((x), XHCI_SCTX_1_RH_PORT_MASK) 566#define XHCI_SCTX_1_RH_PORT_GET(x) __SHIFTOUT((x), XHCI_SCTX_1_RH_PORT_MASK)
563#define XHCI_SCTX_1_NUM_PORTS_MASK __BITS(31, 24) 567#define XHCI_SCTX_1_NUM_PORTS_MASK __BITS(31, 24)
564#define XHCI_SCTX_1_NUM_PORTS_SET(x) __SHIFTIN((x), XHCI_SCTX_1_NUM_PORTS_MASK) 568#define XHCI_SCTX_1_NUM_PORTS_SET(x) __SHIFTIN((x), XHCI_SCTX_1_NUM_PORTS_MASK)
565#define XHCI_SCTX_1_NUM_PORTS_GET(x) __SHIFTOUT((x), XHCI_SCTX_1_NUM_PORTS_MASK) 569#define XHCI_SCTX_1_NUM_PORTS_GET(x) __SHIFTOUT((x), XHCI_SCTX_1_NUM_PORTS_MASK)
566 570
567#define XHCI_SCTX_2_TT_HUB_SID_MASK __BITS(7, 0) 571#define XHCI_SCTX_2_TT_HUB_SID_MASK __BITS(7, 0)
568#define XHCI_SCTX_2_TT_HUB_SID_SET(x) __SHIFTIN((x), XHCI_SCTX_2_TT_HUB_SID_MASK) 572#define XHCI_SCTX_2_TT_HUB_SID_SET(x) __SHIFTIN((x), XHCI_SCTX_2_TT_HUB_SID_MASK)
569#define XHCI_SCTX_2_TT_HUB_SID_GET(x) __SHIFTOUT((x), XHCI_SCTX_2_TT_HUB_SID_MASK) 573#define XHCI_SCTX_2_TT_HUB_SID_GET(x) __SHIFTOUT((x), XHCI_SCTX_2_TT_HUB_SID_MASK)
570#define XHCI_SCTX_2_TT_PORT_NUM_MASK __BITS(15, 8) 574#define XHCI_SCTX_2_TT_PORT_NUM_MASK __BITS(15, 8)
571#define XHCI_SCTX_2_TT_PORT_NUM_SET(x) __SHIFTIN((x), XHCI_SCTX_2_TT_PORT_NUM_MASK) 575#define XHCI_SCTX_2_TT_PORT_NUM_SET(x) __SHIFTIN((x), XHCI_SCTX_2_TT_PORT_NUM_MASK)
572#define XHCI_SCTX_2_TT_PORT_NUM_GET(x) __SHIFTOUT((x), XHCI_SCTX_2_TT_PORT_NUM_MASK) 576#define XHCI_SCTX_2_TT_PORT_NUM_GET(x) __SHIFTOUT((x), XHCI_SCTX_2_TT_PORT_NUM_MASK)
573#define XHCI_SCTX_2_TT_THINK_TIME_MASK __BITS(17, 16) 577#define XHCI_SCTX_2_TT_THINK_TIME_MASK __BITS(17, 16)
574#define XHCI_SCTX_2_TT_THINK_TIME_SET(x) __SHIFTIN((x), XHCI_SCTX_2_TT_THINK_TIME_MASK) 578#define XHCI_SCTX_2_TT_THINK_TIME_SET(x) __SHIFTIN((x), XHCI_SCTX_2_TT_THINK_TIME_MASK)
575#define XHCI_SCTX_2_TT_THINK_TIME_GET(x) __SHIFTOUT((x), XHCI_SCTX_2_TT_THINK_TIME_MASK) 579#define XHCI_SCTX_2_TT_THINK_TIME_GET(x) __SHIFTOUT((x), XHCI_SCTX_2_TT_THINK_TIME_MASK)
576#define XHCI_SCTX_2_IRQ_TARGET_MASK __BITS(31, 22) 580#define XHCI_SCTX_2_IRQ_TARGET_MASK __BITS(31, 22)
577#define XHCI_SCTX_2_IRQ_TARGET_SET(x) __SHIFTIN((x), XHCI_SCTX_2_IRQ_TARGET_MASK) 581#define XHCI_SCTX_2_IRQ_TARGET_SET(x) __SHIFTIN((x), XHCI_SCTX_2_IRQ_TARGET_MASK)
578#define XHCI_SCTX_2_IRQ_TARGET_GET(x) __SHIFTOUT((x), XHCI_SCTX_2_IRQ_TARGET_MASK) 582#define XHCI_SCTX_2_IRQ_TARGET_GET(x) __SHIFTOUT((x), XHCI_SCTX_2_IRQ_TARGET_MASK)
579 583
580#define XHCI_SCTX_3_DEV_ADDR_MASK __BITS(7, 0) 584#define XHCI_SCTX_3_DEV_ADDR_MASK __BITS(7, 0)
581#define XHCI_SCTX_3_DEV_ADDR_SET(x) __SHIFTIN((x), XHCI_SCTX_3_DEV_ADDR_MASK) 585#define XHCI_SCTX_3_DEV_ADDR_SET(x) __SHIFTIN((x), XHCI_SCTX_3_DEV_ADDR_MASK)
582#define XHCI_SCTX_3_DEV_ADDR_GET(x) __SHIFTOUT((x), XHCI_SCTX_3_DEV_ADDR_MASK) 586#define XHCI_SCTX_3_DEV_ADDR_GET(x) __SHIFTOUT((x), XHCI_SCTX_3_DEV_ADDR_MASK)
583#define XHCI_SCTX_3_SLOT_STATE_MASK __BITS(31, 27) 587#define XHCI_SCTX_3_SLOT_STATE_MASK __BITS(31, 27)
584#define XHCI_SCTX_3_SLOT_STATE_SET(x) __SHIFTIN((x), XHCI_SCTX_3_SLOT_STATE_MASK) 588#define XHCI_SCTX_3_SLOT_STATE_SET(x) __SHIFTIN((x), XHCI_SCTX_3_SLOT_STATE_MASK)
585#define XHCI_SCTX_3_SLOT_STATE_GET(x) __SHIFTOUT((x), XHCI_SCTX_3_SLOT_STATE_MASK) 589#define XHCI_SCTX_3_SLOT_STATE_GET(x) __SHIFTOUT((x), XHCI_SCTX_3_SLOT_STATE_MASK)
586#define XHCI_SLOTSTATE_DISABLED 0 /* disabled or enabled */ 590#define XHCI_SLOTSTATE_DISABLED 0 /* disabled or enabled */
587#define XHCI_SLOTSTATE_ENABLED 0 591#define XHCI_SLOTSTATE_ENABLED 0
588#define XHCI_SLOTSTATE_DEFAULT 1 592#define XHCI_SLOTSTATE_DEFAULT 1
589#define XHCI_SLOTSTATE_ADDRESSED 2 593#define XHCI_SLOTSTATE_ADDRESSED 2
590#define XHCI_SLOTSTATE_CONFIGURED 3 594#define XHCI_SLOTSTATE_CONFIGURED 3
591 595
592/* 596/*
593 * 6.2.3 Endpoint Context 597 * 6.2.3 Endpoint Context
594 * */ 598 * */
595#define XHCI_EPCTX_0_EPSTATE_MASK __BITS(2, 0) 599#define XHCI_EPCTX_0_EPSTATE_MASK __BITS(2, 0)
596#define XHCI_EPCTX_0_EPSTATE_SET(x) __SHIFTIN((x), XHCI_EPCTX_0_EPSTATE_MASK) 600#define XHCI_EPCTX_0_EPSTATE_SET(x) __SHIFTIN((x), XHCI_EPCTX_0_EPSTATE_MASK)
597#define XHCI_EPCTX_0_EPSTATE_GET(x) __SHIFTOUT((x), XHCI_EPCTX_0_EPSTATE_MASK) 601#define XHCI_EPCTX_0_EPSTATE_GET(x) __SHIFTOUT((x), XHCI_EPCTX_0_EPSTATE_MASK)
598#define XHCI_EPSTATE_DISABLED 0 602#define XHCI_EPSTATE_DISABLED 0
599#define XHCI_EPSTATE_RUNNING 1 603#define XHCI_EPSTATE_RUNNING 1
600#define XHCI_EPSTATE_HALTED 2 604#define XHCI_EPSTATE_HALTED 2
601#define XHCI_EPSTATE_STOPPED 3 605#define XHCI_EPSTATE_STOPPED 3
602#define XHCI_EPSTATE_ERROR 4 606#define XHCI_EPSTATE_ERROR 4
603#define XHCI_EPCTX_0_MULT_MASK __BITS(9, 8) 607#define XHCI_EPCTX_0_MULT_MASK __BITS(9, 8)
604#define XHCI_EPCTX_0_MULT_SET(x) __SHIFTIN((x), XHCI_EPCTX_0_MULT_MASK) 608#define XHCI_EPCTX_0_MULT_SET(x) __SHIFTIN((x), XHCI_EPCTX_0_MULT_MASK)
605#define XHCI_EPCTX_0_MULT_GET(x) __SHIFTOUT((x), XHCI_EPCTX_0_MULT_MASK) 609#define XHCI_EPCTX_0_MULT_GET(x) __SHIFTOUT((x), XHCI_EPCTX_0_MULT_MASK)
606#define XHCI_EPCTX_0_MAXP_STREAMS_MASK __BITS(14, 10) 610#define XHCI_EPCTX_0_MAXP_STREAMS_MASK __BITS(14, 10)
607#define XHCI_EPCTX_0_MAXP_STREAMS_SET(x) __SHIFTIN((x), XHCI_EPCTX_0_MAXP_STREAMS_MASK) 611#define XHCI_EPCTX_0_MAXP_STREAMS_SET(x) __SHIFTIN((x), XHCI_EPCTX_0_MAXP_STREAMS_MASK)
608#define XHCI_EPCTX_0_MAXP_STREAMS_GET(x) __SHIFTOUT((x), XHCI_EPCTX_0_MAXP_STREAMS_MASK) 612#define XHCI_EPCTX_0_MAXP_STREAMS_GET(x) __SHIFTOUT((x), XHCI_EPCTX_0_MAXP_STREAMS_MASK)
609#define XHCI_EPCTX_0_LSA_MASK __BIT(15) 613#define XHCI_EPCTX_0_LSA_MASK __BIT(15)
610#define XHCI_EPCTX_0_LSA_SET(x) __SHIFTIN((x), XHCI_EPCTX_0_LSA_MASK) 614#define XHCI_EPCTX_0_LSA_SET(x) __SHIFTIN((x), XHCI_EPCTX_0_LSA_MASK)
611#define XHCI_EPCTX_0_LSA_GET(x) __SHIFTOUT((x), XHCI_EPCTX_0_LSA_MASK) 615#define XHCI_EPCTX_0_LSA_GET(x) __SHIFTOUT((x), XHCI_EPCTX_0_LSA_MASK)
612#define XHCI_EPCTX_0_IVAL_MASK __BITS(23, 16) 616#define XHCI_EPCTX_0_IVAL_MASK __BITS(23, 16)
613#define XHCI_EPCTX_0_IVAL_SET(x) __SHIFTIN((x), XHCI_EPCTX_0_IVAL_MASK) 617#define XHCI_EPCTX_0_IVAL_SET(x) __SHIFTIN((x), XHCI_EPCTX_0_IVAL_MASK)
614#define XHCI_EPCTX_0_IVAL_GET(x) __SHIFTOUT((x), XHCI_EPCTX_0_IVAL_MASK) 618#define XHCI_EPCTX_0_IVAL_GET(x) __SHIFTOUT((x), XHCI_EPCTX_0_IVAL_MASK)
615#define XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_MASK __BITS(31, 24) 619#define XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_MASK __BITS(31, 24)
616#define XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(x) __SHIFTIN((x), XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_MASK) 620#define XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(x) __SHIFTIN((x), XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_MASK)
617#define XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_GET(x) __SHIFTOUT((x), XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_MASK) 621#define XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_GET(x) __SHIFTOUT((x), XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_MASK)
618 622
619#define XHCI_EPCTX_1_CERR_MASK __BITS(2, 1) 623#define XHCI_EPCTX_1_CERR_MASK __BITS(2, 1)
620#define XHCI_EPCTX_1_CERR_SET(x) __SHIFTIN((x), XHCI_EPCTX_1_CERR_MASK) 624#define XHCI_EPCTX_1_CERR_SET(x) __SHIFTIN((x), XHCI_EPCTX_1_CERR_MASK)
621#define XHCI_EPCTX_1_CERR_GET(x) __SHIFTOUT((x), XHCI_EPCTX_1_CERR_MASK) 625#define XHCI_EPCTX_1_CERR_GET(x) __SHIFTOUT((x), XHCI_EPCTX_1_CERR_MASK)
622#define XHCI_EPCTX_1_EPTYPE_MASK __BITS(5, 3) 626#define XHCI_EPCTX_1_EPTYPE_MASK __BITS(5, 3)
623#define XHCI_EPCTX_1_EPTYPE_SET(x) __SHIFTIN((x), XHCI_EPCTX_1_EPTYPE_MASK) 627#define XHCI_EPCTX_1_EPTYPE_SET(x) __SHIFTIN((x), XHCI_EPCTX_1_EPTYPE_MASK)
624#define XHCI_EPCTX_1_EPTYPE_GET(x) __SHIFTOUT((x), XHCI_EPCTX_1_EPTYPE_MASK) 628#define XHCI_EPCTX_1_EPTYPE_GET(x) __SHIFTOUT((x), XHCI_EPCTX_1_EPTYPE_MASK)
625#define XHCI_EPCTX_1_HID_MASK __BIT(7) 629#define XHCI_EPCTX_1_HID_MASK __BIT(7)
626#define XHCI_EPCTX_1_HID_SET(x) __SHIFTIN((x), XHCI_EPCTX_1_HID_MASK) 630#define XHCI_EPCTX_1_HID_SET(x) __SHIFTIN((x), XHCI_EPCTX_1_HID_MASK)
627#define XHCI_EPCTX_1_HID_GET(x) __SHIFTOUT((x), XHCI_EPCTX_1_HID_MASK) 631#define XHCI_EPCTX_1_HID_GET(x) __SHIFTOUT((x), XHCI_EPCTX_1_HID_MASK)
628#define XHCI_EPCTX_1_MAXB_MASK __BITS(15, 8) 632#define XHCI_EPCTX_1_MAXB_MASK __BITS(15, 8)
629#define XHCI_EPCTX_1_MAXB_SET(x) __SHIFTIN((x), XHCI_EPCTX_1_MAXB_MASK) 633#define XHCI_EPCTX_1_MAXB_SET(x) __SHIFTIN((x), XHCI_EPCTX_1_MAXB_MASK)
630#define XHCI_EPCTX_1_MAXB_GET(x) __SHIFTOUT((x), XHCI_EPCTX_1_MAXB_MASK) 634#define XHCI_EPCTX_1_MAXB_GET(x) __SHIFTOUT((x), XHCI_EPCTX_1_MAXB_MASK)
631#define XHCI_EPCTX_1_MAXP_SIZE_MASK __BITS(31, 16) 635#define XHCI_EPCTX_1_MAXP_SIZE_MASK __BITS(31, 16)
632#define XHCI_EPCTX_1_MAXP_SIZE_SET(x) __SHIFTIN((x), XHCI_EPCTX_1_MAXP_SIZE_MASK) 636#define XHCI_EPCTX_1_MAXP_SIZE_SET(x) __SHIFTIN((x), XHCI_EPCTX_1_MAXP_SIZE_MASK)
633#define XHCI_EPCTX_1_MAXP_SIZE_GET(x) __SHIFTOUT((x), XHCI_EPCTX_1_MAXP_SIZE_MASK) 637#define XHCI_EPCTX_1_MAXP_SIZE_GET(x) __SHIFTOUT((x), XHCI_EPCTX_1_MAXP_SIZE_MASK)
634 638
635 639
636#define XHCI_EPCTX_2_DCS_MASK __BIT(0) 640#define XHCI_EPCTX_2_DCS_MASK __BIT(0)
637#define XHCI_EPCTX_2_DCS_SET(x) __SHIFTIN((x), XHCI_EPCTX_2_DCS_MASK) 641#define XHCI_EPCTX_2_DCS_SET(x) __SHIFTIN((x), XHCI_EPCTX_2_DCS_MASK)
638#define XHCI_EPCTX_2_DCS_GET(x) __SHIFTOUT((x), XHCI_EPCTX_2_DCS_MASK) 642#define XHCI_EPCTX_2_DCS_GET(x) __SHIFTOUT((x), XHCI_EPCTX_2_DCS_MASK)
639#define XHCI_EPCTX_2_TR_DQ_PTR_MASK 0xFFFFFFFFFFFFFFF0ULL 643#define XHCI_EPCTX_2_TR_DQ_PTR_MASK 0xFFFFFFFFFFFFFFF0ULL
640 644
641#define XHCI_EPCTX_4_AVG_TRB_LEN_MASK __BITS(15, 0) 645#define XHCI_EPCTX_4_AVG_TRB_LEN_MASK __BITS(15, 0)
642#define XHCI_EPCTX_4_AVG_TRB_LEN_SET(x) __SHIFTIN((x), XHCI_EPCTX_4_AVG_TRB_LEN_MASK) 646#define XHCI_EPCTX_4_AVG_TRB_LEN_SET(x) __SHIFTIN((x), XHCI_EPCTX_4_AVG_TRB_LEN_MASK)
643#define XHCI_EPCTX_4_AVG_TRB_LEN_GET(x) __SHIFTOUT((x), XHCI_EPCTX_4_AVG_TRB_LEN_MASK) 647#define XHCI_EPCTX_4_AVG_TRB_LEN_GET(x) __SHIFTOUT((x), XHCI_EPCTX_4_AVG_TRB_LEN_MASK)
644#define XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_MASK __BITS(16, 31) 648#define XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_MASK __BITS(16, 31)
645#define XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(x) __SHIFTIN((x), XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_MASK) 649#define XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(x) __SHIFTIN((x), XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_MASK)
646#define XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_GET(x) __SHIFTOUT((x), XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_MASK) 650#define XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_GET(x) __SHIFTOUT((x), XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_MASK)
647 651
648 652
649#define XHCI_INCTX_NON_CTRL_MASK 0xFFFFFFFCU 653#define XHCI_INCTX_NON_CTRL_MASK 0xFFFFFFFCU
650 654
651#define XHCI_INCTX_0_DROP_MASK(n) __BIT((n)) 655#define XHCI_INCTX_0_DROP_MASK(n) __BIT((n))
652 656
653#define XHCI_INCTX_1_ADD_MASK(n) __BIT((n)) 657#define XHCI_INCTX_1_ADD_MASK(n) __BIT((n))
654 658
655 659
656struct xhci_erste { 660struct xhci_erste {
657 uint64_t erste_0; /* 63:6 base */ 661 uint64_t erste_0; /* 63:6 base */
658 uint32_t erste_2; /* 15:0 trb count (16 to 4096) */ 662 uint32_t erste_2; /* 15:0 trb count (16 to 4096) */
659 uint32_t erste_3; /* RsvdZ */ 663 uint32_t erste_3; /* RsvdZ */
660} __packed __aligned(XHCI_ERSTE_ALIGN); 664} __packed __aligned(XHCI_ERSTE_ALIGN);
661#define XHCI_ERSTE_SIZE sizeof(struct xhci_erste) 665#define XHCI_ERSTE_SIZE sizeof(struct xhci_erste)
662 666
663#endif /* _DEV_USB_XHCIREG_H_ */ 667#endif /* _DEV_USB_XHCIREG_H_ */
cvs diff -r1.17 -r1.18 src/sys/dev/usb/xhcivar.h (switch to unified diff)

--- src/sys/dev/usb/xhcivar.h 2020/08/21 20:46:03 1.17
+++ src/sys/dev/usb/xhcivar.h 2021/05/23 11:49:45 1.18
@@ -1,154 +1,166 @@ @@ -1,154 +1,166 @@
1/* $NetBSD: xhcivar.h,v 1.17 2020/08/21 20:46:03 jakllsch Exp $ */ 1/* $NetBSD: xhcivar.h,v 1.18 2021/05/23 11:49:45 riastradh Exp $ */
2 2
3/* 3/*
4 * Copyright (c) 2013 Jonathan A. Kollasch 4 * Copyright (c) 2013 Jonathan A. Kollasch
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * Redistribution and use in source and binary forms, with or without 7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions 8 * modification, are permitted provided that the following conditions
9 * are met: 9 * are met:
10 * 1. Redistributions of source code must retain the above copyright 10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer. 11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright 12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the 13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution. 14 * documentation and/or other materials provided with the distribution.
15 * 15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */ 27 */
28 28
29#ifndef _DEV_USB_XHCIVAR_H_ 29#ifndef _DEV_USB_XHCIVAR_H_
30#define _DEV_USB_XHCIVAR_H_ 30#define _DEV_USB_XHCIVAR_H_
31 31
32#include <sys/pool.h> 32#include <sys/pool.h>
33 33
34#define XHCI_MAX_DCI 31 34#define XHCI_MAX_DCI 31
35 35
36struct xhci_soft_trb { 36struct xhci_soft_trb {
37 uint64_t trb_0; 37 uint64_t trb_0;
38 uint32_t trb_2; 38 uint32_t trb_2;
39 uint32_t trb_3; 39 uint32_t trb_3;
40}; 40};
41 41
42struct xhci_xfer { 42struct xhci_xfer {
43 struct usbd_xfer xx_xfer; 43 struct usbd_xfer xx_xfer;
44 struct xhci_soft_trb *xx_trb; 44 struct xhci_soft_trb *xx_trb;
45 u_int xx_ntrb; 45 u_int xx_ntrb;
46 u_int xx_isoc_done; 46 u_int xx_isoc_done;
47}; 47};
48 48
49#define XHCI_BUS2SC(bus) ((bus)->ub_hcpriv) 49#define XHCI_BUS2SC(bus) ((bus)->ub_hcpriv)
50#define XHCI_PIPE2SC(pipe) XHCI_BUS2SC((pipe)->up_dev->ud_bus) 50#define XHCI_PIPE2SC(pipe) XHCI_BUS2SC((pipe)->up_dev->ud_bus)
51#define XHCI_XFER2SC(xfer) XHCI_BUS2SC((xfer)->ux_bus) 51#define XHCI_XFER2SC(xfer) XHCI_BUS2SC((xfer)->ux_bus)
52#define XHCI_XFER2BUS(xfer) ((xfer)->ux_bus) 52#define XHCI_XFER2BUS(xfer) ((xfer)->ux_bus)
53#define XHCI_XPIPE2SC(d) XHCI_BUS2SC((d)->xp_pipe.up_dev->ud_bus) 53#define XHCI_XPIPE2SC(d) XHCI_BUS2SC((d)->xp_pipe.up_dev->ud_bus)
54 54
55#define XHCI_XFER2XXFER(xfer) ((struct xhci_xfer *)(xfer)) 55#define XHCI_XFER2XXFER(xfer) ((struct xhci_xfer *)(xfer))
56 56
57struct xhci_ring { 57struct xhci_ring {
58 usb_dma_t xr_dma; 58 usb_dma_t xr_dma;
59 kmutex_t xr_lock; 59 kmutex_t xr_lock;
60 struct xhci_trb * xr_trb; 60 struct xhci_trb * xr_trb;
61 void **xr_cookies; 61 void **xr_cookies;
62 u_int xr_ntrb; /* number of elements for above */ 62 u_int xr_ntrb; /* number of elements for above */
63 u_int xr_ep; /* enqueue pointer */ 63 u_int xr_ep; /* enqueue pointer */
64 u_int xr_cs; /* cycle state */ 64 u_int xr_cs; /* cycle state */
65 bool is_halted; 65 bool is_halted;
66}; 66};
67 67
68struct xhci_slot { 68struct xhci_slot {
69 usb_dma_t xs_dc_dma; /* device context page */ 69 usb_dma_t xs_dc_dma; /* device context page */
70 usb_dma_t xs_ic_dma; /* input context page */ 70 usb_dma_t xs_ic_dma; /* input context page */
71 struct xhci_ring *xs_xr[XHCI_MAX_DCI + 1]; 71 struct xhci_ring *xs_xr[XHCI_MAX_DCI + 1];
72 /* transfer rings */ 72 /* transfer rings */
73 u_int xs_idx; /* slot index */ 73 u_int xs_idx; /* slot index */
74}; 74};
75 75
76struct xhci_softc { 76struct xhci_softc {
77 device_t sc_dev; 77 device_t sc_dev;
78 device_t sc_child; 78 device_t sc_child;
79 device_t sc_child2; 79 device_t sc_child2;
80 bus_size_t sc_ios; 80 bus_size_t sc_ios;
81 bus_space_tag_t sc_iot; 81 bus_space_tag_t sc_iot;
82 bus_space_handle_t sc_ioh; /* Base */ 82 bus_space_handle_t sc_ioh; /* Base */
83 bus_space_handle_t sc_cbh; /* Capability Base */ 83 bus_space_handle_t sc_cbh; /* Capability Base */
84 bus_space_handle_t sc_obh; /* Operational Base */ 84 bus_space_handle_t sc_obh; /* Operational Base */
85 bus_space_handle_t sc_rbh; /* Runtime Base */ 85 bus_space_handle_t sc_rbh; /* Runtime Base */
86 bus_space_handle_t sc_dbh; /* Doorbell Registers */ 86 bus_space_handle_t sc_dbh; /* Doorbell Registers */
87 struct usbd_bus sc_bus; /* USB 3 bus */ 87 struct usbd_bus sc_bus; /* USB 3 bus */
88 struct usbd_bus sc_bus2; /* USB 2 bus */ 88 struct usbd_bus sc_bus2; /* USB 2 bus */
89 89
90 kmutex_t sc_lock; 90 kmutex_t sc_lock;
91 kmutex_t sc_intr_lock; 91 kmutex_t sc_intr_lock;
92 92
93 pool_cache_t sc_xferpool; 93 pool_cache_t sc_xferpool;
94 94
95 bus_size_t sc_pgsz; /* xHCI page size */ 95 bus_size_t sc_pgsz; /* xHCI page size */
96 uint32_t sc_ctxsz; 96 uint32_t sc_ctxsz;
97 int sc_maxslots; 97 int sc_maxslots;
98 int sc_maxintrs; 98 int sc_maxintrs;
99 int sc_maxspbuf; 99 int sc_maxspbuf;
100 100
101 /* 101 /*
102 * Port routing and root hub - xHCI 4.19.7 102 * Port routing and root hub - xHCI 4.19.7
103 */ 103 */
104 int sc_maxports; /* number of controller ports */ 104 int sc_maxports; /* number of controller ports */
105 105
106 uint8_t *sc_ctlrportbus; /* a bus bit per port */ 106 uint8_t *sc_ctlrportbus; /* a bus bit per port */
107 107
108 int *sc_ctlrportmap; 108 int *sc_ctlrportmap;
109 int *sc_rhportmap[2]; 109 int *sc_rhportmap[2];
110 int sc_rhportcount[2]; 110 int sc_rhportcount[2];
111 struct usbd_xfer *sc_intrxfer[2]; 111 struct usbd_xfer *sc_intrxfer[2];
112 112
113 113
114 struct xhci_slot * sc_slots; 114 struct xhci_slot * sc_slots;
115 115
116 struct xhci_ring *sc_cr; /* command ring */ 116 struct xhci_ring *sc_cr; /* command ring */
117 struct xhci_ring *sc_er; /* event ring */ 117 struct xhci_ring *sc_er; /* event ring */
118 118
119 usb_dma_t sc_eventst_dma; 119 usb_dma_t sc_eventst_dma;
120 usb_dma_t sc_dcbaa_dma; 120 usb_dma_t sc_dcbaa_dma;
121 usb_dma_t sc_spbufarray_dma; 121 usb_dma_t sc_spbufarray_dma;
122 usb_dma_t *sc_spbuf_dma; 122 usb_dma_t *sc_spbuf_dma;
123 123
124 kcondvar_t sc_cmdbusy_cv; 124 kcondvar_t sc_cmdbusy_cv;
125 kcondvar_t sc_command_cv; 125 kcondvar_t sc_command_cv;
126 bus_addr_t sc_command_addr; 126 bus_addr_t sc_command_addr;
127 struct xhci_soft_trb sc_result_trb; 127 struct xhci_soft_trb sc_result_trb;
128 bool sc_resultpending; 128 bool sc_resultpending;
129 129
130 bool sc_dying; 130 bool sc_dying;
131 131
132 void (*sc_vendor_init)(struct xhci_softc *); 132 void (*sc_vendor_init)(struct xhci_softc *);
133 int (*sc_vendor_port_status)(struct xhci_softc *, uint32_t, int); 133 int (*sc_vendor_port_status)(struct xhci_softc *, uint32_t, int);
134 134
135 int sc_quirks; 135 int sc_quirks;
136#define XHCI_QUIRK_INTEL __BIT(0) /* Intel xhci chip */ 136#define XHCI_QUIRK_INTEL __BIT(0) /* Intel xhci chip */
137#define XHCI_DEFERRED_START __BIT(1) 137#define XHCI_DEFERRED_START __BIT(1)
138 uint32_t sc_hcc; /* copy of HCCPARAMS1 */ 138 uint32_t sc_hcc; /* copy of HCCPARAMS1 */
139 uint32_t sc_hcc2; /* copy of HCCPARAMS2 */ 139 uint32_t sc_hcc2; /* copy of HCCPARAMS2 */
 140
 141 struct xhci_registers {
 142 uint32_t usbcmd;
 143 uint32_t dnctrl;
 144 uint64_t dcbaap;
 145 uint32_t config;
 146 uint32_t erstsz0;
 147 uint64_t erstba0;
 148 uint64_t erdp0;
 149 uint32_t iman0;
 150 uint32_t imod0;
 151 } sc_regs;
140}; 152};
141 153
142int xhci_init(struct xhci_softc *); 154int xhci_init(struct xhci_softc *);
143void xhci_start(struct xhci_softc *); 155void xhci_start(struct xhci_softc *);
144int xhci_intr(void *); 156int xhci_intr(void *);
145int xhci_detach(struct xhci_softc *, int); 157int xhci_detach(struct xhci_softc *, int);
146int xhci_activate(device_t, enum devact); 158int xhci_activate(device_t, enum devact);
147void xhci_childdet(device_t, device_t); 159void xhci_childdet(device_t, device_t);
148bool xhci_suspend(device_t, const pmf_qual_t *); 160bool xhci_suspend(device_t, const pmf_qual_t *);
149bool xhci_resume(device_t, const pmf_qual_t *); 161bool xhci_resume(device_t, const pmf_qual_t *);
150bool xhci_shutdown(device_t, int); 162bool xhci_shutdown(device_t, int);
151 163
152#define XHCI_TRANSFER_RING_TRBS 256 164#define XHCI_TRANSFER_RING_TRBS 256
153 165
154#endif /* _DEV_USB_XHCIVAR_H_ */ 166#endif /* _DEV_USB_XHCIVAR_H_ */