 @@ -1,218 +1,218 @@
-/* $NetBSD: procfs_machdep.c,v 1.4 2020/10/01 07:31:27 skrll Exp $ */
+/* $NetBSD: procfs_machdep.c,v 1.5 2021/05/27 06:11:20 ryo Exp $ */
 /*-
  * Copyright (c) 2020 Ryo Shimizu <ryo@nerv.org>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
  * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: procfs_machdep.c,v 1.4 2020/10/01 07:31:27 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: procfs_machdep.c,v 1.5 2021/05/27 06:11:20 ryo Exp $");
 #include <sys/param.h>
 #include <sys/cpu.h>
 #include <sys/systm.h>
 #include <miscfs/procfs/procfs.h>
 #include <aarch64/armreg.h>
 #include <aarch64/cpufunc.h>
 /* use variables named 'buf', 'left', 'total' */
 #define FORWARD_BUF(_len)					\
 	do {							\
 		total += _len;					\
 		if (_len < left) {				\
 			buf += _len;				\
 			left -= _len;				\
 		} else {					\
 			buf += left;				\
 			left = 0;				\
 		}						\
 	} while (0 /*CONSTCOND*/)
 #define OUTPUT_BUF(fmt, args...)				\
 	do {							\
 		size_t l = snprintf(buf, left, fmt, ## args);	\
 		FORWARD_BUF(l);					\
 	} while (0/*CONSTCOND*/)
 static int
 procfs_cpuinfo_features(struct cpu_info *ci, char *buf, int buflen)
+{
 	uint64_t isar0, isar1, mmfr2, pfr0, pfr1;
 	size_t left, total;
 	isar0 = ci->ci_id.ac_aa64isar0;
 	isar1 = ci->ci_id.ac_aa64isar1;
 	mmfr2 = ci->ci_id.ac_aa64mmfr2;
 	pfr0 = ci->ci_id.ac_aa64pfr0;
 	pfr1 = ci->ci_id.ac_aa64pfr1;
 	left = buflen;
 	total = 0;
 	/*
 	 * I don't know if we need to mimic the order of HWCAP in linux
 	 */
 	OUTPUT_BUF("Features\t:");
 #define SO_EQ(reg, mask, val)	(__SHIFTOUT((reg), (mask)) == (val))
 	if (SO_EQ(pfr0, ID_AA64PFR0_EL1_FP, ID_AA64PFR0_EL1_FP_IMPL))
 		OUTPUT_BUF(" fp");
 	if (SO_EQ(pfr0, ID_AA64PFR0_EL1_ADVSIMD, ID_AA64PFR0_EL1_ADV_SIMD_IMPL))
 		OUTPUT_BUF(" asimd");
 	/* notyet: " evtstrm" */
 	if (SO_EQ(isar0, ID_AA64ISAR0_EL1_AES, ID_AA64ISAR0_EL1_AES_AES))
 		OUTPUT_BUF(" aes");
 	if (SO_EQ(isar0, ID_AA64ISAR0_EL1_AES, ID_AA64ISAR0_EL1_AES_PMUL))
 		OUTPUT_BUF(" pmull");
 	if (SO_EQ(isar0, ID_AA64ISAR0_EL1_SHA1,
 	    ID_AA64ISAR0_EL1_SHA1_SHA1CPMHSU))
 		OUTPUT_BUF(" sha1");
 	if (SO_EQ(isar0, ID_AA64ISAR0_EL1_SHA2,
 	    ID_AA64ISAR0_EL1_SHA2_SHA256HSU))
 		OUTPUT_BUF(" sha2");
 	if (SO_EQ(isar0, ID_AA64ISAR0_EL1_CRC32, ID_AA64ISAR0_EL1_CRC32_CRC32X))
 		OUTPUT_BUF(" crc32");
 	if (SO_EQ(isar0, ID_AA64ISAR0_EL1_ATOMIC, ID_AA64ISAR0_EL1_ATOMIC_SWP))
 		OUTPUT_BUF(" atomics");
 	if (SO_EQ(pfr0, ID_AA64PFR0_EL1_FP, ID_AA64PFR0_EL1_FP_HP))
 		OUTPUT_BUF(" fphp");
 	if (SO_EQ(pfr0, ID_AA64PFR0_EL1_ADVSIMD, ID_AA64PFR0_EL1_ADV_SIMD_HP))
 		OUTPUT_BUF(" asimdhp");
 	/* notyet: " cpuid" */
 	if (SO_EQ(isar0, ID_AA64ISAR0_EL1_RDM, ID_AA64ISAR0_EL1_RDM_SQRDML))
 		OUTPUT_BUF(" asimdrdm");
 	if (SO_EQ(isar1, ID_AA64ISAR1_EL1_JSCVT,
 	    ID_AA64ISAR1_EL1_JSCVT_SUPPORTED))
 		OUTPUT_BUF(" jscvt");
 	if (SO_EQ(isar1, ID_AA64ISAR1_EL1_FCMA,
 	    ID_AA64ISAR1_EL1_FCMA_SUPPORTED))
 		OUTPUT_BUF(" fcma");
 	if (SO_EQ(isar1, ID_AA64ISAR1_EL1_LRCPC, ID_AA64ISAR1_EL1_LRCPC_PR))
 		OUTPUT_BUF(" lrcpc");
 	if (SO_EQ(isar1, ID_AA64ISAR1_EL1_DPB, ID_AA64ISAR1_EL1_DPB_CVAP))
 		OUTPUT_BUF(" dcpop");
 	if (SO_EQ(isar0, ID_AA64ISAR0_EL1_SHA3, ID_AA64ISAR0_EL1_SHA3_EOR3))
 		OUTPUT_BUF(" sha3");
 	if (SO_EQ(isar0, ID_AA64ISAR0_EL1_SM3, ID_AA64ISAR0_EL1_SM3_SM3))
 		OUTPUT_BUF(" sm3");
 	if (SO_EQ(isar0, ID_AA64ISAR0_EL1_SM4, ID_AA64ISAR0_EL1_SM4_SM4))
 		OUTPUT_BUF(" sm4");
 	if (SO_EQ(isar0, ID_AA64ISAR0_EL1_DP,  ID_AA64ISAR0_EL1_DP_UDOT))
 		OUTPUT_BUF(" asimddp");
 	if (SO_EQ(isar0, ID_AA64ISAR0_EL1_SHA2,
 	    ID_AA64ISAR0_EL1_SHA2_SHA512HSU))
 		OUTPUT_BUF(" sha512");
 	if (SO_EQ(pfr0, ID_AA64PFR0_EL1_SVE, ID_AA64PFR0_EL1_SVE_IMPL))
 		OUTPUT_BUF(" sve");
 	if (SO_EQ(isar0, ID_AA64ISAR0_EL1_FHM, ID_AA64ISAR0_EL1_FHM_FMLAL))
 		OUTPUT_BUF(" asimdfhm");
 	if (SO_EQ(pfr0, ID_AA64PFR0_EL1_DIT, ID_AA64PFR0_EL1_DIT_IMPL))
 		OUTPUT_BUF(" dit");
 	if (SO_EQ(mmfr2, ID_AA64MMFR2_EL1_AT, ID_AA64MMFR2_EL1_AT_16BIT))
 		OUTPUT_BUF(" uscat");
 	if (SO_EQ(isar1, ID_AA64ISAR1_EL1_LRCPC, ID_AA64ISAR1_EL1_LRCPC_PR_UR))
 		OUTPUT_BUF(" ilrcpc");
 	if (SO_EQ(isar0, ID_AA64ISAR0_EL1_TS, ID_AA64ISAR0_EL1_TS_CFINV))
 		OUTPUT_BUF(" flagm");
 	if (SO_EQ(pfr1, ID_AA64PFR1_EL1_SSBS, ID_AA64PFR1_EL1_SSBS_MSR_MRS))
 		OUTPUT_BUF(" ssbs");
 	if (SO_EQ(isar1, ID_AA64ISAR1_EL1_SB, ID_AA64ISAR1_EL1_SB_SUPPORTED))
 		OUTPUT_BUF(" sb");
 #ifdef ARMV83_PAC
 	if (aarch64_pac_enabled)
 		OUTPUT_BUF(" paca pacg");
 #endif
 	if (SO_EQ(isar1, ID_AA64ISAR1_EL1_DPB, ID_AA64ISAR1_EL1_DPB_CVAP_CVADP))
 		OUTPUT_BUF(" dcpodp");
 	/* notyet: " sve2" */
 	/* notyet: " sveaes" */
 	/* notyet: " svepmull" */
 	/* notyet: " svebitperm" */
 	/* notyet: " svesha3" */
 	/* notyet: " svesm4" */
 	if (SO_EQ(isar0, ID_AA64ISAR0_EL1_TS, ID_AA64ISAR0_EL1_TS_AXFLAG))
 		OUTPUT_BUF(" flagm2");
 	if (SO_EQ(isar1, ID_AA64ISAR1_EL1_FRINTTS,
 	    ID_AA64ISAR1_EL1_FRINTTS_SUPPORTED))
 		OUTPUT_BUF(" frint");
 	/* notyet: " svei8mm" */
 	/* notyet: " svef32mm" */
 	/* notyet: " svef64mm" */
 	/* notyet: " svebf16" */
 	if (SO_EQ(isar1, ID_AA64ISAR1_EL1_I8MM,
 	    ID_AA64ISAR1_EL1_I8MM_SUPPORTED))
 		OUTPUT_BUF(" i8mm");
 	if (SO_EQ(isar1, ID_AA64ISAR1_EL1_BF16, ID_AA64ISAR1_EL1_BF16_BFDOT))
 		OUTPUT_BUF(" bf16");
 	if (SO_EQ(isar1, ID_AA64ISAR1_EL1_DGH, ID_AA64ISAR1_EL1_DGH_SUPPORTED))
 		OUTPUT_BUF(" dgh");
 	if (SO_EQ(isar0, ID_AA64ISAR0_EL1_RNDR, ID_AA64ISAR0_EL1_RNDR_RNDRRS))
 		OUTPUT_BUF(" rng");
 #ifdef ARMV85_BTI
 	if (aarch64_bti_enabled)
 		OUTPUT_BUF(" bti");
 #endif
 	OUTPUT_BUF("\n");
 #undef SO_EQ
 	return total;
+}
 int
 procfs_getcpuinfstr(char *buf, size_t *lenp)
+{
 	struct cpu_info *ci;
 	CPU_INFO_ITERATOR cii;
 	size_t left, len, total;
 	int ret = 0;
 	left = *lenp;
 	total = 0;
 	for (CPU_INFO_FOREACH(cii, ci)) {
 		OUTPUT_BUF("processor\t: %d\n", cii);
 		len = procfs_cpuinfo_features(ci, buf, left);
 		FORWARD_BUF(len);
 		OUTPUT_BUF("CPU implementer\t: 0x%02lx\n",
 		    __SHIFTOUT(ci->ci_id.ac_midr, CPU_ID_IMPLEMENTOR_MASK));
 		OUTPUT_BUF("CPU architecture: 8\n");	/* ARMv8 */
 		OUTPUT_BUF("CPU variant\t: 0x%lx\n",
 		    __SHIFTOUT(ci->ci_id.ac_midr, CPU_ID_VARIANT_MASK));
 		OUTPUT_BUF("CPU part\t: 0x%03lx\n",
 		    __SHIFTOUT(ci->ci_id.ac_midr, CPU_ID_PARTNO_MASK));
 		OUTPUT_BUF("CPU revision\t: %lu\n",
 		    __SHIFTOUT(ci->ci_id.ac_midr, CPU_ID_REVISION_MASK));
 		OUTPUT_BUF("\n");
+	}
 	/* not enough buffer? */
 	if (total >= *lenp)
 		ret = -1;
 	*lenp = total + 1;	/* total output + '\0' */
 	return ret;
+}

 @@ -1,252 +1,253 @@
-/*	$NetBSD: cpufunc.h,v 1.19 2020/12/04 08:29:11 skrll Exp $	*/
+/*	$NetBSD: cpufunc.h,v 1.20 2021/05/27 06:11:20 ryo Exp $	*/
 /*
  * Copyright (c) 2017 Ryo Shimizu <ryo@nerv.org>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #ifndef _AARCH64_CPUFUNC_H_
 #define _AARCH64_CPUFUNC_H_
 #ifdef _KERNEL
 #include <arm/armreg.h>
 #include <sys/device_if.h>
 struct aarch64_cache_unit {
 	u_int cache_type;
 #define CACHE_TYPE_VPIPT	0	/* VMID-aware PIPT */
 #define CACHE_TYPE_VIVT		1	/* ASID-tagged VIVT */
 #define CACHE_TYPE_VIPT		2
 #define CACHE_TYPE_PIPT		3
 	u_int cache_line_size;
 	u_int cache_ways;
 	u_int cache_sets;
 	u_int cache_way_size;
 	u_int cache_size;
 };
 struct aarch64_cache_info {
 	u_int cacheable;
 #define CACHE_CACHEABLE_NONE	0
 #define CACHE_CACHEABLE_ICACHE	1	/* instruction cache only */
 #define CACHE_CACHEABLE_DCACHE	2	/* data cache only */
 #define CACHE_CACHEABLE_IDCACHE	3	/* instruction and data caches */
 #define CACHE_CACHEABLE_UNIFIED	4	/* unified cache */
 	struct aarch64_cache_unit icache;
 	struct aarch64_cache_unit dcache;
 };
 #define MAX_CACHE_LEVEL	8		/* ARMv8 has maximum 8 level cache */
 extern u_int aarch64_cache_vindexsize;	/* cachesize/way (VIVT/VIPT) */
 extern u_int aarch64_cache_prefer_mask;
 extern u_int cputype;			/* compat arm */
 extern int aarch64_bti_enabled;
 extern int aarch64_pan_enabled;
 extern int aarch64_pac_enabled;
 void aarch64_pan_init(int);
 int aarch64_pac_init(int);
 int set_cpufuncs(void);
 void aarch64_getcacheinfo(int);
 void aarch64_printcacheinfo(device_t);
 void aarch64_dcache_wbinv_all(void);
 void aarch64_dcache_inv_all(void);
 void aarch64_dcache_wb_all(void);
 void aarch64_icache_inv_all(void);
 /* cache op in cpufunc_asm_armv8.S */
 void aarch64_nullop(void);
 uint32_t aarch64_cpuid(void);
 void aarch64_icache_sync_range(vaddr_t, vsize_t);
 void aarch64_icache_inv_range(vaddr_t, vsize_t);
 void aarch64_icache_barrier_range(vaddr_t, vsize_t);
 void aarch64_idcache_wbinv_range(vaddr_t, vsize_t);
 void aarch64_dcache_wbinv_range(vaddr_t, vsize_t);
 void aarch64_dcache_inv_range(vaddr_t, vsize_t);
 void aarch64_dcache_wb_range(vaddr_t, vsize_t);
 void aarch64_icache_inv_all(void);
 void aarch64_drain_writebuf(void);
 /* tlb op in cpufunc_asm_armv8.S */
 #define cpu_set_ttbr0(t)		curcpu()->ci_cpufuncs.cf_set_ttbr0((t))
 void aarch64_set_ttbr0(uint64_t);
 void aarch64_set_ttbr0_thunderx(uint64_t);
 void aarch64_tlbi_all(void);			/* all ASID, all VA */
 void aarch64_tlbi_by_asid(int);			/*  an ASID, all VA */
 void aarch64_tlbi_by_va(vaddr_t);		/* all ASID, a VA */
 void aarch64_tlbi_by_va_ll(vaddr_t);		/* all ASID, a VA, lastlevel */
 void aarch64_tlbi_by_asid_va(int, vaddr_t);	/*  an ASID, a VA */
 void aarch64_tlbi_by_asid_va_ll(int, vaddr_t);	/*  an ASID, a VA, lastlevel */
 /* misc */
 #define cpu_idnum()			aarch64_cpuid()
 /* cache op */
 #define cpu_dcache_wbinv_all()		aarch64_dcache_wbinv_all()
 #define cpu_dcache_inv_all()		aarch64_dcache_inv_all()
 #define cpu_dcache_wb_all()		aarch64_dcache_wb_all()
 #define cpu_idcache_wbinv_all()		\
 	(aarch64_dcache_wbinv_all(), aarch64_icache_inv_all())
 #define cpu_icache_sync_all()		\
 	(aarch64_dcache_wb_all(), aarch64_icache_inv_all())
 #define cpu_icache_inv_all()		aarch64_icache_inv_all()
 #define cpu_dcache_wbinv_range(v,s)	aarch64_dcache_wbinv_range((v),(s))
 #define cpu_dcache_inv_range(v,s)	aarch64_dcache_inv_range((v),(s))
 #define cpu_dcache_wb_range(v,s)	aarch64_dcache_wb_range((v),(s))
 #define cpu_idcache_wbinv_range(v,s)	aarch64_idcache_wbinv_range((v),(s))
 #define cpu_icache_sync_range(v,s)	\
 	curcpu()->ci_cpufuncs.cf_icache_sync_range((v),(s))
 #define cpu_sdcache_wbinv_range(v,p,s)	((void)0)
 #define cpu_sdcache_inv_range(v,p,s)	((void)0)
 #define cpu_sdcache_wb_range(v,p,s)	((void)0)
 /* others */
 #define cpu_drain_writebuf()		aarch64_drain_writebuf()
 extern u_int arm_dcache_align;
 extern u_int arm_dcache_align_mask;
 static inline bool
 cpu_gtmr_exists_p(void)
+{
 	return true;
+}
 static inline u_int
 cpu_clusterid(void)
+{
 	return __SHIFTOUT(reg_mpidr_el1_read(), MPIDR_AFF1);
+}
 static inline bool
 cpu_earlydevice_va_p(void)
+{
 	extern bool pmap_devmap_bootstrap_done;	/* in pmap.c */
 	/* This function may be called before enabling MMU, or mapping KVA */
 	if ((reg_sctlr_el1_read() & SCTLR_M) == 0)
 		return false;
 	/* device mapping will be availabled after pmap_devmap_bootstrap() */
 	if (!pmap_devmap_bootstrap_done)
 		return false;
 	return true;
+}
 #endif /* _KERNEL */
 /* definitions of TAG and PAC in pointers */
 #define AARCH64_ADDRTOP_TAG_BIT		55
 #define AARCH64_ADDRTOP_TAG		__BIT(55)	/* ECR_EL1.TBI[01]=1 */
 #define AARCH64_ADDRTOP_MSB		__BIT(63)	/* ECR_EL1.TBI[01]=0 */
 #define AARCH64_ADDRESS_TAG_MASK	__BITS(63,56)	/* if TCR.TBI[01]=1 */
 #define AARCH64_ADDRESS_PAC_MASK	__BITS(54,48)	/* depend on VIRT_BIT */
 #define AARCH64_ADDRESS_TAGPAC_MASK	\
 			(AARCH64_ADDRESS_TAG_MASK|AARCH64_ADDRESS_PAC_MASK)
 #ifdef _KERNEL
 /*
  * Which is the address space of this VA?
  * return the space considering TBI. (PAC is not yet)
+ *
  * return value: AARCH64_ADDRSPACE_{LOWER,UPPER}{_OUTOFRANGE}?
  */
 #define AARCH64_ADDRSPACE_LOWER			0	/* -> TTBR0 */
 #define AARCH64_ADDRSPACE_UPPER			1	/* -> TTBR1 */
 #define AARCH64_ADDRSPACE_LOWER_OUTOFRANGE	-1	/* certainly fault */
 #define AARCH64_ADDRSPACE_UPPER_OUTOFRANGE	-2	/* certainly fault */
 static inline int
 aarch64_addressspace(vaddr_t va)
+{
 	uint64_t addrtop, tbi;
 	addrtop = va & AARCH64_ADDRTOP_TAG;
 	tbi = addrtop ? TCR_TBI1 : TCR_TBI0;
 	if (reg_tcr_el1_read() & tbi) {
 		if (addrtop == 0) {
 			/* lower address, and TBI0 enabled */
 			if ((va & AARCH64_ADDRESS_PAC_MASK) != 0)
 				return AARCH64_ADDRSPACE_LOWER_OUTOFRANGE;
 			return AARCH64_ADDRSPACE_LOWER;
+		}
 		/* upper address, and TBI1 enabled */
 		if ((va & AARCH64_ADDRESS_PAC_MASK) != AARCH64_ADDRESS_PAC_MASK)
 			return AARCH64_ADDRSPACE_UPPER_OUTOFRANGE;
 		return AARCH64_ADDRSPACE_UPPER;
+	}
 	addrtop = va & AARCH64_ADDRTOP_MSB;
 	if (addrtop == 0) {
 		/* lower address, and TBI0 disabled */
 		if ((va & AARCH64_ADDRESS_TAGPAC_MASK) != 0)
 			return AARCH64_ADDRSPACE_LOWER_OUTOFRANGE;
 		return AARCH64_ADDRSPACE_LOWER;
+	}
 	/* upper address, and TBI1 disabled */
 	if ((va & AARCH64_ADDRESS_TAGPAC_MASK) != AARCH64_ADDRESS_TAGPAC_MASK)
 		return AARCH64_ADDRSPACE_UPPER_OUTOFRANGE;
 	return AARCH64_ADDRSPACE_UPPER;
+}
 static inline vaddr_t
 aarch64_untag_address(vaddr_t va)
+{
 	uint64_t addrtop, tbi;
 	addrtop = va & AARCH64_ADDRTOP_TAG;
 	tbi = addrtop ? TCR_TBI1 : TCR_TBI0;
 	if (reg_tcr_el1_read() & tbi) {
 		if (addrtop == 0) {
 			/* lower address, and TBI0 enabled */
 			return va & ~AARCH64_ADDRESS_TAG_MASK;
+		}
 		/* upper address, and TBI1 enabled */
 		return va | AARCH64_ADDRESS_TAG_MASK;
+	}
 	/* TBI[01] is disabled, nothing to do */
 	return va;
+}
 #endif /* _KERNEL */
 static __inline uint64_t
 aarch64_strip_pac(uint64_t __val)
+{
 	if (__val & AARCH64_ADDRTOP_TAG)
 		return __val | AARCH64_ADDRESS_TAGPAC_MASK;
 	return __val & ~AARCH64_ADDRESS_TAGPAC_MASK;
+}
 #endif /* _AARCH64_CPUFUNC_H_ */