Thu May 27 22:05:25 2021 UTC ()
Define the arithmetic exception summary bits passed in a0 to entArith.


(thorpej)
diff -r1.53 -r1.54 src/sys/arch/alpha/include/alpha_cpu.h
cvs diff -r1.53 -r1.54 src/sys/arch/alpha/include/alpha_cpu.h (expand / switch to unified diff)

--- src/sys/arch/alpha/include/alpha_cpu.h 2020/10/15 00:55:09 1.53
+++ src/sys/arch/alpha/include/alpha_cpu.h 2021/05/27 22:05:24 1.54
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: alpha_cpu.h,v 1.53 2020/10/15 00:55:09 thorpej Exp $ */ 1/* $NetBSD: alpha_cpu.h,v 1.54 2021/05/27 22:05:24 thorpej Exp $ */
2 2
3/* 3/*
4 * Copyright (c) 1996 Carnegie-Mellon University. 4 * Copyright (c) 1996 Carnegie-Mellon University.
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * Author: Chris G. Demetriou 7 * Author: Chris G. Demetriou
8 * 8 *
9 * Permission to use, copy, modify and distribute this software and 9 * Permission to use, copy, modify and distribute this software and
10 * its documentation is hereby granted, provided that both the copyright 10 * its documentation is hereby granted, provided that both the copyright
11 * notice and this permission notice appear in all copies of the 11 * notice and this permission notice appear in all copies of the
12 * software, derivative works or modified versions, and any portions 12 * software, derivative works or modified versions, and any portions
13 * thereof, and that both notices appear in supporting documentation. 13 * thereof, and that both notices appear in supporting documentation.
14 * 14 *
@@ -34,26 +34,27 @@ @@ -34,26 +34,27 @@
34 * Alpha CPU + OSF/1 PALcode definitions for use by the kernel. 34 * Alpha CPU + OSF/1 PALcode definitions for use by the kernel.
35 * 35 *
36 * Definitions for: 36 * Definitions for:
37 * 37 *
38 * Process Control Block 38 * Process Control Block
39 * Interrupt/Exception/Syscall Stack Frame 39 * Interrupt/Exception/Syscall Stack Frame
40 * Processor Status Register 40 * Processor Status Register
41 * Machine Check Error Summary Register 41 * Machine Check Error Summary Register
42 * Machine Check Logout Area 42 * Machine Check Logout Area
43 * Per CPU state Management of Machine Check Handling 43 * Per CPU state Management of Machine Check Handling
44 * Virtual Memory Management 44 * Virtual Memory Management
45 * Kernel Entry Vectors 45 * Kernel Entry Vectors
46 * MMCSR Fault Type Codes 46 * MMCSR Fault Type Codes
 47 * AESR Fault Code bits
47 * Translation Buffer Invalidation 48 * Translation Buffer Invalidation
48 * 49 *
49 * and miscellaneous PALcode operations. 50 * and miscellaneous PALcode operations.
50 */ 51 */
51 52
52 53
53/* 54/*
54 * Process Control Block definitions [OSF/1 PALcode Specific] 55 * Process Control Block definitions [OSF/1 PALcode Specific]
55 */ 56 */
56 57
57struct alpha_pcb { 58struct alpha_pcb {
58 unsigned long apcb_ksp; /* kernel stack ptr */ 59 unsigned long apcb_ksp; /* kernel stack ptr */
59 unsigned long apcb_usp; /* user stack ptr */ 60 unsigned long apcb_usp; /* user stack ptr */
@@ -255,26 +256,38 @@ typedef unsigned long alpha_pt_entry_t; @@ -255,26 +256,38 @@ typedef unsigned long alpha_pt_entry_t;
255 256
256/* 257/*
257 * Kernel Entry Vectors. [OSF/1 PALcode Specific] 258 * Kernel Entry Vectors. [OSF/1 PALcode Specific]
258 */ 259 */
259 260
260#define ALPHA_KENTRY_INT 0 261#define ALPHA_KENTRY_INT 0
261#define ALPHA_KENTRY_ARITH 1 262#define ALPHA_KENTRY_ARITH 1
262#define ALPHA_KENTRY_MM 2 263#define ALPHA_KENTRY_MM 2
263#define ALPHA_KENTRY_IF 3 264#define ALPHA_KENTRY_IF 3
264#define ALPHA_KENTRY_UNA 4 265#define ALPHA_KENTRY_UNA 4
265#define ALPHA_KENTRY_SYS 5 266#define ALPHA_KENTRY_SYS 5
266 267
267/* 268/*
 269 * Arithmetic Exception Summary Register. [OSF/1 PALcode Specific]
 270 */
 271
 272#define ALPHA_AESR_SWC __BIT(0) /* software completion */
 273#define ALPHA_AESR_INV __BIT(1) /* invalid operation */
 274#define ALPHA_AESR_DZE __BIT(2) /* division by zero */
 275#define ALPHA_AESR_OVF __BIT(3) /* overflow */
 276#define ALPHA_AESR_UNF __BIT(4) /* underflow */
 277#define ALPHA_AESR_INE __BIT(5) /* inexact result */
 278#define ALPHA_AESR_IOV __BIT(6) /* integer overflow */
 279
 280/*
268 * MMCSR Fault Type Codes. [OSF/1 PALcode Specific] 281 * MMCSR Fault Type Codes. [OSF/1 PALcode Specific]
269 */ 282 */
270 283
271#define ALPHA_MMCSR_INVALTRANS 0 284#define ALPHA_MMCSR_INVALTRANS 0
272#define ALPHA_MMCSR_ACCESS 1 285#define ALPHA_MMCSR_ACCESS 1
273#define ALPHA_MMCSR_FOR 2 286#define ALPHA_MMCSR_FOR 2
274#define ALPHA_MMCSR_FOE 3 287#define ALPHA_MMCSR_FOE 3
275#define ALPHA_MMCSR_FOW 4 288#define ALPHA_MMCSR_FOW 4
276 289
277/* 290/*
278 * Instruction Fault Type Codes. [OSF/1 PALcode Specific] 291 * Instruction Fault Type Codes. [OSF/1 PALcode Specific]
279 */ 292 */
280 293