 @@ -1,143 +1,144 @@
-/* $NetBSD: pci_machdep.h,v 1.21 2020/09/26 21:07:48 thorpej Exp $ */
+/* $NetBSD: pci_machdep.h,v 1.22 2021/05/27 22:11:31 thorpej Exp $ */
 /*
  * Copyright (c) 1996 Carnegie-Mellon University.
  * All rights reserved.
+ *
  * Author: Chris G. Demetriou
+ *
  * Permission to use, copy, modify and distribute this software and
  * its documentation is hereby granted, provided that both the copyright
  * notice and this permission notice appear in all copies of the
  * software, derivative works or modified versions, and any portions
  * thereof, and that both notices appear in supporting documentation.
+ *
  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
  * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
  * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
+ *
  * Carnegie Mellon requests users of this software to return to
+ *
  *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
  *  School of Computer Science
  *  Carnegie Mellon University
  *  Pittsburgh PA 15213-3890
+ *
  * any improvements or extensions that they make and grant Carnegie the
  * rights to redistribute these changes.
  */
 #ifndef _ALPHA_PCI_MACHDEP_H_
 #define	_ALPHA_PCI_MACHDEP_H_
 #include <sys/errno.h>
 /*
  * Machine-specific definitions for PCI autoconfiguration.
  */
 #define	__HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH
 #define	_PCI_HAVE_DMA64
 /*
  * Types provided to machine-independent PCI code
  */
 typedef struct alpha_pci_chipset *pci_chipset_tag_t;
 typedef u_long pcitag_t;
 typedef struct {
 	u_long value;
 } pci_intr_handle_t;
 /*
  * Forward declarations.
  */
 struct pci_attach_args;
 struct alpha_shared_intr;
 /*
  * alpha-specific PCI structure and type definitions.
  * NOT TO BE USED DIRECTLY BY MACHINE INDEPENDENT CODE.
  */
 struct alpha_pci_chipset {
 	void		*pc_conf_v;
 	void		(*pc_attach_hook)(device_t, device_t,
 			    struct pcibus_attach_args *);
 	int		(*pc_bus_maxdevs)(void *, int);
 	pcitag_t	(*pc_make_tag)(void *, int, int, int);
 	void		(*pc_decompose_tag)(void *, pcitag_t, int *,
 			    int *, int *);
 	pcireg_t	(*pc_conf_read)(void *, pcitag_t, int);
 	void		(*pc_conf_write)(void *, pcitag_t, int, pcireg_t);
 	void		*pc_intr_v;
 	int		(*pc_intr_map)(const struct pci_attach_args *,
 			    pci_intr_handle_t *);
 	const char	*(*pc_intr_string)(pci_chipset_tag_t,
 			    pci_intr_handle_t, char *, size_t);
 	const struct evcnt *(*pc_intr_evcnt)(pci_chipset_tag_t,
 			    pci_intr_handle_t);
 	void		*(*pc_intr_establish)(pci_chipset_tag_t,
 			    pci_intr_handle_t, int, int (*)(void *), void *);
 	void		(*pc_intr_disestablish)(pci_chipset_tag_t, void *);
 	void		*(*pc_pciide_compat_intr_establish)(device_t,
 			    const struct pci_attach_args *, int,
 			    int (*)(void *), void *);
 	struct alpha_shared_intr *pc_shared_intrs;
 	const char	*pc_intr_desc;
 	u_long		pc_vecbase;
 	u_int		pc_nirq;
 	u_long		pc_eligible_cpus;
 	void		(*pc_intr_enable)(pci_chipset_tag_t, int);
 	void		(*pc_intr_disable)(pci_chipset_tag_t, int);
 	void		(*pc_intr_set_affinity)(pci_chipset_tag_t, int,
 			    struct cpu_info *);
 };
 /*
  * Functions provided to machine-independent PCI code.
  */
 void	pci_attach_hook(device_t, device_t, struct pcibus_attach_args *);
 int	pci_bus_maxdevs(pci_chipset_tag_t, int);
 pcitag_t pci_make_tag(pci_chipset_tag_t, int, int, int);
 void	pci_decompose_tag(pci_chipset_tag_t, pcitag_t, int *, int *, int *);
 pcireg_t pci_conf_read(pci_chipset_tag_t, pcitag_t, int);
 void	pci_conf_write(pci_chipset_tag_t, pcitag_t, int, pcireg_t);
 int	pci_intr_map(const struct pci_attach_args *, pci_intr_handle_t *);
 const char *pci_intr_string(pci_chipset_tag_t, pci_intr_handle_t,
 	    char *, size_t);
 const struct evcnt *pci_intr_evcnt(pci_chipset_tag_t, pci_intr_handle_t);
 void	*pci_intr_establish(pci_chipset_tag_t, pci_intr_handle_t, int,
 	    int (*)(void *), void *);
 void	pci_intr_disestablish(pci_chipset_tag_t, void *);
 /*
  * alpha-specific PCI functions.
  * NOT TO BE USED DIRECTLY BY MACHINE INDEPENDENT CODE.
  */
 void	pci_display_console(bus_space_tag_t, bus_space_tag_t,
 	    pci_chipset_tag_t, int, int, int);
 void	device_pci_register(device_t, void *);
 int	alpha_pci_generic_intr_map(const struct pci_attach_args *,
 	    pci_intr_handle_t *);
 const char *alpha_pci_generic_intr_string(pci_chipset_tag_t,
 	    pci_intr_handle_t, char *, size_t);
 const struct evcnt *alpha_pci_generic_intr_evcnt(pci_chipset_tag_t,
 	    pci_intr_handle_t);
 void	*alpha_pci_generic_intr_establish(pci_chipset_tag_t,
 	    pci_intr_handle_t, int, int (*)(void *), void *);
 void	alpha_pci_generic_intr_disestablish(pci_chipset_tag_t, void *);
 void	alpha_pci_generic_iointr(void *, unsigned long);
 void	alpha_pci_generic_intr_redistribute(pci_chipset_tag_t);
 void	alpha_pci_intr_handle_init(pci_intr_handle_t *, u_int, u_int);
 void	alpha_pci_intr_handle_set_irq(pci_intr_handle_t *, u_int);
 u_int	alpha_pci_intr_handle_get_irq(const pci_intr_handle_t *);
 void	alpha_pci_intr_handle_set_flags(pci_intr_handle_t *, u_int);
 u_int	alpha_pci_intr_handle_get_flags(const pci_intr_handle_t *);
 #endif /* _ALPHA_PCI_MACHDEP_H_ */

 @@ -1,367 +1,367 @@
-/* $NetBSD: tsc.c,v 1.25 2021/04/24 23:36:23 thorpej Exp $ */
+/* $NetBSD: tsc.c,v 1.26 2021/05/27 22:11:31 thorpej Exp $ */
 /*-
  * Copyright (c) 1999 by Ross Harvey.  All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  * 3. All advertising materials mentioning features or use of this software
  *    must display the following acknowledgement:
  *	This product includes software developed by Ross Harvey.
  * 4. The name of Ross Harvey may not be used to endorse or promote products
  *    derived from this software without specific prior written permission.
+ *
  * THIS SOFTWARE IS PROVIDED BY ROSS HARVEY ``AS IS'' AND ANY EXPRESS
  * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURP0SE
  * ARE DISCLAIMED.  IN NO EVENT SHALL ROSS HARVEY BE LIABLE FOR ANY
  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
+ *
  */
 #include "opt_dec_6600.h"
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tsc.c,v 1.25 2021/04/24 23:36:23 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tsc.c,v 1.26 2021/05/27 22:11:31 thorpej Exp $");
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/device.h>
 #include <sys/malloc.h>
 #include <machine/autoconf.h>
 #include <machine/rpb.h>
 #include <machine/sysarch.h>
 #include <dev/isa/isareg.h>
 #include <dev/isa/isavar.h>
 #include <dev/pci/pcireg.h>
 #include <dev/pci/pcivar.h>
 #include <alpha/pci/tsreg.h>
 #include <alpha/pci/tsvar.h>
 #include "tsciic.h"
 #ifdef DEC_6600
 #include <alpha/pci/pci_6600.h>
 #endif
 #define tsc() { Generate ctags(1) key. }
 static int tscmatch(device_t, cfdata_t, void *);
 static void tscattach(device_t, device_t, void *);
 CFATTACH_DECL_NEW(tsc, 0, tscmatch, tscattach, NULL, NULL);
 extern struct cfdriver tsc_cd;
 struct tsp_config tsp_configuration[4];
 static int tscprint(void *, const char *pnp);
 static int tspmatch(device_t, cfdata_t, void *);
 static void tspattach(device_t, device_t, void *);
 CFATTACH_DECL_NEW(tsp, 0, tspmatch, tspattach, NULL, NULL);
 extern struct cfdriver tsp_cd;
 static int tsp_bus_get_window(int, int,
 	struct alpha_bus_space_translation *);
 static int tsciicprint(void *, const char *pnp);
 static int tsciicmatch(device_t, cfdata_t, void *);
 static void tsciicattach(device_t, device_t, void *);
 CFATTACH_DECL_NEW(tsciic, sizeof(struct tsciic_softc), tsciicmatch,
     tsciicattach, NULL, NULL);
 #if NTSCIIC
 extern struct cfdriver tsciic_cd;
 #endif
 /* There can be only one */
 static int tscfound;
 /* Which hose is the display console connected to? */
 int tsp_console_hose;
 static int
 tscmatch(device_t parent, cfdata_t match, void *aux)
+{
 	struct mainbus_attach_args *ma = aux;
 	switch (cputype) {
 	case ST_DEC_6600:
 	case ST_DEC_TITAN:
 		return strcmp(ma->ma_name, tsc_cd.cd_name) == 0 && !tscfound;
 	default:
 		return 0;
+	}
+}
 static void
 tscattach(device_t parent, device_t self, void * aux)
+{
 	int i;
 	int nbus;
 	uint64_t csc, aar;
 	struct tsp_attach_args tsp;
 	struct tsciic_attach_args tsciic;
 	struct mainbus_attach_args *ma = aux;
 	int titan = cputype == ST_DEC_TITAN;
 	tscfound = 1;
 	csc = LDQP(TS_C_CSC);
 	nbus = 1 + (CSC_BC(csc) >= 2);
 	printf(": 2127%c Core Logic Chipset, Cchip rev %d\n"
 		"%s%d: %c Dchips, %d memory bus%s of %d bytes\n",
 		titan ? '4' : '2', (int)MISC_REV(LDQP(TS_C_MISC)),
 		ma->ma_name, ma->ma_slot, "2448"[CSC_BC(csc)],
 		nbus, nbus > 1 ? "es" : "", 16 + 16 * ((csc & CSC_AW) != 0));
 	printf("%s%d: arrays present: ", ma->ma_name, ma->ma_slot);
 	for (i = 0; i < 4; ++i) {
 		aar = LDQP(TS_C_AAR0 + i * TS_STEP);
 		printf("%s%dMB%s", i ? ", " : "", (8 << AAR_ASIZ(aar)) & ~0xf,
 		    aar & AAR_SPLIT ? " (split)" : "");
+	}
 	printf(", Dchip 0 rev %d\n", (int)LDQP(TS_D_DREV) & 0xf);
 	memset(&tsp, 0, sizeof tsp);
 	tsp.tsp_name = "tsp";
 	tsp.tsp_slot = 0;
 	config_found(self, &tsp, tscprint, CFARG_EOL);
 	if (titan) {
 		tsp.tsp_slot += 2;
 		config_found(self, &tsp, tscprint, CFARG_EOL);
+	}
 	if (csc & CSC_P1P) {
 		tsp.tsp_slot = 1;
 		config_found(self, &tsp, tscprint, CFARG_EOL);
 		if (titan) {
 			tsp.tsp_slot += 2;
 			config_found(self, &tsp, tscprint, CFARG_EOL);
+		}
+	}
 	memset(&tsciic, 0, sizeof tsciic);
 	tsciic.tsciic_name = "tsciic";
 	config_found(self, &tsciic, tsciicprint, CFARG_EOL);
+}
 static int
 tscprint(void *aux, const char *p)
+{
 	struct tsp_attach_args *tsp = aux;
 	if (p)
 		aprint_normal("%s%d at %s", tsp->tsp_name, tsp->tsp_slot, p);
 	return UNCONF;
+}
 static int
 tsciicprint(void *aux, const char *p)
+{
 	struct tsciic_attach_args *tsciic = aux;
 	if (p)
 		aprint_normal("%s at %s\n", tsciic->tsciic_name, p);
 	else
 		aprint_normal("\n");
 	return UNCONF;
+}
 #define tsp() { Generate ctags(1) key. }
 static int
 tspmatch(device_t parent, cfdata_t match, void *aux)
+{
 	struct tsp_attach_args *t = aux;
 	switch (cputype) {
 	case ST_DEC_6600:
 	case ST_DEC_TITAN:
 		return strcmp(t->tsp_name, tsp_cd.cd_name) == 0;
 	default:
 		return 0;
+	}
+}
 static void
 tspattach(device_t parent, device_t self, void *aux)
+{
 	struct pcibus_attach_args pba;
 	struct tsp_attach_args *t = aux;
 	struct tsp_config *pcp;
 	printf("\n");
 	pcp = tsp_init(1, t->tsp_slot);
 	tsp_dma_init(pcp);
 	/*
 	 * Do PCI memory initialization that needs to be deferred until
 	 * malloc is safe.  On the Tsunami, we need to do this after
 	 * DMA is initialized, as well.
 	 */
 	tsp_bus_mem_init2(&pcp->pc_memt, pcp);
 	pci_6600_pickintr(pcp);
 	pba.pba_iot = &pcp->pc_iot;
 	pba.pba_memt = &pcp->pc_memt;
 	pba.pba_dmat =
 	    alphabus_dma_get_tag(&pcp->pc_dmat_direct, ALPHA_BUS_PCI);
-	pba.pba_dmat64 = NULL;
+	pba.pba_dmat64 = &pcp->pc_dmat64_direct;
 	pba.pba_pc = &pcp->pc_pc;
 	pba.pba_bus = 0;
 	pba.pba_bridgetag = NULL;
 	pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY |
 	    PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY;
 	config_found(self, &pba, pcibusprint, CFARG_EOL);
+}
 struct tsp_config *
 tsp_init(int mallocsafe, int n)
 	/* n:	 Pchip number */
+{
 	struct tsp_config *pcp;
 	int titan = cputype == ST_DEC_TITAN;
 	KASSERT(n >= 0 && n < __arraycount(tsp_configuration));
 	pcp = &tsp_configuration[n];
 	pcp->pc_pslot = n;
 	pcp->pc_iobase = TS_Pn(n, 0);
 	pcp->pc_csr = S_PAGE(TS_Pn(n & 1, P_CSRBASE));
 	if (n & 2) {
 		/* `A' port of PA Chip */
 		pcp->pc_csr++;
+	}
 	if (titan) {
 		/* same address on G and A ports */
 		pcp->pc_tlbia = &pcp->pc_csr->port.g.tsp_tlbia.tsg_r;
 	} else {
 		pcp->pc_tlbia = &pcp->pc_csr->port.p.tsp_tlbia.tsg_r;
+	}
 	if (!pcp->pc_initted) {
 		tsp_bus_io_init(&pcp->pc_iot, pcp);
 		tsp_bus_mem_init(&pcp->pc_memt, pcp);
 		alpha_bus_window_count[ALPHA_BUS_TYPE_PCI_IO] = 1;
 		alpha_bus_window_count[ALPHA_BUS_TYPE_PCI_MEM] = 1;
 		alpha_bus_get_window = tsp_bus_get_window;
+	}
 	pcp->pc_mallocsafe = mallocsafe;
 	tsp_pci_init(&pcp->pc_pc, pcp);
 	pcp->pc_initted = 1;
 	return pcp;
+}
 static int
 tsp_bus_get_window(int type, int window,
     struct alpha_bus_space_translation *abst)
+{
 	struct tsp_config *tsp = &tsp_configuration[tsp_console_hose];
 	bus_space_tag_t st;
 	int error;
 	switch (type) {
 	case ALPHA_BUS_TYPE_PCI_IO:
 		st = &tsp->pc_iot;
 		break;
 	case ALPHA_BUS_TYPE_PCI_MEM:
 		st = &tsp->pc_memt;
 		break;
 	default:
 		panic("tsp_bus_get_window");
+	}
 	error = alpha_bus_space_get_window(st, window, abst);
 	if (error)
 		return error;
 	abst->abst_sys_start = TS_PHYSADDR(abst->abst_sys_start);
 	abst->abst_sys_end = TS_PHYSADDR(abst->abst_sys_end);
 	return 0;
+}
 #define tsciic() { Generate ctags(1) key. }
 static int
 tsciicmatch(device_t parent, cfdata_t match, void *aux)
+{
 #if NTSCIIC
 	struct tsciic_attach_args *t = aux;
 #endif
 	switch (cputype) {
 	case ST_DEC_6600:
 	case ST_DEC_TITAN:
 #if NTSCIIC
 		return strcmp(t->tsciic_name, tsciic_cd.cd_name) == 0;
 #endif
 	default:
 		return 0;
+	}
+}
 static void
 tsciicattach(device_t parent, device_t self, void *aux)
+{
 #if NTSCIIC
 	tsciic_init(self);
 #endif
+}
 void
 tsc_print_dir(unsigned int indent, unsigned long dir)
+{
 	char buf[60];
 	snprintb(buf, 60,
 		 "\177\20"
 		 "b\77Internal Cchip asynchronous error\0"
 		 "b\76Pchip 0 error\0"
 		 "b\75Pchip 1 error\0"
 		 "b\74Pchip 2 error\0"
 		 "b\73Pchip 3 error\0",
 		 dir);
 	IPRINTF(indent, "DIR = %s\n", buf);
+}
 void
 tsc_print_misc(unsigned int indent, unsigned long misc)
+{
 	unsigned long tmp = MISC_NXM_SRC(misc);
 	if (!MISC_NXM(misc))
 		return;
 	IPRINTF(indent, "NXM address detected\n");
 	IPRINTF(indent, "NXM source         = %s %lu\n",
 		tmp <= 3 ? "CPU" : "Pchip", tmp <= 3 ? tmp : tmp - 4);
+}

 @@ -1,360 +1,413 @@
-/* $NetBSD: tsp_dma.c,v 1.16 2021/05/05 02:15:18 thorpej Exp $ */
+/* $NetBSD: tsp_dma.c,v 1.17 2021/05/27 22:11:31 thorpej Exp $ */
 /*-
  * Copyright (c) 1997, 1998, 2021 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
  * NASA Ames Research Center.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 /*-
  * Copyright (c) 1999 by Ross Harvey.  All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  * 3. All advertising materials mentioning features or use of this software
  *    must display the following acknowledgement:
  *	This product includes software developed by Ross Harvey.
  * 4. The name of Ross Harvey may not be used to endorse or promote products
  *    derived from this software without specific prior written permission.
+ *
  * THIS SOFTWARE IS PROVIDED BY ROSS HARVEY ``AS IS'' AND ANY EXPRESS
  * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURP0SE
  * ARE DISCLAIMED.  IN NO EVENT SHALL ROSS HARVEY BE LIABLE FOR ANY
  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 /*-
  * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc.
  * All rights reserved.
  * This code is derived from software contributed to The NetBSD Foundation
  * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
  * NASA Ames Research Center.
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tsp_dma.c,v 1.16 2021/05/05 02:15:18 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tsp_dma.c,v 1.17 2021/05/27 22:11:31 thorpej Exp $");
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/kernel.h>
 #include <sys/device.h>
 #include <sys/malloc.h>
 #include <machine/autoconf.h>
 #define _ALPHA_BUS_DMA_PRIVATE
 #include <sys/bus.h>
 #include <machine/rpb.h>
 #include <dev/pci/pcireg.h>
 #include <dev/pci/pcivar.h>
 #include <alpha/pci/tsreg.h>
 #include <alpha/pci/tsvar.h>
 #define tsp_dma() { Generate ctags(1) key. }
 #define	EDIFF(a, b) (((a) | WSBA_ENA | WSBA_SG)	!= ((b) | WSBA_ENA | WSBA_SG))
 static bus_dma_tag_t tsp_dma_get_tag(bus_dma_tag_t, alpha_bus_t);
 static int	tsp_bus_dmamap_load_sgmap(bus_dma_tag_t, bus_dmamap_t, void *,
 		    bus_size_t, struct proc *, int);
 static int	tsp_bus_dmamap_load_mbuf_sgmap(bus_dma_tag_t, bus_dmamap_t,
 		    struct mbuf *, int);
 static int	tsp_bus_dmamap_load_uio_sgmap(bus_dma_tag_t, bus_dmamap_t,
 		    struct uio *, int);
 static int	tsp_bus_dmamap_load_raw_sgmap(bus_dma_tag_t, bus_dmamap_t,
 		    bus_dma_segment_t *, int, bus_size_t, int);
 static void	tsp_bus_dmamap_unload_sgmap(bus_dma_tag_t, bus_dmamap_t);
 static void	tsp_tlb_invalidate(struct tsp_config *);
 /*
  * XXX Need to figure out what this is, if any.  Initialize it to
  * XXX something that should be safe.
  */
 #define	TSP_SGMAP_PFTHRESH	256
 /*
  * Quoting the 21272 programmer's reference manual:
+ *
  * <quote>
  * 10.1.4.4 Monster Window DMA Address Translation
+ *
  * In case of a PCI dual-address cycle command, the high-order PCI address
  * bits <63:40> are compared to the constant value 0x0000_01 (that is, bit
  * <40> = 1; all other bits = 0). If these bits match, a monster window hit
  * has occurred and the low-order PCI address bits <34:0> are used unchanged
  * as the system address bits <34:0>. PCI address bits <39:35> are ignored.
  * The high-order 32 PCI address bits are available on b_ad<31:0> in the
  * second cycle of a DAC, and also on b_ad<63:32> in the first cycle of a
  * DAC if b_req64_l is asserted.
  * </quote>
+ *
  * This means that we can address up to 32GB of RAM using a direct-mapped
  * 64-bit DMA tag.  This leaves us possibly having to fall back on SGMAP
  * DMA on a Titan system (those support up to 64GB of RAM), and we may have
  * to address that with an additional large SGMAP DAC window at another
  * time.
  */
 #define	TSP_MONSTER_DMA_WINDOW_BASE	0x100##00000000UL
 #define	TSP_MONSTER_DMA_WINDOW_SIZE	0x008##00000000UL
 void
 tsp_dma_init(struct tsp_config *pcp)
+{
 	int i;
 	bus_dma_tag_t t;
 	struct ts_pchip *pccsr = pcp->pc_csr;
 	bus_addr_t dwbase, dwlen, sgwbase, sgwlen, tbase;
 	static struct map_expected {
 		uint32_t base, mask, enables;
 	} premap[4] = {
 		{ 0x00800000, 0x00700000, WSBA_ENA | WSBA_SG },
 		{ 0x80000000, 0x3ff00000, WSBA_ENA           },
 		{ 0, 0, 0 },
 		{ 0, 0, 0 }
 	};
 	alpha_mb();
 	for(i = 0; i < 4; ++i) {
 		if (EDIFF(pccsr->tsp_wsba[i].tsg_r, premap[i].base) ||
 		    EDIFF(pccsr->tsp_wsm[i].tsg_r, premap[i].mask))
 			printf("tsp%d: window %d: %lx/base %lx/mask %lx"
 			    " reinitialized\n",
 			    pcp->pc_pslot, i,
 			    pccsr->tsp_wsba[i].tsg_r,
 			    pccsr->tsp_wsm[i].tsg_r,
 			    pccsr->tsp_tba[i].tsg_r);
 		pccsr->tsp_wsba[i].tsg_r = premap[i].base | premap[i].enables;
 		pccsr->tsp_wsm[i].tsg_r = premap[i].mask;
+	}
 	/* Ensure the Monster Window is enabled. */
 	pccsr->tsp_pctl.tsg_r |= PCTL_MWIN;
 	alpha_mb();
 	/*
 	 * Initialize the DMA tag used for direct-mapped 64-bit DMA.
 	 */
 	t = &pcp->pc_dmat64_direct;
 	t->_cookie = pcp;
 	t->_wbase = TSP_MONSTER_DMA_WINDOW_BASE;
 	t->_wsize = TSP_MONSTER_DMA_WINDOW_SIZE;
 	t->_next_window = &pcp->pc_dmat_sgmap;
 	t->_boundary = 0;
 	t->_sgmap = NULL;
 	t->_get_tag = tsp_dma_get_tag;
 	t->_dmamap_create = _bus_dmamap_create;
 	t->_dmamap_destroy = _bus_dmamap_destroy;
 	t->_dmamap_load = _bus_dmamap_load_direct;
 	t->_dmamap_load_mbuf = _bus_dmamap_load_mbuf_direct;
 	t->_dmamap_load_uio = _bus_dmamap_load_uio_direct;
 	t->_dmamap_load_raw = _bus_dmamap_load_raw_direct;
 	t->_dmamap_unload = _bus_dmamap_unload;
 	t->_dmamap_sync = _bus_dmamap_sync;
 	t->_dmamem_alloc = _bus_dmamem_alloc;
 	t->_dmamem_free = _bus_dmamem_free;
 	t->_dmamem_map = _bus_dmamem_map;
 	t->_dmamem_unmap = _bus_dmamem_unmap;
 	t->_dmamem_mmap = _bus_dmamem_mmap;
 	/*
 	 * Initialize the DMA tag used for direct-mapped DMA.
 	 */
 	t = &pcp->pc_dmat_direct;
 	t->_cookie = pcp;
 	t->_wbase = dwbase = WSBA_ADDR(pccsr->tsp_wsba[1].tsg_r);
 	t->_wsize = dwlen = WSM_LEN(pccsr->tsp_wsm[1].tsg_r);
 	t->_next_window = &pcp->pc_dmat_sgmap;
 	t->_boundary = 0;
 	t->_sgmap = NULL;
 	t->_get_tag = tsp_dma_get_tag;
 	t->_dmamap_create = _bus_dmamap_create;
 	t->_dmamap_destroy = _bus_dmamap_destroy;
 	t->_dmamap_load = _bus_dmamap_load_direct;
 	t->_dmamap_load_mbuf = _bus_dmamap_load_mbuf_direct;
 	t->_dmamap_load_uio = _bus_dmamap_load_uio_direct;
 	t->_dmamap_load_raw = _bus_dmamap_load_raw_direct;
 	t->_dmamap_unload = _bus_dmamap_unload;
 	t->_dmamap_sync = _bus_dmamap_sync;
 	t->_dmamem_alloc = _bus_dmamem_alloc;
 	t->_dmamem_free = _bus_dmamem_free;
 	t->_dmamem_map = _bus_dmamem_map;
 	t->_dmamem_unmap = _bus_dmamem_unmap;
 	t->_dmamem_mmap = _bus_dmamem_mmap;
 	/*
 	 * Initialize the DMA tag used for sgmap-mapped DMA.
 	 */
 	t = &pcp->pc_dmat_sgmap;
 	t->_cookie = pcp;
 	t->_wbase = sgwbase = WSBA_ADDR(pccsr->tsp_wsba[0].tsg_r);
 	t->_wsize = sgwlen = WSM_LEN(pccsr->tsp_wsm[0].tsg_r);
 	t->_next_window = NULL;
 	t->_boundary = 0;
 	t->_sgmap = &pcp->pc_sgmap;
 	t->_pfthresh = TSP_SGMAP_PFTHRESH;
 	t->_get_tag = tsp_dma_get_tag;
 	t->_dmamap_create = alpha_sgmap_dmamap_create;
 	t->_dmamap_destroy = alpha_sgmap_dmamap_destroy;
 	t->_dmamap_load = tsp_bus_dmamap_load_sgmap;
 	t->_dmamap_load_mbuf = tsp_bus_dmamap_load_mbuf_sgmap;
 	t->_dmamap_load_uio = tsp_bus_dmamap_load_uio_sgmap;
 	t->_dmamap_load_raw = tsp_bus_dmamap_load_raw_sgmap;
 	t->_dmamap_unload = tsp_bus_dmamap_unload_sgmap;
 	t->_dmamap_sync = _bus_dmamap_sync;
 	t->_dmamem_alloc = _bus_dmamem_alloc;
 	t->_dmamem_free = _bus_dmamem_free;
 	t->_dmamem_map = _bus_dmamem_map;
 	t->_dmamem_unmap = _bus_dmamem_unmap;
 	t->_dmamem_mmap = _bus_dmamem_mmap;
 	/*
 	 * Initialize the SGMAP.  Align page table to 32k in case
 	 * window is somewhat larger than expected.
 	 */
 	alpha_sgmap_init(t, &pcp->pc_sgmap, "tsp_sgmap",
 	    sgwbase, 0, sgwlen, sizeof(uint64_t), NULL, (32*1024));
 	/*
 	 * Enable window 0 and enable SG PTE mapping.
 	 */
 	alpha_mb();
 	pccsr->tsp_wsba[0].tsg_r |= WSBA_SG | WSBA_ENA;
 	alpha_mb();
 	/*
 	 * Enable window 1 in direct mode.
 	 */
 	alpha_mb();
 	pccsr->tsp_wsba[1].tsg_r =
 	    (pccsr->tsp_wsba[1].tsg_r & ~WSBA_SG) | WSBA_ENA;
 	alpha_mb();
 	/*
 	 * Check windows for sanity, especially if we later decide to
 	 * use the firmware's initialization in some cases.
 	 */
 	if ((sgwbase <= dwbase && dwbase < sgwbase + sgwlen) ||
 	    (dwbase <= sgwbase && sgwbase < dwbase + dwlen))
 		panic("tsp_dma_init: overlap");
 	tbase = pcp->pc_sgmap.aps_ptpa;
 	if (tbase & ~0x7fffffc00UL)
 		panic("tsp_dma_init: bad page table address");
 	alpha_mb();
 	pccsr->tsp_tba[0].tsg_r = tbase;
 	alpha_mb();
 	tsp_tlb_invalidate(pcp);
 	alpha_mb();
+}
 /*
  * Return the bus dma tag to be used for the specified bus type.
  * INTERNAL USE ONLY!
  */
 static bus_dma_tag_t
 tsp_dma_get_tag(bus_dma_tag_t t, alpha_bus_t bustype)
+{
 	struct tsp_config *pcp = t->_cookie;
 	switch (bustype) {
 	case ALPHA_BUS_PCI:
 	case ALPHA_BUS_EISA:
 		/*
 		 * The direct mapped window will work for most systems,
 		 * most of the time. When it doesn't, we chain to the sgmap
 		 * window automatically.
 		 */
 		return (&pcp->pc_dmat_direct);
 	case ALPHA_BUS_ISA:
 		/*
 		 * ISA doesn't have enough address bits to use
 		 * the direct-mapped DMA window, so we must use
 		 * SGMAPs.
 		 */
 		return (&pcp->pc_dmat_sgmap);
 	default:
 		panic("tsp_dma_get_tag: shouldn't be here, really...");
+	}
+}
 /*
  * Load a TSP SGMAP-mapped DMA map with a linear buffer.
  */
 static int
 tsp_bus_dmamap_load_sgmap(bus_dma_tag_t t, bus_dmamap_t map, void *buf, bus_size_t buflen, struct proc *p, int flags)
+{
 	int error;
 	error = pci_sgmap_pte64_load(t, map, buf, buflen, p, flags,
 	    t->_sgmap);
 	if (error == 0)
 		tsp_tlb_invalidate(t->_cookie);
 	return (error);
+}
 /*
  * Load a TSP SGMAP-mapped DMA map with an mbuf chain.
  */
 static int
 tsp_bus_dmamap_load_mbuf_sgmap(bus_dma_tag_t t, bus_dmamap_t map, struct mbuf *m, int flags)
+{
 	int error;
 	error = pci_sgmap_pte64_load_mbuf(t, map, m, flags, t->_sgmap);
 	if (error == 0)
 		tsp_tlb_invalidate(t->_cookie);
 	return (error);
+}
 /*
  * Load a TSP SGMAP-mapped DMA map with a uio.
  */
 static int
 tsp_bus_dmamap_load_uio_sgmap(bus_dma_tag_t t, bus_dmamap_t map, struct uio *uio, int flags)
+{
 	int error;
 	error = pci_sgmap_pte64_load_uio(t, map, uio, flags, t->_sgmap);
 	if (error == 0)
 		tsp_tlb_invalidate(t->_cookie);
 	return (error);
+}
 /*
  * Load a TSP SGMAP-mapped DMA map with raw memory.
  */
 static int
 tsp_bus_dmamap_load_raw_sgmap(bus_dma_tag_t t, bus_dmamap_t map, bus_dma_segment_t *segs, int nsegs, bus_size_t size, int flags)
+{
 	int error;
 	error = pci_sgmap_pte64_load_raw(t, map, segs, nsegs, size, flags,
 	    t->_sgmap);
 	if (error == 0)
 		tsp_tlb_invalidate(t->_cookie);
 	return (error);
+}
 /*
  * Unload a TSP DMA map.
  */
 static void
 tsp_bus_dmamap_unload_sgmap(bus_dma_tag_t t, bus_dmamap_t map)
+{
 	/*
 	 * Invalidate any SGMAP page table entries used by this
 	 * mapping.
 	 */
 	pci_sgmap_pte64_unload(t, map, t->_sgmap);
 	tsp_tlb_invalidate(t->_cookie);
 	/*
 	 * Do the generic bits of the unload.
 	 */
 	_bus_dmamap_unload_common(t, map);
+}
 /*
  * Flush the TSP scatter/gather TLB.
  */
 static void
 tsp_tlb_invalidate(struct tsp_config *pcp)
+{
 	alpha_mb();
 	*pcp->pc_tlbia = 0;
 	alpha_mb();
+}

 @@ -1,290 +1,313 @@
-/* $NetBSD: tsreg.h,v 1.8 2020/09/23 00:46:17 thorpej Exp $ */
+/* $NetBSD: tsreg.h,v 1.9 2021/05/27 22:11:31 thorpej Exp $ */
 /*-
  * Copyright (c) 1999 by Ross Harvey.  All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  * 3. All advertising materials mentioning features or use of this software
  *    must display the following acknowledgement:
  *	This product includes software developed by Ross Harvey.
  * 4. The name of Ross Harvey may not be used to endorse or promote products
  *    derived from this software without specific prior written permission.
+ *
  * THIS SOFTWARE IS PROVIDED BY ROSS HARVEY ``AS IS'' AND ANY EXPRESS
  * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURP0SE
  * ARE DISCLAIMED.  IN NO EVENT SHALL ROSS HARVEY BE LIABLE FOR ANY
  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
+ *
  */
 /*
  * 21272 Core Logic registers and constants.
  */
 #define	tsreg() { Generate ctags(1) key. }
 /*
  * Superpage pointer from physical address.
  */
 #define	S_PAGE(phys) ((void *)ALPHA_PHYS_TO_K0SEG(phys))
 /*
  * {LD,ST}QP: LoaD and STore Quad Physical
  */
 #define	LDQP(a)	(*(volatile long *)ALPHA_PHYS_TO_K0SEG(a))
 #define	STQP(a) LDQP(a)
 /*
  * Define extraction functions for bit fields via length and left,right bitno
  */
 #define	TSFIELD(r,offs,len) (((r) >> (offs)) & (~0UL >> (64 - (len))))
 #define	TSFIELDBB(r,lb,rb) TSFIELD((r), (rb), (lb) - (rb) + 1)
 /*
  * EV6 has a new superpage which can pass through 44 address bits.  (Umm, a
  * superduperpage?) But, the firmware doesn't turn it on, so we use the old
  * one and let the HW sign extend va/pa<40> to get us the pa<43> that makes
  * the needed I/O space access. This is just as well; it means we don't have
  * to worry about which GENERIC code might get called on other CPU models.
+ *
  *	E.g., we want this:	      0x0801##a000##0000
  *	We use this:		      0x0101##a000##0000
  *	...mix in the old SP:	0xffff##fc00##0000##0000
  *	...after PA sign ext:	0xffff##ff00##a000##0000
  *	(PA<42:41> ignored)
  */
 /*
  * This hack allows us to map the I/O address space without using
  * the KSEG sign extension hack.
  */
 #define	TS_PHYSADDR(x)							\
 	(((x) & ~0x0100##0000##0000) | 0x0800##0000##0000)
 /*
  * Cchip CSR Map
  */
 #define TS_C_CSC	0x101##a000##0000UL	/* Cchip System Configuration */
 #	define	CSC_P1P		(1L << 14)
 #	define	CSC_BC(r)	TSFIELD((r), 0, 2)
 #	define	CSC_AW		(1L << 8)
 #define TS_C_MTR	0x101##a000##0040UL
 #define TS_C_MISC	0x101##a000##0080UL	/* Miscellaneous Register */
 #	define	MISC_NXM(r)	TSFIELD((r), 28, 1)
 #	define	MISC_NXM_SRC(r)	TSFIELD((r), 29, 3)
 #	define	MISC_REV(r)	TSFIELD((r), 39, 8)
 #define TS_C_MPD	0x101##a000##00c0UL
 #	define	MPD_DR	0x08	/* RO: Data receive */
 #	define	MPD_CKR	0x04	/* RO: Clock receive */
 #	define	MPD_DS	0x02	/* WO: Data send - Must be a 1 to receive */
 #	define	MPD_CKS	0x01	/* WO: Clock send */
 #define TS_C_AAR0	0x101##a000##0100UL
 #define TS_C_AAR1	0x101##a000##0140UL
 #define TS_C_AAR2	0x101##a000##0180UL
 #define TS_C_AAR3	0x101##a000##01c0UL
 #	define	AAR_ASIZ(r)	TSFIELD((r), 12, 4)
 #	define	AAR_SPLIT	(1L << 8)
 #define TS_C_DIM0	0x101##a000##0200UL
 #define TS_C_DIM1	0x101##a000##0240UL
 #define TS_C_DIR0	0x101##a000##0280UL
 #define TS_C_DIR1	0x101##a000##02c0UL
 #define TS_C_DRIR	0x101##a000##0300UL
 #define TS_C_PRBEN	0x101##a000##0340UL
 #define TS_C_IIC0	0x101##a000##0380UL
 #define TS_C_IIC1	0x101##a000##03c0UL
 #define TS_C_MPR0	0x101##a000##0400UL
 #define TS_C_MPR1	0x101##a000##0440UL
 #define TS_C_MPR2	0x101##a000##0480UL
 #define TS_C_MPR3	0x101##a000##04c0UL
 #define TS_C_MCTL	0x101##a000##0500UL
 #define TS_C_TTR	0x101##a000##0580UL
 #define TS_C_TDR	0x101##a000##05c0UL
 #define TS_C_DIM2	0x101##a000##0600UL
 #define TS_C_DIM3	0x101##a000##0640UL
 #define TS_C_DIR2	0x101##a000##0680UL
 #define TS_C_DIR3	0x101##a000##06c0UL
 #define TS_C_IIC2	0x101##a000##0700UL
 #define TS_C_IIC3	0x101##a000##0740UL
 /*
  * Dchip CSR Map
  */
 #define TS_D_DSC	0x101##b000##0800UL
 #define TS_D_STR	0x101##b000##0840UL
 #define TS_D_DREV	0x101##b000##0880UL
 #define TS_D_DSC2	0x101##b000##08c0UL
 /*
  * Pchip CSR Offsets
  */
 #define P_WSBA0		0x0000
 #define P_WSBA1		0x0040
 #define P_WSBA2		0x0080
 #define P_WSBA3		0x00c0
 #	define	WSBA_ADDR(r) (TSFIELDBB((r), 31, 20) << 20)
 #	define	WSBA_SG	     2
 #	define	WSBA_ENA     1
 #define P_WSM0		0x0100
 #define P_WSM1		0x0140
 #define P_WSM2		0x0180
 #define P_WSM3		0x01c0
 #	define	WSM_AM(r)    TSFIELDBB((r), 31, 20)
 #	define	WSM_LEN(r)   ((WSM_AM(r) + 1) << 20)
 #define P_TBA0		0x0200
 #define P_TBA1		0x0240
 #define P_TBA2		0x0280
 #define P_TBA3		0x02c0
 #define P_PCTL		0x0300
 #define	PCTL_FDSC	__BIT(0)	/* fast discard enable */
 #define	PCTL_FBTB	__BIT(1)	/* fast back-to-back enable */
 #define	PCTL_THDIS	__BIT(2)	/* disable TLB anti-thrash (debug) */
 #define	PCTL_CHAINDIS	__BIT(3)	/* disable chaining */
 #define	PCTL_TGTLAT	__BIT(4)	/* target latency timers enable */
 #define	PCTL_HOLE	__BIT(5)	/* 512KB->1M hole enable */
 #define	PCTL_MWIN	__BIT(6)	/* monster window enable */
 #define	PCTL_PRIGRP	__BITS(8,14)	/* arbiter priority group */
 #define	PCTL_PPRI	__BIT(15)	/* arbiter priority group for Pchip */
 #define	PCTL_ECCEN	__BIT(18)	/* ECC enable for DMA and SGTE */
 #define	PCTL_PADM	__BIT(19)	/* PADbus mode */
 #define	PCTL_CDQMAX	__BITS(20,23)	/* see manual */
 #define	PCTL_REV	__BITS(24,31)	/* Pchip revision */
 #define	PCTL_CRQMAX	__BITS(32,35)	/* see manual */
 #define	PCTL_PTPMAX	__BITS(36,39)	/* see manual */
 #define	PCTL_PCLKX	__BITS(40,41)	/* PCI clock freq multipler */
 #define	PCTL_FDSDIS	__BIT(42)	/* fast DMA start and SGTE disable */
 #define	PCTL_FDWDIS	__BIT(43)	/* fast DMA read cache block disable */
 #define	PCTL_PTEVRFY	__BIT(44)	/* PTE verify for DMA read */
 #define	PCTL_RPP	__BIT(45)	/* remote Pchip present */
 #define	PCTL_PID	__BITS(46,47)	/* Pchip ID */
 #define P_PLAT		0x0340
 	/* reserved	0x0380 */
 #define P_PERROR	0x03c0
 #	define	PER_ERR(r)	TSFIELD((r),  0, 12)
 #	define	PER_ECC(r)	TSFIELD((r), 10, 2)
 #	define	PER_SADR(r)	TSFIELD((r), 16, 34)
 #	define	PER_PADR(r)	(TSFIELD((r), 18, 32) << 2)
 #	define	PER_TRNS(r)	TSFIELD((r), 16, 2)
 #	define	PER_INV(r)	TSFIELD((r), 51, 1)
 #	define	PER_CMD(r)	TSFIELD((r), 52, 4)
 #	define	PER_SYN(r)	TSFIELD((r), 56, 8)
 #define P_PERRMASK	0x0400
 #define P_PERRSET	0x0440
 #define P_TLBIV		0x0480
 #define P_TLBIA		0x04c0
 #define P_PMONCTL	0x0500
 #define P_PMONCNT	0x0540
 #define P_SPRST		0x0800
 #define	TS_STEP		0x40
 /*
  * Pchip I/O offsets
  */
 #define	P_CSRBASE	 0x001##8000##0000UL
 #define	P_PCI_MEM	 0x800##0000##0000UL
 #define	P_PCI_IO	 0x001##fc00##0000UL
 #define	P_PCI_CONFIG	 0x001##fe00##0000UL
 /*
  * Construct EV6 I/O Space Address for Pchip 0 and Pchip 1.
  */
 #define	TS_P0(offs)	(0x100##0000##0000UL + (offs))
 #define	TS_P1(offs)	(0x102##0000##0000UL + (offs))
 #define	TS_Pn(n, offs)	(0x100##0000##0000UL + 0x2##0000##0000UL * (n) + (offs))
 /*
  * Tsunami Generic Register Type
  */
 typedef struct _ts_gr {
 	volatile uint64_t tsg_r;
 	long	tsg_deadspace[7];
 } TS_GR;
 /*
  * Tsunami Pchip
  */
 struct	ts_pport {
 	TS_GR	tsp_resA;
 	TS_GR	tsp_error;	/* Pchip Error */
 	TS_GR	tsp_perrmask;	/* Pchip Error Mask */
 	TS_GR	tsp_perrset;	/* Pchip Error Set */
 	TS_GR	tsp_tlbiv;	/* Translation Buffer Invalidate Virtual */
 	TS_GR	tsp_tlbia;	/* Translation Buffer Invalidate All */
 	TS_GR	tsp_pmonctl;	/* PChip Monitor Control */
 	TS_GR	tsp_pmoncnt;	/* PChip Monitor Counters */
 	TS_GR	tsp_resB;
 	TS_GR	tsp_resC;
 	TS_GR	tsp_resD_K[8];
 };
 struct	ts_gport {
 	TS_GR	tsp_resA[2];
 	TS_GR	tsp_serror;
 	TS_GR	tsp_serrmask;
 	TS_GR	tsp_serrset;
 	TS_GR	tsp_resB;
 	TS_GR	tsp_gperrmask;
 	TS_GR	tsp_gperren;
 	TS_GR	tsp_gperrset;
 	TS_GR	tsp_resC;
 	TS_GR	tsp_tlbiv;
 	TS_GR	tsp_tlbia;
 	TS_GR	tsp_resD[2];
 	TS_GR	tsp_sctl;
 	TS_GR	tsp_resE[3];
 };
 struct	ts_aport {
 	TS_GR	tsp_resA[2];
 	TS_GR	tsp_agperror;
 	TS_GR	tsp_agperrmask;
 	TS_GR	tsp_agperrset;
 	TS_GR	tsp_agplastwr;
 	TS_GR	tsp_aperror;
 	TS_GR	tsp_aperrmask;
 	TS_GR	tsp_aperrset;
 	TS_GR	tsp_resB;
 	TS_GR	tsp_tlbiv;
 	TS_GR	tsp_tlbia;
 	TS_GR	tsp_resC[6];
 };
 struct	ts_pchip {
 	TS_GR	tsp_wsba[4];	/* Window Space Base Address */
 	TS_GR	tsp_wsm[4];	/* Window Space Mask */
 	TS_GR	tsp_tba[4];	/* Translated Base Address */
 	TS_GR	tsp_pctl;	/* Pchip Control */
 	TS_GR	tsp_plat;	/* Pchip Latency */
 	union {
 		struct ts_pport	p;
 		struct ts_gport	g;
 		struct ts_aport	a;
 	} port;
 	TS_GR	tsp_sprts;	/* ??? */
 	TS_GR   tsp_res[31];
 };

 @@ -1,99 +1,100 @@
-/* $NetBSD: tsvar.h,v 1.14 2020/06/17 03:50:04 thorpej Exp $ */
+/* $NetBSD: tsvar.h,v 1.15 2021/05/27 22:11:31 thorpej Exp $ */
 /*-
  * Copyright (c) 1999 by Ross Harvey.  All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  * 3. All advertising materials mentioning features or use of this software
  *    must display the following acknowledgement:
  *	This product includes software developed by Ross Harvey.
  * 4. The name of Ross Harvey may not be used to endorse or promote products
  *    derived from this software without specific prior written permission.
+ *
  * THIS SOFTWARE IS PROVIDED BY ROSS HARVEY ``AS IS'' AND ANY EXPRESS
  * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURP0SE
  * ARE DISCLAIMED.  IN NO EVENT SHALL ROSS HARVEY BE LIABLE FOR ANY
  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
+ *
  */
 #include <sys/extent.h>
 #include <dev/isa/isavar.h>
 #include <dev/pci/pcivar.h>
 #include <dev/i2c/i2cvar.h>
 #include <alpha/pci/pci_sgmap_pte64.h>
 #define	_FSTORE	(EXTENT_FIXED_STORAGE_SIZE(8) / sizeof(long))
 #define	tsvar() { Generate ctags(1) key. }
 struct tsp_config {
 	int	pc_pslot;		/* Pchip 0 or 1 */
 	int	pc_initted;		/* Initialized */
 	uint64_t pc_iobase;		/* All Pchip space starts here */
 	struct	ts_pchip *pc_csr;	/* Pchip CSR space starts here */
 	volatile uint64_t *pc_tlbia;  	/* Pchip TLBIA register address */
 	struct	alpha_bus_space pc_iot, pc_memt;
 	struct	alpha_pci_chipset pc_pc;
 	struct	alpha_bus_dma_tag pc_dmat64_direct;
 	struct	alpha_bus_dma_tag pc_dmat_direct;
 	struct	alpha_bus_dma_tag pc_dmat_sgmap;
 	struct alpha_sgmap pc_sgmap;
 	uint32_t pc_hae_mem;
 	uint32_t pc_hae_io;
 	long	pc_io_exstorage[_FSTORE];
 	long	pc_mem_exstorage[_FSTORE];
 	struct	extent *pc_io_ex, *pc_mem_ex;
 	int	pc_mallocsafe;
 };
 struct tsp_attach_args {
 	const char *tsp_name;
 	int	tsp_slot;
 };
 struct tsciic_softc {
 	device_t	sc_dev;
 	struct		i2c_controller sc_i2c;
 };
 struct tsciic_attach_args {
 	const char *tsciic_name;
 };
 extern int tsp_console_hose;
 struct	tsp_config *tsp_init(int, int);
 void	tsp_pci_init(pci_chipset_tag_t, void *);
 void	tsp_dma_init(struct tsp_config *);
 void	tsp_bus_io_init(bus_space_tag_t, void *);
 void	tsp_bus_mem_init(bus_space_tag_t, void *);
 void	tsp_bus_mem_init2(bus_space_tag_t, void *);
 void	tsciic_init(device_t);
 void	tsp_print_error(unsigned int, unsigned long);
 void	tsc_print_misc(unsigned int, unsigned long);
 void	tsc_print_dir(unsigned int, unsigned long);
 #define IPRINTF(i, f, ...)	printf("%*s" f, i * 4, "", ##__VA_ARGS__)