 @@ -1,2029 +1,2029 @@
-/*	$NetBSD: xhci.c,v 1.142 2021/05/27 11:09:15 skrll Exp $	*/
+/*	$NetBSD: xhci.c,v 1.143 2021/05/29 16:49:30 riastradh Exp $	*/
 /*
  * Copyright (c) 2013 Jonathan A. Kollasch
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 /*
  * USB rev 2.0 and rev 3.1 specification
  *  http://www.usb.org/developers/docs/
  * xHCI rev 1.1 specification
  *  http://www.intel.com/technology/usb/spec.htm
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: xhci.c,v 1.142 2021/05/27 11:09:15 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: xhci.c,v 1.143 2021/05/29 16:49:30 riastradh Exp $");
 #ifdef _KERNEL_OPT
 #include "opt_usb.h"
 #endif
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/kernel.h>
 #include <sys/kmem.h>
 #include <sys/device.h>
 #include <sys/select.h>
 #include <sys/proc.h>
 #include <sys/queue.h>
 #include <sys/mutex.h>
 #include <sys/condvar.h>
 #include <sys/bus.h>
 #include <sys/cpu.h>
 #include <sys/sysctl.h>
 #include <machine/endian.h>
 #include <dev/usb/usb.h>
 #include <dev/usb/usbdi.h>
 #include <dev/usb/usbdivar.h>
 #include <dev/usb/usbdi_util.h>
 #include <dev/usb/usbhist.h>
 #include <dev/usb/usb_mem.h>
 #include <dev/usb/usb_quirks.h>
 #include <dev/usb/xhcireg.h>
 #include <dev/usb/xhcivar.h>
 #include <dev/usb/usbroothub.h>
 #ifdef USB_DEBUG
 #ifndef XHCI_DEBUG
 #define xhcidebug 0
 #else /* !XHCI_DEBUG */
 #define HEXDUMP(a, b, c) \
     do { \
 	    if (xhcidebug > 0) \
 		    hexdump(printf, a, b, c); \
     } while (/*CONSTCOND*/0)
 static int xhcidebug = 0;
 SYSCTL_SETUP(sysctl_hw_xhci_setup, "sysctl hw.xhci setup")
+{
 	int err;
 	const struct sysctlnode *rnode;
 	const struct sysctlnode *cnode;
 	err = sysctl_createv(clog, 0, NULL, &rnode,
 	    CTLFLAG_PERMANENT, CTLTYPE_NODE, "xhci",
 	    SYSCTL_DESCR("xhci global controls"),
 	    NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL);
 	if (err)
 		goto fail;
 	/* control debugging printfs */
 	err = sysctl_createv(clog, 0, &rnode, &cnode,
 	    CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT,
 	    "debug", SYSCTL_DESCR("Enable debugging output"),
 	    NULL, 0, &xhcidebug, sizeof(xhcidebug), CTL_CREATE, CTL_EOL);
 	if (err)
 		goto fail;
 	return;
 fail:
 	aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err);
+}
 #endif /* !XHCI_DEBUG */
 #endif /* USB_DEBUG */
 #ifndef HEXDUMP
 #define HEXDUMP(a, b, c)
 #endif
 #define DPRINTF(FMT,A,B,C,D)	USBHIST_LOG(xhcidebug,FMT,A,B,C,D)
 #define DPRINTFN(N,FMT,A,B,C,D)	USBHIST_LOGN(xhcidebug,N,FMT,A,B,C,D)
 #define XHCIHIST_FUNC()		USBHIST_FUNC()
 #define XHCIHIST_CALLED(name)	USBHIST_CALLED(xhcidebug)
 #define XHCIHIST_CALLARGS(FMT,A,B,C,D) \
 				USBHIST_CALLARGS(xhcidebug,FMT,A,B,C,D)
 #define XHCI_DCI_SLOT 0
 #define XHCI_DCI_EP_CONTROL 1
 #define XHCI_ICI_INPUT_CONTROL 0
 struct xhci_pipe {
 	struct usbd_pipe xp_pipe;
 	struct usb_task xp_async_task;
 	int16_t xp_isoc_next; /* next frame */
 	uint8_t xp_maxb; /* max burst */
 	uint8_t xp_mult;
 };
 #define XHCI_COMMAND_RING_TRBS 256
 #define XHCI_EVENT_RING_TRBS 256
 #define XHCI_EVENT_RING_SEGMENTS 1
 #define XHCI_TRB_3_ED_BIT XHCI_TRB_3_ISP_BIT
 static usbd_status xhci_open(struct usbd_pipe *);
 static void xhci_close_pipe(struct usbd_pipe *);
 static int xhci_intr1(struct xhci_softc * const);
 static void xhci_softintr(void *);
 static void xhci_poll(struct usbd_bus *);
 static struct usbd_xfer *xhci_allocx(struct usbd_bus *, unsigned int);
 static void xhci_freex(struct usbd_bus *, struct usbd_xfer *);
 static void xhci_abortx(struct usbd_xfer *);
 static bool xhci_dying(struct usbd_bus *);
 static void xhci_get_lock(struct usbd_bus *, kmutex_t **);
 static usbd_status xhci_new_device(device_t, struct usbd_bus *, int, int, int,
     struct usbd_port *);
 static int xhci_roothub_ctrl(struct usbd_bus *, usb_device_request_t *,
     void *, int);
 static usbd_status xhci_configure_endpoint(struct usbd_pipe *);
 //static usbd_status xhci_unconfigure_endpoint(struct usbd_pipe *);
 static usbd_status xhci_reset_endpoint(struct usbd_pipe *);
 static usbd_status xhci_stop_endpoint_cmd(struct xhci_softc *,
     struct xhci_slot *, u_int, uint32_t);
 static usbd_status xhci_stop_endpoint(struct usbd_pipe *);
 static void xhci_host_dequeue(struct xhci_ring * const);
 static usbd_status xhci_set_dequeue(struct usbd_pipe *);
 static usbd_status xhci_do_command(struct xhci_softc * const,
     struct xhci_soft_trb * const, int);
 static usbd_status xhci_do_command_locked(struct xhci_softc * const,
     struct xhci_soft_trb * const, int);
 static usbd_status xhci_init_slot(struct usbd_device *, uint32_t);
 static void xhci_free_slot(struct xhci_softc *, struct xhci_slot *);
 static usbd_status xhci_set_address(struct usbd_device *, uint32_t, bool);
 static usbd_status xhci_enable_slot(struct xhci_softc * const,
     uint8_t * const);
 static usbd_status xhci_disable_slot(struct xhci_softc * const, uint8_t);
 static usbd_status xhci_address_device(struct xhci_softc * const,
     uint64_t, uint8_t, bool);
 static void xhci_set_dcba(struct xhci_softc * const, uint64_t, int);
 static usbd_status xhci_update_ep0_mps(struct xhci_softc * const,
     struct xhci_slot * const, u_int);
 static usbd_status xhci_ring_init(struct xhci_softc * const,
     struct xhci_ring **, size_t, size_t);
 static void xhci_ring_free(struct xhci_softc * const,
     struct xhci_ring ** const);
 static void xhci_setup_ctx(struct usbd_pipe *);
 static void xhci_setup_route(struct usbd_pipe *, uint32_t *);
 static void xhci_setup_tthub(struct usbd_pipe *, uint32_t *);
 static void xhci_setup_maxburst(struct usbd_pipe *, uint32_t *);
 static uint32_t xhci_bival2ival(uint32_t, uint32_t);
 static void xhci_noop(struct usbd_pipe *);
 static usbd_status xhci_root_intr_transfer(struct usbd_xfer *);
 static usbd_status xhci_root_intr_start(struct usbd_xfer *);
 static void xhci_root_intr_abort(struct usbd_xfer *);
 static void xhci_root_intr_close(struct usbd_pipe *);
 static void xhci_root_intr_done(struct usbd_xfer *);
 static usbd_status xhci_device_ctrl_transfer(struct usbd_xfer *);
 static usbd_status xhci_device_ctrl_start(struct usbd_xfer *);
 static void xhci_device_ctrl_abort(struct usbd_xfer *);
 static void xhci_device_ctrl_close(struct usbd_pipe *);
 static void xhci_device_ctrl_done(struct usbd_xfer *);
 static usbd_status xhci_device_isoc_transfer(struct usbd_xfer *);
 static usbd_status xhci_device_isoc_enter(struct usbd_xfer *);
 static void xhci_device_isoc_abort(struct usbd_xfer *);
 static void xhci_device_isoc_close(struct usbd_pipe *);
 static void xhci_device_isoc_done(struct usbd_xfer *);
 static usbd_status xhci_device_intr_transfer(struct usbd_xfer *);
 static usbd_status xhci_device_intr_start(struct usbd_xfer *);
 static void xhci_device_intr_abort(struct usbd_xfer *);
 static void xhci_device_intr_close(struct usbd_pipe *);
 static void xhci_device_intr_done(struct usbd_xfer *);
 static usbd_status xhci_device_bulk_transfer(struct usbd_xfer *);
 static usbd_status xhci_device_bulk_start(struct usbd_xfer *);
 static void xhci_device_bulk_abort(struct usbd_xfer *);
 static void xhci_device_bulk_close(struct usbd_pipe *);
 static void xhci_device_bulk_done(struct usbd_xfer *);
 static const struct usbd_bus_methods xhci_bus_methods = {
 	.ubm_open = xhci_open,
 	.ubm_softint = xhci_softintr,
 	.ubm_dopoll = xhci_poll,
 	.ubm_allocx = xhci_allocx,
 	.ubm_freex = xhci_freex,
 	.ubm_abortx = xhci_abortx,
 	.ubm_dying = xhci_dying,
 	.ubm_getlock = xhci_get_lock,
 	.ubm_newdev = xhci_new_device,
 	.ubm_rhctrl = xhci_roothub_ctrl,
 };
 static const struct usbd_pipe_methods xhci_root_intr_methods = {
 	.upm_transfer = xhci_root_intr_transfer,
 	.upm_start = xhci_root_intr_start,
 	.upm_abort = xhci_root_intr_abort,
 	.upm_close = xhci_root_intr_close,
 	.upm_cleartoggle = xhci_noop,
 	.upm_done = xhci_root_intr_done,
 };
 static const struct usbd_pipe_methods xhci_device_ctrl_methods = {
 	.upm_transfer = xhci_device_ctrl_transfer,
 	.upm_start = xhci_device_ctrl_start,
 	.upm_abort = xhci_device_ctrl_abort,
 	.upm_close = xhci_device_ctrl_close,
 	.upm_cleartoggle = xhci_noop,
 	.upm_done = xhci_device_ctrl_done,
 };
 static const struct usbd_pipe_methods xhci_device_isoc_methods = {
 	.upm_transfer = xhci_device_isoc_transfer,
 	.upm_abort = xhci_device_isoc_abort,
 	.upm_close = xhci_device_isoc_close,
 	.upm_cleartoggle = xhci_noop,
 	.upm_done = xhci_device_isoc_done,
 };
 static const struct usbd_pipe_methods xhci_device_bulk_methods = {
 	.upm_transfer = xhci_device_bulk_transfer,
 	.upm_start = xhci_device_bulk_start,
 	.upm_abort = xhci_device_bulk_abort,
 	.upm_close = xhci_device_bulk_close,
 	.upm_cleartoggle = xhci_noop,
 	.upm_done = xhci_device_bulk_done,
 };
 static const struct usbd_pipe_methods xhci_device_intr_methods = {
 	.upm_transfer = xhci_device_intr_transfer,
 	.upm_start = xhci_device_intr_start,
 	.upm_abort = xhci_device_intr_abort,
 	.upm_close = xhci_device_intr_close,
 	.upm_cleartoggle = xhci_noop,
 	.upm_done = xhci_device_intr_done,
 };
 static inline uint32_t
 xhci_read_1(const struct xhci_softc * const sc, bus_size_t offset)
+{
 	return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset);
+}
 static inline uint32_t
 xhci_read_2(const struct xhci_softc * const sc, bus_size_t offset)
+{
 	return bus_space_read_2(sc->sc_iot, sc->sc_ioh, offset);
+}
 static inline uint32_t
 xhci_read_4(const struct xhci_softc * const sc, bus_size_t offset)
+{
 	return bus_space_read_4(sc->sc_iot, sc->sc_ioh, offset);
+}
 static inline void
 xhci_write_1(const struct xhci_softc * const sc, bus_size_t offset,
     uint32_t value)
+{
 	bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, value);
+}
 #if 0 /* unused */
 static inline void
 xhci_write_4(const struct xhci_softc * const sc, bus_size_t offset,
     uint32_t value)
+{
 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, offset, value);
+}
 #endif /* unused */
 static inline void
 xhci_barrier(const struct xhci_softc * const sc, int flags)
+{
 	bus_space_barrier(sc->sc_iot, sc->sc_ioh, 0, sc->sc_ios, flags);
+}
 static inline uint32_t
 xhci_cap_read_4(const struct xhci_softc * const sc, bus_size_t offset)
+{
 	return bus_space_read_4(sc->sc_iot, sc->sc_cbh, offset);
+}
 static inline uint32_t
 xhci_op_read_4(const struct xhci_softc * const sc, bus_size_t offset)
+{
 	return bus_space_read_4(sc->sc_iot, sc->sc_obh, offset);
+}
 static inline void
 xhci_op_write_4(const struct xhci_softc * const sc, bus_size_t offset,
     uint32_t value)
+{
 	bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value);
+}
 static inline uint64_t
 xhci_op_read_8(const struct xhci_softc * const sc, bus_size_t offset)
+{
 	uint64_t value;
 	if (XHCI_HCC_AC64(sc->sc_hcc)) {
 #ifdef XHCI_USE_BUS_SPACE_8
 		value = bus_space_read_8(sc->sc_iot, sc->sc_obh, offset);
 #else
 		value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset);
 		value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_obh,
 		    offset + 4) << 32;
 #endif
 	} else {
 		value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset);
+	}
 	return value;
+}
 static inline void
 xhci_op_write_8(const struct xhci_softc * const sc, bus_size_t offset,
     uint64_t value)
+{
 	if (XHCI_HCC_AC64(sc->sc_hcc)) {
 #ifdef XHCI_USE_BUS_SPACE_8
 		bus_space_write_8(sc->sc_iot, sc->sc_obh, offset, value);
 #else
 		bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 0,
 		    (value >> 0) & 0xffffffff);
 		bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 4,
 		    (value >> 32) & 0xffffffff);
 #endif
 	} else {
 		bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value);
+	}
+}
 static inline uint32_t
 xhci_rt_read_4(const struct xhci_softc * const sc, bus_size_t offset)
+{
 	return bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset);
+}
 static inline void
 xhci_rt_write_4(const struct xhci_softc * const sc, bus_size_t offset,
     uint32_t value)
+{
 	bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value);
+}
 static inline uint64_t
 xhci_rt_read_8(const struct xhci_softc * const sc, bus_size_t offset)
+{
 	uint64_t value;
 	if (XHCI_HCC_AC64(sc->sc_hcc)) {
 #ifdef XHCI_USE_BUS_SPACE_8
 		value = bus_space_read_8(sc->sc_iot, sc->sc_rbh, offset);
 #else
 		value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset);
 		value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_rbh,
 		    offset + 4) << 32;
 #endif
 	} else {
 		value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset);
+	}
 	return value;
+}
 static inline void
 xhci_rt_write_8(const struct xhci_softc * const sc, bus_size_t offset,
     uint64_t value)
+{
 	if (XHCI_HCC_AC64(sc->sc_hcc)) {
 #ifdef XHCI_USE_BUS_SPACE_8
 		bus_space_write_8(sc->sc_iot, sc->sc_rbh, offset, value);
 #else
 		bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 0,
 		    (value >> 0) & 0xffffffff);
 		bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 4,
 		    (value >> 32) & 0xffffffff);
 #endif
 	} else {
 		bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value);
+	}
+}
 #if 0 /* unused */
 static inline uint32_t
 xhci_db_read_4(const struct xhci_softc * const sc, bus_size_t offset)
+{
 	return bus_space_read_4(sc->sc_iot, sc->sc_dbh, offset);
+}
 #endif /* unused */
 static inline void
 xhci_db_write_4(const struct xhci_softc * const sc, bus_size_t offset,
     uint32_t value)
+{
 	bus_space_write_4(sc->sc_iot, sc->sc_dbh, offset, value);
+}
 /* --- */
 static inline uint8_t
 xhci_ep_get_type(usb_endpoint_descriptor_t * const ed)
+{
 	u_int eptype = 0;
 	switch (UE_GET_XFERTYPE(ed->bmAttributes)) {
 	case UE_CONTROL:
 		eptype = 0x0;
 		break;
 	case UE_ISOCHRONOUS:
 		eptype = 0x1;
 		break;
 	case UE_BULK:
 		eptype = 0x2;
 		break;
 	case UE_INTERRUPT:
 		eptype = 0x3;
 		break;
+	}
 	if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) ||
 	    (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN))
 		return eptype | 0x4;
 	else
 		return eptype;
+}
 static u_int
 xhci_ep_get_dci(usb_endpoint_descriptor_t * const ed)
+{
 	/* xHCI 1.0 section 4.5.1 */
 	u_int epaddr = UE_GET_ADDR(ed->bEndpointAddress);
 	u_int in = 0;
 	if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) ||
 	    (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN))
 		in = 1;
 	return epaddr * 2 + in;
+}
 static inline u_int
 xhci_dci_to_ici(const u_int i)
+{
 	return i + 1;
+}
 static inline void *
 xhci_slot_get_dcv(struct xhci_softc * const sc, struct xhci_slot * const xs,
     const u_int dci)
+{
 	return KERNADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci);
+}
 #if 0 /* unused */
 static inline bus_addr_t
 xhci_slot_get_dcp(struct xhci_softc * const sc, struct xhci_slot * const xs,
     const u_int dci)
+{
 	return DMAADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci);
+}
 #endif /* unused */
 static inline void *
 xhci_slot_get_icv(struct xhci_softc * const sc, struct xhci_slot * const xs,
     const u_int ici)
+{
 	return KERNADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici);
+}
 static inline bus_addr_t
 xhci_slot_get_icp(struct xhci_softc * const sc, struct xhci_slot * const xs,
     const u_int ici)
+{
 	return DMAADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici);
+}
 static inline struct xhci_trb *
 xhci_ring_trbv(struct xhci_ring * const xr, u_int idx)
+{
 	return KERNADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx);
+}
 static inline bus_addr_t
 xhci_ring_trbp(struct xhci_ring * const xr, u_int idx)
+{
 	return DMAADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx);
+}
 static inline void
 xhci_xfer_put_trb(struct xhci_xfer * const xx, u_int idx,
     uint64_t parameter, uint32_t status, uint32_t control)
+{
 	KASSERTMSG(idx < xx->xx_ntrb, "idx=%u xx_ntrb=%u", idx, xx->xx_ntrb);
 	xx->xx_trb[idx].trb_0 = parameter;
 	xx->xx_trb[idx].trb_2 = status;
 	xx->xx_trb[idx].trb_3 = control;
+}
 static inline void
 xhci_trb_put(struct xhci_trb * const trb, uint64_t parameter, uint32_t status,
     uint32_t control)
+{
 	trb->trb_0 = htole64(parameter);
 	trb->trb_2 = htole32(status);
 	trb->trb_3 = htole32(control);
+}
 static int
 xhci_trb_get_idx(struct xhci_ring *xr, uint64_t trb_0, int *idx)
+{
 	/* base address of TRBs */
 	bus_addr_t trbp = xhci_ring_trbp(xr, 0);
 	/* trb_0 range sanity check */
 	if (trb_0 == 0 || trb_0 < trbp ||
 	    (trb_0 - trbp) % sizeof(struct xhci_trb) != 0 ||
 	    (trb_0 - trbp) / sizeof(struct xhci_trb) >= xr->xr_ntrb) {
 		return 1;
+	}
 	*idx = (trb_0 - trbp) / sizeof(struct xhci_trb);
 	return 0;
+}
 static unsigned int
 xhci_get_epstate(struct xhci_softc * const sc, struct xhci_slot * const xs,
     u_int dci)
+{
 	uint32_t *cp;
 	usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD);
 	cp = xhci_slot_get_dcv(sc, xs, dci);
 	return XHCI_EPCTX_0_EPSTATE_GET(le32toh(cp[0]));
+}
 static inline unsigned int
 xhci_ctlrport2bus(struct xhci_softc * const sc, unsigned int ctlrport)
+{
 	const unsigned int port = ctlrport - 1;
 	const uint8_t bit = __BIT(port % NBBY);
 	return __SHIFTOUT(sc->sc_ctlrportbus[port / NBBY], bit);
+}
 /*
  * Return the roothub port for a controller port.  Both are 1..n.
  */
 static inline unsigned int
 xhci_ctlrport2rhport(struct xhci_softc * const sc, unsigned int ctrlport)
+{
 	return sc->sc_ctlrportmap[ctrlport - 1];
+}
 /*
  * Return the controller port for a bus roothub port.  Both are 1..n.
  */
 static inline unsigned int
 xhci_rhport2ctlrport(struct xhci_softc * const sc, unsigned int bn,
     unsigned int rhport)
+{
 	return sc->sc_rhportmap[bn][rhport - 1];
+}
 /* --- */
 void
 xhci_childdet(device_t self, device_t child)
+{
 	struct xhci_softc * const sc = device_private(self);
 	KASSERT((sc->sc_child == child) || (sc->sc_child2 == child));
 	if (child == sc->sc_child2)
 		sc->sc_child2 = NULL;
 	else if (child == sc->sc_child)
 		sc->sc_child = NULL;
+}
 int
 xhci_detach(struct xhci_softc *sc, int flags)
+{
 	int rv = 0;
 	if (sc->sc_child2 != NULL) {
 		rv = config_detach(sc->sc_child2, flags);
 		if (rv != 0)
 			return rv;
 		KASSERT(sc->sc_child2 == NULL);
+	}
 	if (sc->sc_child != NULL) {
 		rv = config_detach(sc->sc_child, flags);
 		if (rv != 0)
 			return rv;
 		KASSERT(sc->sc_child == NULL);
+	}
 	/* XXX unconfigure/free slots */
 	/* verify: */
 	xhci_rt_write_4(sc, XHCI_IMAN(0), 0);
 	xhci_op_write_4(sc, XHCI_USBCMD, 0);
 	/* do we need to wait for stop? */
 	xhci_op_write_8(sc, XHCI_CRCR, 0);
 	xhci_ring_free(sc, &sc->sc_cr);
 	cv_destroy(&sc->sc_command_cv);
 	cv_destroy(&sc->sc_cmdbusy_cv);
 	xhci_rt_write_4(sc, XHCI_ERSTSZ(0), 0);
 	xhci_rt_write_8(sc, XHCI_ERSTBA(0), 0);
 	xhci_rt_write_8(sc, XHCI_ERDP(0), 0 | XHCI_ERDP_BUSY);
 	xhci_ring_free(sc, &sc->sc_er);
 	usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma);
 	xhci_op_write_8(sc, XHCI_DCBAAP, 0);
 	usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma);
 	kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * sc->sc_maxslots);
 	kmem_free(sc->sc_ctlrportbus,
 	    howmany(sc->sc_maxports * sizeof(uint8_t), NBBY));
 	kmem_free(sc->sc_ctlrportmap, sc->sc_maxports * sizeof(int));
 	for (size_t j = 0; j < __arraycount(sc->sc_rhportmap); j++) {
 		kmem_free(sc->sc_rhportmap[j], sc->sc_maxports * sizeof(int));
+	}
 	mutex_destroy(&sc->sc_lock);
 	mutex_destroy(&sc->sc_intr_lock);
 	pool_cache_destroy(sc->sc_xferpool);
 	return rv;
+}
 int
 xhci_activate(device_t self, enum devact act)
+{
 	struct xhci_softc * const sc = device_private(self);
 	switch (act) {
 	case DVACT_DEACTIVATE:
 		sc->sc_dying = true;
 		return 0;
 	default:
 		return EOPNOTSUPP;
+	}
+}
 bool
 xhci_suspend(device_t self, const pmf_qual_t *qual)
+{
 	struct xhci_softc * const sc = device_private(self);
 	size_t i, j, bn, dci;
 	int port;
 	uint32_t v;
 	usbd_status err;
 	bool ok = false;
 	XHCIHIST_FUNC(); XHCIHIST_CALLED();
 	mutex_enter(&sc->sc_lock);
 	/*
 	 * Block issuance of new commands, and wait for all pending
 	 * commands to complete.
 	 */
 	KASSERT(sc->sc_suspender == NULL);
 	sc->sc_suspender = curlwp;
 	while (sc->sc_command_addr != 0)
 		cv_wait(&sc->sc_cmdbusy_cv, &sc->sc_lock);
 	/*
 	 * xHCI Requirements Specification 1.2, May 2019, Sec. 4.23.2:
 	 * xHCI Power Management, p. 342
 	 * https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/extensible-host-controler-interface-usb-xhci.pdf#page=342
 	 */
 	/*
 	 * `1. Stop all USB activity by issuing Stop Endpoint Commands
 	 *     for Busy endpoints in the Running state.  If the Force
 	 *     Save Context Capability (FSC = ``0'') is not supported,
 	 *     then Stop Endpoint Commands shall be issued for all idle
 	 *     endpoints in the Running state as well.  The Stop
 	 *     Endpoint Command causes the xHC to update the respective
 	 *     Endpoint or Stream Contexts in system memory, e.g. the
 	 *     TR Dequeue Pointer, DCS, etc. fields.  Refer to
 	 *     Implementation Note "0".'
 	 */
 	for (i = 0; i < sc->sc_maxslots; i++) {
 		struct xhci_slot *xs = &sc->sc_slots[i];
 		/* Skip if the slot is not in use.  */
 		if (xs->xs_idx == 0)
 			continue;
 		for (dci = XHCI_DCI_SLOT; dci <= XHCI_MAX_DCI; dci++) {
 			/* Skip if the endpoint is not Running.  */
 			/* XXX What about Busy?  */
 			if (xhci_get_epstate(sc, xs, dci) !=
 			    XHCI_EPSTATE_RUNNING)
 				continue;
 			/* Stop endpoint.  */
 			err = xhci_stop_endpoint_cmd(sc, xs, dci,
 			    XHCI_TRB_3_SUSP_EP_BIT);
 			if (err) {
 				device_printf(self, "failed to stop endpoint"
 				    " slot %zu dci %zu err %d\n",
 				    i, dci, err);
 				goto out;
+			}
+		}
+	}
 	/*
 	 * Next, suspend all the ports:
+	 *
 	 * xHCI Requirements Specification 1.2, May 2019, Sec. 4.15:
 	 * Suspend-Resume, pp. 276-283
 	 * https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/extensible-host-controler-interface-usb-xhci.pdf#page=276
 	 */
 	for (bn = 0; bn < 2; bn++) {
 		for (i = 1; i <= sc->sc_rhportcount[bn]; i++) {
 			/* 4.15.1: Port Suspend.  */
 			port = XHCI_PORTSC(xhci_rhport2ctlrport(sc, bn, i));
 			/*
 			 * `System software places individual ports
 			 *  into suspend mode by writing a ``3'' into
 			 *  the appropriate PORTSC register Port Link
 			 *  State (PLS) field (refer to Section 5.4.8).
 			 *  Software should only set the PLS field to
 			 *  ``3'' when the port is in the Enabled
 			 *  state.'
+			 *
 			 * `Software should not attempt to suspend a
 			 *  port unless the port reports that it is in
 			 *  the enabled (PED = ``1''; PLS < ``3'')
 			 *  state (refer to Section 5.4.8 for more
 			 *  information about PED and PLS).'
 			 */
 			v = xhci_op_read_4(sc, port);
 			if (((v & XHCI_PS_PED) == 0) ||
 			    XHCI_PS_PLS_GET(v) >= XHCI_PS_PLS_U3)
 				continue;
 			v &= ~(XHCI_PS_PLS_MASK | XHCI_PS_CLEAR);
 			v |= XHCI_PS_LWS | XHCI_PS_PLS_SET(XHCI_PS_PLS_SETU3);
 			xhci_op_write_4(sc, port, v);
 			/*
 			 * `When the PLS field is written with U3
 			 *  (``3''), the status of the PLS bit will not
 			 *  change to the target U state U3 until the
 			 *  suspend signaling has completed to the
 			 *  attached device (which may be as long as
 			 *  10ms.).'
+			 *
 			 * `Software is required to wait for U3
 			 *  transitions to complete before it puts the
 			 *  xHC into a low power state, and before
 			 *  resuming the port.'
+			 *
 			 * XXX Take advantage of the technique to
 			 * reduce polling on host controllers that
 			 * support the U3C capability.
 			 */
 			for (j = 0; j < XHCI_WAIT_PLS_U3; j++) {
 				v = xhci_op_read_4(sc, port);
 				if (XHCI_PS_PLS_GET(v) == XHCI_PS_PLS_U3)
 					break;
 				usb_delay_ms(&sc->sc_bus, 1);
+			}
 			if (j == XHCI_WAIT_PLS_U3) {
 				device_printf(self,
 				    "suspend timeout on bus %zu port %zu\n",
 				    bn, i);
 				goto out;
+			}
+		}
+	}
 	/*
 	 * `2. Ensure that the Command Ring is in the Stopped state
 	 *     (CRR = ``0'') or Idle (i.e. the Command Transfer Ring is
 	 *     empty), and all Command Completion Events associated
 	 *     with them have been received.'
+	 *
 	 * XXX
 	 */
 	/* `3. Stop the controller by setting Run/Stop (R/S) = ``0''.'  */
 	xhci_op_write_4(sc, XHCI_USBCMD,
 	    xhci_op_read_4(sc, XHCI_USBCMD) & ~XHCI_CMD_RS);
 	/*
 	 * `4. Read the Operational Runtime, and VTIO registers in the
 	 *     following order: USBCMD, DNCTRL, DCBAAP, CONFIG, ERSTSZ,
 	 *     ERSTBA, ERDP, IMAN, IMOD, and VTIO and save their
 	 *     state.'
+	 *
 	 * (We don't use VTIO here (XXX for now?).)
 	 */
 	sc->sc_regs.usbcmd = xhci_op_read_4(sc, XHCI_USBCMD);
 	sc->sc_regs.dnctrl = xhci_op_read_4(sc, XHCI_DNCTRL);
 	sc->sc_regs.dcbaap = xhci_op_read_8(sc, XHCI_DCBAAP);
 	sc->sc_regs.config = xhci_op_read_4(sc, XHCI_CONFIG);
 	sc->sc_regs.erstsz0 = xhci_rt_read_4(sc, XHCI_ERSTSZ(0));
 	sc->sc_regs.erstba0 = xhci_rt_read_8(sc, XHCI_ERSTBA(0));
 	sc->sc_regs.erdp0 = xhci_rt_read_8(sc, XHCI_ERDP(0));
 	sc->sc_regs.iman0 = xhci_rt_read_4(sc, XHCI_IMAN(0));
 	sc->sc_regs.imod0 = xhci_rt_read_4(sc, XHCI_IMOD(0));
 	/*
 	 * `5. Set the Controller Save State (CSS) flag in the USBCMD
 	 *     register (5.4.1)...'
 	 */
 	xhci_op_write_4(sc, XHCI_USBCMD,
 	    xhci_op_read_4(sc, XHCI_USBCMD) | XHCI_CMD_CSS);
 	/*
 	 *    `...and wait for the Save State Status (SSS) flag in the
 	 *     USBSTS register (5.4.2) to transition to ``0''.'
 	 */
 	for (i = 0; i < XHCI_WAIT_SSS; i++) {
 		if ((xhci_op_read_4(sc, XHCI_USBSTS) & XHCI_STS_SSS) == 0)
 			break;
 		usb_delay_ms(&sc->sc_bus, 1);
+	}
 	if (i >= XHCI_WAIT_SSS) {
 		device_printf(self, "suspend timeout, USBSTS.SSS\n");
 		/*
 		 * Just optimistically go on and check SRE anyway --
 		 * what's the worst that could happen?
 		 */
+	}
 	/*
 	 * `Note: After a Save or Restore operation completes, the
 	 *  Save/Restore Error (SRE) flag in the USBSTS register should
 	 *  be checked to ensure that the operation completed
 	 *  successfully.'
 	 */
 	if (xhci_op_read_4(sc, XHCI_USBSTS) & XHCI_STS_SRE) {
 		device_printf(self, "suspend error, USBSTS.SRE\n");
 		goto out;
+	}
 	/* Success!  */
 	ok = true;
 out:	mutex_exit(&sc->sc_lock);
 	return ok;
+}
 bool
 xhci_resume(device_t self, const pmf_qual_t *qual)
+{
 	struct xhci_softc * const sc = device_private(self);
 	size_t i, j, bn, dci;
 	int port;
 	uint32_t v;
 	bool ok = false;
 	XHCIHIST_FUNC(); XHCIHIST_CALLED();
 	mutex_enter(&sc->sc_lock);
 	KASSERT(sc->sc_suspender);
 	/*
 	 * xHCI Requirements Specification 1.2, May 2019, Sec. 4.23.2:
 	 * xHCI Power Management, p. 343
 	 * https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/extensible-host-controler-interface-usb-xhci.pdf#page=343
 	 */
 	/*
 	 * `4. Restore the Operational Runtime, and VTIO registers with
 	 *     their previously saved state in the following order:
 	 *     DNCTRL, DCBAAP, CONFIG, ERSTSZ, ERSTBA, ERDP, IMAN,
 	 *     IMOD, and VTIO.'
+	 *
 	 * (We don't use VTIO here (for now?).)
 	 */
 	xhci_op_write_4(sc, XHCI_USBCMD, sc->sc_regs.usbcmd);
 	xhci_op_write_4(sc, XHCI_DNCTRL, sc->sc_regs.dnctrl);
 	xhci_op_write_8(sc, XHCI_DCBAAP, sc->sc_regs.dcbaap);
 	xhci_op_write_4(sc, XHCI_CONFIG, sc->sc_regs.config);
 	xhci_rt_write_4(sc, XHCI_ERSTSZ(0), sc->sc_regs.erstsz0);
 	xhci_rt_write_8(sc, XHCI_ERSTBA(0), sc->sc_regs.erstba0);
 	xhci_rt_write_8(sc, XHCI_ERDP(0), sc->sc_regs.erdp0);
 	xhci_rt_write_4(sc, XHCI_IMAN(0), sc->sc_regs.iman0);
 	xhci_rt_write_4(sc, XHCI_IMOD(0), sc->sc_regs.imod0);
 	memset(&sc->sc_regs, 0, sizeof(sc->sc_regs)); /* paranoia */
 	/*
 	 * `5. Set the Controller Restore State (CRS) flag in the
 	 *     USBCMD register (5.4.1) to ``1''...'
 	 */
 	xhci_op_write_4(sc, XHCI_USBCMD,
 	    xhci_op_read_4(sc, XHCI_USBCMD) | XHCI_CMD_CRS);
 	/*
 	 *    `...and wait for the Restore State Status (RSS) in the
 	 *     USBSTS register (5.4.2) to transition to ``0''.'
 	 */
 	for (i = 0; i < XHCI_WAIT_RSS; i++) {
 		if ((xhci_op_read_4(sc, XHCI_USBSTS) & XHCI_STS_RSS) == 0)
 			break;
 		usb_delay_ms(&sc->sc_bus, 1);
+	}
 	if (i >= XHCI_WAIT_RSS) {
 		device_printf(self, "suspend timeout, USBSTS.RSS\n");
 		goto out;
+	}
 	/*
 	 * `6. Reinitialize the Command Ring, i.e. so its Cycle bits
 	 *     are consistent with the RCS values to be written to the
 	 *     CRCR.'
+	 *
 	 * XXX Hope just zeroing it is good enough!
 	 */
 	xhci_host_dequeue(sc->sc_cr);
 	/*
 	 * `7. Write the CRCR with the address and RCS value of the
 	 *     reinitialized Command Ring.  Note that this write will
 	 *     cause the Command Ring to restart at the address
 	 *     specified by the CRCR.'
 	 */
 	xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(sc->sc_cr, 0) |
 	    sc->sc_cr->xr_cs);
 	/*
 	 * `8. Enable the controller by setting Run/Stop (R/S) =
 	 *     ``1''.'
 	 */
 	xhci_op_write_4(sc, XHCI_USBCMD,
 	    xhci_op_read_4(sc, XHCI_USBCMD) | XHCI_CMD_RS);
 	/*
 	 * `9. Software shall walk the USB topology and initialize each
 	 *     of the xHC PORTSC, PORTPMSC, and PORTLI registers, and
 	 *     external hub ports attached to USB devices.'
+	 *
 	 * This follows the procedure in 4.15 `Suspend-Resume', 4.15.2
 	 * `Port Resume', 4.15.2.1 `Host Initiated'.
+	 *
 	 * XXX We should maybe batch up initiating the state
 	 * transitions, and then wait for them to complete all at once.
 	 */
 	for (bn = 0; bn < 2; bn++) {
 		for (i = 1; i <= sc->sc_rhportcount[bn]; i++) {
 			port = XHCI_PORTSC(xhci_rhport2ctlrport(sc, bn, i));
 			/* `When a port is in the U3 state: ...' */
 			v = xhci_op_read_4(sc, port);
 			if (XHCI_PS_PLS_GET(v) != XHCI_PS_PLS_U3)
 				continue;
 			/*
 			 * `For a USB2 protocol port, software shall
 			 *  write a ``15'' (Resume) to the PLS field to
 			 *  initiate resume signaling.  The port shall
 			 *  transition to the Resume substate and the
 			 *  xHC shall transmit the resume signaling
 			 *  within 1ms (T_URSM).  Software shall ensure
 			 *  that resume is signaled for at least 20ms
 			 *  (T_DRSMDN).  Software shall start timing
 			 *  T_DRSMDN from the write of ``15'' (Resume)
 			 *  to PLS.'
 			 */
 			if (bn == 1) {
 				KASSERT(sc->sc_bus2.ub_revision == USBREV_2_0);
 				v &= ~(XHCI_PS_PLS_MASK | XHCI_PS_CLEAR);
 				v |= XHCI_PS_LWS;
 				v |= XHCI_PS_PLS_SET(XHCI_PS_PLS_SETRESUME);
 				xhci_op_write_4(sc, port, v);
-				usb_delay_ms(&sc->sc_bus, 20);
+				usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT);
 			} else {
 				KASSERT(sc->sc_bus.ub_revision > USBREV_2_0);
+			}
 			/*
 			 * `For a USB3 protocol port [and a USB2
 			 *  protocol port after transitioning to
 			 *  Resume], software shall write a ``0'' (U0)
 			 *  to the PLS field...'
 			 */
 			v = xhci_op_read_4(sc, port);
 			v &= ~(XHCI_PS_PLS_MASK | XHCI_PS_CLEAR);
 			v |= XHCI_PS_LWS | XHCI_PS_PLS_SET(XHCI_PS_PLS_SETU0);
 			xhci_op_write_4(sc, port, v);
 			for (j = 0; j < XHCI_WAIT_PLS_U0; j++) {
 				v = xhci_op_read_4(sc, port);
 				if (XHCI_PS_PLS_GET(v) == XHCI_PS_PLS_U0)
 					break;
 				usb_delay_ms(&sc->sc_bus, 1);
+			}
 			if (j == XHCI_WAIT_PLS_U0) {
 				device_printf(self,
 				    "resume timeout on bus %zu port %zu\n",
 				    bn, i);
 				goto out;
+			}
+		}
+	}
 	/*
 	 * `10. Restart each of the previously Running endpoints by
 	 *      ringing their doorbells.'
 	 */
 	for (i = 0; i < sc->sc_maxslots; i++) {
 		struct xhci_slot *xs = &sc->sc_slots[i];
 		/* Skip if the slot is not in use.  */
 		if (xs->xs_idx == 0)
 			continue;
 		for (dci = XHCI_DCI_SLOT; dci <= XHCI_MAX_DCI; dci++) {
 			/* Skip if the endpoint is not Running.  */
 			if (xhci_get_epstate(sc, xs, dci) !=
 			    XHCI_EPSTATE_RUNNING)
 				continue;
 			/* Ring the doorbell.  */
 			xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci);
+		}
+	}
 	/*
 	 * `Note: After a Save or Restore operation completes, the
 	 *  Save/Restore Error (SRE) flag in the USBSTS register should
 	 *  be checked to ensure that the operation completed
 	 *  successfully.'
 	 */
 	if (xhci_op_read_4(sc, XHCI_USBSTS) & XHCI_STS_SRE) {
 		device_printf(self, "resume error, USBSTS.SRE\n");
 		goto out;
+	}
 	/* Resume command issuance.  */
 	sc->sc_suspender = NULL;
 	cv_broadcast(&sc->sc_cmdbusy_cv);
 	/* Success!  */
 	ok = true;
 out:	mutex_exit(&sc->sc_lock);
 	return ok;
+}
 bool
 xhci_shutdown(device_t self, int flags)
+{
 	return false;
+}
 static int
 xhci_hc_reset(struct xhci_softc * const sc)
+{
 	uint32_t usbcmd, usbsts;
 	int i;
 	/* Check controller not ready */
 	for (i = 0; i < XHCI_WAIT_CNR; i++) {
 		usbsts = xhci_op_read_4(sc, XHCI_USBSTS);
 		if ((usbsts & XHCI_STS_CNR) == 0)
 			break;
 		usb_delay_ms(&sc->sc_bus, 1);
+	}
 	if (i >= XHCI_WAIT_CNR) {
 		aprint_error_dev(sc->sc_dev, "controller not ready timeout\n");
 		return EIO;
+	}
 	/* Halt controller */
 	usbcmd = 0;
 	xhci_op_write_4(sc, XHCI_USBCMD, usbcmd);
 	usb_delay_ms(&sc->sc_bus, 1);
 	/* Reset controller */
 	usbcmd = XHCI_CMD_HCRST;
 	xhci_op_write_4(sc, XHCI_USBCMD, usbcmd);
 	for (i = 0; i < XHCI_WAIT_HCRST; i++) {
 		/*
 		 * Wait 1ms first. Existing Intel xHCI requies 1ms delay to
 		 * prevent system hang (Errata).
 		 */
 		usb_delay_ms(&sc->sc_bus, 1);
 		usbcmd = xhci_op_read_4(sc, XHCI_USBCMD);
 		if ((usbcmd & XHCI_CMD_HCRST) == 0)
 			break;
+	}
 	if (i >= XHCI_WAIT_HCRST) {
 		aprint_error_dev(sc->sc_dev, "host controller reset timeout\n");
 		return EIO;
+	}
 	/* Check controller not ready */
 	for (i = 0; i < XHCI_WAIT_CNR; i++) {
 		usbsts = xhci_op_read_4(sc, XHCI_USBSTS);
 		if ((usbsts & XHCI_STS_CNR) == 0)
 			break;
 		usb_delay_ms(&sc->sc_bus, 1);
+	}
 	if (i >= XHCI_WAIT_CNR) {
 		aprint_error_dev(sc->sc_dev,
 		    "controller not ready timeout after reset\n");
 		return EIO;
+	}
 	return 0;
+}
 /* 7.2 xHCI Support Protocol Capability */
 static void
 xhci_id_protocols(struct xhci_softc *sc, bus_size_t ecp)
+{
 	XHCIHIST_FUNC(); XHCIHIST_CALLED();
 	/* XXX Cache this lot */
 	const uint32_t w0 = xhci_read_4(sc, ecp);
 	const uint32_t w4 = xhci_read_4(sc, ecp + 4);
 	const uint32_t w8 = xhci_read_4(sc, ecp + 8);
 	const uint32_t wc = xhci_read_4(sc, ecp + 0xc);
 	aprint_debug_dev(sc->sc_dev,
 	    " SP: 0x%08x 0x%08x 0x%08x 0x%08x\n", w0, w4, w8, wc);
 	if (w4 != XHCI_XECP_USBID)
 		return;
 	const int major = XHCI_XECP_SP_W0_MAJOR(w0);
 	const int minor = XHCI_XECP_SP_W0_MINOR(w0);
 	const uint8_t cpo = XHCI_XECP_SP_W8_CPO(w8);
 	const uint8_t cpc = XHCI_XECP_SP_W8_CPC(w8);
 	const uint16_t mm = __SHIFTOUT(w0, __BITS(31, 16));
 	switch (mm) {
 	case 0x0200:
 	case 0x0300:
 	case 0x0301:
 	case 0x0310:
 		aprint_debug_dev(sc->sc_dev, " %s ports %d - %d\n",
 		    major == 3 ? "ss" : "hs", cpo, cpo + cpc -1);
 		break;
 	default:
 		aprint_error_dev(sc->sc_dev, " unknown major/minor (%d/%d)\n",
 		    major, minor);
 		return;
+	}
 	const size_t bus = (major == 3) ? 0 : 1;
 	/* Index arrays with 0..n-1 where ports are numbered 1..n */
 	for (size_t cp = cpo - 1; cp < cpo + cpc - 1; cp++) {
 		if (sc->sc_ctlrportmap[cp] != 0) {
 			aprint_error_dev(sc->sc_dev, "controller port %zu "
 			    "already assigned", cp);
 			continue;
+		}
 		sc->sc_ctlrportbus[cp / NBBY] |=
 		    bus == 0 ? 0 : __BIT(cp % NBBY);
 		const size_t rhp = sc->sc_rhportcount[bus]++;
 		KASSERTMSG(sc->sc_rhportmap[bus][rhp] == 0,
 		    "bus %zu rhp %zu is %d", bus, rhp,
 		    sc->sc_rhportmap[bus][rhp]);
 		sc->sc_rhportmap[bus][rhp] = cp + 1;
 		sc->sc_ctlrportmap[cp] = rhp + 1;
+	}
+}
 /* Process extended capabilities */
 static void
 xhci_ecp(struct xhci_softc *sc)
+{
 	XHCIHIST_FUNC(); XHCIHIST_CALLED();
 	bus_size_t ecp = XHCI_HCC_XECP(sc->sc_hcc) * 4;
 	while (ecp != 0) {
 		uint32_t ecr = xhci_read_4(sc, ecp);
 		aprint_debug_dev(sc->sc_dev, "ECR: 0x%08x\n", ecr);
 		switch (XHCI_XECP_ID(ecr)) {
 		case XHCI_ID_PROTOCOLS: {
 			xhci_id_protocols(sc, ecp);
 			break;
+		}
 		case XHCI_ID_USB_LEGACY: {
 			uint8_t bios_sem;
 			/* Take host controller ownership from BIOS */
 			bios_sem = xhci_read_1(sc, ecp + XHCI_XECP_BIOS_SEM);
 			if (bios_sem) {
 				/* sets xHCI to be owned by OS */
 				xhci_write_1(sc, ecp + XHCI_XECP_OS_SEM, 1);
 				aprint_debug_dev(sc->sc_dev,
 				    "waiting for BIOS to give up control\n");
 				for (int i = 0; i < 5000; i++) {
 					bios_sem = xhci_read_1(sc, ecp +
 					    XHCI_XECP_BIOS_SEM);
 					if (bios_sem == 0)
 						break;
 					DELAY(1000);
+				}
 				if (bios_sem) {
 					aprint_error_dev(sc->sc_dev,
 					    "timed out waiting for BIOS\n");
+				}
+			}
 			break;
+		}
 		default:
 			break;
+		}
 		ecr = xhci_read_4(sc, ecp);
 		if (XHCI_XECP_NEXT(ecr) == 0) {
 			ecp = 0;
 		} else {
 			ecp += XHCI_XECP_NEXT(ecr) * 4;
+		}
+	}
+}
 #define XHCI_HCCPREV1_BITS	\
 	"\177\020"	/* New bitmask */			\
 	"f\020\020XECP\0"					\
 	"f\014\4MAXPSA\0"					\
 	"b\013CFC\0"						\
 	"b\012SEC\0"						\
 	"b\011SBD\0"						\
 	"b\010FSE\0"						\
 	"b\7NSS\0"						\
 	"b\6LTC\0"						\
 	"b\5LHRC\0"						\
 	"b\4PIND\0"						\
 	"b\3PPC\0"						\
 	"b\2CZC\0"						\
 	"b\1BNC\0"						\
 	"b\0AC64\0"						\
 	"\0"
 #define XHCI_HCCV1_x_BITS	\
 	"\177\020"	/* New bitmask */			\
 	"f\020\020XECP\0"					\
 	"f\014\4MAXPSA\0"					\
 	"b\013CFC\0"						\
 	"b\012SEC\0"						\
 	"b\011SPC\0"						\
 	"b\010PAE\0"						\
 	"b\7NSS\0"						\
 	"b\6LTC\0"						\
 	"b\5LHRC\0"						\
 	"b\4PIND\0"						\
 	"b\3PPC\0"						\
 	"b\2CSZ\0"						\
 	"b\1BNC\0"						\
 	"b\0AC64\0"						\
 	"\0"
 #define XHCI_HCC2_BITS	\
 	"\177\020"	/* New bitmask */			\
 	"b\7ETC_TSC\0"						\
 	"b\6ETC\0"						\
 	"b\5CIC\0"						\
 	"b\4LEC\0"						\
 	"b\3CTC\0"						\
 	"b\2FSC\0"						\
 	"b\1CMC\0"						\
 	"b\0U3C\0"						\
 	"\0"
 void
 xhci_start(struct xhci_softc *sc)
+{
 	xhci_rt_write_4(sc, XHCI_IMAN(0), XHCI_IMAN_INTR_ENA);
 	if ((sc->sc_quirks & XHCI_QUIRK_INTEL) != 0)
 		/* Intel xhci needs interrupt rate moderated. */
 		xhci_rt_write_4(sc, XHCI_IMOD(0), XHCI_IMOD_DEFAULT_LP);
 	else
 		xhci_rt_write_4(sc, XHCI_IMOD(0), 0);
 	aprint_debug_dev(sc->sc_dev, "current IMOD %u\n",
 	    xhci_rt_read_4(sc, XHCI_IMOD(0)));
 	/* Go! */
 	xhci_op_write_4(sc, XHCI_USBCMD, XHCI_CMD_INTE|XHCI_CMD_RS);
 	aprint_debug_dev(sc->sc_dev, "USBCMD 0x%08"PRIx32"\n",
 	    xhci_op_read_4(sc, XHCI_USBCMD));
+}
 int
 xhci_init(struct xhci_softc *sc)
+{
 	bus_size_t bsz;
 	uint32_t hcs1, hcs2, hcs3, dboff, rtsoff;
 	uint32_t pagesize, config;
 	int i = 0;
 	uint16_t hciversion;
 	uint8_t caplength;
 	XHCIHIST_FUNC(); XHCIHIST_CALLED();
 	/* Set up the bus struct for the usb 3 and usb 2 buses */
 	sc->sc_bus.ub_methods = &xhci_bus_methods;
 	sc->sc_bus.ub_pipesize = sizeof(struct xhci_pipe);
 	sc->sc_bus.ub_usedma = true;
 	sc->sc_bus.ub_hcpriv = sc;
 	sc->sc_bus2.ub_methods = &xhci_bus_methods;
 	sc->sc_bus2.ub_pipesize = sizeof(struct xhci_pipe);
 	sc->sc_bus2.ub_revision = USBREV_2_0;
 	sc->sc_bus2.ub_usedma = true;
 	sc->sc_bus2.ub_hcpriv = sc;
 	sc->sc_bus2.ub_dmatag = sc->sc_bus.ub_dmatag;
 	caplength = xhci_read_1(sc, XHCI_CAPLENGTH);
 	hciversion = xhci_read_2(sc, XHCI_HCIVERSION);
 	if (hciversion < XHCI_HCIVERSION_0_96 ||
 	    hciversion >= 0x0200) {
 		aprint_normal_dev(sc->sc_dev,
 		    "xHCI version %x.%x not known to be supported\n",
 		    (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff);
 	} else {
 		aprint_verbose_dev(sc->sc_dev, "xHCI version %x.%x\n",
 		    (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff);
+	}
 	if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 0, caplength,
 	    &sc->sc_cbh) != 0) {
 		aprint_error_dev(sc->sc_dev, "capability subregion failure\n");
 		return ENOMEM;
+	}
 	hcs1 = xhci_cap_read_4(sc, XHCI_HCSPARAMS1);
 	sc->sc_maxslots = XHCI_HCS1_MAXSLOTS(hcs1);
 	sc->sc_maxintrs = XHCI_HCS1_MAXINTRS(hcs1);
 	sc->sc_maxports = XHCI_HCS1_MAXPORTS(hcs1);
 	hcs2 = xhci_cap_read_4(sc, XHCI_HCSPARAMS2);
 	hcs3 = xhci_cap_read_4(sc, XHCI_HCSPARAMS3);
 	aprint_debug_dev(sc->sc_dev,
 	    "hcs1=%"PRIx32" hcs2=%"PRIx32" hcs3=%"PRIx32"\n", hcs1, hcs2, hcs3);
 	sc->sc_hcc = xhci_cap_read_4(sc, XHCI_HCCPARAMS);
 	sc->sc_ctxsz = XHCI_HCC_CSZ(sc->sc_hcc) ? 64 : 32;
 	char sbuf[128];
 	if (hciversion < XHCI_HCIVERSION_1_0)
 		snprintb(sbuf, sizeof(sbuf), XHCI_HCCPREV1_BITS, sc->sc_hcc);
 	else
 		snprintb(sbuf, sizeof(sbuf), XHCI_HCCV1_x_BITS, sc->sc_hcc);
 	aprint_debug_dev(sc->sc_dev, "hcc=%s\n", sbuf);
 	aprint_debug_dev(sc->sc_dev, "xECP %" __PRIxBITS "\n",
 	    XHCI_HCC_XECP(sc->sc_hcc) * 4);
 	if (hciversion >= XHCI_HCIVERSION_1_1) {
 		sc->sc_hcc2 = xhci_cap_read_4(sc, XHCI_HCCPARAMS2);
 		snprintb(sbuf, sizeof(sbuf), XHCI_HCC2_BITS, sc->sc_hcc2);
 		aprint_debug_dev(sc->sc_dev, "hcc2=%s\n", sbuf);
+	}
 	/* default all ports to bus 0, i.e. usb 3 */
 	sc->sc_ctlrportbus = kmem_zalloc(
 	    howmany(sc->sc_maxports * sizeof(uint8_t), NBBY), KM_SLEEP);
 	sc->sc_ctlrportmap = kmem_zalloc(sc->sc_maxports * sizeof(int), KM_SLEEP);
 	/* controller port to bus roothub port map */
 	for (size_t j = 0; j < __arraycount(sc->sc_rhportmap); j++) {
 		sc->sc_rhportmap[j] = kmem_zalloc(sc->sc_maxports * sizeof(int), KM_SLEEP);
+	}
 	/*
 	 * Process all Extended Capabilities
 	 */
 	xhci_ecp(sc);
 	bsz = XHCI_PORTSC(sc->sc_maxports);
 	if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, caplength, bsz,
 	    &sc->sc_obh) != 0) {
 		aprint_error_dev(sc->sc_dev, "operational subregion failure\n");
 		return ENOMEM;
+	}
 	dboff = xhci_cap_read_4(sc, XHCI_DBOFF);
 	if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, dboff,
 	    sc->sc_maxslots * 4, &sc->sc_dbh) != 0) {
 		aprint_error_dev(sc->sc_dev, "doorbell subregion failure\n");
 		return ENOMEM;
+	}
 	rtsoff = xhci_cap_read_4(sc, XHCI_RTSOFF);
 	if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, rtsoff,
 	    sc->sc_maxintrs * 0x20, &sc->sc_rbh) != 0) {
 		aprint_error_dev(sc->sc_dev, "runtime subregion failure\n");
 		return ENOMEM;
+	}
 	int rv;
 	rv = xhci_hc_reset(sc);
 	if (rv != 0) {
 		return rv;
+	}
 	if (sc->sc_vendor_init)
 		sc->sc_vendor_init(sc);
 	pagesize = xhci_op_read_4(sc, XHCI_PAGESIZE);
 	aprint_debug_dev(sc->sc_dev, "PAGESIZE 0x%08x\n", pagesize);
 	pagesize = ffs(pagesize);
 	if (pagesize == 0) {
 		aprint_error_dev(sc->sc_dev, "pagesize is 0\n");
 		return EIO;
+	}
 	sc->sc_pgsz = 1 << (12 + (pagesize - 1));
 	aprint_debug_dev(sc->sc_dev, "sc_pgsz 0x%08x\n", (uint32_t)sc->sc_pgsz);
 	aprint_debug_dev(sc->sc_dev, "sc_maxslots 0x%08x\n",
 	    (uint32_t)sc->sc_maxslots);
 	aprint_debug_dev(sc->sc_dev, "sc_maxports %d\n", sc->sc_maxports);
 	int err;
 	sc->sc_maxspbuf = XHCI_HCS2_MAXSPBUF(hcs2);
 	aprint_debug_dev(sc->sc_dev, "sc_maxspbuf %d\n", sc->sc_maxspbuf);
 	if (sc->sc_maxspbuf != 0) {
 		err = usb_allocmem(&sc->sc_bus,
 		    sizeof(uint64_t) * sc->sc_maxspbuf, sizeof(uint64_t),
 		    USBMALLOC_COHERENT | USBMALLOC_ZERO,
 		    &sc->sc_spbufarray_dma);
 		if (err) {
 			aprint_error_dev(sc->sc_dev,
 			    "spbufarray init fail, err %d\n", err);
 			return ENOMEM;
+		}
 		sc->sc_spbuf_dma = kmem_zalloc(sizeof(*sc->sc_spbuf_dma) *
 		    sc->sc_maxspbuf, KM_SLEEP);
 		uint64_t *spbufarray = KERNADDR(&sc->sc_spbufarray_dma, 0);
 		for (i = 0; i < sc->sc_maxspbuf; i++) {
 			usb_dma_t * const dma = &sc->sc_spbuf_dma[i];
 			/* allocate contexts */
 			err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz,
 			    sc->sc_pgsz, USBMALLOC_COHERENT | USBMALLOC_ZERO,
 			    dma);
 			if (err) {
 				aprint_error_dev(sc->sc_dev,
 				    "spbufarray_dma init fail, err %d\n", err);
 				rv = ENOMEM;
 				goto bad1;
+			}
 			spbufarray[i] = htole64(DMAADDR(dma, 0));
 			usb_syncmem(dma, 0, sc->sc_pgsz,
 			    BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
+		}
 		usb_syncmem(&sc->sc_spbufarray_dma, 0,
 		    sizeof(uint64_t) * sc->sc_maxspbuf, BUS_DMASYNC_PREWRITE);
+	}
 	config = xhci_op_read_4(sc, XHCI_CONFIG);
 	config &= ~0xFF;
 	config |= sc->sc_maxslots & 0xFF;
 	xhci_op_write_4(sc, XHCI_CONFIG, config);
 	err = xhci_ring_init(sc, &sc->sc_cr, XHCI_COMMAND_RING_TRBS,
 	    XHCI_COMMAND_RING_SEGMENTS_ALIGN);
 	if (err) {
 		aprint_error_dev(sc->sc_dev, "command ring init fail, err %d\n",
 		    err);
 		rv = ENOMEM;
 		goto bad1;
+	}
 	err = xhci_ring_init(sc, &sc->sc_er, XHCI_EVENT_RING_TRBS,
 	    XHCI_EVENT_RING_SEGMENTS_ALIGN);
 	if (err) {
 		aprint_error_dev(sc->sc_dev, "event ring init fail, err %d\n",
 		    err);
 		rv = ENOMEM;
 		goto bad2;
+	}
 	usb_dma_t *dma;
 	size_t size;
 	size_t align;
 	dma = &sc->sc_eventst_dma;
 	size = roundup2(XHCI_EVENT_RING_SEGMENTS * XHCI_ERSTE_SIZE,
 	    XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN);
 	KASSERTMSG(size <= (512 * 1024), "eventst size %zu too large", size);
 	align = XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN;
 	err = usb_allocmem(&sc->sc_bus, size, align,
 	    USBMALLOC_COHERENT | USBMALLOC_ZERO, dma);
 	if (err) {
 		aprint_error_dev(sc->sc_dev, "eventst init fail, err %d\n",
 		    err);
 		rv = ENOMEM;
 		goto bad3;
+	}
 	aprint_debug_dev(sc->sc_dev, "eventst: 0x%016jx %p %zx\n",
 	    (uintmax_t)DMAADDR(&sc->sc_eventst_dma, 0),
 	    KERNADDR(&sc->sc_eventst_dma, 0),
 	    sc->sc_eventst_dma.udma_block->size);
 	dma = &sc->sc_dcbaa_dma;
 	size = (1 + sc->sc_maxslots) * sizeof(uint64_t);
 	KASSERTMSG(size <= 2048, "dcbaa size %zu too large", size);
 	align = XHCI_DEVICE_CONTEXT_BASE_ADDRESS_ARRAY_ALIGN;
 	err = usb_allocmem(&sc->sc_bus, size, align,
 	    USBMALLOC_COHERENT | USBMALLOC_ZERO, dma);
 	if (err) {
 		aprint_error_dev(sc->sc_dev, "dcbaa init fail, err %d\n", err);
 		rv = ENOMEM;
 		goto bad4;
+	}
 	aprint_debug_dev(sc->sc_dev, "dcbaa: 0x%016jx %p %zx\n",
 	    (uintmax_t)DMAADDR(&sc->sc_dcbaa_dma, 0),
 	    KERNADDR(&sc->sc_dcbaa_dma, 0),
 	    sc->sc_dcbaa_dma.udma_block->size);
 	if (sc->sc_maxspbuf != 0) {
 		/*
 		 * DCBA entry 0 hold the scratchbuf array pointer.
 		 */
 		*(uint64_t *)KERNADDR(dma, 0) =
 		    htole64(DMAADDR(&sc->sc_spbufarray_dma, 0));
 		usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE);
+	}
 	sc->sc_slots = kmem_zalloc(sizeof(*sc->sc_slots) * sc->sc_maxslots,
 	    KM_SLEEP);
 	if (sc->sc_slots == NULL) {
 		aprint_error_dev(sc->sc_dev, "slots init fail, err %d\n", err);
 		rv = ENOMEM;
 		goto bad;
+	}
 	sc->sc_xferpool = pool_cache_init(sizeof(struct xhci_xfer), 0, 0, 0,
 	    "xhcixfer", NULL, IPL_USB, NULL, NULL, NULL);
 	if (sc->sc_xferpool == NULL) {
 		aprint_error_dev(sc->sc_dev, "pool_cache init fail, err %d\n",
 		    err);
 		rv = ENOMEM;
 		goto bad;
+	}
 	cv_init(&sc->sc_command_cv, "xhcicmd");
 	cv_init(&sc->sc_cmdbusy_cv, "xhcicmdq");
 	mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB);
 	mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB);
 	struct xhci_erste *erst;
 	erst = KERNADDR(&sc->sc_eventst_dma, 0);
 	erst[0].erste_0 = htole64(xhci_ring_trbp(sc->sc_er, 0));
 	erst[0].erste_2 = htole32(sc->sc_er->xr_ntrb);
 	erst[0].erste_3 = htole32(0);
 	usb_syncmem(&sc->sc_eventst_dma, 0,
 	    XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS, BUS_DMASYNC_PREWRITE);
 	xhci_rt_write_4(sc, XHCI_ERSTSZ(0), XHCI_EVENT_RING_SEGMENTS);
 	xhci_rt_write_8(sc, XHCI_ERSTBA(0), DMAADDR(&sc->sc_eventst_dma, 0));
 	xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(sc->sc_er, 0) |
 	    XHCI_ERDP_BUSY);
 	xhci_op_write_8(sc, XHCI_DCBAAP, DMAADDR(&sc->sc_dcbaa_dma, 0));
 	xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(sc->sc_cr, 0) |
 	    sc->sc_cr->xr_cs);
 	xhci_barrier(sc, BUS_SPACE_BARRIER_WRITE);
 	HEXDUMP("eventst", KERNADDR(&sc->sc_eventst_dma, 0),
 	    XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS);
 	if ((sc->sc_quirks & XHCI_DEFERRED_START) == 0)
 		xhci_start(sc);
 	return 0;
  bad:
 	if (sc->sc_xferpool) {
 		pool_cache_destroy(sc->sc_xferpool);
 		sc->sc_xferpool = NULL;
+	}
 	if (sc->sc_slots) {
 		kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) *
 		    sc->sc_maxslots);
 		sc->sc_slots = NULL;
+	}
 	usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma);
  bad4:
 	usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma);
  bad3:
 	xhci_ring_free(sc, &sc->sc_er);
  bad2:
 	xhci_ring_free(sc, &sc->sc_cr);
 	i = sc->sc_maxspbuf;
  bad1:
 	for (int j = 0; j < i; j++)
 		usb_freemem(&sc->sc_bus, &sc->sc_spbuf_dma[j]);
 	usb_freemem(&sc->sc_bus, &sc->sc_spbufarray_dma);
 	return rv;
+}
 static inline bool
 xhci_polling_p(struct xhci_softc * const sc)
+{
 	return sc->sc_bus.ub_usepolling || sc->sc_bus2.ub_usepolling;
+}
 int
 xhci_intr(void *v)
+{
 	struct xhci_softc * const sc = v;
 	int ret = 0;
 	XHCIHIST_FUNC(); XHCIHIST_CALLED();
 	if (sc == NULL)
 		return 0;
 	mutex_spin_enter(&sc->sc_intr_lock);
 	if (sc->sc_dying || !device_has_power(sc->sc_dev))
 		goto done;
 	/* If we get an interrupt while polling, then just ignore it. */
 	if (xhci_polling_p(sc)) {
 #ifdef DIAGNOSTIC
 		DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0);
 #endif
 		goto done;
+	}
 	ret = xhci_intr1(sc);
 	if (ret) {
 		KASSERT(sc->sc_child || sc->sc_child2);
 		/*
 		 * One of child busses could be already detached. It doesn't
 		 * matter on which of the two the softintr is scheduled.
 		 */
 		if (sc->sc_child)
 			usb_schedsoftintr(&sc->sc_bus);
 		else
 			usb_schedsoftintr(&sc->sc_bus2);
+	}
 done:
 	mutex_spin_exit(&sc->sc_intr_lock);
 	return ret;
+}
 int
 xhci_intr1(struct xhci_softc * const sc)
+{
 	uint32_t usbsts;
 	uint32_t iman;
 	XHCIHIST_FUNC();
 	usbsts = xhci_op_read_4(sc, XHCI_USBSTS);
 	XHCIHIST_CALLARGS("USBSTS 0x%08jx", usbsts, 0, 0, 0);
 	if ((usbsts & (XHCI_STS_HSE | XHCI_STS_EINT | XHCI_STS_PCD |
 	    XHCI_STS_HCE)) == 0) {
 		DPRINTFN(16, "ignored intr not for %jd",
 		    device_unit(sc->sc_dev), 0, 0, 0);
 		return 0;
+	}
 	/*
 	 * Clear EINT and other transient flags, to not misenterpret
 	 * next shared interrupt. Also, to avoid race, EINT must be cleared
 	 * before XHCI_IMAN_INTR_PEND is cleared.
 	 */
 	xhci_op_write_4(sc, XHCI_USBSTS, usbsts & XHCI_STS_RSVDP0);
 #ifdef XHCI_DEBUG
 	usbsts = xhci_op_read_4(sc, XHCI_USBSTS);
 	DPRINTFN(16, "USBSTS 0x%08jx", usbsts, 0, 0, 0);
 #endif
 	iman = xhci_rt_read_4(sc, XHCI_IMAN(0));
 	DPRINTFN(16, "IMAN0 0x%08jx", iman, 0, 0, 0);
 	iman |= XHCI_IMAN_INTR_PEND;
 	xhci_rt_write_4(sc, XHCI_IMAN(0), iman);
 #ifdef XHCI_DEBUG
 	iman = xhci_rt_read_4(sc, XHCI_IMAN(0));
 	DPRINTFN(16, "IMAN0 0x%08jx", iman, 0, 0, 0);
 	usbsts = xhci_op_read_4(sc, XHCI_USBSTS);
 	DPRINTFN(16, "USBSTS 0x%08jx", usbsts, 0, 0, 0);
 #endif
 	return 1;
+}
 /*
  * 3 port speed types used in USB stack
+ *
  * usbdi speed
  *	definition: USB_SPEED_* in usb.h
  *	They are used in struct usbd_device in USB stack.
  *	ioctl interface uses these values too.
  * port_status speed
  *	definition: UPS_*_SPEED in usb.h
  *	They are used in usb_port_status_t and valid only for USB 2.0.
  *	Speed value is always 0 for Super Speed or more, and dwExtPortStatus
  *	of usb_port_status_ext_t indicates port speed.
  *	Note that some 3.0 values overlap with 2.0 values.
  *	(e.g. 0x200 means UPS_POER_POWER_SS in SS and
  *	            means UPS_LOW_SPEED in HS.)
  *	port status returned from hub also uses these values.
  *	On NetBSD UPS_OTHER_SPEED indicates port speed is super speed
  *	or more.
  * xspeed:
  *	definition: Protocol Speed ID (PSI) (xHCI 1.1 7.2.1)
  *	They are used in only slot context and PORTSC reg of xhci.
  *	The difference between usbdi speed and xspeed is
  *	that FS and LS values are swapped.
  */
 /* convert usbdi speed to xspeed */
 static int
 xhci_speed2xspeed(int speed)
+{
 	switch (speed) {
 	case USB_SPEED_LOW:	return 2;
 	case USB_SPEED_FULL:	return 1;
 	default:		return speed;
+	}
+}
 #if 0
 /* convert xspeed to usbdi speed */
 static int
 xhci_xspeed2speed(int xspeed)
+{
 	switch (xspeed) {
 	case 1: return USB_SPEED_FULL;
 	case 2: return USB_SPEED_LOW;
 	default: return xspeed;
+	}
+}
 #endif
 /* convert xspeed to port status speed */
 static int
 xhci_xspeed2psspeed(int xspeed)
+{
 	switch (xspeed) {
 	case 0: return 0;
 	case 1: return UPS_FULL_SPEED;
 	case 2: return UPS_LOW_SPEED;
 	case 3: return UPS_HIGH_SPEED;
 	default: return UPS_OTHER_SPEED;
+	}
+}
 /*
  * Construct input contexts and issue TRB to open pipe.
  */
 static usbd_status
 xhci_configure_endpoint(struct usbd_pipe *pipe)
+{
 	struct xhci_softc * const sc = XHCI_PIPE2SC(pipe);
 	struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv;
 #ifdef USB_DEBUG
 	const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc);
 #endif
 	struct xhci_soft_trb trb;
 	usbd_status err;
 	XHCIHIST_FUNC();
 	XHCIHIST_CALLARGS("slot %ju dci %ju epaddr 0x%02jx attr 0x%02jx",
 	    xs->xs_idx, dci, pipe->up_endpoint->ue_edesc->bEndpointAddress,
 	    pipe->up_endpoint->ue_edesc->bmAttributes);
 	/* XXX ensure input context is available? */
 	memset(xhci_slot_get_icv(sc, xs, 0), 0, sc->sc_pgsz);
 	/* set up context */
 	xhci_setup_ctx(pipe);
 	HEXDUMP("input control context", xhci_slot_get_icv(sc, xs, 0),
 	    sc->sc_ctxsz * 1);
 	HEXDUMP("input endpoint context", xhci_slot_get_icv(sc, xs,
 	    xhci_dci_to_ici(dci)), sc->sc_ctxsz * 1);
 	trb.trb_0 = xhci_slot_get_icp(sc, xs, 0);
 	trb.trb_2 = 0;
 	trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) |
 	    XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP);
 	err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT);
 	usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD);
 	HEXDUMP("output context", xhci_slot_get_dcv(sc, xs, dci),
 	    sc->sc_ctxsz * 1);
 	return err;
+}
 #if 0
 static usbd_status
 xhci_unconfigure_endpoint(struct usbd_pipe *pipe)
+{
 #ifdef USB_DEBUG
 	struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv;
 #endif
 	XHCIHIST_FUNC();
 	XHCIHIST_CALLARGS("slot %ju", xs->xs_idx, 0, 0, 0);
 	return USBD_NORMAL_COMPLETION;
+}
 #endif
 /* 4.6.8, 6.4.3.7 */
 static usbd_status
 xhci_reset_endpoint_locked(struct usbd_pipe *pipe)
+{
 	struct xhci_softc * const sc = XHCI_PIPE2SC(pipe);
 	struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv;
 	const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc);
 	struct xhci_soft_trb trb;
 	usbd_status err;
 	XHCIHIST_FUNC();
 	XHCIHIST_CALLARGS("slot %ju dci %ju", xs->xs_idx, dci, 0, 0);
 	KASSERT(mutex_owned(&sc->sc_lock));
 	trb.trb_0 = 0;
 	trb.trb_2 = 0;
 	trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) |
 	    XHCI_TRB_3_EP_SET(dci) |
 	    XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP);
 	err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT);
 	return err;
+}
 static usbd_status
 xhci_reset_endpoint(struct usbd_pipe *pipe)
+{
 	struct xhci_softc * const sc = XHCI_PIPE2SC(pipe);
 	mutex_enter(&sc->sc_lock);
 	usbd_status ret = xhci_reset_endpoint_locked(pipe);
 	mutex_exit(&sc->sc_lock);
 	return ret;
+}
 /*
  * 4.6.9, 6.4.3.8
  * Stop execution of TDs on xfer ring.
  * Should be called with sc_lock held.
  */
 static usbd_status
 xhci_stop_endpoint_cmd(struct xhci_softc *sc, struct xhci_slot *xs, u_int dci,
     uint32_t trb3flags)
+{
 	struct xhci_soft_trb trb;
 	usbd_status err;
 	XHCIHIST_FUNC();
 	XHCIHIST_CALLARGS("slot %ju dci %ju", xs->xs_idx, dci, 0, 0);
 	KASSERT(mutex_owned(&sc->sc_lock));
 	trb.trb_0 = 0;
 	trb.trb_2 = 0;
 	trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) |
 	    XHCI_TRB_3_EP_SET(dci) |
 	    XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) |
 	    trb3flags;
 	err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT);
 	return err;
+}
 static usbd_status
 xhci_stop_endpoint(struct usbd_pipe *pipe)
+{
 	struct xhci_softc * const sc = XHCI_PIPE2SC(pipe);
 	struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv;
 	const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc);
 	XHCIHIST_FUNC();
 	XHCIHIST_CALLARGS("slot %ju dci %ju", xs->xs_idx, dci, 0, 0);
 	KASSERT(mutex_owned(&sc->sc_lock));
 	return xhci_stop_endpoint_cmd(sc, xs, dci, 0);
+}
 /*
  * Set TR Dequeue Pointer.
  * xHCI 1.1  4.6.10  6.4.3.9
  * Purge all of the TRBs on ring and reinitialize ring.
  * Set TR dequeue Pointr to 0 and Cycle State to 1.
  * EPSTATE of endpoint must be ERROR or STOPPED, otherwise CONTEXT_STATE
  * error will be generated.
  */
 static usbd_status
 xhci_set_dequeue_locked(struct usbd_pipe *pipe)
+{
 	struct xhci_softc * const sc = XHCI_PIPE2SC(pipe);
 	struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv;
 	const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc);
 	struct xhci_ring * const xr = xs->xs_xr[dci];
 	struct xhci_soft_trb trb;
 	usbd_status err;
 	XHCIHIST_FUNC();
 	XHCIHIST_CALLARGS("slot %ju dci %ju", xs->xs_idx, dci, 0, 0);
 	KASSERT(mutex_owned(&sc->sc_lock));
 	KASSERT(xr != NULL);
 	xhci_host_dequeue(xr);
 	/* set DCS */
 	trb.trb_0 = xhci_ring_trbp(xr, 0) | 1; /* XXX */
 	trb.trb_2 = 0;
 	trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) |
 	    XHCI_TRB_3_EP_SET(dci) |
 	    XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE);
 	err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT);
 	return err;
+}
 static usbd_status
 xhci_set_dequeue(struct usbd_pipe *pipe)
+{
 	struct xhci_softc * const sc = XHCI_PIPE2SC(pipe);
 	mutex_enter(&sc->sc_lock);
 	usbd_status ret = xhci_set_dequeue_locked(pipe);
 	mutex_exit(&sc->sc_lock);
 	return ret;
+}
 /*
  * Open new pipe: called from usbd_setup_pipe_flags.
  * Fills methods of pipe.
  * If pipe is not for ep0, calls configure_endpoint.
  */
 static usbd_status
 xhci_open(struct usbd_pipe *pipe)
+{
 	struct usbd_device * const dev = pipe->up_dev;
 	struct xhci_pipe * const xpipe = (struct xhci_pipe *)pipe;
 	struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus);
 	struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv;
 	usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc;
 	const u_int dci = xhci_ep_get_dci(ed);
 	const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes);
 	usbd_status err;
 	XHCIHIST_FUNC();
 	XHCIHIST_CALLARGS("addr %jd depth %jd port %jd speed %jd", dev->ud_addr,
 	    dev->ud_depth, dev->ud_powersrc->up_portno, dev->ud_speed);
 	DPRINTFN(1, " dci %ju type 0x%02jx epaddr 0x%02jx attr 0x%02jx",
 	    xhci_ep_get_dci(ed), ed->bDescriptorType, ed->bEndpointAddress,
 	    ed->bmAttributes);