 @@ -1,14 +1,14 @@
-/* $NetBSD: pmap.c,v 1.278 2021/05/24 03:43:24 thorpej Exp $ */
+/* $NetBSD: pmap.c,v 1.279 2021/05/29 21:54:50 thorpej Exp $ */
 /*-
  * Copyright (c) 1998, 1999, 2000, 2001, 2007, 2008, 2020
  * 	The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
  * NASA Ames Research Center, by Andrew Doran and Mindaugas Rasiukevicius,
  * and by Chris G. Demetriou.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
 @@ -125,27 +125,27 @@
  *	this module may delay invalidate or reduced protection
  *	operations until such time as they are actually
  *	necessary.  This module is given full information as
  *	to which processors are currently using which maps,
  *	and to when physical maps must be made correct.
  */
 #include "opt_lockdebug.h"
 #include "opt_sysv.h"
 #include "opt_multiprocessor.h"
 #include <sys/cdefs.h>			/* RCS ID & Copyright macro defns */
-__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.278 2021/05/24 03:43:24 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.279 2021/05/29 21:54:50 thorpej Exp $");
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/kernel.h>
 #include <sys/proc.h>
 #include <sys/malloc.h>
 #include <sys/pool.h>
 #include <sys/buf.h>
 #include <sys/evcnt.h>
 #include <sys/atomic.h>
 #include <sys/cpu.h>
 #include <uvm/uvm.h>
 @@ -255,29 +255,29 @@ int		pmap_pv_lowat __read_mostly = PMAP_
  * List of all pmaps, used to update them when e.g. additional kernel
  * page tables are allocated.  This list is kept LRU-ordered by
  * pmap_activate().
  */
 static TAILQ_HEAD(, pmap) pmap_all_pmaps __cacheline_aligned;
 /*
  * The pools from which pmap structures and sub-structures are allocated.
  */
 static struct pool_cache pmap_pmap_cache __read_mostly;
 static struct pool_cache pmap_l1pt_cache __read_mostly;
 static struct pool_cache pmap_pv_cache __read_mostly;
-CTASSERT(offsetof(struct pmap, pm_asni[0]) == COHERENCY_UNIT);
+CTASSERT(offsetof(struct pmap, pm_percpu[0]) == COHERENCY_UNIT);
 CTASSERT(PMAP_SIZEOF(ALPHA_MAXPROCS) < ALPHA_PGBYTES);
-CTASSERT(sizeof(struct pmap_asn_info) == COHERENCY_UNIT);
+CTASSERT(sizeof(struct pmap_percpu) == COHERENCY_UNIT);
 /*
  * Address Space Numbers.
+ *
  * On many implementations of the Alpha architecture, the TLB entries and
  * I-cache blocks are tagged with a unique number within an implementation-
  * specified range.  When a process context becomes active, the ASN is used
  * to match TLB entries; if a TLB entry for a particular VA does not match
  * the current ASN, it is ignored (one could think of the processor as
  * having a collection of <max ASN> separate TLBs).  This allows operating
  * system software to skip the TLB flush that would otherwise be necessary
  * at context switch time.
+ *
 @@ -870,27 +870,27 @@ pmap_tlb_invalidate(const struct pmap_tl
 		/*
 		 * For CPUs that don't implement ASNs, the SWPCTX call
 		 * does all of the TLB invalidation work for us.
 		 */
 		if (__predict_false(pmap_max_asn == 0)) {
 			return;
+		}
 		/*
 		 * We cannot directly invalidate the TLB in this case,
 		 * so force allocation of a new ASN when the pmap becomes
 		 * active again.
 		 */
-		pmap->pm_asni[ci->ci_cpuid].pma_asngen = PMAP_ASNGEN_INVALID;
+		pmap->pm_percpu[ci->ci_cpuid].pmc_asngen = PMAP_ASNGEN_INVALID;
 		atomic_and_ulong(&pmap->pm_cpus, ~cpu_mask);
 		/*
 		 * This isn't strictly necessary; when we allocate a
 		 * new ASN, we're going to clear this bit and skip
 		 * syncing the I-stream.  But we will keep this bit
 		 * of accounting for internal consistency.
 		 */
 		if (TLB_CTX_FLAGS(tlbctx) & TLB_CTX_F_IMB) {
 			atomic_or_ulong(&pmap->pm_needisync, cpu_mask);
+		}
 		return;
+	}
 @@ -1570,28 +1570,28 @@ pmap_create(void)
 #endif
 	pmap = pool_cache_get(&pmap_pmap_cache, PR_WAITOK);
 	memset(pmap, 0, sizeof(*pmap));
 	atomic_store_relaxed(&pmap->pm_count, 1);
 	/*
 	 * There are only kernel mappings at this point; give the pmap
 	 * the kernel ASN.  This will be initialized to correct values
 	 * when the pmap is activated.
 	 */
 	for (i = 0; i < pmap_ncpuids; i++) {
-		pmap->pm_asni[i].pma_asn = PMAP_ASN_KERNEL;
+		pmap->pm_percpu[i].pmc_asn = PMAP_ASN_KERNEL;
-		pmap->pm_asni[i].pma_asngen = PMAP_ASNGEN_INVALID;
+		pmap->pm_percpu[i].pmc_asngen = PMAP_ASNGEN_INVALID;
+	}
  try_again:
 	rw_enter(&pmap_growkernel_lock, RW_READER);
 	pmap->pm_lev1map = pool_cache_get(&pmap_l1pt_cache, PR_NOWAIT);
 	if (__predict_false(pmap->pm_lev1map == NULL)) {
 		rw_exit(&pmap_growkernel_lock);
 		(void) kpause("pmap_create", false, hz >> 2, NULL);
 		goto try_again;
+	}
 	mutex_enter(&pmap_all_pmaps_lock);
 @@ -3804,44 +3804,44 @@ pmap_asn_alloc(pmap_t const pmap, struct
 #ifdef DEBUG
 	if (pmapdebug & (PDB_FOLLOW|PDB_ASN))
 		printf("pmap_asn_alloc(%p)\n", pmap);
 #endif
 	KASSERT(pmap != pmap_kernel());
 	KASSERT(pmap->pm_lev1map != kernel_lev1map);
 	KASSERT(kpreempt_disabled());
 	/* No work to do if the the CPU does not implement ASNs. */
 	if (pmap_max_asn == 0)
 		return 0;
-	struct pmap_asn_info * const pma = &pmap->pm_asni[ci->ci_cpuid];
+	struct pmap_percpu * const pmc = &pmap->pm_percpu[ci->ci_cpuid];
 	/*
 	 * Hopefully, we can continue using the one we have...
+	 *
 	 * N.B. the generation check will fail the first time
 	 * any pmap is activated on a given CPU, because we start
 	 * the generation counter at 1, but initialize pmaps with
 	 * 0; this forces the first ASN allocation to occur.
 	 */
-	if (pma->pma_asngen == ci->ci_asn_gen) {
+	if (pmc->pmc_asngen == ci->ci_asn_gen) {
 #ifdef DEBUG
 		if (pmapdebug & PDB_ASN)
 			printf("pmap_asn_alloc: same generation, keeping %u\n",
-			    pma->pma_asn);
+			    pmc->pmc_asn);
 #endif
 		TLB_COUNT(asn_reuse);
-		return pma->pma_asn;
+		return pmc->pmc_asn;
+	}
 	/*
 	 * Need to assign a new ASN.  Grab the next one, incrementing
 	 * the generation number if we have to.
 	 */
 	if (ci->ci_next_asn > pmap_max_asn) {
 		/*
 		 * Invalidate all non-PG_ASM TLB entries and the
 		 * I-cache, and bump the generation number.
 		 */
 		ALPHA_TBIAP();
 		alpha_pal_imb();
 @@ -3864,30 +3864,30 @@ pmap_asn_alloc(pmap_t const pmap, struct
 		 * So, we don't bother.
 		 */
 		KASSERT(ci->ci_asn_gen != PMAP_ASNGEN_INVALID);
 #ifdef DEBUG
 		if (pmapdebug & PDB_ASN)
 			printf("pmap_asn_alloc: generation bumped to %lu\n",
 			    ci->ci_asn_ge);
 #endif
+	}
 	/*
 	 * Assign the new ASN and validate the generation number.
 	 */
-	pma->pma_asn = ci->ci_next_asn++;
+	pmc->pmc_asn = ci->ci_next_asn++;
-	pma->pma_asngen = ci->ci_asn_gen;
+	pmc->pmc_asngen = ci->ci_asn_gen;
 	TLB_COUNT(asn_assign);
 	/*
 	 * We have a new ASN, so we can skip any pending I-stream sync
 	 * on the way back out to user space.
 	 */
 	atomic_and_ulong(&pmap->pm_needisync, ~(1UL << ci->ci_cpuid));
 #ifdef DEBUG
 	if (pmapdebug & PDB_ASN)
 		printf("pmap_asn_alloc: assigning %u to pmap %p\n",
-		    pma->pma_asn, pmap);
+		    pmc->pmc_asn, pmap);
 #endif
-	return pma->pma_asn;
+	return pmc->pmc_asn;
+}

 @@ -1,14 +1,14 @@
-/* $NetBSD: pmap.h,v 1.85 2021/05/24 03:43:24 thorpej Exp $ */
+/* $NetBSD: pmap.h,v 1.86 2021/05/29 21:54:51 thorpej Exp $ */
 /*-
  * Copyright (c) 1998, 1999, 2000, 2001, 2007 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
  * NASA Ames Research Center and by Chris G. Demetriou.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
 @@ -121,49 +121,49 @@
  * If we ever support processor numbers higher than 63, we'll have to
  * rethink the CPU mask.
+ *
  * Note pm_asn and pm_asngen are arrays allocated in pmap_create().
  * Their size is based on the PCS count from the HWRPB, and indexed
  * by processor ID (from `whami').  This is all padded to COHERENCY_UNIT
  * to avoid false sharing.
+ *
  * The kernel pmap is a special case; since the kernel uses only ASM
  * mappings and uses a reserved ASN to keep the TLB clean, we don't
  * allocate any ASN info for the kernel pmap at all.
  * arrays which hold enough for ALPHA_MAXPROCS.
  */
-struct pmap_asn_info {
+struct pmap_percpu {
-	unsigned int		pma_asn;	/* address space number */
+	unsigned int		pmc_asn;	/* address space number */
-	unsigned int		pma_pad0;
+	unsigned int		pmc_pad0;
-	unsigned long		pma_asngen;	/* ASN generation number */
+	unsigned long		pmc_asngen;	/* ASN generation number */
-	unsigned long		pma_padN[(COHERENCY_UNIT / 8) - 2];
+	unsigned long		pmc_padN[(COHERENCY_UNIT / 8) - 2];
 };
 struct pmap {	/* pmaps are aligned to COHERENCY_UNIT boundaries */
 		/* pmaps are locked by hashed mutexes */
 	pt_entry_t		*pm_lev1map;	/* [ 0] level 1 map */
 	unsigned long		pm_cpus;	/* [ 8] CPUs using pmap */
 	unsigned long		pm_needisync;	/* [16] CPUs needing isync */
 	struct pmap_statistics	pm_stats;	/* [32] statistics */
 	unsigned int		pm_count;	/* [40] reference count */
 	unsigned int		__pm_spare;	/* [44] spare field */
 	TAILQ_ENTRY(pmap)	pm_list;	/* [48] list of all pmaps */
 	/* -- COHERENCY_UNIT boundary -- */
-	struct pmap_asn_info	pm_asni[];	/* [64] ASN information */
+	struct pmap_percpu	pm_percpu[];	/* [64] per-CPU data */
 			/*	variable length		*/
 };
 #define	PMAP_SIZEOF(x)							\
-	(ALIGN(offsetof(struct pmap, pm_asni[(x)])))
+	(ALIGN(offsetof(struct pmap, pm_percpu[(x)])))
 #define	PMAP_ASN_KERNEL		0	/* kernel-reserved ASN */
 #define	PMAP_ASN_FIRST_USER	1	/* first user ASN */
 #define	PMAP_ASNGEN_INVALID	0	/* reserved (invalid) ASN generation */
 #define	PMAP_ASNGEN_INITIAL	1	/* first valid generatation */
 /*
  * For each struct vm_page, there is a list of all currently valid virtual
  * mappings of that page.  An entry is a pv_entry_t, the list is pv_table.
  */
 typedef struct pv_entry {
 	struct pv_entry	*pv_next;	/* next pv_entry on list */
 	struct pmap	*pv_pmap;	/* pmap where mapping lies */