 @@ -1,14 +1,14 @@
-/* $NetBSD: jensenio_intr.c,v 1.17 2021/07/04 22:42:35 thorpej Exp $ */
+/* $NetBSD: jensenio_intr.c,v 1.18 2021/07/15 01:43:54 thorpej Exp $ */
 /*-
  * Copyright (c) 1999, 2000 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Jason R. Thorpe.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
 @@ -21,39 +21,41 @@
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <sys/cdefs.h>			/* RCS ID & Copyright macro defns */
-__KERNEL_RCSID(0, "$NetBSD: jensenio_intr.c,v 1.17 2021/07/04 22:42:35 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: jensenio_intr.c,v 1.18 2021/07/15 01:43:54 thorpej Exp $");
 #include <sys/types.h>
 #include <sys/param.h>
 #include <sys/time.h>
 #include <sys/systm.h>
 #include <sys/errno.h>
 #include <sys/device.h>
 #include <sys/cpu.h>
 #include <sys/syslog.h>
 #include <machine/autoconf.h>
 #include <dev/ic/i8259reg.h>
 #include <dev/eisa/eisavar.h>
 #include <dev/isa/isareg.h>
 #include <dev/isa/isavar.h>
 #include <alpha/jensenio/jenseniovar.h>
 static bus_space_tag_t pic_iot;
 static bus_space_handle_t pic_ioh[2];
 static bus_space_handle_t pic_elcr_ioh;
 static int		jensenio_eisa_intr_map(void *, u_int,
 			    eisa_intr_handle_t *);
 @@ -87,31 +89,32 @@ static const int jensenio_intr_deftype[J
 	IST_NONE,		/*  9: EISA pin B04 */
 	IST_NONE,		/* 10: EISA pin D03 */
 	IST_NONE,		/* 11: EISA pin D04 */
 	IST_NONE,		/* 12: EISA pin D05 */
 	IST_UNUSABLE,		/* 13: not connected */
 	IST_NONE,		/* 14: EISA pin D07 (SCSI) */
 	IST_NONE,		/* 15: EISA pin D06 */
 };
 static inline void
 jensenio_specific_eoi(int irq)
+{
-	if (irq > 7)
+	if (irq > 7) {
-		bus_space_write_1(pic_iot, pic_ioh[1],
+		bus_space_write_1(pic_iot, pic_ioh[1], PIC_OCW2,
-, 0x20 | (irq & 0x07));
+		    OCW2_EOI | OCW2_SL | (irq & 0x07));
 	bus_space_write_1(pic_iot, pic_ioh[0],
-, 0x20 | (irq > 7 ? 2 : irq));
+	bus_space_write_1(pic_iot, pic_ioh[0], PIC_OCW2,
 	    OCW2_EOI | OCW2_SL | (irq > 7 ? 2 : irq));
+}
 void
 jensenio_intr_init(struct jensenio_config *jcp)
+{
 	eisa_chipset_tag_t ec = &jcp->jc_ec;
 	isa_chipset_tag_t ic = &jcp->jc_ic;
 	struct evcnt *ev;
 	const char *cp;
 	int i;
 	pic_iot = &jcp->jc_eisa_iot;
 @@ -331,32 +334,32 @@ jensenio_iointr(void *framep, u_long vec
 	jensenio_specific_eoi(irq);
+}
 static void
 jensenio_enable_intr(int irq, int onoff)
+{
 	int pic;
 	uint8_t bit, mask;
 	pic = irq >> 3;
 	bit = 1 << (irq & 0x7);
-	mask = bus_space_read_1(pic_iot, pic_ioh[pic], 1);
+	mask = bus_space_read_1(pic_iot, pic_ioh[pic], PIC_OCW1);
 	if (onoff)
 		mask &= ~bit;
 	else
 		mask |= bit;
-	bus_space_write_1(pic_iot, pic_ioh[pic], 1, mask);
+	bus_space_write_1(pic_iot, pic_ioh[pic], PIC_OCW1, mask);
+}
 void
 jensenio_setlevel(int irq, int level)
+{
 	int elcr;
 	uint8_t bit, mask;
 	elcr = irq >> 3;
 	bit = 1 << (irq & 0x7);
 	mask = bus_space_read_1(pic_iot, pic_elcr_ioh, elcr);
 	if (level)
 @@ -368,22 +371,25 @@ jensenio_setlevel(int irq, int level)
 static void
 jensenio_pic_init(void)
+{
 	static const int picaddr[2] = { IO_ICU1, IO_ICU2 };
 	int pic;
 	/*
 	 * Map the PICs and mask off the interrupts on them.
 	 */
 	for (pic = 0; pic < 2; pic++) {
 		if (bus_space_map(pic_iot, picaddr[pic], 2, 0, &pic_ioh[pic]))
 			panic("jensenio_init_intr: unable to map PIC %d", pic);
-		bus_space_write_1(pic_iot, pic_ioh[pic], 1, 0xff);
+		bus_space_write_1(pic_iot, pic_ioh[pic], PIC_OCW1, 0xff);
+	}
 	/*
-	 * Map the ELCR registers.
+	 * Map the ELCR registers and initialize all interrupts to EDGE
 	 * trigger.
 	 */
 	if (bus_space_map(pic_iot, 0x4d0, 2, 0, &pic_elcr_ioh))
 		panic("jensenio_init_intr: unable to map ELCR registers");
 	bus_space_write_1(pic_iot, pic_elcr_ioh, 0, 0);
 	bus_space_write_1(pic_iot, pic_elcr_ioh, 1, 0);
+}