Fri Jul 16 17:09:33 2021 UTC ()
Define the memory controller registers, and contents for the Cache
register.


(thorpej)
diff -r1.9 -r1.10 src/sys/arch/alpha/pci/lcareg.h
cvs diff -r1.9 -r1.10 src/sys/arch/alpha/pci/lcareg.h (expand / switch to unified diff)

--- src/sys/arch/alpha/pci/lcareg.h 2012/02/06 02:14:14 1.9
+++ src/sys/arch/alpha/pci/lcareg.h 2021/07/16 17:09:33 1.10
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: lcareg.h,v 1.9 2012/02/06 02:14:14 matt Exp $ */ 1/* $NetBSD: lcareg.h,v 1.10 2021/07/16 17:09:33 thorpej Exp $ */
2 2
3/* 3/*
4 * Copyright (c) 1995 Carnegie-Mellon University. 4 * Copyright (c) 1995 Carnegie-Mellon University.
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * Authors: Jeffrey Hsu, Jason R. Thorpe 7 * Authors: Jeffrey Hsu, Jason R. Thorpe
8 * 8 *
9 * Permission to use, copy, modify and distribute this software and 9 * Permission to use, copy, modify and distribute this software and
10 * its documentation is hereby granted, provided that both the copyright 10 * its documentation is hereby granted, provided that both the copyright
11 * notice and this permission notice appear in all copies of the 11 * notice and this permission notice appear in all copies of the
12 * software, derivative works or modified versions, and any portions 12 * software, derivative works or modified versions, and any portions
13 * thereof, and that both notices appear in supporting documentation. 13 * thereof, and that both notices appear in supporting documentation.
14 * 14 *
@@ -27,32 +27,72 @@ @@ -27,32 +27,72 @@
27 * rights to redistribute these changes. 27 * rights to redistribute these changes.
28 */ 28 */
29 29
30/* 30/*
31 * 21066 chip registers 31 * 21066 chip registers
32 */ 32 */
33 33
34#define REGVAL(r) (*(volatile int32_t *)ALPHA_PHYS_TO_K0SEG(r)) 34#define REGVAL(r) (*(volatile int32_t *)ALPHA_PHYS_TO_K0SEG(r))
35#define REGVAL64(r) (*(volatile int64_t *)ALPHA_PHYS_TO_K0SEG(r)) 35#define REGVAL64(r) (*(volatile int64_t *)ALPHA_PHYS_TO_K0SEG(r))
36 36
37/* 37/*
38 * Base addresses 38 * Base addresses
39 */ 39 */
 40#define LCA_MEMC_BASE 0x120000000L /* LCA memory controller regs */
40#define LCA_IOC_BASE 0x180000000L /* LCA IOC Regs */ 41#define LCA_IOC_BASE 0x180000000L /* LCA IOC Regs */
41#define LCA_PCI_SIO 0x1c0000000L /* PCI Sp. I/O Space */ 42#define LCA_PCI_SIO 0x1c0000000L /* PCI Sp. I/O Space */
42#define LCA_PCI_CONF 0x1e0000000L /* PCI Conf. Space */ 43#define LCA_PCI_CONF 0x1e0000000L /* PCI Conf. Space */
43#define LCA_PCI_SPARSE 0x200000000L /* PCI Sparse Space */ 44#define LCA_PCI_SPARSE 0x200000000L /* PCI Sparse Space */
44#define LCA_PCI_DENSE 0x300000000L /* PCI Dense Space */ 45#define LCA_PCI_DENSE 0x300000000L /* PCI Dense Space */
45 46
 47#define LCA_MEMC_BCR0 (LCA_MEMC_BASE + 0x00) /* Bank Configuration 0 */
 48#define LCA_MEMC_BCR1 (LCA_MEMC_BASE + 0x08) /* Bank Configuration 1 */
 49#define LCA_MEMC_BCR2 (LCA_MEMC_BASE + 0x10) /* Bank Configuration 2 */
 50#define LCA_MEMC_BCR3 (LCA_MEMC_BASE + 0x18) /* Bank Configuration 3 */
 51#define LCA_MEMC_BMR0 (LCA_MEMC_BASE + 0x20) /* Bank Address Mask 0 */
 52#define LCA_MEMC_BMR1 (LCA_MEMC_BASE + 0x28) /* Bank Address Mask 1 */
 53#define LCA_MEMC_BMR2 (LCA_MEMC_BASE + 0x30) /* Bank Address Mask 2 */
 54#define LCA_MEMC_BMR3 (LCA_MEMC_BASE + 0x38) /* Bank Address Mask 3 */
 55#define LCA_MEMC_BTR0 (LCA_MEMC_BASE + 0x40) /* Bank Timing 0 */
 56#define LCA_MEMC_BTR1 (LCA_MEMC_BASE + 0x48) /* Bank Timing 1 */
 57#define LCA_MEMC_BTR2 (LCA_MEMC_BASE + 0x50) /* Bank Timing 2 */
 58#define LCA_MEMC_BTR3 (LCA_MEMC_BASE + 0x58) /* Bank Timing 3 */
 59#define LCA_MEMC_GTR (LCA_MEMC_BASE + 0x60) /* Global Timing */
 60#define LCA_MEMC_ESR (LCA_MEMC_BASE + 0x68) /* Error Status */
 61#define LCA_MEMC_EAR (LCA_MEMC_BASE + 0x70) /* Error Address */
 62#define LCA_MEMC_CAR (LCA_MEMC_BASE + 0x78) /* Cache */
 63#define LCA_MEMC_VGR (LCA_MEMC_BASE + 0x80) /* Video and Graphics Control */
 64#define LCA_MEMC_PLM (LCA_MEMC_BASE + 0x88) /* Plane mask */
 65#define LCA_MEMC_FOR (LCA_MEMC_BASE + 0x90) /* Foreground */
 66
 67#define MEMC_CAR_BCE __BIT(0) /* Bcache enable */
 68#define MEMC_CAR_ETP __BIT(2) /* Enable tag parity check */
 69#define MEMC_CAR_WWP __BIT(3) /* Write wrong tag parity */
 70#define MEMC_CAR_ECE __BIT(4) /* Enable Bcache ECC */
 71#define MEMC_CAR_BCS __BITS(5,7) /* Bcache size */
 72#define MEMC_CAR_RCC __BITS(8,10) /* Read Cycle Count */
 73#define MEMC_CAR_WCC __BITS(11,13) /* Write Cycle Count */
 74#define MEMC_CAR_WHD __BIT(14) /* Write Hold Time */
 75#define MEMC_CAR_PWR __BIT(15) /* Power Saving */
 76#define MEMC_CAR_TAG __BITS(16,30) /* latched Bcache tag value */
 77#define MEMC_CAR_HIT __BIT(31) /* Bcache hit */
 78
 79#define BCS_64K 0
 80#define BCS_128K 1
 81#define BCS_256K 2
 82#define BCS_512K 3
 83#define BCS_1M 4
 84#define BCS_2M 5
 85
46#define LCA_IOC_HAE LCA_IOC_BASE /* Host Address Ext. (64) */ 86#define LCA_IOC_HAE LCA_IOC_BASE /* Host Address Ext. (64) */
47#define IOC_HAE_ADDREXT 0x00000000f8000000UL 87#define IOC_HAE_ADDREXT 0x00000000f8000000UL
48#define IOC_HAE_RSVSD 0xffffffff07ffffffUL 88#define IOC_HAE_RSVSD 0xffffffff07ffffffUL
49 89
50#define LCA_IOC_CONF (LCA_IOC_BASE + 0x020) /* Configuration Cycle Type */ 90#define LCA_IOC_CONF (LCA_IOC_BASE + 0x020) /* Configuration Cycle Type */
51 91
52#define LCA_IOC_STAT0 (LCA_IOC_BASE + 0x040) /* Status 0 */ 92#define LCA_IOC_STAT0 (LCA_IOC_BASE + 0x040) /* Status 0 */
53#define IOC_STAT0_CMD 0x000000000000000fUL /* PCI command mask */ 93#define IOC_STAT0_CMD 0x000000000000000fUL /* PCI command mask */
54#define IOC_STAT0_ERR 0x0000000000000010UL /* IOC error indicator R/W1C */ 94#define IOC_STAT0_ERR 0x0000000000000010UL /* IOC error indicator R/W1C */
55#define IOC_STAT0_LOST 0x0000000000000020UL /* IOC lose error info R/W1C */ 95#define IOC_STAT0_LOST 0x0000000000000020UL /* IOC lose error info R/W1C */
56#define IOC_STAT0_THIT 0x0000000000000040UL /* test hit */ 96#define IOC_STAT0_THIT 0x0000000000000040UL /* test hit */
57#define IOC_STAT0_TREF 0x0000000000000080UL /* test reference */ 97#define IOC_STAT0_TREF 0x0000000000000080UL /* test reference */
58#define IOC_STAT0_CODE 0x0000000000000700UL /* code mask */ 98#define IOC_STAT0_CODE 0x0000000000000700UL /* code mask */