Sun Oct 10 08:36:49 2021 UTC ()
Add a placeholder for PRRR


(skrll)
diff -r1.131 -r1.132 src/sys/arch/arm/include/armreg.h
cvs diff -r1.131 -r1.132 src/sys/arch/arm/include/armreg.h (expand / switch to unified diff)

--- src/sys/arch/arm/include/armreg.h 2021/09/03 21:55:00 1.131
+++ src/sys/arch/arm/include/armreg.h 2021/10/10 08:36:49 1.132
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: armreg.h,v 1.131 2021/09/03 21:55:00 andvar Exp $ */ 1/* $NetBSD: armreg.h,v 1.132 2021/10/10 08:36:49 skrll Exp $ */
2 2
3/* 3/*
4 * Copyright (c) 1998, 2001 Ben Harris 4 * Copyright (c) 1998, 2001 Ben Harris
5 * Copyright (c) 1994-1996 Mark Brinicombe. 5 * Copyright (c) 1994-1996 Mark Brinicombe.
6 * Copyright (c) 1994 Brini. 6 * Copyright (c) 1994 Brini.
7 * All rights reserved. 7 * All rights reserved.
8 * 8 *
9 * This code is derived from software written for Brini by Mark Brinicombe 9 * This code is derived from software written for Brini by Mark Brinicombe
10 * 10 *
11 * Redistribution and use in source and binary forms, with or without 11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions 12 * modification, are permitted provided that the following conditions
13 * are met: 13 * are met:
14 * 1. Redistributions of source code must retain the above copyright 14 * 1. Redistributions of source code must retain the above copyright
@@ -528,26 +528,27 @@ @@ -528,26 +528,27 @@
528#define NMRR_NC 0 // non-cacheable 528#define NMRR_NC 0 // non-cacheable
529#define NMRR_WBWA 1 // write-back write-allocate 529#define NMRR_WBWA 1 // write-back write-allocate
530#define NMRR_WT 2 // write-through 530#define NMRR_WT 2 // write-through
531#define NMRR_WB 3 // write-back 531#define NMRR_WB 3 // write-back
532#define PRRR_NOSn(n) __BITS(24+(n)) // Memory region is Inner Shareable only 532#define PRRR_NOSn(n) __BITS(24+(n)) // Memory region is Inner Shareable only
533#define PRRR_NS1 __BIT(19) // Normal Shareable S=1 is Shareable 533#define PRRR_NS1 __BIT(19) // Normal Shareable S=1 is Shareable
534#define PRRR_NS0 __BIT(18) // Normal Shareable S=0 is Shareable 534#define PRRR_NS0 __BIT(18) // Normal Shareable S=0 is Shareable
535#define PRRR_DS1 __BIT(17) // Device Shareable S=1 is Shareable 535#define PRRR_DS1 __BIT(17) // Device Shareable S=1 is Shareable
536#define PRRR_DS0 __BIT(16) // Device Shareable S=0 is Shareable 536#define PRRR_DS0 __BIT(16) // Device Shareable S=0 is Shareable
537#define PRRR_TRn(n) __BITS(1+2*(n),0+2*(n)) 537#define PRRR_TRn(n) __BITS(1+2*(n),0+2*(n))
538#define PRRR_TR_STRONG 0 // Strongly Ordered 538#define PRRR_TR_STRONG 0 // Strongly Ordered
539#define PRRR_TR_DEVICE 1 // Device 539#define PRRR_TR_DEVICE 1 // Device
540#define PRRR_TR_NORMAL 2 // Normal Memory 540#define PRRR_TR_NORMAL 2 // Normal Memory
 541 // 3 is reserved
541 542
542/* ARMv7 MPIDR, Multiprocessor Affinity Register generic format */ 543/* ARMv7 MPIDR, Multiprocessor Affinity Register generic format */
543#define MPIDR_MP __BIT(31) /* 1 = Have MP Extension */ 544#define MPIDR_MP __BIT(31) /* 1 = Have MP Extension */
544#define MPIDR_U __BIT(30) /* 1 = Uni-Processor System */ 545#define MPIDR_U __BIT(30) /* 1 = Uni-Processor System */
545#define MPIDR_MT __BIT(24) /* 1 = SMT(AFF0 is logical) */ 546#define MPIDR_MT __BIT(24) /* 1 = SMT(AFF0 is logical) */
546#define MPIDR_AFF2 __BITS(23,16) /* Affinity Level 2 */ 547#define MPIDR_AFF2 __BITS(23,16) /* Affinity Level 2 */
547#define MPIDR_AFF1 __BITS(15,8) /* Affinity Level 1 */ 548#define MPIDR_AFF1 __BITS(15,8) /* Affinity Level 1 */
548#define MPIDR_AFF0 __BITS(7,0) /* Affinity Level 0 */ 549#define MPIDR_AFF0 __BITS(7,0) /* Affinity Level 0 */
549 550
550/* MPIDR implementation of ARM Cortex A9: SMT and AFF2 is not used */ 551/* MPIDR implementation of ARM Cortex A9: SMT and AFF2 is not used */
551#define CORTEXA9_MPIDR_MP MPIDR_MP 552#define CORTEXA9_MPIDR_MP MPIDR_MP
552#define CORTEXA9_MPIDR_U MPIDR_U 553#define CORTEXA9_MPIDR_U MPIDR_U
553#define CORTEXA9_MPIDR_CLID __BITS(11,8) /* AFF1 = cluster id */ 554#define CORTEXA9_MPIDR_CLID __BITS(11,8) /* AFF1 = cluster id */