Thu Oct 21 06:06:16 2021 UTC ()
fix gimplish


(skrll)
diff -r1.80 -r1.81 src/sys/arch/aarch64/aarch64/locore.S
cvs diff -r1.80 -r1.81 src/sys/arch/aarch64/aarch64/locore.S (expand / switch to unified diff)

--- src/sys/arch/aarch64/aarch64/locore.S 2021/09/30 21:19:16 1.80
+++ src/sys/arch/aarch64/aarch64/locore.S 2021/10/21 06:06:16 1.81
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: locore.S,v 1.80 2021/09/30 21:19:16 skrll Exp $ */ 1/* $NetBSD: locore.S,v 1.81 2021/10/21 06:06:16 skrll Exp $ */
2 2
3/* 3/*
4 * Copyright (c) 2017 Ryo Shimizu <ryo@nerv.org> 4 * Copyright (c) 2017 Ryo Shimizu <ryo@nerv.org>
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * Redistribution and use in source and binary forms, with or without 7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions 8 * modification, are permitted provided that the following conditions
9 * are met: 9 * are met:
10 * 1. Redistributions of source code must retain the above copyright 10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer. 11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright 12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the 13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution. 14 * documentation and/or other materials provided with the distribution.
@@ -28,27 +28,27 @@ @@ -28,27 +28,27 @@
28 28
29#include "opt_arm_debug.h" 29#include "opt_arm_debug.h"
30#include "opt_console.h" 30#include "opt_console.h"
31#include "opt_cpuoptions.h" 31#include "opt_cpuoptions.h"
32#include "opt_ddb.h" 32#include "opt_ddb.h"
33#include "opt_fdt.h" 33#include "opt_fdt.h"
34#include "opt_kasan.h" 34#include "opt_kasan.h"
35#include "opt_multiprocessor.h" 35#include "opt_multiprocessor.h"
36 36
37#include <aarch64/asm.h> 37#include <aarch64/asm.h>
38#include <aarch64/hypervisor.h> 38#include <aarch64/hypervisor.h>
39#include "assym.h" 39#include "assym.h"
40 40
41RCSID("$NetBSD: locore.S,v 1.80 2021/09/30 21:19:16 skrll Exp $") 41RCSID("$NetBSD: locore.S,v 1.81 2021/10/21 06:06:16 skrll Exp $")
42 42
43#ifdef AARCH64_DEVICE_MEM_STRONGLY_ORDERED 43#ifdef AARCH64_DEVICE_MEM_STRONGLY_ORDERED
44#define MAIR_DEVICE_MEM MAIR_DEVICE_nGnRnE 44#define MAIR_DEVICE_MEM MAIR_DEVICE_nGnRnE
45#else 45#else
46#define MAIR_DEVICE_MEM MAIR_DEVICE_nGnRE 46#define MAIR_DEVICE_MEM MAIR_DEVICE_nGnRE
47#endif 47#endif
48#define MAIR_DEVICE_MEM_SO MAIR_DEVICE_nGnRnE 48#define MAIR_DEVICE_MEM_SO MAIR_DEVICE_nGnRnE
49 49
50/*#define DEBUG_LOCORE // debug print */ 50/*#define DEBUG_LOCORE // debug print */
51/*#define DEBUG_LOCORE_PRINT_LOCK // avoid mixing AP's output */ 51/*#define DEBUG_LOCORE_PRINT_LOCK // avoid mixing AP's output */
52 52
53#define LOCORE_EL2 53#define LOCORE_EL2
54 54
@@ -470,27 +470,27 @@ mp_vstart: @@ -470,27 +470,27 @@ mp_vstart:
470 hint 0x24 /* bti j */ 470 hint 0x24 /* bti j */
471 471
472 CPU_DPRINTREG("PC = ", x20) 472 CPU_DPRINTREG("PC = ", x20)
473 CPU_DPRINTREG("SP = ", sp) 473 CPU_DPRINTREG("SP = ", sp)
474 474
475 CPU_DPRINTSREG("TTBR0 = ", ttbr0_el1) 475 CPU_DPRINTSREG("TTBR0 = ", ttbr0_el1)
476 CPU_DPRINTSREG("TTBR1 = ", ttbr1_el1) 476 CPU_DPRINTSREG("TTBR1 = ", ttbr1_el1)
477 477
478 /* Set SP to VA */ 478 /* Set SP to VA */
479 adrl x0, kern_vtopdiff 479 adrl x0, kern_vtopdiff
480 ldr x0, [x0] 480 ldr x0, [x0]
481 add sp, sp, x0 481 add sp, sp, x0
482 482
483 /* stop using TTBR0 - CPU_DPRINT{,REG,SREG} no longer after this */ 483 /* disable TTBR0 - CPU_DPRINT{,REG,SREG} no longer work after this */
484 mrs x0, tcr_el1 484 mrs x0, tcr_el1
485 orr x0, x0, #TCR_EPD0 485 orr x0, x0, #TCR_EPD0
486 msr tcr_el1, x0 486 msr tcr_el1, x0
487 isb 487 isb
488 488
489 tlbi vmalle1is 489 tlbi vmalle1is
490 dsb ish 490 dsb ish
491 isb 491 isb
492 492
493 /* set exception vector */ 493 /* set exception vector */
494 adrl x0, _C_LABEL(el1_vectors) 494 adrl x0, _C_LABEL(el1_vectors)
495 msr vbar_el1, x0 495 msr vbar_el1, x0
496 496