Thu Nov 11 07:26:41 2021 UTC ()
Trailing whitespace


(skrll)
diff -r1.16 -r1.17 src/sys/arch/arm/arm/cpufunc_asm.S
cvs diff -r1.16 -r1.17 src/sys/arch/arm/arm/cpufunc_asm.S (expand / switch to unified diff)

--- src/sys/arch/arm/arm/cpufunc_asm.S 2013/08/18 06:28:18 1.16
+++ src/sys/arch/arm/arm/cpufunc_asm.S 2021/11/11 07:26:41 1.17
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: cpufunc_asm.S,v 1.16 2013/08/18 06:28:18 matt Exp $ */ 1/* $NetBSD: cpufunc_asm.S,v 1.17 2021/11/11 07:26:41 skrll Exp $ */
2 2
3/* 3/*
4 * Copyright (c) 1997,1998 Mark Brinicombe. 4 * Copyright (c) 1997,1998 Mark Brinicombe.
5 * Copyright (c) 1997 Causality Limited 5 * Copyright (c) 1997 Causality Limited
6 * All rights reserved. 6 * All rights reserved.
7 * 7 *
8 * Redistribution and use in source and binary forms, with or without 8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions 9 * modification, are permitted provided that the following conditions
10 * are met: 10 * are met:
11 * 1. Redistributions of source code must retain the above copyright 11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer. 12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright 13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the 14 * notice, this list of conditions and the following disclaimer in the
@@ -24,33 +24,33 @@ @@ -24,33 +24,33 @@
24 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT, 26 * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT,
27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * SUCH DAMAGE. 33 * SUCH DAMAGE.
34 * 34 *
35 * RiscBSD kernel project 35 * RiscBSD kernel project
36 * 36 *
37 * cpufunc.S  37 * cpufunc.S
38 * 38 *
39 * Assembly functions for CPU / MMU / TLB specific operations 39 * Assembly functions for CPU / MMU / TLB specific operations
40 * 40 *
41 * Created : 30/01/97 41 * Created : 30/01/97
42 */ 42 */
43  43
44#include <arm/armreg.h> 44#include <arm/armreg.h>
45#include <machine/asm.h> 45#include <machine/asm.h>
46 46
47 .text 47 .text
48 .align 0 48 .align 0
49 49
50ENTRY(cpufunc_nullop) 50ENTRY(cpufunc_nullop)
51 RET 51 RET
52END(cpufunc_nullop) 52END(cpufunc_nullop)
53 53
54/* 54/*
55 * Generic functions to read the internal coprocessor registers 55 * Generic functions to read the internal coprocessor registers
56 * 56 *
@@ -81,54 +81,54 @@ ENTRY(cpufunc_faultstatus) @@ -81,54 +81,54 @@ ENTRY(cpufunc_faultstatus)
81 RET 81 RET
82END(cpufunc_faultstatus) 82END(cpufunc_faultstatus)
83 83
84ENTRY(cpufunc_faultaddress) 84ENTRY(cpufunc_faultaddress)
85 mrc p15, 0, r0, c6, c0, 0 85 mrc p15, 0, r0, c6, c0, 0
86 RET 86 RET
87END(cpufunc_faultaddress) 87END(cpufunc_faultaddress)
88 88
89 89
90/* 90/*
91 * Generic functions to write the internal coprocessor registers 91 * Generic functions to write the internal coprocessor registers
92 * 92 *
93 * 93 *
94 * Currently these registers are  94 * Currently these registers are
95 * c1 - CPU Control 95 * c1 - CPU Control
96 * c3 - Domain Access Control 96 * c3 - Domain Access Control
97 * 97 *
98 * All other registers are CPU architecture specific 98 * All other registers are CPU architecture specific
99 */ 99 */
100  100
101#if 0 /* See below. */ 101#if 0 /* See below. */
102ENTRY(cpufunc_control) 102ENTRY(cpufunc_control)
103 mcr p15, 0, r0, c1, c0, 0 103 mcr p15, 0, r0, c1, c0, 0
104 RET 104 RET
105#endif 105#endif
106 106
107ENTRY(cpufunc_domains) 107ENTRY(cpufunc_domains)
108 mcr p15, 0, r0, c3, c0, 0 108 mcr p15, 0, r0, c3, c0, 0
109 RET 109 RET
110END(cpufunc_domains) 110END(cpufunc_domains)
111 111
112/* 112/*
113 * Generic functions to read/modify/write the internal coprocessor registers 113 * Generic functions to read/modify/write the internal coprocessor registers
114 * 114 *
115 * 115 *
116 * Currently these registers are  116 * Currently these registers are
117 * c1 - CPU Control 117 * c1 - CPU Control
118 * 118 *
119 * All other registers are CPU architecture specific 119 * All other registers are CPU architecture specific
120 */ 120 */
121  121
122ENTRY(cpufunc_control) 122ENTRY(cpufunc_control)
123 mrc p15, 0, r3, c1, c0, 0 /* Read the control register */ 123 mrc p15, 0, r3, c1, c0, 0 /* Read the control register */
124 bics r2, r3, r0 /* Clear bits */ 124 bics r2, r3, r0 /* Clear bits */
125 eors r2, r2, r1 /* XOR bits */ 125 eors r2, r2, r1 /* XOR bits */
126 126
127 teq r2, r3 /* Only write if there is a change */ 127 teq r2, r3 /* Only write if there is a change */
128#ifdef __thumb__ 128#ifdef __thumb__
129 it ne 129 it ne
130#endif 130#endif
131 mcrne p15, 0, r2, c1, c0, 0 /* Write new control register */ 131 mcrne p15, 0, r2, c1, c0, 0 /* Write new control register */
132 movs r0, r3 /* Return old value */ 132 movs r0, r3 /* Return old value */
133 RET 133 RET
134END(cpufunc_control) 134END(cpufunc_control)