 @@ -1,14 +1,14 @@
-#	$NetBSD: files,v 1.1289 2021/10/11 13:42:33 jmcneill Exp $
+#	$NetBSD: files,v 1.1290 2021/11/19 23:46:54 rin Exp $
 #	@(#)files.newconf	7.5 (Berkeley) 5/10/93
 version 	20171118
+#
 # device classes
+#
 devclass disk
 devclass tape
 devclass ifnet
 devclass tty
 devclass audiodev
 devclass displaydev
 @@ -1026,26 +1026,27 @@ defparam opt_ata.h	ATADEBUG_MASK
 defflag opt_wdc.h	WDC_NO_IDS
 device	atabus: atapi,ata_hl
 attach	atabus at ata
 # The strange expression is to dump ata_* definitions to ata_dma.h.
 file	dev/ic/wdc.c			(ata_dma | ata_udma | ata_piobm | atabus) & atabus & wdc_common	needs-flag
 # Workbit NinjaATA-32 IDE controllers
 device	njata: ata, ata_piobm, wdc_common
 file	dev/ic/ninjaata32.c		njata
 # AHCI-compatible SATA controllers
 defflag	opt_ahcisata.h	AHCISATA_EXTRA_DELAY
 defparam opt_ahcisata.h	AHCISATA_EXTRA_DELAY_MS
 define ahcisata_core
 file dev/ic/ahcisata_core.c ahcisata_core
 device ahcisata: ata, ata_dma, ata_udma, sata, sata_fis, sata_pmp, ahcisata_core
 # Silicon Image SteelVine SATA-II controllers
 define	siisata
 file	dev/ic/siisata.c		siisata
 device	siisata: ata, ata_dma, ata_udma, sata, sata_fis, sata_pmp, siisata
 # Marvell Serial-ATA Host Controller
 define mvsata
 file dev/ic/mvsata.c			mvsata
 device mvsata: ata, ata_dma, ata_udma, wdc_common, sata, sata_fis, sata_pmp, mvsata

 @@ -1,14 +1,14 @@
-/*	$NetBSD: ahcisata_core.c,v 1.104 2021/11/10 17:19:30 msaitoh Exp $	*/
+/*	$NetBSD: ahcisata_core.c,v 1.105 2021/11/19 23:46:55 rin Exp $	*/
 /*
  * Copyright (c) 2006 Manuel Bouyer.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
 @@ -16,27 +16,27 @@
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: ahcisata_core.c,v 1.104 2021/11/10 17:19:30 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: ahcisata_core.c,v 1.105 2021/11/19 23:46:55 rin Exp $");
 #include <sys/types.h>
 #include <sys/malloc.h>
 #include <sys/param.h>
 #include <sys/kernel.h>
 #include <sys/systm.h>
 #include <sys/disklabel.h>
 #include <sys/proc.h>
 #include <sys/buf.h>
 #include <dev/ata/atareg.h>
 #include <dev/ata/satavar.h>
 #include <dev/ata/satareg.h>
 @@ -105,26 +105,41 @@ static const struct scsipi_bustype ahci_
 	.bustype_type = SCSIPI_BUSTYPE_ATAPI,
 	.bustype_cmd = atapi_scsipi_cmd,
 	.bustype_interpret_sense = atapi_interpret_sense,
 	.bustype_printaddr = atapi_print_addr,
 	.bustype_kill_pending = ahci_atapi_kill_pending,
 	.bustype_async_event_xfer_mode = NULL,
 };
 #endif /* NATAPIBUS */
 #define ATA_DELAY 10000 /* 10s for a drive I/O */
 #define ATA_RESET_DELAY 31000 /* 31s for a drive reset */
 #define AHCI_RST_WAIT (ATA_RESET_DELAY / 10)
 #ifndef AHCISATA_EXTRA_DELAY_MS
 #define	AHCISATA_EXTRA_DELAY_MS	500	/* XXX need to adjust */
 #endif
 #ifdef AHCISATA_EXTRA_DELAY
 #define	AHCISATA_DO_EXTRA_DELAY(sc, chp, msg, flags)			\
     ata_delay(chp, AHCISATA_EXTRA_DELAY_MS, msg, flags)
 #else
 #define	AHCISATA_DO_EXTRA_DELAY(sc, chp, msg, flags)			\
     do {								\
 	if ((sc)->sc_ahci_quirks & AHCI_QUIRK_EXTRA_DELAY)		\
 		ata_delay(chp, AHCISATA_EXTRA_DELAY_MS, msg, flags);	\
     } while (0)
 #endif
 const struct ata_bustype ahci_ata_bustype = {
 	.bustype_type = SCSIPI_BUSTYPE_ATA,
 	.ata_bio = ahci_ata_bio,
 	.ata_reset_drive = ahci_reset_drive,
 	.ata_reset_channel = ahci_reset_channel,
 	.ata_exec_command = ahci_exec_command,
 	.ata_get_params = ata_get_params,
 	.ata_addref = ahci_ata_addref,
 	.ata_delref = ahci_ata_delref,
 	.ata_killpending = ahci_killpending,
 	.ata_recovery = ahci_channel_recover,
 };
 @@ -960,55 +975,51 @@ again:
 		    AHCINAME(sc), sig);
 		goto end;
+	}
 	AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10),
 	    DEBUG_PROBE);
 	sig = AHCI_READ(sc, AHCI_P_SIG(chp->ch_channel));
 	if (sigp)
 		*sigp = sig;
 	AHCIDEBUG_PRINT(("%s: port %d: sig=0x%x CMD=0x%x\n",
 	    AHCINAME(sc), chp->ch_channel, sig,
 	    AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel))), DEBUG_PROBE);
 end:
 	ahci_channel_stop(sc, chp, flags);
-#ifdef AHCISATA_EXTRA_DELAY
+	AHCISATA_DO_EXTRA_DELAY(sc, chp, "ahcirst", flags);
 	ata_delay(chp, 500, "ahcirst", flags);
 #endif
 	/* clear port interrupt register */
 	AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff);
 	ahci_channel_start(sc, chp, flags,
 	    (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0);
 	return error;
+}
 static void
 ahci_reset_channel(struct ata_channel *chp, int flags)
+{
 	struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
 	struct ahci_channel *achp = (struct ahci_channel *)chp;
 	int i, tfd;
 	ata_channel_lock_owned(chp);
 	ahci_channel_stop(sc, chp, flags);
 	if (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol,
 	    achp->ahcic_sstatus, flags) != SStatus_DET_DEV) {
 		printf("%s: port %d reset failed\n", AHCINAME(sc), chp->ch_channel);
 		/* XXX and then ? */
+	}
 	ata_kill_active(chp, KILL_RESET, flags);
-#ifdef AHCISATA_EXTRA_DELAY
+	AHCISATA_DO_EXTRA_DELAY(sc, chp, "ahcirst", flags);
 	ata_delay(chp, 500, "ahcirst", flags);
 #endif
 	/* clear port interrupt register */
 	AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff);
 	/* clear SErrors and start operations */
 	ahci_channel_start(sc, chp, flags,
 	    (sc->sc_ahci_cap & AHCI_CAP_CLO) ? 1 : 0);
 	/* wait 31s for BSY to clear */
 	for (i = 0; i < AHCI_RST_WAIT; i++) {
 		tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel));
 		if ((AHCI_TFD_ST(tfd) & WDCS_BSY) == 0)
 			break;
 		ata_delay(chp, 10, "ahcid2h", flags);
+	}
 	if ((AHCI_TFD_ST(tfd) & WDCS_BSY) != 0)
 @@ -1058,29 +1069,27 @@ ahci_probe_drive(struct ata_channel *chp
 		    __func__, chp->ch_channel);
 		ata_channel_unlock(chp);
 		return;
+	}
 	/* bring interface up, accept FISs, power up and spin up device */
 	AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel),
 	    AHCI_P_CMD_ICC_AC | AHCI_P_CMD_FRE |
 	    AHCI_P_CMD_POD | AHCI_P_CMD_SUD);
 	/* reset the PHY and bring online */
 	switch (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol,
 	    achp->ahcic_sstatus, AT_WAIT)) {
 	case SStatus_DET_DEV:
-#ifdef AHCISATA_EXTRA_DELAY
+		AHCISATA_DO_EXTRA_DELAY(sc, chp, "ahcidv", AT_WAIT);
 		ata_delay(chp, 500, "ahcidv", AT_WAIT);
 #endif
 		/* Initial value, used in case the soft reset fails */
 		sig = AHCI_READ(sc, AHCI_P_SIG(chp->ch_channel));
 		if (sc->sc_ahci_cap & AHCI_CAP_SPM) {
 			error = ahci_do_reset_drive(chp, PMP_PORT_CTL, AT_WAIT,
 			    &sig, c_slot);
 			/* If probe for PMP failed, just fallback to drive 0 */
 			if (error) {
 				aprint_error("%s port %d: drive %d reset "
 				    "failed, disabling PMP\n",
 				    AHCINAME(sc), chp->ch_channel,
 @@ -1099,30 +1108,31 @@ ahci_probe_drive(struct ata_channel *chp
 			AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel),
 			    AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) |
 			    AHCI_P_CMD_PMA);
+		}
 		/* clear port interrupt register */
 		AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff);
 		/* and enable interrupts */
 		AHCI_WRITE(sc, AHCI_P_IE(chp->ch_channel),
 		    AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_HBDS |
 		    AHCI_P_IX_IFS |
 		    AHCI_P_IX_OFS | AHCI_P_IX_DPS | AHCI_P_IX_UFS |
 		    AHCI_P_IX_PSS | AHCI_P_IX_DHRS | AHCI_P_IX_SDBS);
-#ifdef AHCISATA_EXTRA_DELAY
+		/*
-		/* wait 500ms before actually starting operations */
+		 * optionally, wait AHCISATA_EXTRA_DELAY_MS msec before
-		ata_delay(chp, 500, "ahciprb", AT_WAIT);
+		 * actually starting operations
-#endif
+		 */
 		AHCISATA_DO_EXTRA_DELAY(sc, chp, "ahciprb", AT_WAIT);
 		break;
 	default:
 		break;
+	}
 	ata_queue_free_slot(chp, c_slot);
 	ata_channel_unlock(chp);
+}
 static void
 ahci_setup_channel(struct ata_channel *chp)

 @@ -1,14 +1,14 @@
-/*	$NetBSD: ahcisatavar.h,v 1.26 2020/12/28 14:08:42 jmcneill Exp $	*/
+/*	$NetBSD: ahcisatavar.h,v 1.27 2021/11/19 23:46:55 rin Exp $	*/
 /*
  * Copyright (c) 2006 Manuel Bouyer.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
 @@ -49,26 +49,27 @@ struct ahci_softc {
 	bus_space_handle_t sc_ahcih;
 	bus_size_t sc_ahcis;
 	bus_dma_tag_t sc_dmat; /* DMA memory mappings: */
 	void *sc_cmd_hdr; /* command tables and received FIS */
 	bus_dmamap_t sc_cmd_hdrd;
 	bus_dma_segment_t sc_cmd_hdr_seg;
 	int sc_cmd_hdr_nseg;
 	int sc_atac_capflags;
 	int sc_ahci_quirks;
 #define AHCI_PCI_QUIRK_FORCE	__BIT(0)  /* force attach */
 #define AHCI_PCI_QUIRK_BAD64	__BIT(1)  /* broken 64-bit DMA */
 #define AHCI_QUIRK_BADPMP	__BIT(2)  /* broken PMP support, ignore */
 #define AHCI_QUIRK_BADNCQ	__BIT(3)  /* possibly broken NCQ support, ignore */
 #define AHCI_QUIRK_EXTRA_DELAY	__BIT(4)  /* needs extra delay */
 	uint32_t sc_ahci_cap;	/* copy of AHCI_CAP */
 	int sc_ncmds; /* number of command slots */
 	uint32_t sc_ahci_ports;
 	struct ata_channel *sc_chanarray[AHCI_MAX_PORTS];
 	struct ahci_channel {
 		struct ata_channel ata_channel; /* generic part */
 		bus_space_handle_t ahcic_scontrol;
 		bus_space_handle_t ahcic_sstatus;
 		bus_space_handle_t ahcic_serror;
 		/* pointers allocated from sc_cmd_hdrd */
 		struct ahci_r_fis *ahcic_rfis; /* received FIS */
 		bus_addr_t ahcic_bus_rfis;

 @@ -1,14 +1,14 @@
-/*	$NetBSD: ahcisata_pci.c,v 1.60 2021/11/12 07:06:06 skrll Exp $	*/
+/*	$NetBSD: ahcisata_pci.c,v 1.61 2021/11/19 23:46:55 rin Exp $	*/
 /*
  * Copyright (c) 2006 Manuel Bouyer.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
 @@ -16,27 +16,27 @@
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: ahcisata_pci.c,v 1.60 2021/11/12 07:06:06 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: ahcisata_pci.c,v 1.61 2021/11/19 23:46:55 rin Exp $");
 #ifdef _KERNEL_OPT
 #include "opt_ahcisata_pci.h"
 #endif
 #include <sys/types.h>
 #include <sys/kmem.h>
 #include <sys/param.h>
 #include <sys/kernel.h>
 #include <sys/systm.h>
 #include <sys/disklabel.h>
 #include <sys/pmf.h>
 @@ -194,26 +194,45 @@ static const struct ahci_pci_quirk ahci_
 	    AHCI_PCI_QUIRK_FORCE },
 	{ PCI_VENDOR_ASMEDIA, PCI_PRODUCT_ASMEDIA_ASM1061_02,
 	    AHCI_PCI_QUIRK_FORCE },
 	{ PCI_VENDOR_ASMEDIA, PCI_PRODUCT_ASMEDIA_ASM1061_11,
 	    AHCI_PCI_QUIRK_FORCE },
 	{ PCI_VENDOR_ASMEDIA, PCI_PRODUCT_ASMEDIA_ASM1061_12,
 	    AHCI_PCI_QUIRK_FORCE },
 	{ PCI_VENDOR_AMD, PCI_PRODUCT_AMD_HUDSON_SATA,
 	    AHCI_PCI_QUIRK_FORCE },
 	{ PCI_VENDOR_AMD, PCI_PRODUCT_AMD_HUDSON_SATA_AHCI,
 	    AHCI_QUIRK_BADPMP },
 	{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JI_SATA_AHCI,
 	    AHCI_QUIRK_BADPMP },
 	{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C600_AHCI,
 	    AHCI_QUIRK_EXTRA_DELAY },
 #if 0
 	/*
 	 * XXX Non-reproducible failures reported. May need extra-delay quirk.
 	 */
 	{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_BAYTRAIL_SATA_AHCI_0,
 	    AHCI_QUIRK_EXTRA_DELAY },
 	{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_BAYTRAIL_SATA_AHCI_1,
 	    AHCI_QUIRK_EXTRA_DELAY },
 	{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_SATA_4,
 	    AHCI_QUIRK_EXTRA_DELAY },
 	{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_SATA_5,
 	    AHCI_QUIRK_EXTRA_DELAY },
 	{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_SATA_6,
 	    AHCI_QUIRK_EXTRA_DELAY },
 	{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_SATA_7,
 	    AHCI_QUIRK_EXTRA_DELAY },
 #endif
 };
 struct ahci_pci_softc {
 	struct ahci_softc ah_sc;
 	pci_chipset_tag_t sc_pc;
 	pcitag_t sc_pcitag;
 	pci_intr_handle_t *sc_pihp;
 	int sc_nintr;
 	void **sc_ih;
 };
 static int  ahci_pci_has_quirk(pci_vendor_id_t, pci_product_id_t);
 static int  ahci_pci_match(device_t, cfdata_t, void *);