Wed Nov 24 00:22:00 2021 UTC ()

Teach the LLVM-derived unwinder about the DWARF pseudo-registers defined
by GCC for SuperH for GBR, MACH, MACL, and SR.


(thorpej)

diff -r1.36 -r1.37 src/sys/lib/libunwind/Registers.hpp

--- src/sys/lib/libunwind/Registers.hpp 2021/11/22 16:41:00	1.36
+++ src/sys/lib/libunwind/Registers.hpp 2021/11/24 00:21:59	1.37

 @@ -645,56 +645,76 @@ public:
 private:
   typedef uint32_t fpreg_t[3];
   uint32_t reg[REGNO_M68K_PC + 1];
   uint32_t dummy;
   fpreg_t fpreg[8];
 };
 enum {
   DWARF_SH3_R0 = 0,
   DWARF_SH3_R15 = 15,
   DWARF_SH3_PC = 16,
   DWARF_SH3_PR = 17,
   DWARF_SH3_GBR = 18,
   DWARF_SH3_MACH = 20,
   DWARF_SH3_MACL = 21,
   DWARF_SH3_SR = 22,
   REGNO_SH3_R0 = 0,
   REGNO_SH3_R15 = 15,
   REGNO_SH3_PC = 16,
   REGNO_SH3_PR = 17,
   REGNO_SH3_GBR = 18,
   REGNO_SH3_MACH = 20,
   REGNO_SH3_MACL = 21,
   REGNO_SH3_SR = 22,
 };
 class Registers_SH3 {
 public:
   enum {
-    LAST_REGISTER = REGNO_SH3_PR,
+    LAST_REGISTER = REGNO_SH3_SR,
-    LAST_RESTORE_REG = REGNO_SH3_PR,
+    LAST_RESTORE_REG = REGNO_SH3_SR,
     RETURN_OFFSET = 0,
     RETURN_MASK = 0,
   };
   __dso_hidden Registers_SH3();
   static int dwarf2regno(int num) {
     if (num >= DWARF_SH3_R0 && num <= DWARF_SH3_R15)
       return REGNO_SH3_R0 + (num - DWARF_SH3_R0);
-    if (num == DWARF_SH3_PC)
+    switch (num) {
     case DWARF_SH3_PC:
       return REGNO_SH3_PC;
-    if (num == DWARF_SH3_PR)
+    case DWARF_SH3_PR:
       return REGNO_SH3_PR;
-    return LAST_REGISTER + 1;
+    case DWARF_SH3_GBR:
       return REGNO_SH3_GBR;
     case DWARF_SH3_MACH:
       return REGNO_SH3_MACH;
     case DWARF_SH3_MACL:
       return REGNO_SH3_MACL;
     case DWARF_SH3_SR:
       return REGNO_SH3_SR;
     default:
       return LAST_REGISTER + 1;
+    }
+  }
   bool validRegister(int num) const {
-    return num >= 0 && num <= REGNO_SH3_PR;
+    return (num >= 0 && num <= REGNO_SH3_GBR) ||
 	(num >= REGNO_SH3_MACH && num <= REGNO_SH3_SR);
+  }
   uint64_t getRegister(int num) const {
     assert(validRegister(num));
     return reg[num];
+  }
   void setRegister(int num, uint64_t value) {
     assert(validRegister(num));
     reg[num] = value;
+  }
   uint64_t getIP() const { return reg[REGNO_SH3_PC]; }
 @@ -702,27 +722,27 @@ public:
   void setIP(uint64_t value) { reg[REGNO_SH3_PC] = value; }
   uint64_t getSP() const { return reg[REGNO_SH3_R15]; }
   void setSP(uint64_t value) { reg[REGNO_SH3_R15] = value; }
   bool validFloatVectorRegister(int num) const { return false; }
   void copyFloatVectorRegister(int num, uint64_t addr_) {}
   __dso_hidden void jumpto() const __dead;
 private:
-  uint32_t reg[REGNO_SH3_PR + 1];
+  uint32_t reg[REGNO_SH3_SR + 1];
 };
 enum {
   DWARF_SPARC64_R0 = 0,
   DWARF_SPARC64_R31 = 31,
   DWARF_SPARC64_PC = 32,
   REGNO_SPARC64_R0 = 0,
   REGNO_SPARC64_R14 = 14,
   REGNO_SPARC64_R15 = 15,
   REGNO_SPARC64_R31 = 31,
   REGNO_SPARC64_PC = 32,
 };