 @@ -1,14 +1,14 @@
-/*	$NetBSD: i915_irq.c,v 1.20 2021/12/18 23:45:28 riastradh Exp $	*/
+/*	$NetBSD: i915_irq.c,v 1.21 2021/12/19 01:43:37 riastradh Exp $	*/
 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
  */
 /*
  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
  * All Rights Reserved.
+ *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the
  * "Software"), to deal in the Software without restriction, including
  * without limitation the rights to use, copy, modify, merge, publish,
  * distribute, sub license, and/or sell copies of the Software, and to
  * permit persons to whom the Software is furnished to do so, subject to
 @@ -19,27 +19,27 @@
  * of the Software.
+ *
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: i915_irq.c,v 1.20 2021/12/18 23:45:28 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: i915_irq.c,v 1.21 2021/12/19 01:43:37 riastradh Exp $");
 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 #include <linux/circ_buf.h>
 #include <linux/slab.h>
 #include <linux/sysrq.h>
 #include <drm/drm_drv.h>
 #include <drm/drm_irq.h>
 #include <drm/i915_drm.h>
 #include "display/intel_display_types.h"
 #include "display/intel_fifo_underrun.h"
 @@ -2401,68 +2401,66 @@ static inline u32 gen8_master_intr_disab
 	 * and will generate new interrupt after enabling master.
 	 */
 	return raw_reg_read(regs, GEN8_MASTER_IRQ);
+}
 static inline void gen8_master_intr_enable(void __iomem * const regs)
+{
 	raw_reg_write(regs, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
+}
 static irqreturn_t gen8_irq_handler(int irq, void *arg)
+{
 	struct drm_i915_private *dev_priv = arg;
 	void __iomem * const regs = dev_priv->uncore.regs;
 	u32 master_ctl;
 	u32 gt_iir[4];
 	if (!intel_irqs_enabled(dev_priv))
 		return IRQ_NONE;
-	master_ctl = gen8_master_intr_disable(regs);
+	master_ctl = gen8_master_intr_disable(&dev_priv->uncore);
 	if (!master_ctl) {
-		gen8_master_intr_enable(regs);
+		gen8_master_intr_enable(&dev_priv->uncore);
 		return IRQ_NONE;
+	}
 	/* Find, clear, then process each source of interrupt */
 	gen8_gt_irq_ack(&dev_priv->gt, master_ctl, gt_iir);
 	/* IRQs are synced during runtime_suspend, we don't require a wakeref */
 	if (master_ctl & ~GEN8_GT_IRQS) {
 		disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
 		gen8_de_irq_handler(dev_priv, master_ctl);
 		enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
+	}
-	gen8_master_intr_enable(regs);
+	gen8_master_intr_enable(&dev_priv->uncore);
 	gen8_gt_irq_handler(&dev_priv->gt, master_ctl, gt_iir);
 	return IRQ_HANDLED;
+}
 static u32
 gen11_gu_misc_irq_ack(struct intel_gt *gt, const u32 master_ctl)
+{
 	void __iomem * const regs = gt->uncore->regs;
 	u32 iir;
 	if (!(master_ctl & GEN11_GU_MISC_IRQ))
 		return 0;
-	iir = raw_reg_read(regs, GEN11_GU_MISC_IIR);
+	iir = raw_reg_read(gt->uncore, GEN11_GU_MISC_IIR);
 	if (likely(iir))
-		raw_reg_write(regs, GEN11_GU_MISC_IIR, iir);
+		raw_reg_write(gt->uncore, GEN11_GU_MISC_IIR, iir);
 	return iir;
+}
 static void
 gen11_gu_misc_irq_handler(struct intel_gt *gt, const u32 iir)
+{
 	if (iir & GEN11_GU_MISC_GSE)
 		intel_opregion_asle_intr(gt->i915);
+}
 static inline u32 gen11_master_intr_disable(void __iomem * const regs)
+{
 @@ -2475,71 +2473,69 @@ static inline u32 gen11_master_intr_disa
 	 * and will generate new interrupt after enabling master.
 	 */
 	return raw_reg_read(regs, GEN11_GFX_MSTR_IRQ);
+}
 static inline void gen11_master_intr_enable(void __iomem * const regs)
+{
 	raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ);
+}
 static void
 gen11_display_irq_handler(struct drm_i915_private *i915)
+{
-	void __iomem * const regs = i915->uncore.regs;
+	const u32 disp_ctl = raw_reg_read(&i915->uncore, GEN11_DISPLAY_INT_CTL);
 	const u32 disp_ctl = raw_reg_read(regs, GEN11_DISPLAY_INT_CTL);
 	disable_rpm_wakeref_asserts(&i915->runtime_pm);
 	/*
 	 * GEN11_DISPLAY_INT_CTL has same format as GEN8_MASTER_IRQ
 	 * for the display related bits.
 	 */
-	raw_reg_write(regs, GEN11_DISPLAY_INT_CTL, 0x0);
+	raw_reg_write(&i915->uncore, GEN11_DISPLAY_INT_CTL, 0x0);
 	gen8_de_irq_handler(i915, disp_ctl);
-	raw_reg_write(regs, GEN11_DISPLAY_INT_CTL,
+	raw_reg_write(&i915->uncore, GEN11_DISPLAY_INT_CTL,
 		      GEN11_DISPLAY_IRQ_ENABLE);
 	enable_rpm_wakeref_asserts(&i915->runtime_pm);
+}
 static __always_inline irqreturn_t
 __gen11_irq_handler(struct drm_i915_private * const i915,
 		    u32 (*intr_disable)(void __iomem * const regs),
 		    void (*intr_enable)(void __iomem * const regs))
+{
 	void __iomem * const regs = i915->uncore.regs;
 	struct intel_gt *gt = &i915->gt;
 	u32 master_ctl;
 	u32 gu_misc_iir;
 	if (!intel_irqs_enabled(i915))
 		return IRQ_NONE;
-	master_ctl = intr_disable(regs);
+	master_ctl = intr_disable(&i915->uncore);
 	if (!master_ctl) {
-		intr_enable(regs);
+		intr_enable(&i915->uncore);
 		return IRQ_NONE;
+	}
 	/* Find, clear, then process each source of interrupt. */
 	gen11_gt_irq_handler(gt, master_ctl);
 	/* IRQs are synced during runtime_suspend, we don't require a wakeref */
 	if (master_ctl & GEN11_DISPLAY_IRQ)
 		gen11_display_irq_handler(i915);
 	gu_misc_iir = gen11_gu_misc_irq_ack(gt, master_ctl);
-	intr_enable(regs);
+	intr_enable(&i915->uncore);
 	gen11_gu_misc_irq_handler(gt, gu_misc_iir);
 	return IRQ_HANDLED;
+}
 static irqreturn_t gen11_irq_handler(int irq, void *arg)
+{
 	return __gen11_irq_handler(arg,
 				   gen11_master_intr_disable,
 				   gen11_master_intr_enable);
+}

 @@ -1,14 +1,14 @@
-/*	$NetBSD: intel_uncore.h,v 1.2 2021/12/18 23:45:29 riastradh Exp $	*/
+/*	$NetBSD: intel_uncore.h,v 1.3 2021/12/19 01:43:37 riastradh Exp $	*/
 /*
  * Copyright © 2017 Intel Corporation
+ *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
  * to deal in the Software without restriction, including without limitation
  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  * and/or sell copies of the Software, and to permit persons to whom the
  * Software is furnished to do so, subject to the following conditions:
+ *
  * The above copyright notice and this permission notice (including the next
  * paragraph) shall be included in all copies or substantial portions of the
 @@ -401,19 +401,28 @@ static inline void intel_uncore_rmw_fw(s
 static inline int intel_uncore_write_and_verify(struct intel_uncore *uncore,
 						i915_reg_t reg, u32 val,
 						u32 mask, u32 expected_val)
+{
 	u32 reg_val;
 	intel_uncore_write(uncore, reg, val);
 	reg_val = intel_uncore_read(uncore, reg);
 	return (reg_val & mask) != expected_val ? -EINVAL : 0;
+}
 #ifdef __NetBSD__
 #define	raw_reg_read(i915, reg)						      \
 	bus_space_read_4((i915)->regs_bst, (i915)->regs_bsh,		      \
 	    i915_mmio_reg_offset(reg))
 #define	raw_reg_write(i915, reg, value)					      \
 	bus_space_write_4((i915)->regs_bst, (i915)->regs_bsh,		      \
 	    i915_mmio_reg_offset(reg), (value))
 #else
 #define raw_reg_read(base, reg) \
 	readl(base + i915_mmio_reg_offset(reg))
 #define raw_reg_write(base, reg, value) \
 	writel(value, base + i915_mmio_reg_offset(reg))
 #endif
 #endif /* !__INTEL_UNCORE_H__ */

 @@ -1,23 +1,23 @@
-/*	$NetBSD: intel_gt_irq.c,v 1.2 2021/12/18 23:45:30 riastradh Exp $	*/
+/*	$NetBSD: intel_gt_irq.c,v 1.3 2021/12/19 01:43:37 riastradh Exp $	*/
 /*
  * SPDX-License-Identifier: MIT
+ *
  * Copyright © 2019 Intel Corporation
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: intel_gt_irq.c,v 1.2 2021/12/18 23:45:30 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: intel_gt_irq.c,v 1.3 2021/12/19 01:43:37 riastradh Exp $");
 #include <linux/sched/clock.h>
 #include "i915_drv.h"
 #include "i915_irq.h"
 #include "intel_gt.h"
 #include "intel_gt_irq.h"
 #include "intel_uncore.h"
 #include "intel_rps.h"
 static void guc_irq_handler(struct intel_guc *guc, u16 iir)
+{
 	if (iir & GUC_INTR_GUC2HOST)
 @@ -35,51 +35,50 @@ cs_irq_handler(struct intel_engine_cs *e
 	if (iir & GT_RENDER_USER_INTERRUPT) {
 		intel_engine_signal_breadcrumbs(engine);
 		tasklet |= intel_engine_needs_breadcrumb_tasklet(engine);
+	}
 	if (tasklet)
 		tasklet_hi_schedule(&engine->execlists.tasklet);
+}
 static u32
 gen11_gt_engine_identity(struct intel_gt *gt,
 			 const unsigned int bank, const unsigned int bit)
+{
 	void __iomem * const regs = gt->uncore->regs;
 	u32 timeout_ts;
 	u32 ident;
 	lockdep_assert_held(&gt->irq_lock);
-	raw_reg_write(regs, GEN11_IIR_REG_SELECTOR(bank), BIT(bit));
+	raw_reg_write(gt->uncore, GEN11_IIR_REG_SELECTOR(bank), BIT(bit));
 	/*
 	 * NB: Specs do not specify how long to spin wait,
 	 * so we do ~100us as an educated guess.
 	 */
 	timeout_ts = (local_clock() >> 10) + 100;
 	do {
-		ident = raw_reg_read(regs, GEN11_INTR_IDENTITY_REG(bank));
+		ident = raw_reg_read(gt->uncore, GEN11_INTR_IDENTITY_REG(bank));
 	} while (!(ident & GEN11_INTR_DATA_VALID) &&
 		 !time_after32(local_clock() >> 10, timeout_ts));
 	if (unlikely(!(ident & GEN11_INTR_DATA_VALID))) {
 		DRM_ERROR("INTR_IDENTITY_REG%u:%u 0x%08x not valid!\n",
 			  bank, bit, ident);
 		return 0;
+	}
-	raw_reg_write(regs, GEN11_INTR_IDENTITY_REG(bank),
+	raw_reg_write(gt->uncore, GEN11_INTR_IDENTITY_REG(bank),
 		      GEN11_INTR_DATA_VALID);
 	return ident;
+}
 static void
 gen11_other_irq_handler(struct intel_gt *gt, const u8 instance,
 			const u16 iir)
+{
 	if (instance == OTHER_GUC_INSTANCE)
 		return guc_irq_handler(&gt->uc.guc, iir);
 	if (instance == OTHER_GTPM_INSTANCE)
 @@ -120,81 +119,79 @@ gen11_gt_identity_handler(struct intel_g
 	if (class <= COPY_ENGINE_CLASS)
 		return gen11_engine_irq_handler(gt, class, instance, intr);
 	if (class == OTHER_CLASS)
 		return gen11_other_irq_handler(gt, instance, intr);
 	WARN_ONCE(1, "unknown interrupt class=0x%x, instance=0x%x, intr=0x%x\n",
 		  class, instance, intr);
+}
 static void
 gen11_gt_bank_handler(struct intel_gt *gt, const unsigned int bank)
+{
 	void __iomem * const regs = gt->uncore->regs;
 	unsigned long intr_dw;
 	unsigned int bit;
 	lockdep_assert_held(&gt->irq_lock);
-	intr_dw = raw_reg_read(regs, GEN11_GT_INTR_DW(bank));
+	intr_dw = raw_reg_read(gt->uncore, GEN11_GT_INTR_DW(bank));
 	for_each_set_bit(bit, &intr_dw, 32) {
 		const u32 ident = gen11_gt_engine_identity(gt, bank, bit);
 		gen11_gt_identity_handler(gt, ident);
+	}
 	/* Clear must be after shared has been served for engine */
-	raw_reg_write(regs, GEN11_GT_INTR_DW(bank), intr_dw);
+	raw_reg_write(gt->uncore, GEN11_GT_INTR_DW(bank), intr_dw);
+}
 void gen11_gt_irq_handler(struct intel_gt *gt, const u32 master_ctl)
+{
 	unsigned int bank;
 	spin_lock(&gt->irq_lock);
 	for (bank = 0; bank < 2; bank++) {
 		if (master_ctl & GEN11_GT_DW_IRQ(bank))
 			gen11_gt_bank_handler(gt, bank);
+	}
 	spin_unlock(&gt->irq_lock);
+}
 bool gen11_gt_reset_one_iir(struct intel_gt *gt,
 			    const unsigned int bank, const unsigned int bit)
+{
 	void __iomem * const regs = gt->uncore->regs;
 	u32 dw;
 	lockdep_assert_held(&gt->irq_lock);
-	dw = raw_reg_read(regs, GEN11_GT_INTR_DW(bank));
+	dw = raw_reg_read(gt->uncore, GEN11_GT_INTR_DW(bank));
 	if (dw & BIT(bit)) {
 		/*
 		 * According to the BSpec, DW_IIR bits cannot be cleared without
 		 * first servicing the Selector & Shared IIR registers.
 		 */
 		gen11_gt_engine_identity(gt, bank, bit);
 		/*
 		 * We locked GT INT DW by reading it. If we want to (try
 		 * to) recover from this successfully, we need to clear
 		 * our bit, otherwise we are locking the register for
 		 * everybody.
 		 */
-		raw_reg_write(regs, GEN11_GT_INTR_DW(bank), BIT(bit));
+		raw_reg_write(gt->uncore, GEN11_GT_INTR_DW(bank), BIT(bit));
 		return true;
+	}
 	return false;
+}
 void gen11_gt_irq_reset(struct intel_gt *gt)
+{
 	struct intel_uncore *uncore = gt->uncore;
 	/* Disable RCS, BCS, VCS and VECS class engines. */
 	intel_uncore_write(uncore, GEN11_RENDER_COPY_INTR_ENABLE, 0);
 @@ -283,50 +280,49 @@ void gen6_gt_irq_handler(struct intel_gt
 		intel_engine_signal_breadcrumbs(gt->engine_class[COPY_ENGINE_CLASS][0]);
 	if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
 		      GT_BSD_CS_ERROR_INTERRUPT |
 		      GT_RENDER_CS_MASTER_ERROR_INTERRUPT))
 		DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir);
 	if (gt_iir & GT_PARITY_ERROR(gt->i915))
 		gen7_parity_error_irq_handler(gt, gt_iir);
+}
 void gen8_gt_irq_ack(struct intel_gt *gt, u32 master_ctl, u32 gt_iir[4])
+{
 	void __iomem * const regs = gt->uncore->regs;
 	if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
-		gt_iir[0] = raw_reg_read(regs, GEN8_GT_IIR(0));
+		gt_iir[0] = raw_reg_read(gt->uncore, GEN8_GT_IIR(0));
 		if (likely(gt_iir[0]))
-			raw_reg_write(regs, GEN8_GT_IIR(0), gt_iir[0]);
+			raw_reg_write(gt->uncore, GEN8_GT_IIR(0), gt_iir[0]);
+	}
 	if (master_ctl & (GEN8_GT_VCS0_IRQ | GEN8_GT_VCS1_IRQ)) {
-		gt_iir[1] = raw_reg_read(regs, GEN8_GT_IIR(1));
+		gt_iir[1] = raw_reg_read(gt->uncore, GEN8_GT_IIR(1));
 		if (likely(gt_iir[1]))
-			raw_reg_write(regs, GEN8_GT_IIR(1), gt_iir[1]);
+			raw_reg_write(gt->uncore, GEN8_GT_IIR(1), gt_iir[1]);
+	}
 	if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) {
-		gt_iir[2] = raw_reg_read(regs, GEN8_GT_IIR(2));
+		gt_iir[2] = raw_reg_read(gt->uncore, GEN8_GT_IIR(2));
 		if (likely(gt_iir[2]))
-			raw_reg_write(regs, GEN8_GT_IIR(2), gt_iir[2]);
+			raw_reg_write(gt->uncore, GEN8_GT_IIR(2), gt_iir[2]);
+	}
 	if (master_ctl & GEN8_GT_VECS_IRQ) {
-		gt_iir[3] = raw_reg_read(regs, GEN8_GT_IIR(3));
+		gt_iir[3] = raw_reg_read(gt->uncore, GEN8_GT_IIR(3));
 		if (likely(gt_iir[3]))
-			raw_reg_write(regs, GEN8_GT_IIR(3), gt_iir[3]);
+			raw_reg_write(gt->uncore, GEN8_GT_IIR(3), gt_iir[3]);
+	}
+}
 void gen8_gt_irq_handler(struct intel_gt *gt, u32 master_ctl, u32 gt_iir[4])
+{
 	if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
 		cs_irq_handler(gt->engine_class[RENDER_CLASS][0],
 			       gt_iir[0] >> GEN8_RCS_IRQ_SHIFT);
 		cs_irq_handler(gt->engine_class[COPY_ENGINE_CLASS][0],
 			       gt_iir[0] >> GEN8_BCS_IRQ_SHIFT);
+	}
 	if (master_ctl & (GEN8_GT_VCS0_IRQ | GEN8_GT_VCS1_IRQ)) {