 @@ -1,14 +1,14 @@
-#	$NetBSD: files.amdgpu,v 1.17 2021/12/19 11:24:37 riastradh Exp $
+#	$NetBSD: files.amdgpu,v 1.18 2021/12/19 11:35:06 riastradh Exp $
 version	20180827
 define	amdgpufbbus	{ }
 device	amdgpu: drmkms, drmkms_pci, drmkms_ttm, amdgpufbbus, firmload
 attach	amdgpu at pci
 defflag	opt_amdgpu_cik.h AMDGPU_CIK
 device	amdgpufb: amdgpufbbus, drmfb, drmfb_pci, wsemuldisplaydev
 attach	amdgpufb at amdgpufbbus
 makeoptions	amdgpufb	"CPPFLAGS.amdgpufb"+="${CPPFLAGS.amdgpu}"
 @@ -38,26 +38,34 @@ makeoptions	amdgpu	"CWARNFLAGS.amdgpu"+=
 makeoptions	amdgpu	"CWARNFLAGS.amdgpu"+="-Wno-missing-prototypes"
 makeoptions	amdgpu	"CWARNFLAGS.amdgpu"+="-Wno-shadow"
 makeoptions	amdgpu	"CWARNFLAGS.amdgpu"+="-Wno-pointer-arith"
 makeoptions	amdgpu	"CWARNFLAGS.amdgpu"+="-Wno-override-init"
 # Half the file strips const qualifier; file is small enough this is
 # not an issue.
 makeoptions	amdgpu	"CWARNFLAGS.amdgpu_arct_reg_init.c"+="-Wno-cast-qual"
 # -Wtype-limits raises warnings about code that is careful to avoid
 # overflow in arithmetic, which is the opposite of helpful.  &@!#*
 makeoptions	amdgpu	"CWARNFLAGS.amdgpu_bo_list.c"+="-Wno-type-limits"
 ifdef amd64
 makeoptions	amdgpu	"COPTS.amdgpu_dcn20_resource.c"+="-mhard-float -msse -msse2"
 makeoptions	amdgpu	"COPTS.amdgpu_dcn21_resource.c"+="-mhard-float -msse -msse2"
 makeoptions	amdgpu	"COPTS.amdgpu_dcn_calc_auto.c"+="-mhard-float -msse -msse2"
 makeoptions	amdgpu	"COPTS.amdgpu_dcn_calc_math.c"+="-mhard-float -msse -msse2"
 makeoptions	amdgpu	"COPTS.amdgpu_dcn_calcs.c"+="-mhard-float -msse -msse2"
 endif
 # Local additions.
 file	external/bsd/drm2/amdgpu/amdgpu_module.c	amdgpu
 file	external/bsd/drm2/amdgpu/amdgpu_pci.c		amdgpu
 file	external/bsd/drm2/amdgpu/amdgpufb.c		amdgpufb
 # Generated from amdgpu2netbsd.
 file	external/bsd/drm2/dist/drm/amd/amdgpu/../acp/amdgpu_acp_hw.c	amdgpu
 file	external/bsd/drm2/dist/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c	amdgpu
 file	external/bsd/drm2/dist/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_color.c	amdgpu
 file	external/bsd/drm2/dist/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_hdcp.c	amdgpu
 file	external/bsd/drm2/dist/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_helpers.c	amdgpu
 file	external/bsd/drm2/dist/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_irq.c	amdgpu
 file	external/bsd/drm2/dist/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_mst_types.c	amdgpu

 @@ -1,14 +1,14 @@
-/*	$NetBSD: amdgpu.h,v 1.5 2021/12/18 23:44:58 riastradh Exp $	*/
+/*	$NetBSD: amdgpu.h,v 1.6 2021/12/19 11:35:06 riastradh Exp $	*/
 /*
  * Copyright 2008 Advanced Micro Devices, Inc.
  * Copyright 2008 Red Hat Inc.
  * Copyright 2009 Jerome Glisse.
+ *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
  * to deal in the Software without restriction, including without limitation
  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  * and/or sell copies of the Software, and to permit persons to whom the
  * Software is furnished to do so, subject to the following conditions:
+ *
 @@ -1254,28 +1254,32 @@ int amdgpu_cs_find_mapping(struct amdgpu
 #if defined(CONFIG_DRM_AMD_DC)
 int amdgpu_dm_display_resume(struct amdgpu_device *adev );
 #else
 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; }
 #endif
 void amdgpu_register_gpu_instance(struct amdgpu_device *adev);
 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev);
 #include "amdgpu_object.h"
 #ifdef __NetBSD__	       /* XXX amdgpu sysfs */
 #define	AMDGPU_PMU_ATTR(_name, _object) CTASSERT(1)
 #else
 /* used by df_v3_6.c and amdgpu_pmu.c */
 #define AMDGPU_PMU_ATTR(_name, _object)					\
 static ssize_t								\
 _name##_show(struct device *dev,					\
 			       struct device_attribute *attr,		\
 			       char *page)				\
 {									\
 	BUILD_BUG_ON(sizeof(_object) >= PAGE_SIZE - 1);			\
 	return sprintf(page, _object "\n");				\
 }									\
+									\
 static struct device_attribute pmu_attr_##_name = __ATTR_RO(_name)
 #endif
 #endif

 @@ -1,14 +1,14 @@
-/*	$NetBSD: amdgpu_device.c,v 1.7 2021/12/18 23:44:58 riastradh Exp $	*/
+/*	$NetBSD: amdgpu_device.c,v 1.8 2021/12/19 11:35:07 riastradh Exp $	*/
 /*
  * Copyright 2008 Advanced Micro Devices, Inc.
  * Copyright 2008 Red Hat Inc.
  * Copyright 2009 Jerome Glisse.
+ *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
  * to deal in the Software without restriction, including without limitation
  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  * and/or sell copies of the Software, and to permit persons to whom the
  * Software is furnished to do so, subject to the following conditions:
+ *
 @@ -18,27 +18,27 @@
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  * OTHER DEALINGS IN THE SOFTWARE.
+ *
  * Authors: Dave Airlie
  *          Alex Deucher
  *          Jerome Glisse
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: amdgpu_device.c,v 1.7 2021/12/18 23:44:58 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: amdgpu_device.c,v 1.8 2021/12/19 11:35:07 riastradh Exp $");
 #include <linux/power_supply.h>
 #include <linux/kthread.h>
 #include <linux/module.h>
 #include <linux/console.h>
 #include <linux/slab.h>
 #include <drm/drm_atomic_helper.h>
 #include <drm/drm_probe_helper.h>
 #include <drm/amdgpu_drm.h>
 #include <linux/vgaarb.h>
 #include <linux/vga_switcheroo.h>
 #include <linux/efi.h>
 @@ -109,48 +109,52 @@ const char *amdgpu_asic_name[] = {
 	"VEGAM",
 	"VEGA10",
 	"VEGA12",
 	"VEGA20",
 	"RAVEN",
 	"ARCTURUS",
 	"RENOIR",
 	"NAVI10",
 	"NAVI14",
 	"NAVI12",
 	"LAST",
 };
 #ifndef __NetBSD__		/* XXX amdgpu sysfs */
 /**
  * DOC: pcie_replay_count
+ *
  * The amdgpu driver provides a sysfs API for reporting the total number
  * of PCIe replays (NAKs)
  * The file pcie_replay_count is used for this and returns the total
  * number of replays as a sum of the NAKs generated and NAKs received
  */
 static ssize_t amdgpu_device_get_pcie_replay_count(struct device *dev,
 		struct device_attribute *attr, char *buf)
+{
 	struct drm_device *ddev = dev_get_drvdata(dev);
 	struct amdgpu_device *adev = ddev->dev_private;
 	uint64_t cnt = amdgpu_asic_get_pcie_replay_count(adev);
 	return snprintf(buf, PAGE_SIZE, "%llu\n", cnt);
+}
 static DEVICE_ATTR(pcie_replay_count, S_IRUGO,
 		amdgpu_device_get_pcie_replay_count, NULL);
 #endif	/* __NetBSD__ */
 static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev);
 /**
  * amdgpu_device_supports_boco - Is the device a dGPU with HG/PX power control
+ *
  * @dev: drm_device pointer
+ *
  * Returns true if the device is a dGPU with HG/PX power control,
  * otherwise return false.
  */
 bool amdgpu_device_supports_boco(struct drm_device *dev)
+{
 	struct amdgpu_device *adev = dev->dev_private;
 @@ -256,48 +260,58 @@ uint32_t amdgpu_mm_rreg(struct amdgpu_de
+ *
 */
 /**
  * amdgpu_mm_rreg8 - read a memory mapped IO register
+ *
  * @adev: amdgpu_device pointer
  * @offset: byte aligned register offset
+ *
  * Returns the 8 bit value from the offset specified.
  */
 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset) {
 	if (offset < adev->rmmio_size)
 #ifdef __NetBSD__
 		return bus_space_read_1(adev->rmmiot, adev->rmmioh,
 		    adev->rmmio_base + offset);
 #else
 		return (readb(adev->rmmio + offset));
 #endif
 	BUG();
+}
 /*
  * MMIO register write with bytes helper functions
  * @offset:bytes offset from MMIO start
  * @value: the value want to be written to the register
+ *
 */
 /**
  * amdgpu_mm_wreg8 - read a memory mapped IO register
+ *
  * @adev: amdgpu_device pointer
  * @offset: byte aligned register offset
  * @value: 8 bit value to write
+ *
  * Writes the value specified to the offset specified.
  */
 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value) {
 	if (offset < adev->rmmio_size)
 #ifdef __NetBSD__
 		bus_space_write_1(adev->rmmiot, adev->rmmioh,
 		    adev->rmmio_base + offset, value);
 #else
 		writeb(value, adev->rmmio + offset);
 #endif
 	else
 		BUG();
+}
 /**
  * amdgpu_mm_wreg - write to a memory mapped IO register
+ *
  * @adev: amdgpu_device pointer
  * @reg: dword aligned register offset
  * @v: 32 bit value to write to the register
  * @acc_flags: access flags which require special behavior
+ *
  * Writes the value specified to the offset specified.
 @@ -457,47 +471,57 @@ void amdgpu_mm_wdoorbell(struct amdgpu_d
 /**
  * amdgpu_mm_rdoorbell64 - read a doorbell Qword
+ *
  * @adev: amdgpu_device pointer
  * @index: doorbell index
+ *
  * Returns the value in the doorbell aperture at the
  * requested doorbell index (VEGA10+).
  */
 u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index)
+{
 	if (index < adev->doorbell.num_doorbells) {
 #ifdef __NetBSD__
 		return bus_space_read_8(adev->doorbell.bst, adev->doorbell.bsh,
 *index);
 #else
 		return atomic64_read((atomic64_t *)(adev->doorbell.ptr + index));
 #endif
 	} else {
 		DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
 		return 0;
+	}
+}
 /**
  * amdgpu_mm_wdoorbell64 - write a doorbell Qword
+ *
  * @adev: amdgpu_device pointer
  * @index: doorbell index
  * @v: value to write
+ *
  * Writes @v to the doorbell aperture at the
  * requested doorbell index (VEGA10+).
  */
 void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v)
+{
 	if (index < adev->doorbell.num_doorbells) {
 #ifdef __NetBSD__
 		bus_space_write_8(adev->doorbell.bst, adev->doorbell.bsh,
 *index, v);
 #else
 		atomic64_set((atomic64_t *)(adev->doorbell.ptr + index), v);
 #endif
 	} else {
 		DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
+	}
+}
 /**
  * amdgpu_invalid_rreg - dummy reg read function
+ *
  * @adev: amdgpu device pointer
  * @reg: offset of register
+ *
  * Dummy register read function.  Used for register blocks
  * that certain asics don't have (all asics).
 @@ -3242,31 +3266,33 @@ fence_driver_init:
 	r = amdgpu_device_ip_late_init(adev);
 	if (r) {
 		dev_err(adev->dev, "amdgpu_device_ip_late_init failed\n");
 		amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r);
 		goto failed;
+	}
 	/* must succeed. */
 	amdgpu_ras_resume(adev);
 	queue_delayed_work(system_wq, &adev->delayed_init_work,
 			   msecs_to_jiffies(AMDGPU_RESUME_MS));
 #ifndef __NetBSD__		/* XXX amdgpu sysfs */
 	r = device_create_file(adev->dev, &dev_attr_pcie_replay_count);
 	if (r) {
 		dev_err(adev->dev, "Could not create pcie_replay_count");
 		return r;
+	}
 #endif
 	if (IS_ENABLED(CONFIG_PERF_EVENTS))
 		r = amdgpu_pmu_init(adev);
 	if (r)
 		dev_err(adev->dev, "amdgpu_pmu_init failed\n");
 	return 0;
 failed:
 	amdgpu_vf_error_trans_all(adev);
 	if (boco)
 		vga_switcheroo_fini_domain_pm_ops(adev->dev);

 @@ -1,53 +1,55 @@
-/*	$NetBSD: amdgpu_df_v3_6.c,v 1.2 2021/12/18 23:44:58 riastradh Exp $	*/
+/*	$NetBSD: amdgpu_df_v3_6.c,v 1.3 2021/12/19 11:35:07 riastradh Exp $	*/
 /*
  * Copyright 2018 Advanced Micro Devices, Inc.
+ *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
  * to deal in the Software without restriction, including without limitation
  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  * and/or sell copies of the Software, and to permit persons to whom the
  * Software is furnished to do so, subject to the following conditions:
+ *
  * The above copyright notice and this permission notice shall be included in
  * all copies or substantial portions of the Software.
+ *
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  * OTHER DEALINGS IN THE SOFTWARE.
+ *
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: amdgpu_df_v3_6.c,v 1.2 2021/12/18 23:44:58 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: amdgpu_df_v3_6.c,v 1.3 2021/12/19 11:35:07 riastradh Exp $");
 #include "amdgpu.h"
 #include "df_v3_6.h"
 #include "df/df_3_6_default.h"
 #include "df/df_3_6_offset.h"
 #include "df/df_3_6_sh_mask.h"
 #define DF_3_6_SMN_REG_INST_DIST        0x8
 #define DF_3_6_INST_CNT                 8
 static u32 df_v3_6_channel_number[] = {1, 2, 0, 4, 0, 8, 0,
 , 32, 0, 0, 0, 2, 4, 8};
 #ifndef __NetBSD__		/* XXX amdgpu sysfs */
 /* init df format attrs */
 AMDGPU_PMU_ATTR(event,		"config:0-7");
 AMDGPU_PMU_ATTR(instance,	"config:8-15");
 AMDGPU_PMU_ATTR(umask,		"config:16-23");
 /* df format attributes  */
 static struct attribute *df_v3_6_format_attrs[] = {
 	&pmu_attr_event.attr,
 	&pmu_attr_instance.attr,
 	&pmu_attr_umask.attr,
 	NULL
 };
 @@ -91,26 +93,28 @@ static struct attribute *df_v3_6_event_a
 /* df event attribute group */
 static struct attribute_group df_v3_6_event_attr_group = {
 	.name = "events",
 	.attrs = df_v3_6_event_attrs
 };
 /* df event attr groups  */
 const struct attribute_group *df_v3_6_attr_groups[] = {
 		&df_v3_6_format_attr_group,
 		&df_v3_6_event_attr_group,
 		NULL
 };
 #endif	/* __NetBSD__ */
 static uint64_t df_v3_6_get_fica(struct amdgpu_device *adev,
 				 uint32_t ficaa_val)
+{
 	unsigned long flags, address, data;
 	uint32_t ficadl_val, ficadh_val;
 	address = adev->nbio.funcs->get_pcie_index_offset(adev);
 	data = adev->nbio.funcs->get_pcie_data_offset(adev);
 	spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 	WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessAddress3);
 	WREG32(data, ficaa_val);
 @@ -236,50 +240,54 @@ static int df_v3_6_perfmon_arm_with_retr
 	while (countdown) {
 		if (!df_v3_6_perfmon_arm_with_status(adev, lo_addr, lo_val,
 						     hi_addr, hi_val))
 			break;
 		countdown -= ARM_RETRY_USEC_INTERVAL;
 		udelay(ARM_RETRY_USEC_INTERVAL);
+	}
 	return countdown > 0 ? 0 : -ETIME;
+}
 #ifndef __NetBSD__		/* XXX amdgpu sysfs */
 /* get the number of df counters available */
 static ssize_t df_v3_6_get_df_cntr_avail(struct device *dev,
 		struct device_attribute *attr,
 		char *buf)
+{
 	struct amdgpu_device *adev;
 	struct drm_device *ddev;
 	int i, count;
 	ddev = dev_get_drvdata(dev);
 	adev = ddev->dev_private;
 	count = 0;
 	for (i = 0; i < DF_V3_6_MAX_COUNTERS; i++) {
 		if (adev->df_perfmon_config_assign_mask[i] == 0)
 			count++;
+	}
 	return snprintf(buf, PAGE_SIZE,	"%i\n", count);
+}
 /* device attr for available perfmon counters */
 static DEVICE_ATTR(df_cntr_avail, S_IRUGO, df_v3_6_get_df_cntr_avail, NULL);
 #endif	/* __NetBSD__ */
 static void df_v3_6_query_hashes(struct amdgpu_device *adev)
+{
 	u32 tmp;
 	adev->df.hash_status.hash_64k = false;
 	adev->df.hash_status.hash_2m = false;
 	adev->df.hash_status.hash_1g = false;
 	if (adev->asic_type != CHIP_ARCTURUS)
 		return;
 	/* encoding for hash-enabled on Arcturus */
 	if (adev->df.funcs->get_fb_channel_number(adev) == 0xe) {
 @@ -291,40 +299,46 @@ static void df_v3_6_query_hashes(struct
 						DF_CS_UMC_AON0_DfGlobalCtrl,
 						GlbHashIntlvCtl2M);
 		adev->df.hash_status.hash_1g = REG_GET_FIELD(tmp,
 						DF_CS_UMC_AON0_DfGlobalCtrl,
 						GlbHashIntlvCtl1G);
+	}
+}
 /* init perfmons */
 static void df_v3_6_sw_init(struct amdgpu_device *adev)
+{
 	int i, ret;
 #ifdef __NetBSD__		/* XXX amdgpu sysfs */
 	__USE(ret);
 #else
 	ret = device_create_file(adev->dev, &dev_attr_df_cntr_avail);
 	if (ret)
 		DRM_ERROR("failed to create file for available df counters\n");
 #endif
 	for (i = 0; i < AMDGPU_MAX_DF_PERFMONS; i++)
 		adev->df_perfmon_config_assign_mask[i] = 0;
 	df_v3_6_query_hashes(adev);
+}
 static void df_v3_6_sw_fini(struct amdgpu_device *adev)
+{
 #ifndef __NetBSD__		/* XXX amdgpu sysfs */
 	device_remove_file(adev->dev, &dev_attr_df_cntr_avail);
 #endif
+}
 static void df_v3_6_enable_broadcast_mode(struct amdgpu_device *adev,
 					  bool enable)
+{
 	u32 tmp;
 	if (enable) {
 		tmp = RREG32_SOC15(DF, 0, mmFabricConfigAccessControl);
 		tmp &= ~FabricConfigAccessControl__CfgRegInstAccEn_MASK;
 		WREG32_SOC15(DF, 0, mmFabricConfigAccessControl, tmp);
 	} else
 @@ -475,27 +489,27 @@ static int df_v3_6_pmc_get_ctrl_settings
+	}
 	eventsel = DF_V3_6_GET_EVENT(config) & 0x3f;
 	unitmask = DF_V3_6_GET_UNITMASK(config) & 0xf;
 	instance = DF_V3_6_GET_INSTANCE(config);
 	instance_10 = instance & 0x3;
 	instance_5432 = (instance >> 2) & 0xf;
 	instance_76 = (instance >> 6) & 0x3;
 	*lo_val = (unitmask << 8) | (instance_10 << 6) | eventsel | (1 << 22);
 	*hi_val = (instance_76 << 29) | instance_5432;
-	DRM_DEBUG_DRIVER("config=%llx addr=%08x:%08x val=%08x:%08x",
+	DRM_DEBUG_DRIVER("config=%"PRIx64" addr=%08x:%08x val=%08x:%08x",
 		config, *lo_base_addr, *hi_base_addr, *lo_val, *hi_val);
 	return 0;
+}
 /* add df performance counters for read */
 static int df_v3_6_pmc_add_cntr(struct amdgpu_device *adev,
 				   uint64_t config)
+{
 	int i, target_cntr;
 	target_cntr = df_v3_6_pmc_config_2_cntr(adev, config);

 @@ -1,14 +1,14 @@
-/*	$NetBSD: os_types.h,v 1.2 2021/12/18 23:45:00 riastradh Exp $	*/
+/*	$NetBSD: os_types.h,v 1.3 2021/12/19 11:35:07 riastradh Exp $	*/
 /*
  * Copyright 2012-16 Advanced Micro Devices, Inc.
  * Copyright 2019 Raptor Engineering, LLC
+ *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
  * to deal in the Software without restriction, including without limitation
  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  * and/or sell copies of the Software, and to permit persons to whom the
  * Software is furnished to do so, subject to the following conditions:
+ *
  * The above copyright notice and this permission notice shall be included in
 @@ -44,29 +44,35 @@
 #define BIGENDIAN_CPU
 #elif defined(__LITTLE_ENDIAN) && !defined(LITTLEENDIAN_CPU)
 #define LITTLEENDIAN_CPU
 #endif
 #undef FRAME_SIZE
 #define dm_output_to_console(fmt, ...) DRM_DEBUG_KMS(fmt, ##__VA_ARGS__)
 #define dm_error(fmt, ...) DRM_ERROR(fmt, ##__VA_ARGS__)
 #if defined(CONFIG_DRM_AMD_DC_DCN)
 #if defined(CONFIG_X86)
 #ifdef __NetBSD__
 #include <x86/fpu.h>
 #define	DC_FP_START()	fpu_kern_enter()
 #define	DC_FP_END()	fpu_kern_leave()
 #else
 #include <asm/fpu/api.h>
 #define DC_FP_START() kernel_fpu_begin()
 #define DC_FP_END() kernel_fpu_end()
 #endif
 #elif defined(CONFIG_PPC64)
 #include <asm/switch_to.h>
 #include <asm/cputable.h>
 #define DC_FP_START() { \
 	if (cpu_has_feature(CPU_FTR_VSX_COMP)) { \
 		preempt_disable(); \
 		enable_kernel_vsx(); \
 	} else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) { \
 		preempt_disable(); \
 		enable_kernel_altivec(); \
 	} else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) { \
 		preempt_disable(); \
 		enable_kernel_fp(); \

 @@ -1,14 +1,14 @@
-/*	$NetBSD: amdgpu_dcn_calcs.c,v 1.2 2021/12/18 23:45:01 riastradh Exp $	*/
+/*	$NetBSD: amdgpu_dcn_calcs.c,v 1.3 2021/12/19 11:35:07 riastradh Exp $	*/
 /*
  * Copyright 2017 Advanced Micro Devices, Inc.
  * Copyright 2019 Raptor Engineering, LLC
+ *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
  * to deal in the Software without restriction, including without limitation
  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  * and/or sell copies of the Software, and to permit persons to whom the
  * Software is furnished to do so, subject to the following conditions:
+ *
  * The above copyright notice and this permission notice shall be included in
 @@ -17,27 +17,27 @@
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  * OTHER DEALINGS IN THE SOFTWARE.
+ *
  * Authors: AMD
+ *
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: amdgpu_dcn_calcs.c,v 1.2 2021/12/18 23:45:01 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: amdgpu_dcn_calcs.c,v 1.3 2021/12/19 11:35:07 riastradh Exp $");
 #include "dm_services.h"
 #include "dc.h"
 #include "dcn_calcs.h"
 #include "dcn_calc_auto.h"
 #include "dal_asic_id.h"
 #include "resource.h"
 #include "dcn10/dcn10_resource.h"
 #include "dcn10/dcn10_hubbub.h"
 #include "dml/dml1_display_rq_dlg_calc.h"
 #include "dcn_calc_math.h"
 @@ -436,27 +436,27 @@ static void pipe_ctx_to_e2e_pipe_params
 	input->dest.vstartup_start = pipe->pipe_dlg_param.vstartup_start;
 	input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset;
 	input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset;
 	input->dest.vupdate_width = pipe->pipe_dlg_param.vupdate_width;
+}
 static void dcn_bw_calc_rq_dlg_ttu(
 		const struct dc *dc,
 		const struct dcn_bw_internal_vars *v,
 		struct pipe_ctx *pipe,
 		int in_idx)
+{
-	struct display_mode_lib *dml = (struct display_mode_lib *)(&dc->dml);
+	struct display_mode_lib *dml = (struct display_mode_lib *)__UNCONST(&dc->dml);
 	struct _vcs_dpi_display_dlg_regs_st *dlg_regs = &pipe->dlg_regs;
 	struct _vcs_dpi_display_ttu_regs_st *ttu_regs = &pipe->ttu_regs;
 	struct _vcs_dpi_display_rq_regs_st *rq_regs = &pipe->rq_regs;
 	struct _vcs_dpi_display_rq_params_st rq_param = {0};
 	struct _vcs_dpi_display_dlg_sys_params_st dlg_sys_param = {0};
 	struct _vcs_dpi_display_e2e_pipe_params_st input = { { { 0 } } };
 	float total_active_bw = 0;
 	float total_prefetch_bw = 0;
 	int total_flip_bytes = 0;
 	int i;
 	memset(dlg_regs, 0, sizeof(*dlg_regs));
 	memset(ttu_regs, 0, sizeof(*ttu_regs));

 @@ -1,14 +1,14 @@
-/*	$NetBSD: amdgpu_dcn21_hubp.c,v 1.2 2021/12/18 23:45:03 riastradh Exp $	*/
+/*	$NetBSD: amdgpu_dcn21_hubp.c,v 1.3 2021/12/19 11:35:07 riastradh Exp $	*/
 /*
 * Copyright 2018 Advanced Micro Devices, Inc.
+ *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
  * to deal in the Software without restriction, including without limitation
  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  * and/or sell copies of the Software, and to permit persons to whom the
  * Software is furnished to do so, subject to the following conditions:
+ *
  * The above copyright notice and this permission notice shall be included in
  * all copies or substantial portions of the Software.
 @@ -16,27 +16,27 @@
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  * OTHER DEALINGS IN THE SOFTWARE.
+ *
  * Authors: AMD
+ *
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: amdgpu_dcn21_hubp.c,v 1.2 2021/12/18 23:45:03 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: amdgpu_dcn21_hubp.c,v 1.3 2021/12/19 11:35:07 riastradh Exp $");
 #include "dcn10/dcn10_hubp.h"
 #include "dcn21_hubp.h"
 #include "dm_services.h"
 #include "reg_helper.h"
 #include "dc_dmub_srv.h"
 #define DC_LOGGER_INIT(logger)
 #define REG(reg)\
 	hubp21->hubp_regs->reg
 @@ -320,27 +320,27 @@ static void hubp21_apply_PLAT_54186_wa(
 	ASSERT(patched_viewport_height && patched_viewport_height < 5000);
 	ASSERT(patched_viewport_width && patched_viewport_width < 5000);
 	REG_UPDATE_2(DCSURF_PRI_VIEWPORT_DIMENSION_C,
 			PRI_VIEWPORT_WIDTH_C, patched_viewport_width,
 			PRI_VIEWPORT_HEIGHT_C, patched_viewport_height);
+}
 void hubp21_set_vm_system_aperture_settings(struct hubp *hubp,
 		struct vm_system_aperture_param *apt)
+{
 	struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);
-	PHYSICAL_ADDRESS_LOC mc_vm_apt_default;
+	PHYSICAL_ADDRESS_LOC mc_vm_apt_default __unused;
 	PHYSICAL_ADDRESS_LOC mc_vm_apt_low;
 	PHYSICAL_ADDRESS_LOC mc_vm_apt_high;
 	// The format of default addr is 48:12 of the 48 bit addr
 	mc_vm_apt_default.quad_part = apt->sys_default.quad_part >> 12;
 	// The format of high/low are 48:18 of the 48 bit addr
 	mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 18;
 	mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 18;
 	REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0,
 			MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.quad_part);

 @@ -1,14 +1,14 @@
-/*	$NetBSD: amdgpu_dcn21_resource.c,v 1.2 2021/12/18 23:45:03 riastradh Exp $	*/
+/*	$NetBSD: amdgpu_dcn21_resource.c,v 1.3 2021/12/19 11:35:07 riastradh Exp $	*/
 /*
 * Copyright 2018 Advanced Micro Devices, Inc.
  * Copyright 2019 Raptor Engineering, LLC
+ *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
  * to deal in the Software without restriction, including without limitation
  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  * and/or sell copies of the Software, and to permit persons to whom the
  * Software is furnished to do so, subject to the following conditions:
+ *
  * The above copyright notice and this permission notice shall be included in
 @@ -17,27 +17,27 @@
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  * OTHER DEALINGS IN THE SOFTWARE.
+ *
  * Authors: AMD
+ *
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: amdgpu_dcn21_resource.c,v 1.2 2021/12/18 23:45:03 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: amdgpu_dcn21_resource.c,v 1.3 2021/12/19 11:35:07 riastradh Exp $");
 #include <linux/slab.h>
 #include "dm_services.h"
 #include "dc.h"
 #include "dcn21_init.h"
 #include "resource.h"
 #include "include/irq_service_interface.h"
 #include "dcn20/dcn20_resource.h"
 #include "clk_mgr.h"
 @@ -933,30 +933,32 @@ static void dcn21_resource_destruct(stru
+	}
 	for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
 		if (pool->base.dwbc[i] != NULL) {
 			kfree(TO_DCN20_DWBC(pool->base.dwbc[i]));
 			pool->base.dwbc[i] = NULL;
+		}
 		if (pool->base.mcif_wb[i] != NULL) {
 			kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i]));
 			pool->base.mcif_wb[i] = NULL;
+		}
+	}
 #ifndef __NetBSD__		/* XXX amdgpu audio */
 	for (i = 0; i < pool->base.audio_count; i++) {
 		if (pool->base.audios[i])
 			dce_aud_destroy(&pool->base.audios[i]);
+	}
 #endif
 	for (i = 0; i < pool->base.clk_src_count; i++) {
 		if (pool->base.clock_sources[i] != NULL) {
 			dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
 			pool->base.clock_sources[i] = NULL;
+		}
+	}
 	if (pool->base.dp_clock_source != NULL) {
 		dcn20_clock_source_destroy(&pool->base.dp_clock_source);
 		pool->base.dp_clock_source = NULL;
+	}
 @@ -1420,32 +1422,34 @@ static struct pp_smu_funcs *dcn21_pp_smu
+	}
 	return pp_smu;
+}
 static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu)
+{
 	if (pp_smu && *pp_smu) {
 		kfree(*pp_smu);
 		*pp_smu = NULL;
+	}
+}
 #ifndef __NetBSD__		/* XXX amdgpu audio */
 static struct audio *dcn21_create_audio(
 		struct dc_context *ctx, unsigned int inst)
+{
 	return dce_audio_create(ctx, inst,
 			&audio_regs[inst], &audio_shift, &audio_mask);
+}
 #endif
 static struct dc_cap_funcs cap_funcs = {
 	.get_dcc_compression_cap = dcn20_get_dcc_compression_cap
 };
 struct stream_encoder *dcn21_stream_encoder_create(
 	enum engine_id eng_id,
 	struct dc_context *ctx)
+{
 	struct dcn10_stream_encoder *enc1 =
 		kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
 	if (!enc1)
 @@ -1477,27 +1481,29 @@ static struct dce_hwseq *dcn21_hwseq_cre
 	if (hws) {
 		hws->ctx = ctx;
 		hws->regs = &hwseq_reg;
 		hws->shifts = &hwseq_shift;
 		hws->masks = &hwseq_mask;
 		hws->wa.DEGVIDCN21 = true;
+	}
 	return hws;
+}
 static const struct resource_create_funcs res_create_funcs = {
 	.read_dce_straps = read_dce_straps,
 #ifndef __NetBSD__		/* XXX amdgpu audio */
 	.create_audio = dcn21_create_audio,
 #endif
 	.create_stream_encoder = dcn21_stream_encoder_create,
 	.create_hwseq = dcn21_hwseq_create,
 };
 static const struct resource_create_funcs res_create_maximus_funcs = {
 	.read_dce_straps = NULL,
 	.create_audio = NULL,
 	.create_stream_encoder = NULL,
 	.create_hwseq = dcn21_hwseq_create,
 };
 static const struct encoder_feature_support link_enc_feature = {
 		.max_hdmi_deep_color = COLOR_DEPTH_121212,