 @@ -1,14 +1,14 @@
-/*	$NetBSD: i386.c,v 1.74.6.13 2021/12/24 13:02:24 martin Exp $	*/
+/*	$NetBSD: i386.c,v 1.74.6.14 2022/01/31 17:52:44 martin Exp $	*/
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Frank van der Linden,  and by Jason R. Thorpe.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
 @@ -47,27 +47,27 @@
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
 #ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.74.6.13 2021/12/24 13:02:24 martin Exp $");
+__RCSID("$NetBSD: i386.c,v 1.74.6.14 2022/01/31 17:52:44 martin Exp $");
 #endif /* not lint */
 #include <sys/types.h>
 #include <sys/param.h>
 #include <sys/bitops.h>
 #include <sys/sysctl.h>
 #include <sys/ioctl.h>
 #include <sys/cpuio.h>
 #include <errno.h>
 #include <string.h>
 #include <stdio.h>
 #include <stdlib.h>
 @@ -341,31 +341,37 @@ const struct cpu_cpuid_nameclass i386_cp
 				[0x5e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)",
 				[0x5f] = "Atom (Goldmont, Denverton)",
 				[0x66] = "8th gen Core i3 (Cannon Lake)",
 				[0x6a] = "3rd gen Xeon Scalable (Ice Lake)",
 				[0x6c] = "3rd gen Xeon Scalable (Ice Lake)",
 				[0x7a] = "Atom (Goldmont Plus)",
 				[0x7d] = "10th gen Core (Ice Lake)",
 				[0x7e] = "10th gen Core (Ice Lake)",
 				[0x85] = "Xeon Phi 7215, 7285, 7295 (Knights Mill)",
 				[0x86] = "Atom (Tremont)",
 				[0x8c] = "11th gen Core (Tiger Lake)",
 				[0x8d] = "11th gen Core (Tiger Lake)",
 				[0x8e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake) or Xeon E (Coffee Lake)",
 				[0x8f] = "future Xeon (Sapphire Rapids)",
 				[0x96] = "Atom x6000E (Elkhart Lake)",
 				[0x97] = "12th gen Core (Alder Lake)",
 				[0x9a] = "12th gen Core (Alder Lake)",
 				[0x9c] = "Pentium Silver N6xxx, Celeron N45xx, Celeron N51xx (Jasper Lake)",
 				[0x9e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake) or Xeon E (Coffee Lake)",
 				[0xa5] = "10th gen Core (Comet Lake)",
 				[0xa6] = "10th gen Core (Comet Lake)",
 				[0xa7] = "11th gen Core (Rocket Lake)",
 				[0xa8] = "11th gen Core (Rocket Lake)",
 				[0xbf] = "12th gen Core (Alder Lake)",
 			},
 			"Pentium Pro, II or III",	/* Default */
 			NULL,
 			intel_family_new_probe,
 			intel_cpu_cacheinfo,
 		},
 		/* Family > 6 */
+		{
 			CPUCLASS_686,
+			{
 , 0, 0, 0, 0, 0, 0, 0,
 , 0, 0, 0, 0, 0, 0, 0,
 			},
 @@ -2154,51 +2160,45 @@ identifycpu(int fd, const char *cpuname)
 			aprint_verbose("%s: SVM Rev. %d\n", cpuname,
 			    descs[0] & 0xf);
 			aprint_verbose("%s: SVM NASID %d\n", cpuname,
 			    descs[1]);
 			print_bits(cpuname, "SVM features",
 			    CPUID_AMD_SVM_FLAGS, descs[3]);
+		}
 		if (ci->ci_max_ext_cpuid >= 0x8000001f) {
 			x86_cpuid(0x8000001f, descs);
 			print_bits(cpuname, "Encrypted Memory features",
 			    CPUID_AMD_ENCMEM_FLAGS, descs[0]);
+		}
 	} else if (cpu_vendor == CPUVENDOR_INTEL) {
-		int32_t bi_index;
+		if (ci->ci_max_cpuid >= 0x0a) {
 			x86_cpuid(0x0a, descs);
-		for (bi_index = 1; bi_index <= ci->ci_max_cpuid; bi_index++) {
+			print_bits(cpuname, "Perfmon-eax",
-			x86_cpuid(bi_index, descs);
+			    CPUID_PERF_FLAGS0, descs[0]);
-			switch (bi_index) {
+			print_bits(cpuname, "Perfmon-ebx",
-			case 0x0a:
+			    CPUID_PERF_FLAGS1, descs[1]);
-				print_bits(cpuname, "Perfmon-eax",
+			print_bits(cpuname, "Perfmon-edx",
-				    CPUID_PERF_FLAGS0, descs[0]);
+			    CPUID_PERF_FLAGS3, descs[3]);
 				print_bits(cpuname, "Perfmon-ebx",
-				    CPUID_PERF_FLAGS1, descs[1]);
+		if (ci->ci_max_cpuid >= 0x1a) {
-				print_bits(cpuname, "Perfmon-edx",
+			x86_cpuid(0x1a, descs);
-				    CPUID_PERF_FLAGS3, descs[3]);
+			if (descs[0] != 0) {
-				break;
+				aprint_verbose("%s: Hybrid: Core type %02x, "
-			default:
+				    "Native Model ID %07x\n",
-#if 0
+				    cpuname,
-				aprint_verbose("%s: basic %08x-eax %08x\n",
+				    (uint8_t)__SHIFTOUT(descs[0],
-				    cpuname, bi_index, descs[0]);
+					CPUID_HYBRID_CORETYPE),
-				aprint_verbose("%s: basic %08x-ebx %08x\n",
+				    (uint32_t)__SHIFTOUT(descs[0],
-				    cpuname, bi_index, descs[1]);
+					CPUID_HYBRID_NATIVEID));
 				aprint_verbose("%s: basic %08x-ecx %08x\n",
 				    cpuname, bi_index, descs[2]);
 				aprint_verbose("%s: basic %08x-edx %08x\n",
 				    cpuname, bi_index, descs[3]);
 #endif
 				break;
+			}
+		}
+	}
 #ifdef INTEL_ONDEMAND_CLOCKMOD
 	clockmod_init();
 #endif
 	if (cpu_vendor == CPUVENDOR_AMD)
 		ucode.loader_version = CPU_UCODE_LOADER_AMD;
 	else if (cpu_vendor == CPUVENDOR_INTEL)
 		ucode.loader_version = CPU_UCODE_LOADER_INTEL1;
 	else