Tue Feb 1 04:59:16 2022 UTC ()
Increment legacy interrupt counter after checking INTx sharing.


(msaitoh)
diff -r1.305 -r1.306 src/sys/dev/pci/ixgbe/ixgbe.c
cvs diff -r1.305 -r1.306 src/sys/dev/pci/ixgbe/ixgbe.c (expand / switch to unified diff)

--- src/sys/dev/pci/ixgbe/ixgbe.c 2022/01/25 01:56:22 1.305
+++ src/sys/dev/pci/ixgbe/ixgbe.c 2022/02/01 04:59:16 1.306
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: ixgbe.c,v 1.305 2022/01/25 01:56:22 msaitoh Exp $ */ 1/* $NetBSD: ixgbe.c,v 1.306 2022/02/01 04:59:16 msaitoh Exp $ */
2 2
3/****************************************************************************** 3/******************************************************************************
4 4
5 Copyright (c) 2001-2017, Intel Corporation 5 Copyright (c) 2001-2017, Intel Corporation
6 All rights reserved. 6 All rights reserved.
7 7
8 Redistribution and use in source and binary forms, with or without 8 Redistribution and use in source and binary forms, with or without
9 modification, are permitted provided that the following conditions are met: 9 modification, are permitted provided that the following conditions are met:
10 10
11 1. Redistributions of source code must retain the above copyright notice, 11 1. Redistributions of source code must retain the above copyright notice,
12 this list of conditions and the following disclaimer. 12 this list of conditions and the following disclaimer.
13 13
14 2. Redistributions in binary form must reproduce the above copyright 14 2. Redistributions in binary form must reproduce the above copyright
@@ -54,27 +54,27 @@ @@ -54,27 +54,27 @@
54 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 54 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
55 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 55 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
56 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 56 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
57 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 57 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
58 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 58 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
59 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 59 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
60 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 60 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
61 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 61 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
62 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 62 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
63 * POSSIBILITY OF SUCH DAMAGE. 63 * POSSIBILITY OF SUCH DAMAGE.
64 */ 64 */
65 65
66#include <sys/cdefs.h> 66#include <sys/cdefs.h>
67__KERNEL_RCSID(0, "$NetBSD: ixgbe.c,v 1.305 2022/01/25 01:56:22 msaitoh Exp $"); 67__KERNEL_RCSID(0, "$NetBSD: ixgbe.c,v 1.306 2022/02/01 04:59:16 msaitoh Exp $");
68 68
69#ifdef _KERNEL_OPT 69#ifdef _KERNEL_OPT
70#include "opt_inet.h" 70#include "opt_inet.h"
71#include "opt_inet6.h" 71#include "opt_inet6.h"
72#include "opt_net_mpsafe.h" 72#include "opt_net_mpsafe.h"
73#endif 73#endif
74 74
75#include "ixgbe.h" 75#include "ixgbe.h"
76#include "ixgbe_phy.h" 76#include "ixgbe_phy.h"
77#include "ixgbe_sriov.h" 77#include "ixgbe_sriov.h"
78 78
79#include <sys/cprng.h> 79#include <sys/cprng.h>
80#include <dev/mii/mii.h> 80#include <dev/mii/mii.h>
@@ -5263,32 +5263,32 @@ ixgbe_legacy_irq(void *arg) @@ -5263,32 +5263,32 @@ ixgbe_legacy_irq(void *arg)
5263 u32 eims_enable = 0; 5263 u32 eims_enable = 0;
5264 u32 eims_disable = 0; 5264 u32 eims_disable = 0;
5265 5265
5266 eims_orig = IXGBE_READ_REG(hw, IXGBE_EIMS); 5266 eims_orig = IXGBE_READ_REG(hw, IXGBE_EIMS);
5267 /* 5267 /*
5268 * Silicon errata #26 on 82598. Disable all interrupts before reading 5268 * Silicon errata #26 on 82598. Disable all interrupts before reading
5269 * EICR. 5269 * EICR.
5270 */ 5270 */
5271 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); 5271 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
5272 5272
5273 /* Read and clear EICR */ 5273 /* Read and clear EICR */
5274 eicr = IXGBE_READ_REG(hw, IXGBE_EICR); 5274 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
5275 5275
5276 IXGBE_EVC_ADD(&adapter->stats.pf.legint, 1); 
5277 if (eicr == 0) { 5276 if (eicr == 0) {
5278 IXGBE_EVC_ADD(&adapter->stats.pf.intzero, 1); 5277 IXGBE_EVC_ADD(&adapter->stats.pf.intzero, 1);
5279 IXGBE_WRITE_REG(hw, IXGBE_EIMS, eims_orig); 5278 IXGBE_WRITE_REG(hw, IXGBE_EIMS, eims_orig);
5280 return 0; 5279 return 0;
5281 } 5280 }
 5281 IXGBE_EVC_ADD(&adapter->stats.pf.legint, 1);
5282 5282
5283 /* Queue (0) intr */ 5283 /* Queue (0) intr */
5284 if ((eicr & IXGBE_EIMC_RTX_QUEUE) != 0) { 5284 if ((eicr & IXGBE_EIMC_RTX_QUEUE) != 0) {
5285 IXGBE_EVC_ADD(&que->irqs, 1); 5285 IXGBE_EVC_ADD(&que->irqs, 1);
5286 5286
5287 /* 5287 /*
5288 * The same as ixgbe_msix_que() about 5288 * The same as ixgbe_msix_que() about
5289 * "que->txrx_use_workqueue". 5289 * "que->txrx_use_workqueue".
5290 */ 5290 */
5291 que->txrx_use_workqueue = adapter->txrx_use_workqueue; 5291 que->txrx_use_workqueue = adapter->txrx_use_workqueue;
5292 5292
5293 IXGBE_TX_LOCK(txr); 5293 IXGBE_TX_LOCK(txr);
5294 ixgbe_txeof(txr); 5294 ixgbe_txeof(txr);