 @@ -1,14 +1,14 @@
-/*	$NetBSD: membar_ops.S,v 1.10 2020/08/10 14:37:38 skrll Exp $	*/
+/*	$NetBSD: membar_ops.S,v 1.11 2022/02/12 17:10:02 riastradh Exp $	*/
 /*-
  * Copyright (c) 2006, 2007 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Jason R. Thorpe, and by Andrew Doran.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
 @@ -36,36 +36,26 @@
 LEAF(_membar_sync)
 	j	ra
 	 BDSYNC
 END(_membar_sync)
 #ifdef __OCTEON__
 LEAF(_membar_producer)
 	j	ra
 	 syncw
 END(_membar_producer)
 #endif
 #ifdef _KERNEL
 STRONG_ALIAS(mb_read, _membar_sync)
 #ifdef __OCTEON__
 STRONG_ALIAS(mb_write, _membar_producer)
 #else
 STRONG_ALIAS(mb_write, _membar_sync)
 #endif
 STRONG_ALIAS(mb_memory, _membar_sync)
 #endif
 ATOMIC_OP_ALIAS(membar_sync,_membar_sync)
 ATOMIC_OP_ALIAS(membar_enter,_membar_sync)
 STRONG_ALIAS(_membar_enter,_membar_sync)
 #ifdef __OCTEON__
 ATOMIC_OP_ALIAS(membar_exit,_membar_producer)
 STRONG_ALIAS(_membar_exit,_membar_producer)
 STRONG_ALIAS(membar_producer,_membar_producer)
 #else
 ATOMIC_OP_ALIAS(membar_exit,_membar_sync)
 STRONG_ALIAS(_membar_exit,_membar_sync)
 ATOMIC_OP_ALIAS(membar_producer,_membar_sync)
 STRONG_ALIAS(_membar_producer,_membar_sync)
 #endif

 @@ -1,14 +1,14 @@
-/*	$NetBSD: lock.h,v 1.21 2020/08/05 05:24:44 simonb Exp $	*/
+/*	$NetBSD: lock.h,v 1.22 2022/02/12 17:10:02 riastradh Exp $	*/
 /*-
  * Copyright (c) 2001, 2007 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Wayne Knowles and Andrew Doran.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
 @@ -31,26 +31,28 @@
 /*
  * Machine-dependent spin lock operations for MIPS processors.
+ *
  * Note: R2000/R3000 doesn't have any atomic update instructions; this
  * will cause problems for user applications using this header.
  */
 #ifndef _MIPS_LOCK_H_
 #define	_MIPS_LOCK_H_
 #include <sys/param.h>
 #include <sys/atomic.h>
 static __inline int
 __SIMPLELOCK_LOCKED_P(const __cpu_simple_lock_t *__ptr)
+{
 	return *__ptr != __SIMPLELOCK_UNLOCKED;
+}
 static __inline int
 __SIMPLELOCK_UNLOCKED_P(const __cpu_simple_lock_t *__ptr)
+{
 	return *__ptr == __SIMPLELOCK_UNLOCKED;
+}
 static __inline void
 @@ -88,109 +90,117 @@ __cpu_simple_lock_try(__cpu_simple_lock_
 		"	j	3f		\n"
 		"	 nop			\n"
 		"	nop			\n"
 		"2:	li	%1, 0		\n"
 		"3:				\n"
 		"	.set pop		\n"
 		"# -- END __cpu_simple_lock_try	\n"
 		: "=r" (t0), "=r" (v0), "+m" (*lp)
 		: "i" (__SIMPLELOCK_LOCKED), "m" (*lp));
 	return (v0 != 0);
+}
 #ifdef MIPS1
 static __inline void
 mb_read(void)
 	__insn_barrier();
 static __inline void
 mb_write(void)
 	__insn_barrier();
 static __inline void
 mb_memory(void)
 	__insn_barrier();
 #else	/* MIPS1*/
 static __inline void
 mb_read(void)
 	__asm volatile(
 		"	.set push		\n"
 		"	.set mips2		\n"
 		"	sync			\n"
 		"	.set pop"
 		::: "memory"
 	);
 static __inline void
 mb_write(void)
 	mb_read();
 static __inline void
 mb_memory(void)
 	mb_read();
 #endif	/* MIPS1 */
 #else	/* !_HARDKERNEL */
 u_int	_atomic_cas_uint(volatile u_int *, u_int, u_int);
 u_long	_atomic_cas_ulong(volatile u_long *, u_long, u_long);
 void *	_atomic_cas_ptr(volatile void *, void *, void *);
 void	mb_read(void);
 void	mb_write(void);
 void	mb_memory(void);
 static __inline int
 __cpu_simple_lock_try(__cpu_simple_lock_t *lp)
+{
 	/*
 	 * Successful _atomic_cas_uint functions as a load-acquire --
 	 * on MP systems, it issues sync after the LL/SC CAS succeeds;
 	 * on non-MP systems every load is a load-acquire so it's moot.
 	 * This pairs with the membar_exit and store sequence in
 	 * __cpu_simple_unlock that functions as a store-release
 	 * operation.
+	 *
 	 * NOTE: This applies only to _atomic_cas_uint (with the
 	 * underscore), in sys/arch/mips/mips/lock_stubs_*.S.  Not true
 	 * for atomic_cas_uint (without the underscore), from
 	 * common/lib/libc/arch/mips/atomic/atomic_cas.S which does not
 	 * imply a load-acquire.  It is unclear why these disagree.
 	 */
 	return _atomic_cas_uint(lp,
 	    __SIMPLELOCK_UNLOCKED, __SIMPLELOCK_LOCKED) ==
 	    __SIMPLELOCK_UNLOCKED;
+}
 #endif	/* _HARDKERNEL */
 static __inline void
 __cpu_simple_lock_init(__cpu_simple_lock_t *lp)
+{
 	*lp = __SIMPLELOCK_UNLOCKED;
 	mb_memory();
+}
 static __inline void
 __cpu_simple_lock(__cpu_simple_lock_t *lp)
+{
 	while (!__cpu_simple_lock_try(lp)) {
 		while (*lp == __SIMPLELOCK_LOCKED)
 			/* spin */;
+	}
+}
 static __inline void
 __cpu_simple_unlock(__cpu_simple_lock_t *lp)
+{
-#ifndef _MIPS_ARCH_OCTEONP
+	/*
-	mb_memory();
+	 * The membar_exit and then store functions as a store-release
-#endif
+	 * operation that pairs with the load-acquire operation in
 	 * successful __cpu_simple_lock_try.
+	 *
 	 * Can't use atomic_store_release here because that's not
 	 * available in userland at the moment.
 	 */
 	membar_exit();
 	*lp = __SIMPLELOCK_UNLOCKED;
 #ifdef _MIPS_ARCH_OCTEONP
-	mb_write();
+	/*
 	 * On Cavium's recommendation, we issue an extra SYNCW that is
 	 * not necessary for correct ordering because apparently stores
 	 * can get stuck in Octeon store buffers for hundreds of
 	 * thousands of cycles, according to the following note:
+	 *
 	 *	Programming Notes:
 	 *	[...]
 	 *	Core A (writer)
 	 *	SW R1, DATA
 	 *	LI R2, 1
 	 *	SYNCW
 	 *	SW R2, FLAG
 	 *	SYNCW
 	 *	[...]
+	 *
 	 *	The second SYNCW instruction executed by core A is not
 	 *	necessary for correctness, but has very important
 	 *	performance effects on OCTEON.  Without it, the store
 	 *	to FLAG may linger in core A's write buffer before it
 	 *	becomes visible to other cores.  (If core A is not
 	 *	performing many stores, this may add hundreds of
 	 *	thousands of cycles to the flag release time since the
 	 *	OCTEON core normally retains stores to attempt to merge
 	 *	them before sending the store on the CMB.)
 	 *	Applications should include this second SYNCW
 	 *	instruction after flag or lock releases.
+	 *
 	 * Cavium Networks OCTEON Plus CN50XX Hardware Reference
 	 * Manual, July 2008, Appendix A, p. 943.
 	 * https://storage.googleapis.com/google-code-archive-downloads/v2/code.google.com/hactive/CN50XX-HRM-V0.99E.pdf
+	 *
 	 * XXX It might be prudent to put this into
 	 * atomic_store_release itself.
 	 */
 	__asm volatile("syncw" ::: "memory");
 #endif
+}
 #endif /* _MIPS_LOCK_H_ */