Sun Feb 13 00:39:45 2022 UTC ()
s/Errorrs/Errors/


(andvar)
diff -r1.3 -r1.4 src/sys/arch/arm/at91/at91usartreg.h
cvs diff -r1.3 -r1.4 src/sys/arch/arm/at91/at91usartreg.h (expand / switch to unified diff)

--- src/sys/arch/arm/at91/at91usartreg.h 2009/10/23 06:53:13 1.3
+++ src/sys/arch/arm/at91/at91usartreg.h 2022/02/13 00:39:45 1.4
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: at91usartreg.h,v 1.3 2009/10/23 06:53:13 snj Exp $ */ 1/* $NetBSD: at91usartreg.h,v 1.4 2022/02/13 00:39:45 andvar Exp $ */
2 2
3/* 3/*
4 * Copyright (c) 2007 Embedtronics Oy. All rights reserved. 4 * Copyright (c) 2007 Embedtronics Oy. All rights reserved.
5 * 5 *
6 * Redistribution and use in source and binary forms, with or without 6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions 7 * modification, are permitted provided that the following conditions
8 * are met: 8 * are met:
9 * 1. Redistributions of source code must retain the above copyright 9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer. 10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright 11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the 12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution. 13 * documentation and/or other materials provided with the distribution.
14 * 14 *
@@ -30,27 +30,27 @@ @@ -30,27 +30,27 @@
30 30
31#define US_CR 0x00U /* 0x00: Control Register */ 31#define US_CR 0x00U /* 0x00: Control Register */
32#define US_MR 0x04U /* 0x04: Mode Register */ 32#define US_MR 0x04U /* 0x04: Mode Register */
33#define US_IER 0x08U /* 0x08: Interrupt Enable Reg */ 33#define US_IER 0x08U /* 0x08: Interrupt Enable Reg */
34#define US_IDR 0x0CU /* 0x0C: Interrupt Disable Reg */ 34#define US_IDR 0x0CU /* 0x0C: Interrupt Disable Reg */
35#define US_IMR 0x10U /* 0x10: Interrupt Mask Reg */ 35#define US_IMR 0x10U /* 0x10: Interrupt Mask Reg */
36#define US_CSR 0x14U /* 0x14: Channel Status Reg */ 36#define US_CSR 0x14U /* 0x14: Channel Status Reg */
37#define US_RHR 0x18U /* 0x18: Receive Holding Reg */ 37#define US_RHR 0x18U /* 0x18: Receive Holding Reg */
38#define US_THR 0x1CU /* 0x1C: Transmit Holding Reg */ 38#define US_THR 0x1CU /* 0x1C: Transmit Holding Reg */
39#define US_BRGR 0x20U /* 0x20: Baud Rate Generator Rg */ 39#define US_BRGR 0x20U /* 0x20: Baud Rate Generator Rg */
40#define US_RTOR 0x24U /* 0x24: Receiver Time-out Reg */ 40#define US_RTOR 0x24U /* 0x24: Receiver Time-out Reg */
41#define US_TTGR 0x28U /* 0x28: Transmitter Timeguard Reg */ 41#define US_TTGR 0x28U /* 0x28: Transmitter Timeguard Reg */
42#define US_FIDI 0x40U /* 0x40: FI DI Ratio Register */ 42#define US_FIDI 0x40U /* 0x40: FI DI Ratio Register */
43#define US_NER 0x44U /* 0x44: Number of Errorrs Reg */ 43#define US_NER 0x44U /* 0x44: Number of Errors Reg */
44#define US_IF 0x4CU /* 0x4C: IrDA Filter Register */ 44#define US_IF 0x4CU /* 0x4C: IrDA Filter Register */
45#define US_PDC 0x100U /* 0x100: PDC */ 45#define US_PDC 0x100U /* 0x100: PDC */
46 46
47/* Control Register bits: */ 47/* Control Register bits: */
48#define US_CR_RTSDIS 0x00080000U /* 1 = disable RTS */ 48#define US_CR_RTSDIS 0x00080000U /* 1 = disable RTS */
49#define US_CR_RTSEN 0x00040000U /* 1 = enable RTS */ 49#define US_CR_RTSEN 0x00040000U /* 1 = enable RTS */
50#define US_CR_DTRDIS 0x00020000U /* 1 = disable DTR */ 50#define US_CR_DTRDIS 0x00020000U /* 1 = disable DTR */
51#define US_CR_DTREN 0x00010000U /* 1 = enable DTR */ 51#define US_CR_DTREN 0x00010000U /* 1 = enable DTR */
52#define US_CR_RETTO 0x00008000U /* 1 = Rearm Time-out */ 52#define US_CR_RETTO 0x00008000U /* 1 = Rearm Time-out */
53#define US_CR_RSTNACK 0x00004000U /* 1 = Reset Non Acknowledge */ 53#define US_CR_RSTNACK 0x00004000U /* 1 = Reset Non Acknowledge */
54#define US_CR_RSTIT 0x00002000U /* 1 = Reset Iterations */ 54#define US_CR_RSTIT 0x00002000U /* 1 = Reset Iterations */
55#define US_CR_SENDA 0x00001000U /* 1 = Send Address */ 55#define US_CR_SENDA 0x00001000U /* 1 = Send Address */
56#define US_CR_STTTO 0x00000800U /* 1 = Start Time-out */ 56#define US_CR_STTTO 0x00000800U /* 1 = Start Time-out */