Sun Feb 13 13:42:30 2022 UTC ()
alpha: __cpu_simple_lock audit.

Add missing "cc" and "memory" asm clobbers to the compiler can't
reorder memory access around these.  The necessary memory barrier
instructions, mb, already appear in all the right places.


(riastradh)
diff -r1.32 -r1.33 src/sys/arch/alpha/include/lock.h
cvs diff -r1.32 -r1.33 src/sys/arch/alpha/include/lock.h (expand / switch to unified diff)

--- src/sys/arch/alpha/include/lock.h 2022/02/12 17:17:53 1.32
+++ src/sys/arch/alpha/include/lock.h 2022/02/13 13:42:30 1.33
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: lock.h,v 1.32 2022/02/12 17:17:53 riastradh Exp $ */ 1/* $NetBSD: lock.h,v 1.33 2022/02/13 13:42:30 riastradh Exp $ */
2 2
3/*- 3/*-
4 * Copyright (c) 1998, 1999, 2000 The NetBSD Foundation, Inc. 4 * Copyright (c) 1998, 1999, 2000 The NetBSD Foundation, Inc.
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * This code is derived from software contributed to The NetBSD Foundation 7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
9 * NASA Ames Research Center. 9 * NASA Ames Research Center.
10 * 10 *
11 * Redistribution and use in source and binary forms, with or without 11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions 12 * modification, are permitted provided that the following conditions
13 * are met: 13 * are met:
14 * 1. Redistributions of source code must retain the above copyright 14 * 1. Redistributions of source code must retain the above copyright
@@ -91,66 +91,68 @@ __cpu_simple_lock(__cpu_simple_lock_t *a @@ -91,66 +91,68 @@ __cpu_simple_lock(__cpu_simple_lock_t *a
91 " bis $31, %2, %0 \n" 91 " bis $31, %2, %0 \n"
92 " stl_c %0, %1 \n" 92 " stl_c %0, %1 \n"
93 " beq %0, 3f \n" 93 " beq %0, 3f \n"
94 " mb \n" 94 " mb \n"
95 " br 4f \n" 95 " br 4f \n"
96 "2: ldl %0, %3 \n" 96 "2: ldl %0, %3 \n"
97 " beq %0, 1b \n" 97 " beq %0, 1b \n"
98 " br 2b \n" 98 " br 2b \n"
99 "3: br 1b \n" 99 "3: br 1b \n"
100 "4: \n" 100 "4: \n"
101 " # END __cpu_simple_lock\n" 101 " # END __cpu_simple_lock\n"
102 : "=&r" (t0), "=m" (*alp) 102 : "=&r" (t0), "=m" (*alp)
103 : "i" (__SIMPLELOCK_LOCKED), "m" (*alp) 103 : "i" (__SIMPLELOCK_LOCKED), "m" (*alp)
104 : "memory"); 104 : "cc", "memory");
105} 105}
106 106
107static __inline int 107static __inline int
108__cpu_simple_lock_try(__cpu_simple_lock_t *alp) 108__cpu_simple_lock_try(__cpu_simple_lock_t *alp)
109{ 109{
110 unsigned long t0, v0; 110 unsigned long t0, v0;
111 111
112 __asm volatile( 112 __asm volatile(
113 "# BEGIN __cpu_simple_lock_try\n" 113 "# BEGIN __cpu_simple_lock_try\n"
114 "1: ldl_l %0, %4 \n" 114 "1: ldl_l %0, %4 \n"
115 " bne %0, 2f \n" 115 " bne %0, 2f \n"
116 " bis $31, %3, %0 \n" 116 " bis $31, %3, %0 \n"
117 " stl_c %0, %2 \n" 117 " stl_c %0, %2 \n"
118 " beq %0, 3f \n" 118 " beq %0, 3f \n"
119 " mb \n" 119 " mb \n"
120 " bis $31, 1, %1 \n" 120 " bis $31, 1, %1 \n"
121 " br 4f \n" 121 " br 4f \n"
122 "2: bis $31, $31, %1 \n" 122 "2: bis $31, $31, %1 \n"
123 " br 4f \n" 123 " br 4f \n"
124 "3: br 1b \n" 124 "3: br 1b \n"
125 "4: \n" 125 "4: \n"
126 " # END __cpu_simple_lock_try" 126 " # END __cpu_simple_lock_try"
127 : "=&r" (t0), "=r" (v0), "=m" (*alp) 127 : "=&r" (t0), "=r" (v0), "=m" (*alp)
128 : "i" (__SIMPLELOCK_LOCKED), "m" (*alp) 128 : "i" (__SIMPLELOCK_LOCKED), "m" (*alp)
129 : "memory"); 129 : "cc", "memory");
130 130
131 return (v0 != 0); 131 return (v0 != 0);
132} 132}
133 133
134static __inline void 134static __inline void
135__cpu_simple_unlock(__cpu_simple_lock_t *alp) 135__cpu_simple_unlock(__cpu_simple_lock_t *alp)
136{ 136{
137 137
138 __asm volatile( 138 __asm volatile(
139 "# BEGIN __cpu_simple_unlock\n" 139 "# BEGIN __cpu_simple_unlock\n"
140 " mb \n" 140 " mb \n"
141 " stl $31, %0 \n" 141 " stl $31, %0 \n"
142 " # END __cpu_simple_unlock" 142 " # END __cpu_simple_unlock"
143 : "=m" (*alp)); 143 : "=m" (*alp)
 144 : /* no inputs */
 145 : "memory");
144} 146}
145 147
146#if defined(MULTIPROCESSOR) 148#if defined(MULTIPROCESSOR)
147/* 149/*
148 * On the Alpha, interprocessor interrupts come in at device priority 150 * On the Alpha, interprocessor interrupts come in at device priority
149 * level (ALPHA_PSL_IPL_CLOCK). This can cause some problems while 151 * level (ALPHA_PSL_IPL_CLOCK). This can cause some problems while
150 * waiting for spin locks from a high'ish priority level (like spin 152 * waiting for spin locks from a high'ish priority level (like spin
151 * mutexes used by the scheduler): IPIs that come in will not be 153 * mutexes used by the scheduler): IPIs that come in will not be
152 * processed. This can lead to deadlock. 154 * processed. This can lead to deadlock.
153 * 155 *
154 * This hook allows IPIs to be processed while spinning. Note we only 156 * This hook allows IPIs to be processed while spinning. Note we only
155 * do the special thing if IPIs are blocked (current IPL >= IPL_CLOCK). 157 * do the special thing if IPIs are blocked (current IPL >= IPL_CLOCK).
156 * IPIs will be processed in the normal fashion otherwise, and checking 158 * IPIs will be processed in the normal fashion otherwise, and checking