 @@ -1,1084 +1,1084 @@
-/*	$NetBSD: if_wm.c,v 1.726 2021/12/31 14:25:23 riastradh Exp $	*/
+/*	$NetBSD: if_wm.c,v 1.727 2022/02/16 03:15:27 msaitoh Exp $	*/
 /*
  * Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc.
  * All rights reserved.
+ *
  * Written by Jason R. Thorpe for Wasabi Systems, Inc.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  * 3. All advertising materials mentioning features or use of this software
  *    must display the following acknowledgement:
  *	This product includes software developed for the NetBSD Project by
  *	Wasabi Systems, Inc.
  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
  *    or promote products derived from this software without specific prior
  *    written permission.
+ *
  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 /*******************************************************************************
   Copyright (c) 2001-2005, Intel Corporation
   All rights reserved.
   Redistribution and use in source and binary forms, with or without
   modification, are permitted provided that the following conditions are met:
 . Redistributions of source code must retain the above copyright notice,
       this list of conditions and the following disclaimer.
 . Redistributions in binary form must reproduce the above copyright
       notice, this list of conditions and the following disclaimer in the
       documentation and/or other materials provided with the distribution.
 . Neither the name of the Intel Corporation nor the names of its
       contributors may be used to endorse or promote products derived from
       this software without specific prior written permission.
   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE.
 *******************************************************************************/
 /*
  * Device driver for the Intel i8254x family of Gigabit Ethernet chips.
+ *
  * TODO (in order of importance):
+ *
  *	- Check XXX'ed comments
  *	- TX Multi queue improvement (refine queue selection logic)
  *	- Split header buffer for newer descriptors
  *	- EEE (Energy Efficiency Ethernet) for I354
  *	- Virtual Function
  *	- Set LED correctly (based on contents in EEPROM)
  *	- Rework how parameters are loaded from the EEPROM.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.726 2021/12/31 14:25:23 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.727 2022/02/16 03:15:27 msaitoh Exp $");
 #ifdef _KERNEL_OPT
 #include "opt_net_mpsafe.h"
 #include "opt_if_wm.h"
 #endif
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/callout.h>
 #include <sys/mbuf.h>
 #include <sys/malloc.h>
 #include <sys/kmem.h>
 #include <sys/kernel.h>
 #include <sys/socket.h>
 #include <sys/ioctl.h>
 #include <sys/errno.h>
 #include <sys/device.h>
 #include <sys/queue.h>
 #include <sys/syslog.h>
 #include <sys/interrupt.h>
 #include <sys/cpu.h>
 #include <sys/pcq.h>
 #include <sys/sysctl.h>
 #include <sys/workqueue.h>
 #include <sys/atomic.h>
 #include <sys/rndsource.h>
 #include <net/if.h>
 #include <net/if_dl.h>
 #include <net/if_media.h>
 #include <net/if_ether.h>
 #include <net/bpf.h>
 #include <net/rss_config.h>
 #include <netinet/in.h>			/* XXX for struct ip */
 #include <netinet/in_systm.h>		/* XXX for struct ip */
 #include <netinet/ip.h>			/* XXX for struct ip */
 #include <netinet/ip6.h>		/* XXX for struct ip6_hdr */
 #include <netinet/tcp.h>		/* XXX for struct tcphdr */
 #include <sys/bus.h>
 #include <sys/intr.h>
 #include <machine/endian.h>
 #include <dev/mii/mii.h>
 #include <dev/mii/mdio.h>
 #include <dev/mii/miivar.h>
 #include <dev/mii/miidevs.h>
 #include <dev/mii/mii_bitbang.h>
 #include <dev/mii/ikphyreg.h>
 #include <dev/mii/igphyreg.h>
 #include <dev/mii/igphyvar.h>
 #include <dev/mii/inbmphyreg.h>
 #include <dev/mii/ihphyreg.h>
 #include <dev/mii/makphyreg.h>
 #include <dev/pci/pcireg.h>
 #include <dev/pci/pcivar.h>
 #include <dev/pci/pcidevs.h>
 #include <dev/pci/if_wmreg.h>
 #include <dev/pci/if_wmvar.h>
 #ifdef WM_DEBUG
 #define	WM_DEBUG_LINK		__BIT(0)
 #define	WM_DEBUG_TX		__BIT(1)
 #define	WM_DEBUG_RX		__BIT(2)
 #define	WM_DEBUG_GMII		__BIT(3)
 #define	WM_DEBUG_MANAGE		__BIT(4)
 #define	WM_DEBUG_NVM		__BIT(5)
 #define	WM_DEBUG_INIT		__BIT(6)
 #define	WM_DEBUG_LOCK		__BIT(7)
 #if 0
 #define WM_DEBUG_DEFAULT	WM_DEBUG_TX | WM_DEBUG_RX | WM_DEBUG_LINK | \
 	WM_DEBUG_GMII | WM_DEBUG_MANAGE | WM_DEBUG_NVM | WM_DEBUG_INIT |    \
 	WM_DEBUG_LOCK
 #endif
 #define	DPRINTF(sc, x, y)			  \
 	do {					  \
 		if ((sc)->sc_debug & (x))	  \
 			printf y;		  \
 	} while (0)
 #else
 #define	DPRINTF(sc, x, y)	__nothing
 #endif /* WM_DEBUG */
 #ifdef NET_MPSAFE
 #define WM_MPSAFE	1
 #define WM_CALLOUT_FLAGS	CALLOUT_MPSAFE
 #define WM_SOFTINT_FLAGS	SOFTINT_MPSAFE
 #define WM_WORKQUEUE_FLAGS	WQ_PERCPU | WQ_MPSAFE
 #else
 #define WM_CALLOUT_FLAGS	0
 #define WM_SOFTINT_FLAGS	0
 #define WM_WORKQUEUE_FLAGS	WQ_PERCPU
 #endif
 #define WM_WORKQUEUE_PRI PRI_SOFTNET
 /*
  * This device driver's max interrupt numbers.
  */
 #define WM_MAX_NQUEUEINTR	16
 #define WM_MAX_NINTR		(WM_MAX_NQUEUEINTR + 1)
 #ifndef WM_DISABLE_MSI
 #define	WM_DISABLE_MSI 0
 #endif
 #ifndef WM_DISABLE_MSIX
 #define	WM_DISABLE_MSIX 0
 #endif
 int wm_disable_msi = WM_DISABLE_MSI;
 int wm_disable_msix = WM_DISABLE_MSIX;
 #ifndef WM_WATCHDOG_TIMEOUT
 #define WM_WATCHDOG_TIMEOUT 5
 #endif
 static int wm_watchdog_timeout = WM_WATCHDOG_TIMEOUT;
 /*
  * Transmit descriptor list size.  Due to errata, we can only have
  * 256 hardware descriptors in the ring on < 82544, but we use 4096
  * on >= 82544. We tell the upper layers that they can queue a lot
  * of packets, and we go ahead and manage up to 64 (16 for the i82547)
  * of them at a time.
+ *
  * We allow up to 64 DMA segments per packet.  Pathological packet
  * chains containing many small mbufs have been observed in zero-copy
  * situations with jumbo frames. If a mbuf chain has more than 64 DMA segments,
  * m_defrag() is called to reduce it.
  */
 #define	WM_NTXSEGS		64
 #define	WM_IFQUEUELEN		256
 #define	WM_TXQUEUELEN_MAX	64
 #define	WM_TXQUEUELEN_MAX_82547	16
 #define	WM_TXQUEUELEN(txq)	((txq)->txq_num)
 #define	WM_TXQUEUELEN_MASK(txq)	(WM_TXQUEUELEN(txq) - 1)
 #define	WM_TXQUEUE_GC(txq)	(WM_TXQUEUELEN(txq) / 8)
 #define	WM_NTXDESC_82542	256
 #define	WM_NTXDESC_82544	4096
 #define	WM_NTXDESC(txq)		((txq)->txq_ndesc)
 #define	WM_NTXDESC_MASK(txq)	(WM_NTXDESC(txq) - 1)
 #define	WM_TXDESCS_SIZE(txq)	(WM_NTXDESC(txq) * (txq)->txq_descsize)
 #define	WM_NEXTTX(txq, x)	(((x) + 1) & WM_NTXDESC_MASK(txq))
 #define	WM_NEXTTXS(txq, x)	(((x) + 1) & WM_TXQUEUELEN_MASK(txq))
 #define	WM_MAXTXDMA		 (2 * round_page(IP_MAXPACKET)) /* for TSO */
 #define	WM_TXINTERQSIZE		256
 #ifndef WM_TX_PROCESS_LIMIT_DEFAULT
 #define	WM_TX_PROCESS_LIMIT_DEFAULT		100U
 #endif
 #ifndef WM_TX_INTR_PROCESS_LIMIT_DEFAULT
 #define	WM_TX_INTR_PROCESS_LIMIT_DEFAULT	0U
 #endif
 /*
  * Receive descriptor list size.  We have one Rx buffer for normal
  * sized packets.  Jumbo packets consume 5 Rx buffers for a full-sized
  * packet.  We allocate 256 receive descriptors, each with a 2k
  * buffer (MCLBYTES), which gives us room for 50 jumbo packets.
  */
 #define	WM_NRXDESC		256U
 #define	WM_NRXDESC_MASK		(WM_NRXDESC - 1)
 #define	WM_NEXTRX(x)		(((x) + 1) & WM_NRXDESC_MASK)
 #define	WM_PREVRX(x)		(((x) - 1) & WM_NRXDESC_MASK)
 #ifndef WM_RX_PROCESS_LIMIT_DEFAULT
 #define	WM_RX_PROCESS_LIMIT_DEFAULT		100U
 #endif
 #ifndef WM_RX_INTR_PROCESS_LIMIT_DEFAULT
 #define	WM_RX_INTR_PROCESS_LIMIT_DEFAULT	0U
 #endif
 typedef union txdescs {
 	wiseman_txdesc_t sctxu_txdescs[WM_NTXDESC_82544];
 	nq_txdesc_t	 sctxu_nq_txdescs[WM_NTXDESC_82544];
 } txdescs_t;
 typedef union rxdescs {
 	wiseman_rxdesc_t sctxu_rxdescs[WM_NRXDESC];
 	ext_rxdesc_t	 sctxu_ext_rxdescs[WM_NRXDESC]; /* 82574 only */
 	nq_rxdesc_t	 sctxu_nq_rxdescs[WM_NRXDESC]; /* 82575 and newer */
 } rxdescs_t;
 #define	WM_CDTXOFF(txq, x)	((txq)->txq_descsize * (x))
 #define	WM_CDRXOFF(rxq, x)	((rxq)->rxq_descsize * (x))
 /*
  * Software state for transmit jobs.
  */
 struct wm_txsoft {
 	struct mbuf *txs_mbuf;		/* head of our mbuf chain */
 	bus_dmamap_t txs_dmamap;	/* our DMA map */
 	int txs_firstdesc;		/* first descriptor in packet */
 	int txs_lastdesc;		/* last descriptor in packet */
 	int txs_ndesc;			/* # of descriptors used */
 };
 /*
  * Software state for receive buffers. Each descriptor gets a 2k (MCLBYTES)
  * buffer and a DMA map. For packets which fill more than one buffer, we chain
  * them together.
  */
 struct wm_rxsoft {
 	struct mbuf *rxs_mbuf;		/* head of our mbuf chain */
 	bus_dmamap_t rxs_dmamap;	/* our DMA map */
 };
 #define WM_LINKUP_TIMEOUT	50
 static uint16_t swfwphysem[] = {
 	SWFW_PHY0_SM,
 	SWFW_PHY1_SM,
 	SWFW_PHY2_SM,
 	SWFW_PHY3_SM
 };
 static const uint32_t wm_82580_rxpbs_table[] = {
 , 72, 144, 1, 2, 4, 8, 16, 35, 70, 140
 };
 struct wm_softc;
 #if defined(_LP64) && !defined(WM_DISABLE_EVENT_COUNTERS)
 #if !defined(WM_EVENT_COUNTERS)
 #define WM_EVENT_COUNTERS 1
 #endif
 #endif
 #ifdef WM_EVENT_COUNTERS
 #define WM_Q_EVCNT_DEFINE(qname, evname)				\
 	char qname##_##evname##_evcnt_name[sizeof("qname##XX##evname")]; \
 	struct evcnt qname##_ev_##evname;
 #define WM_Q_EVCNT_ATTACH(qname, evname, q, qnum, xname, evtype)	\
 	do {								\
 		snprintf((q)->qname##_##evname##_evcnt_name,		\
 		    sizeof((q)->qname##_##evname##_evcnt_name),		\
 		    "%s%02d%s", #qname, (qnum), #evname);		\
 		evcnt_attach_dynamic(&(q)->qname##_ev_##evname,		\
 		    (evtype), NULL, (xname),				\
 		    (q)->qname##_##evname##_evcnt_name);		\
 	} while (0)
 #define WM_Q_MISC_EVCNT_ATTACH(qname, evname, q, qnum, xname)		\
 	WM_Q_EVCNT_ATTACH(qname, evname, q, qnum, xname, EVCNT_TYPE_MISC)
 #define WM_Q_INTR_EVCNT_ATTACH(qname, evname, q, qnum, xname)		\
 	WM_Q_EVCNT_ATTACH(qname, evname, q, qnum, xname, EVCNT_TYPE_INTR)
 #define WM_Q_EVCNT_DETACH(qname, evname, q, qnum)	\
 	evcnt_detach(&(q)->qname##_ev_##evname);
 #endif /* WM_EVENT_COUNTERS */
 struct wm_txqueue {
 	kmutex_t *txq_lock;		/* lock for tx operations */
 	struct wm_softc *txq_sc;	/* shortcut (skip struct wm_queue) */
 	/* Software state for the transmit descriptors. */
 	int txq_num;			/* must be a power of two */
 	struct wm_txsoft txq_soft[WM_TXQUEUELEN_MAX];
 	/* TX control data structures. */
 	int txq_ndesc;			/* must be a power of two */
 	size_t txq_descsize;		/* a tx descriptor size */
 	txdescs_t *txq_descs_u;
 	bus_dmamap_t txq_desc_dmamap;	/* control data DMA map */
 	bus_dma_segment_t txq_desc_seg;	/* control data segment */
 	int txq_desc_rseg;		/* real number of control segment */
 #define	txq_desc_dma	txq_desc_dmamap->dm_segs[0].ds_addr
 #define	txq_descs	txq_descs_u->sctxu_txdescs
 #define	txq_nq_descs	txq_descs_u->sctxu_nq_txdescs
 	bus_addr_t txq_tdt_reg;		/* offset of TDT register */
 	int txq_free;			/* number of free Tx descriptors */
 	int txq_next;			/* next ready Tx descriptor */
 	int txq_sfree;			/* number of free Tx jobs */
 	int txq_snext;			/* next free Tx job */
 	int txq_sdirty;			/* dirty Tx jobs */
 	/* These 4 variables are used only on the 82547. */
 	int txq_fifo_size;		/* Tx FIFO size */
 	int txq_fifo_head;		/* current head of FIFO */
 	uint32_t txq_fifo_addr;		/* internal address of start of FIFO */
 	int txq_fifo_stall;		/* Tx FIFO is stalled */
 	/*
 	 * When ncpu > number of Tx queues, a Tx queue is shared by multiple
 	 * CPUs. This queue intermediate them without block.
 	 */
 	pcq_t *txq_interq;
 	/*
 	 * NEWQUEUE devices must use not ifp->if_flags but txq->txq_flags
 	 * to manage Tx H/W queue's busy flag.
 	 */
 	int txq_flags;			/* flags for H/W queue, see below */
 #define	WM_TXQ_NO_SPACE		0x1
 #define	WM_TXQ_LINKDOWN_DISCARD	0x2
 	bool txq_stopping;
 	bool txq_sending;
 	time_t txq_lastsent;
 	/* Checksum flags used for previous packet */
 	uint32_t	txq_last_hw_cmd;
 	uint8_t		txq_last_hw_fields;
 	uint16_t	txq_last_hw_ipcs;
 	uint16_t	txq_last_hw_tucs;
 	uint32_t txq_packets;		/* for AIM */
 	uint32_t txq_bytes;		/* for AIM */
 #ifdef WM_EVENT_COUNTERS
 	/* TX event counters */
 	WM_Q_EVCNT_DEFINE(txq, txsstall)    /* Stalled due to no txs */
 	WM_Q_EVCNT_DEFINE(txq, txdstall)    /* Stalled due to no txd */
 	WM_Q_EVCNT_DEFINE(txq, fifo_stall)  /* FIFO stalls (82547) */
 	WM_Q_EVCNT_DEFINE(txq, txdw)	    /* Tx descriptor interrupts */
 	WM_Q_EVCNT_DEFINE(txq, txqe)	    /* Tx queue empty interrupts */
 					    /* XXX not used? */
 	WM_Q_EVCNT_DEFINE(txq, ipsum)	    /* IP checksums comp. */
 	WM_Q_EVCNT_DEFINE(txq, tusum)	    /* TCP/UDP cksums comp. */
 	WM_Q_EVCNT_DEFINE(txq, tusum6)	    /* TCP/UDP v6 cksums comp. */
 	WM_Q_EVCNT_DEFINE(txq, tso)	    /* TCP seg offload (IPv4) */
 	WM_Q_EVCNT_DEFINE(txq, tso6)	    /* TCP seg offload (IPv6) */
 	WM_Q_EVCNT_DEFINE(txq, tsopain)	    /* Painful header manip. for TSO */
 	WM_Q_EVCNT_DEFINE(txq, pcqdrop)	    /* Pkt dropped in pcq */
 	WM_Q_EVCNT_DEFINE(txq, descdrop)    /* Pkt dropped in MAC desc ring */
 					    /* other than toomanyseg */
 	WM_Q_EVCNT_DEFINE(txq, toomanyseg)  /* Pkt dropped(toomany DMA segs) */
 	WM_Q_EVCNT_DEFINE(txq, defrag)	    /* m_defrag() */
 	WM_Q_EVCNT_DEFINE(txq, underrun)    /* Tx underrun */
 	WM_Q_EVCNT_DEFINE(txq, skipcontext) /* Tx skip wring cksum context */
 	char txq_txseg_evcnt_names[WM_NTXSEGS][sizeof("txqXXtxsegXXX")];
 	struct evcnt txq_ev_txseg[WM_NTXSEGS]; /* Tx packets w/ N segments */
 #endif /* WM_EVENT_COUNTERS */
 };
 struct wm_rxqueue {
 	kmutex_t *rxq_lock;		/* lock for rx operations */
 	struct wm_softc *rxq_sc;	/* shortcut (skip struct wm_queue) */
 	/* Software state for the receive descriptors. */
 	struct wm_rxsoft rxq_soft[WM_NRXDESC];
 	/* RX control data structures. */
 	int rxq_ndesc;			/* must be a power of two */
 	size_t rxq_descsize;		/* a rx descriptor size */
 	rxdescs_t *rxq_descs_u;
 	bus_dmamap_t rxq_desc_dmamap;	/* control data DMA map */
 	bus_dma_segment_t rxq_desc_seg;	/* control data segment */
 	int rxq_desc_rseg;		/* real number of control segment */
 #define	rxq_desc_dma	rxq_desc_dmamap->dm_segs[0].ds_addr
 #define	rxq_descs	rxq_descs_u->sctxu_rxdescs
 #define	rxq_ext_descs	rxq_descs_u->sctxu_ext_rxdescs
 #define	rxq_nq_descs	rxq_descs_u->sctxu_nq_rxdescs
 	bus_addr_t rxq_rdt_reg;		/* offset of RDT register */
 	int rxq_ptr;			/* next ready Rx desc/queue ent */
 	int rxq_discard;
 	int rxq_len;
 	struct mbuf *rxq_head;
 	struct mbuf *rxq_tail;
 	struct mbuf **rxq_tailp;
 	bool rxq_stopping;
 	uint32_t rxq_packets;		/* for AIM */
 	uint32_t rxq_bytes;		/* for AIM */
 #ifdef WM_EVENT_COUNTERS
 	/* RX event counters */
 	WM_Q_EVCNT_DEFINE(rxq, intr);	/* Interrupts */
 	WM_Q_EVCNT_DEFINE(rxq, defer);	/* Rx deferred processing */
 	WM_Q_EVCNT_DEFINE(rxq, ipsum);	/* IP checksums checked */
 	WM_Q_EVCNT_DEFINE(rxq, tusum);	/* TCP/UDP cksums checked */
 #endif
 };
 struct wm_queue {
 	int wmq_id;			/* index of TX/RX queues */
 	int wmq_intr_idx;		/* index of MSI-X tables */
 	uint32_t wmq_itr;		/* interrupt interval per queue. */
 	bool wmq_set_itr;
 	struct wm_txqueue wmq_txq;
 	struct wm_rxqueue wmq_rxq;
 	char sysctlname[32];		/* Name for sysctl */
 	bool wmq_txrx_use_workqueue;
 	struct work wmq_cookie;
 	void *wmq_si;
 };
 struct wm_phyop {
 	int (*acquire)(struct wm_softc *);
 	void (*release)(struct wm_softc *);
 	int (*readreg_locked)(device_t, int, int, uint16_t *);
 	int (*writereg_locked)(device_t, int, int, uint16_t);
 	int reset_delay_us;
 	bool no_errprint;
 };
 struct wm_nvmop {
 	int (*acquire)(struct wm_softc *);
 	void (*release)(struct wm_softc *);
 	int (*read)(struct wm_softc *, int, int, uint16_t *);
 };
 /*
  * Software state per device.
  */
 struct wm_softc {
 	device_t sc_dev;		/* generic device information */
 	bus_space_tag_t sc_st;		/* bus space tag */
 	bus_space_handle_t sc_sh;	/* bus space handle */
 	bus_size_t sc_ss;		/* bus space size */
 	bus_space_tag_t sc_iot;		/* I/O space tag */
 	bus_space_handle_t sc_ioh;	/* I/O space handle */
 	bus_size_t sc_ios;		/* I/O space size */
 	bus_space_tag_t sc_flasht;	/* flash registers space tag */
 	bus_space_handle_t sc_flashh;	/* flash registers space handle */
 	bus_size_t sc_flashs;		/* flash registers space size */
 	off_t sc_flashreg_offset;	/*
 					 * offset to flash registers from
 					 * start of BAR
 					 */
 	bus_dma_tag_t sc_dmat;		/* bus DMA tag */
 	struct ethercom sc_ethercom;	/* ethernet common data */
 	struct mii_data sc_mii;		/* MII/media information */
 	pci_chipset_tag_t sc_pc;
 	pcitag_t sc_pcitag;
 	int sc_bus_speed;		/* PCI/PCIX bus speed */
 	int sc_pcixe_capoff;		/* PCI[Xe] capability reg offset */
 	uint16_t sc_pcidevid;		/* PCI device ID */
 	wm_chip_type sc_type;		/* MAC type */
 	int sc_rev;			/* MAC revision */
 	wm_phy_type sc_phytype;		/* PHY type */
 	uint8_t sc_sfptype;		/* SFP type */
 	uint32_t sc_mediatype;		/* Media type (Copper, Fiber, SERDES)*/
 #define	WM_MEDIATYPE_UNKNOWN		0x00
 #define	WM_MEDIATYPE_FIBER		0x01
 #define	WM_MEDIATYPE_COPPER		0x02
 #define	WM_MEDIATYPE_SERDES		0x03 /* Internal SERDES */
 	int sc_funcid;			/* unit number of the chip (0 to 3) */
 	int sc_flags;			/* flags; see below */
 	u_short sc_if_flags;		/* last if_flags */
 	int sc_ec_capenable;		/* last ec_capenable */
 	int sc_flowflags;		/* 802.3x flow control flags */
 	uint16_t eee_lp_ability;	/* EEE link partner's ability */
 	int sc_align_tweak;
 	void *sc_ihs[WM_MAX_NINTR];	/*
 					 * interrupt cookie.
 					 * - legacy and msi use sc_ihs[0] only
 					 * - msix use sc_ihs[0] to sc_ihs[nintrs-1]
 					 */
 	pci_intr_handle_t *sc_intrs;	/*
 					 * legacy and msi use sc_intrs[0] only
 					 * msix use sc_intrs[0] to sc_ihs[nintrs-1]
 					 */
 	int sc_nintrs;			/* number of interrupts */
 	int sc_link_intr_idx;		/* index of MSI-X tables */
 	callout_t sc_tick_ch;		/* tick callout */
 	bool sc_core_stopping;
 	int sc_nvm_ver_major;
 	int sc_nvm_ver_minor;
 	int sc_nvm_ver_build;
 	int sc_nvm_addrbits;		/* NVM address bits */
 	unsigned int sc_nvm_wordsize;	/* NVM word size */
 	int sc_ich8_flash_base;
 	int sc_ich8_flash_bank_size;
 	int sc_nvm_k1_enabled;
 	int sc_nqueues;
 	struct wm_queue *sc_queue;
 	u_int sc_tx_process_limit;	/* Tx proc. repeat limit in softint */
 	u_int sc_tx_intr_process_limit;	/* Tx proc. repeat limit in H/W intr */
 	u_int sc_rx_process_limit;	/* Rx proc. repeat limit in softint */
 	u_int sc_rx_intr_process_limit;	/* Rx proc. repeat limit in H/W intr */
 	struct workqueue *sc_queue_wq;
 	bool sc_txrx_use_workqueue;
 	int sc_affinity_offset;
 #ifdef WM_EVENT_COUNTERS
 	/* Event counters. */
 	struct evcnt sc_ev_linkintr;	/* Link interrupts */
 	/* WM_T_82542_2_1 only */
 	struct evcnt sc_ev_tx_xoff;	/* Tx PAUSE(!0) frames */
 	struct evcnt sc_ev_tx_xon;	/* Tx PAUSE(0) frames */
 	struct evcnt sc_ev_rx_xoff;	/* Rx PAUSE(!0) frames */
 	struct evcnt sc_ev_rx_xon;	/* Rx PAUSE(0) frames */
 	struct evcnt sc_ev_rx_macctl;	/* Rx Unsupported */
 #endif /* WM_EVENT_COUNTERS */
 	struct sysctllog *sc_sysctllog;
 	/* This variable are used only on the 82547. */
 	callout_t sc_txfifo_ch;		/* Tx FIFO stall work-around timer */
 	uint32_t sc_ctrl;		/* prototype CTRL register */
 #if 0
 	uint32_t sc_ctrl_ext;		/* prototype CTRL_EXT register */
 #endif
 	uint32_t sc_icr;		/* prototype interrupt bits */
 	uint32_t sc_itr_init;		/* prototype intr throttling reg */
 	uint32_t sc_tctl;		/* prototype TCTL register */
 	uint32_t sc_rctl;		/* prototype RCTL register */
 	uint32_t sc_txcw;		/* prototype TXCW register */
 	uint32_t sc_tipg;		/* prototype TIPG register */
 	uint32_t sc_fcrtl;		/* prototype FCRTL register */
 	uint32_t sc_pba;		/* prototype PBA register */
 	int sc_tbi_linkup;		/* TBI link status */
 	int sc_tbi_serdes_anegticks;	/* autonegotiation ticks */
 	int sc_tbi_serdes_ticks;	/* tbi ticks */
 	int sc_mchash_type;		/* multicast filter offset */
 	krndsource_t rnd_source;	/* random source */
 	struct if_percpuq *sc_ipq;	/* softint-based input queues */
 	kmutex_t *sc_core_lock;		/* lock for softc operations */
 	kmutex_t *sc_ich_phymtx;	/*
 					 * 82574/82583/ICH/PCH specific PHY
 					 * mutex. For 82574/82583, the mutex
 					 * is used for both PHY and NVM.
 					 */
 	kmutex_t *sc_ich_nvmmtx;	/* ICH/PCH specific NVM mutex */
 	struct wm_phyop phy;
 	struct wm_nvmop nvm;
 #ifdef WM_DEBUG
 	uint32_t sc_debug;
 #endif
 };
 #define WM_CORE_LOCK(_sc)						\
 	if ((_sc)->sc_core_lock) mutex_enter((_sc)->sc_core_lock)
 #define WM_CORE_UNLOCK(_sc)						\
 	if ((_sc)->sc_core_lock) mutex_exit((_sc)->sc_core_lock)
 #define WM_CORE_LOCKED(_sc)						\
 	(!(_sc)->sc_core_lock || mutex_owned((_sc)->sc_core_lock))
 #define	WM_RXCHAIN_RESET(rxq)						\
 do {									\
 	(rxq)->rxq_tailp = &(rxq)->rxq_head;				\
 	*(rxq)->rxq_tailp = NULL;					\
 	(rxq)->rxq_len = 0;						\
 } while (/*CONSTCOND*/0)
 #define	WM_RXCHAIN_LINK(rxq, m)						\
 do {									\
 	*(rxq)->rxq_tailp = (rxq)->rxq_tail = (m);			\
 	(rxq)->rxq_tailp = &(m)->m_next;				\
 } while (/*CONSTCOND*/0)
 #ifdef WM_EVENT_COUNTERS
 #ifdef __HAVE_ATOMIC64_LOADSTORE
 #define	WM_EVCNT_INCR(ev)						\
 	atomic_store_relaxed(&((ev)->ev_count),				\
 	    atomic_load_relaxed(&(ev)->ev_count) + 1)
 #define	WM_EVCNT_ADD(ev, val)						\
 	atomic_store_relaxed(&((ev)->ev_count),				\
 	    atomic_load_relaxed(&(ev)->ev_count) + (val))
 #else
 #define	WM_EVCNT_INCR(ev)						\
 	((ev)->ev_count)++
 #define	WM_EVCNT_ADD(ev, val)						\
 	(ev)->ev_count += (val)
 #endif
 #define WM_Q_EVCNT_INCR(qname, evname)			\
 	WM_EVCNT_INCR(&(qname)->qname##_ev_##evname)
 #define WM_Q_EVCNT_ADD(qname, evname, val)		\
 	WM_EVCNT_ADD(&(qname)->qname##_ev_##evname, (val))
 #else /* !WM_EVENT_COUNTERS */
 #define	WM_EVCNT_INCR(ev)	/* nothing */
 #define	WM_EVCNT_ADD(ev, val)	/* nothing */
 #define WM_Q_EVCNT_INCR(qname, evname)		/* nothing */
 #define WM_Q_EVCNT_ADD(qname, evname, val)	/* nothing */
 #endif /* !WM_EVENT_COUNTERS */
 #define	CSR_READ(sc, reg)						\
 	bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
 #define	CSR_WRITE(sc, reg, val)						\
 	bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
 #define	CSR_WRITE_FLUSH(sc)						\
 	(void)CSR_READ((sc), WMREG_STATUS)
 #define ICH8_FLASH_READ32(sc, reg)					\
 	bus_space_read_4((sc)->sc_flasht, (sc)->sc_flashh,		\
 	    (reg) + sc->sc_flashreg_offset)
 #define ICH8_FLASH_WRITE32(sc, reg, data)				\
 	bus_space_write_4((sc)->sc_flasht, (sc)->sc_flashh,		\
 	    (reg) + sc->sc_flashreg_offset, (data))
 #define ICH8_FLASH_READ16(sc, reg)					\
 	bus_space_read_2((sc)->sc_flasht, (sc)->sc_flashh,		\
 	    (reg) + sc->sc_flashreg_offset)
 #define ICH8_FLASH_WRITE16(sc, reg, data)				\
 	bus_space_write_2((sc)->sc_flasht, (sc)->sc_flashh,		\
 	    (reg) + sc->sc_flashreg_offset, (data))
 #define	WM_CDTXADDR(txq, x)	((txq)->txq_desc_dma + WM_CDTXOFF((txq), (x)))
 #define	WM_CDRXADDR(rxq, x)	((rxq)->rxq_desc_dma + WM_CDRXOFF((rxq), (x)))
 #define	WM_CDTXADDR_LO(txq, x)	(WM_CDTXADDR((txq), (x)) & 0xffffffffU)
 #define	WM_CDTXADDR_HI(txq, x)						\
 	(sizeof(bus_addr_t) == 8 ?					\
 	 (uint64_t)WM_CDTXADDR((txq), (x)) >> 32 : 0)
 #define	WM_CDRXADDR_LO(rxq, x)	(WM_CDRXADDR((rxq), (x)) & 0xffffffffU)
 #define	WM_CDRXADDR_HI(rxq, x)						\
 	(sizeof(bus_addr_t) == 8 ?					\
 	 (uint64_t)WM_CDRXADDR((rxq), (x)) >> 32 : 0)
 /*
  * Register read/write functions.
  * Other than CSR_{READ|WRITE}().
  */
 #if 0
 static inline uint32_t wm_io_read(struct wm_softc *, int);
 #endif
 static inline void wm_io_write(struct wm_softc *, int, uint32_t);
 static inline void wm_82575_write_8bit_ctlr_reg(struct wm_softc *, uint32_t,
     uint32_t, uint32_t);
 static inline void wm_set_dma_addr(volatile wiseman_addr_t *, bus_addr_t);
 /*
  * Descriptor sync/init functions.
  */
 static inline void wm_cdtxsync(struct wm_txqueue *, int, int, int);
 static inline void wm_cdrxsync(struct wm_rxqueue *, int, int);
 static inline void wm_init_rxdesc(struct wm_rxqueue *, int);
 /*
  * Device driver interface functions and commonly used functions.
  * match, attach, detach, init, start, stop, ioctl, watchdog and so on.
  */
 static const struct wm_product *wm_lookup(const struct pci_attach_args *);
 static int	wm_match(device_t, cfdata_t, void *);
 static void	wm_attach(device_t, device_t, void *);
 static int	wm_detach(device_t, int);
 static bool	wm_suspend(device_t, const pmf_qual_t *);
 static bool	wm_resume(device_t, const pmf_qual_t *);
 static void	wm_watchdog(struct ifnet *);
 static void	wm_watchdog_txq(struct ifnet *, struct wm_txqueue *,
     uint16_t *);
 static void	wm_watchdog_txq_locked(struct ifnet *, struct wm_txqueue *,
     uint16_t *);
 static void	wm_tick(void *);
 static int	wm_ifflags_cb(struct ethercom *);
 static int	wm_ioctl(struct ifnet *, u_long, void *);
 /* MAC address related */
 static uint16_t	wm_check_alt_mac_addr(struct wm_softc *);
 static int	wm_read_mac_addr(struct wm_softc *, uint8_t *);
 static void	wm_set_ral(struct wm_softc *, const uint8_t *, int);
 static uint32_t	wm_mchash(struct wm_softc *, const uint8_t *);
 static int	wm_rar_count(struct wm_softc *);
 static void	wm_set_filter(struct wm_softc *);
 /* Reset and init related */
 static void	wm_set_vlan(struct wm_softc *);
 static void	wm_set_pcie_completion_timeout(struct wm_softc *);
 static void	wm_get_auto_rd_done(struct wm_softc *);
 static void	wm_lan_init_done(struct wm_softc *);
 static void	wm_get_cfg_done(struct wm_softc *);
 static int	wm_phy_post_reset(struct wm_softc *);
 static int	wm_write_smbus_addr(struct wm_softc *);
 static int	wm_init_lcd_from_nvm(struct wm_softc *);
 static int	wm_oem_bits_config_ich8lan(struct wm_softc *, bool);
 static void	wm_initialize_hardware_bits(struct wm_softc *);
 static uint32_t	wm_rxpbs_adjust_82580(uint32_t);
 static int	wm_reset_phy(struct wm_softc *);
 static void	wm_flush_desc_rings(struct wm_softc *);
 static void	wm_reset(struct wm_softc *);
 static int	wm_add_rxbuf(struct wm_rxqueue *, int);
 static void	wm_rxdrain(struct wm_rxqueue *);
 static void	wm_init_rss(struct wm_softc *);
 static void	wm_adjust_qnum(struct wm_softc *, int);
 static inline bool	wm_is_using_msix(struct wm_softc *);
 static inline bool	wm_is_using_multiqueue(struct wm_softc *);
 static int	wm_softint_establish_queue(struct wm_softc *, int, int);
 static int	wm_setup_legacy(struct wm_softc *);
 static int	wm_setup_msix(struct wm_softc *);
 static int	wm_init(struct ifnet *);
 static int	wm_init_locked(struct ifnet *);
 static void	wm_init_sysctls(struct wm_softc *);
 static void	wm_unset_stopping_flags(struct wm_softc *);
 static void	wm_set_stopping_flags(struct wm_softc *);
 static void	wm_stop(struct ifnet *, int);
 static void	wm_stop_locked(struct ifnet *, bool, bool);
 static void	wm_dump_mbuf_chain(struct wm_softc *, struct mbuf *);
 static void	wm_82547_txfifo_stall(void *);
 static int	wm_82547_txfifo_bugchk(struct wm_softc *, struct mbuf *);
 static void	wm_itrs_writereg(struct wm_softc *, struct wm_queue *);
 /* DMA related */
 static int	wm_alloc_tx_descs(struct wm_softc *, struct wm_txqueue *);
 static void	wm_free_tx_descs(struct wm_softc *, struct wm_txqueue *);
 static void	wm_init_tx_descs(struct wm_softc *, struct wm_txqueue *);
 static void	wm_init_tx_regs(struct wm_softc *, struct wm_queue *,
     struct wm_txqueue *);
 static int	wm_alloc_rx_descs(struct wm_softc *, struct wm_rxqueue *);
 static void	wm_free_rx_descs(struct wm_softc *, struct wm_rxqueue *);
 static void	wm_init_rx_regs(struct wm_softc *, struct wm_queue *,
     struct wm_rxqueue *);
 static int	wm_alloc_tx_buffer(struct wm_softc *, struct wm_txqueue *);
 static void	wm_free_tx_buffer(struct wm_softc *, struct wm_txqueue *);
 static void	wm_init_tx_buffer(struct wm_softc *, struct wm_txqueue *);
 static int	wm_alloc_rx_buffer(struct wm_softc *, struct wm_rxqueue *);
 static void	wm_free_rx_buffer(struct wm_softc *, struct wm_rxqueue *);
 static int	wm_init_rx_buffer(struct wm_softc *, struct wm_rxqueue *);
 static void	wm_init_tx_queue(struct wm_softc *, struct wm_queue *,
     struct wm_txqueue *);
 static int	wm_init_rx_queue(struct wm_softc *, struct wm_queue *,
     struct wm_rxqueue *);
 static int	wm_alloc_txrx_queues(struct wm_softc *);
 static void	wm_free_txrx_queues(struct wm_softc *);
 static int	wm_init_txrx_queues(struct wm_softc *);
 /* Start */
 static void	wm_tx_offload(struct wm_softc *, struct wm_txqueue *,
     struct wm_txsoft *, uint32_t *, uint8_t *);
 static inline int	wm_select_txqueue(struct ifnet *, struct mbuf *);
 static void	wm_start(struct ifnet *);
 static void	wm_start_locked(struct ifnet *);
 static int	wm_transmit(struct ifnet *, struct mbuf *);
 static void	wm_transmit_locked(struct ifnet *, struct wm_txqueue *);
 static void	wm_send_common_locked(struct ifnet *, struct wm_txqueue *,
 		    bool);
 static void	wm_nq_tx_offload(struct wm_softc *, struct wm_txqueue *,
     struct wm_txsoft *, uint32_t *, uint32_t *, bool *);
 static void	wm_nq_start(struct ifnet *);
 static void	wm_nq_start_locked(struct ifnet *);
 static int	wm_nq_transmit(struct ifnet *, struct mbuf *);
 static void	wm_nq_transmit_locked(struct ifnet *, struct wm_txqueue *);
 static void	wm_nq_send_common_locked(struct ifnet *, struct wm_txqueue *,
 		    bool);
 static void	wm_deferred_start_locked(struct wm_txqueue *);
 static void	wm_handle_queue(void *);
 static void	wm_handle_queue_work(struct work *, void *);
 /* Interrupt */
 static bool	wm_txeof(struct wm_txqueue *, u_int);
 static bool	wm_rxeof(struct wm_rxqueue *, u_int);
 static void	wm_linkintr_gmii(struct wm_softc *, uint32_t);
 static void	wm_linkintr_tbi(struct wm_softc *, uint32_t);
 static void	wm_linkintr_serdes(struct wm_softc *, uint32_t);
 static void	wm_linkintr(struct wm_softc *, uint32_t);
 static int	wm_intr_legacy(void *);
 static inline void	wm_txrxintr_disable(struct wm_queue *);
 static inline void	wm_txrxintr_enable(struct wm_queue *);
 static void	wm_itrs_calculate(struct wm_softc *, struct wm_queue *);
 static int	wm_txrxintr_msix(void *);
 static int	wm_linkintr_msix(void *);
 /*
  * Media related.
  * GMII, SGMII, TBI, SERDES and SFP.
  */
 /* Common */
 static void	wm_tbi_serdes_set_linkled(struct wm_softc *);
 /* GMII related */
 static void	wm_gmii_reset(struct wm_softc *);
 static void	wm_gmii_setup_phytype(struct wm_softc *, uint32_t, uint16_t);
 static int	wm_get_phy_id_82575(struct wm_softc *);
 static void	wm_gmii_mediainit(struct wm_softc *, pci_product_id_t);
 static int	wm_gmii_mediachange(struct ifnet *);
 static void	wm_gmii_mediastatus(struct ifnet *, struct ifmediareq *);
 static void	wm_i82543_mii_sendbits(struct wm_softc *, uint32_t, int);
 static uint16_t	wm_i82543_mii_recvbits(struct wm_softc *);
 static int	wm_gmii_i82543_readreg(device_t, int, int, uint16_t *);
 static int	wm_gmii_i82543_writereg(device_t, int, int, uint16_t);
 static int	wm_gmii_mdic_readreg(device_t, int, int, uint16_t *);
 static int	wm_gmii_mdic_writereg(device_t, int, int, uint16_t);
 static int	wm_gmii_i82544_readreg(device_t, int, int, uint16_t *);
 static int	wm_gmii_i82544_readreg_locked(device_t, int, int, uint16_t *);
 static int	wm_gmii_i82544_writereg(device_t, int, int, uint16_t);
 static int	wm_gmii_i82544_writereg_locked(device_t, int, int, uint16_t);
 static int	wm_gmii_i80003_readreg(device_t, int, int, uint16_t *);
 static int	wm_gmii_i80003_writereg(device_t, int, int, uint16_t);
 static int	wm_gmii_bm_readreg(device_t, int, int, uint16_t *);
 static int	wm_gmii_bm_writereg(device_t, int, int, uint16_t);
 static int	wm_enable_phy_wakeup_reg_access_bm(device_t, uint16_t *);
 static int	wm_disable_phy_wakeup_reg_access_bm(device_t, uint16_t *);
 static int	wm_access_phy_wakeup_reg_bm(device_t, int, int16_t *, int,
 	bool);
 static int	wm_gmii_hv_readreg(device_t, int, int, uint16_t *);
 static int	wm_gmii_hv_readreg_locked(device_t, int, int, uint16_t *);
 static int	wm_gmii_hv_writereg(device_t, int, int, uint16_t);
 static int	wm_gmii_hv_writereg_locked(device_t, int, int, uint16_t);
 static int	wm_gmii_82580_readreg(device_t, int, int, uint16_t *);
 static int	wm_gmii_82580_writereg(device_t, int, int, uint16_t);
 static int	wm_gmii_gs40g_readreg(device_t, int, int, uint16_t *);
 static int	wm_gmii_gs40g_writereg(device_t, int, int, uint16_t);
 static void	wm_gmii_statchg(struct ifnet *);
 /*
  * kumeran related (80003, ICH* and PCH*).
  * These functions are not for accessing MII registers but for accessing
  * kumeran specific registers.
  */
 static int	wm_kmrn_readreg(struct wm_softc *, int, uint16_t *);
 static int	wm_kmrn_readreg_locked(struct wm_softc *, int, uint16_t *);
 static int	wm_kmrn_writereg(struct wm_softc *, int, uint16_t);
 static int	wm_kmrn_writereg_locked(struct wm_softc *, int, uint16_t);
 /* EMI register related */
 static int	wm_access_emi_reg_locked(device_t, int, uint16_t *, bool);
 static int	wm_read_emi_reg_locked(device_t, int, uint16_t *);
 static int	wm_write_emi_reg_locked(device_t, int, uint16_t);
 /* SGMII */
 static bool	wm_sgmii_uses_mdio(struct wm_softc *);
 static void	wm_sgmii_sfp_preconfig(struct wm_softc *);
 static int	wm_sgmii_readreg(device_t, int, int, uint16_t *);
 static int	wm_sgmii_readreg_locked(device_t, int, int, uint16_t *);
 static int	wm_sgmii_writereg(device_t, int, int, uint16_t);
 static int	wm_sgmii_writereg_locked(device_t, int, int, uint16_t);
 /* TBI related */
 static bool	wm_tbi_havesignal(struct wm_softc *, uint32_t);
 static void	wm_tbi_mediainit(struct wm_softc *);
 static int	wm_tbi_mediachange(struct ifnet *);
 static void	wm_tbi_mediastatus(struct ifnet *, struct ifmediareq *);
 static int	wm_check_for_link(struct wm_softc *);
 static void	wm_tbi_tick(struct wm_softc *);
 /* SERDES related */
 static void	wm_serdes_power_up_link_82575(struct wm_softc *);
 static int	wm_serdes_mediachange(struct ifnet *);
 static void	wm_serdes_mediastatus(struct ifnet *, struct ifmediareq *);
 static void	wm_serdes_tick(struct wm_softc *);
 /* SFP related */
 static int	wm_sfp_read_data_byte(struct wm_softc *, uint16_t, uint8_t *);
 static uint32_t	wm_sfp_get_media_type(struct wm_softc *);
 /*
  * NVM related.
  * Microwire, SPI (w/wo EERD) and Flash.
  */
 /* Misc functions */
 static void	wm_eeprom_sendbits(struct wm_softc *, uint32_t, int);
 static void	wm_eeprom_recvbits(struct wm_softc *, uint32_t *, int);
 static int	wm_nvm_set_addrbits_size_eecd(struct wm_softc *);
 /* Microwire */
 static int	wm_nvm_read_uwire(struct wm_softc *, int, int, uint16_t *);
 /* SPI */
 static int	wm_nvm_ready_spi(struct wm_softc *);
 static int	wm_nvm_read_spi(struct wm_softc *, int, int, uint16_t *);
 /* Using with EERD */
 static int	wm_poll_eerd_eewr_done(struct wm_softc *, int);
 static int	wm_nvm_read_eerd(struct wm_softc *, int, int, uint16_t *);
 /* Flash */
 static int	wm_nvm_valid_bank_detect_ich8lan(struct wm_softc *,
     unsigned int *);
 static int32_t	wm_ich8_cycle_init(struct wm_softc *);
 static int32_t	wm_ich8_flash_cycle(struct wm_softc *, uint32_t);
 static int32_t	wm_read_ich8_data(struct wm_softc *, uint32_t, uint32_t,
     uint32_t *);
 static int32_t	wm_read_ich8_byte(struct wm_softc *, uint32_t, uint8_t *);
 static int32_t	wm_read_ich8_word(struct wm_softc *, uint32_t, uint16_t *);
 static int32_t	wm_read_ich8_dword(struct wm_softc *, uint32_t, uint32_t *);
 static int	wm_nvm_read_ich8(struct wm_softc *, int, int, uint16_t *);
 static int	wm_nvm_read_spt(struct wm_softc *, int, int, uint16_t *);
 /* iNVM */
 static int	wm_nvm_read_word_invm(struct wm_softc *, uint16_t, uint16_t *);
 static int	wm_nvm_read_invm(struct wm_softc *, int, int, uint16_t *);
 /* Lock, detecting NVM type, validate checksum and read */
 static int	wm_nvm_is_onboard_eeprom(struct wm_softc *);
 static int	wm_nvm_flash_presence_i210(struct wm_softc *);
 static int	wm_nvm_validate_checksum(struct wm_softc *);
 static void	wm_nvm_version_invm(struct wm_softc *);
 static void	wm_nvm_version(struct wm_softc *);
 static int	wm_nvm_read(struct wm_softc *, int, int, uint16_t *);
 /*
  * Hardware semaphores.
  * Very complexed...
  */
 static int	wm_get_null(struct wm_softc *);
 static void	wm_put_null(struct wm_softc *);
 static int	wm_get_eecd(struct wm_softc *);
 static void	wm_put_eecd(struct wm_softc *);
 static int	wm_get_swsm_semaphore(struct wm_softc *); /* 8257[123] */
 static void	wm_put_swsm_semaphore(struct wm_softc *);
 static int	wm_get_swfw_semaphore(struct wm_softc *, uint16_t);
 static void	wm_put_swfw_semaphore(struct wm_softc *, uint16_t);
 static int	wm_get_nvm_80003(struct wm_softc *);
 static void	wm_put_nvm_80003(struct wm_softc *);
 static int	wm_get_nvm_82571(struct wm_softc *);
 static void	wm_put_nvm_82571(struct wm_softc *);
 static int	wm_get_phy_82575(struct wm_softc *);
 static void	wm_put_phy_82575(struct wm_softc *);
 static int	wm_get_swfwhw_semaphore(struct wm_softc *); /* For 574/583 */
 static void	wm_put_swfwhw_semaphore(struct wm_softc *);
 static int	wm_get_swflag_ich8lan(struct wm_softc *);	/* For PHY */
 static void	wm_put_swflag_ich8lan(struct wm_softc *);
 static int	wm_get_nvm_ich8lan(struct wm_softc *);
 static void	wm_put_nvm_ich8lan(struct wm_softc *);
 static int	wm_get_hw_semaphore_82573(struct wm_softc *);
 static void	wm_put_hw_semaphore_82573(struct wm_softc *);
 /*
  * Management mode and power management related subroutines.
  * BMC, AMT, suspend/resume and EEE.
  */
 #if 0
 static int	wm_check_mng_mode(struct wm_softc *);
 static int	wm_check_mng_mode_ich8lan(struct wm_softc *);
 static int	wm_check_mng_mode_82574(struct wm_softc *);
 static int	wm_check_mng_mode_generic(struct wm_softc *);
 #endif
 static int	wm_enable_mng_pass_thru(struct wm_softc *);
 static bool	wm_phy_resetisblocked(struct wm_softc *);
 static void	wm_get_hw_control(struct wm_softc *);
 static void	wm_release_hw_control(struct wm_softc *);
 static void	wm_gate_hw_phy_config_ich8lan(struct wm_softc *, bool);
 static int	wm_init_phy_workarounds_pchlan(struct wm_softc *);
 static void	wm_init_manageability(struct wm_softc *);
 static void	wm_release_manageability(struct wm_softc *);
 static void	wm_get_wakeup(struct wm_softc *);
 static int	wm_ulp_disable(struct wm_softc *);
 static int	wm_enable_phy_wakeup(struct wm_softc *);
 static void	wm_igp3_phy_powerdown_workaround_ich8lan(struct wm_softc *);
 static void	wm_suspend_workarounds_ich8lan(struct wm_softc *);
 static int	wm_resume_workarounds_pchlan(struct wm_softc *);
 static void	wm_enable_wakeup(struct wm_softc *);
 static void	wm_disable_aspm(struct wm_softc *);
 /* LPLU (Low Power Link Up) */
 static void	wm_lplu_d0_disable(struct wm_softc *);
 /* EEE */
 static int	wm_set_eee_i350(struct wm_softc *);
 static int	wm_set_eee_pchlan(struct wm_softc *);
 static int	wm_set_eee(struct wm_softc *);
 /*
  * Workarounds (mainly PHY related).
  * Basically, PHY's workarounds are in the PHY drivers.
  */
 static int	wm_kmrn_lock_loss_workaround_ich8lan(struct wm_softc *);
 static void	wm_gig_downshift_workaround_ich8lan(struct wm_softc *);
 static int	wm_hv_phy_workarounds_ich8lan(struct wm_softc *);
 static void	wm_copy_rx_addrs_to_phy_ich8lan(struct wm_softc *);
 static void	wm_copy_rx_addrs_to_phy_ich8lan_locked(struct wm_softc *);
 static int	wm_lv_jumbo_workaround_ich8lan(struct wm_softc *, bool);
 static int	wm_lv_phy_workarounds_ich8lan(struct wm_softc *);
 static int	wm_k1_workaround_lpt_lp(struct wm_softc *, bool);
 static int	wm_k1_gig_workaround_hv(struct wm_softc *, int);
 static int	wm_k1_workaround_lv(struct wm_softc *);
 static int	wm_link_stall_workaround_hv(struct wm_softc *);
 static int	wm_set_mdio_slow_mode_hv(struct wm_softc *);
 static void	wm_configure_k1_ich8lan(struct wm_softc *, int);
 static void	wm_reset_init_script_82575(struct wm_softc *);
 static void	wm_reset_mdicnfg_82580(struct wm_softc *);
 static bool	wm_phy_is_accessible_pchlan(struct wm_softc *);
 static void	wm_toggle_lanphypc_pch_lpt(struct wm_softc *);
 static int	wm_platform_pm_pch_lpt(struct wm_softc *, bool);
 static int	wm_pll_workaround_i210(struct wm_softc *);
 static void	wm_legacy_irq_quirk_spt(struct wm_softc *);
 static bool	wm_phy_need_linkdown_discard(struct wm_softc *);
 static void	wm_set_linkdown_discard(struct wm_softc *);
 static void	wm_clear_linkdown_discard(struct wm_softc *);
 static int	wm_sysctl_tdh_handler(SYSCTLFN_PROTO);
 static int	wm_sysctl_tdt_handler(SYSCTLFN_PROTO);
 #ifdef WM_DEBUG
 static int	wm_sysctl_debug(SYSCTLFN_PROTO);
 #endif
 CFATTACH_DECL3_NEW(wm, sizeof(struct wm_softc),
     wm_match, wm_attach, wm_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN);
 /*
  * Devices supported by this driver.
  */
 static const struct wm_product {
 	pci_vendor_id_t		wmp_vendor;
 @@ -9576,1999 +9576,1998 @@ wm_linkintr_gmii(struct wm_softc *sc, ui
 		uint32_t speed = __SHIFTOUT(status, STATUS_SPEED);
 		bool fdx;
 		uint16_t emi_addr, emi_val;
 		tipg_reg = CSR_READ(sc, WMREG_TIPG);
 		tipg_reg &= ~TIPG_IPGT_MASK;
 		fdx = status & STATUS_FD;
 		if (!fdx && (speed == STATUS_SPEED_10)) {
 			tipg_reg |= 0xff;
 			/* Reduce Rx latency in analog PHY */
 			emi_val = 0;
 		} else if ((sc->sc_type >= WM_T_PCH_SPT) &&
 		    fdx && speed != STATUS_SPEED_1000) {
 			tipg_reg |= 0xc;
 			emi_val = 1;
 		} else {
 			/* Roll back the default values */
 			tipg_reg |= 0x08;
 			emi_val = 1;
+		}
 		CSR_WRITE(sc, WMREG_TIPG, tipg_reg);
 		rv = sc->phy.acquire(sc);
 		if (rv)
 			return;
 		if (sc->sc_type == WM_T_PCH2)
 			emi_addr = I82579_RX_CONFIG;
 		else
 			emi_addr = I217_RX_CONFIG;
 		rv = wm_write_emi_reg_locked(dev, emi_addr, emi_val);
 		if (sc->sc_type >= WM_T_PCH_LPT) {
 			uint16_t phy_reg;
 			sc->phy.readreg_locked(dev, 2,
 			    I217_PLL_CLOCK_GATE_REG, &phy_reg);
 			phy_reg &= ~I217_PLL_CLOCK_GATE_MASK;
 			if (speed == STATUS_SPEED_100
 			    || speed == STATUS_SPEED_10)
 				phy_reg |= 0x3e8;
 			else
 				phy_reg |= 0xfa;
 			sc->phy.writereg_locked(dev, 2,
 			    I217_PLL_CLOCK_GATE_REG, phy_reg);
 			if (speed == STATUS_SPEED_1000) {
 				sc->phy.readreg_locked(dev, 2,
 				    HV_PM_CTRL, &phy_reg);
 				phy_reg |= HV_PM_CTRL_K1_CLK_REQ;
 				sc->phy.writereg_locked(dev, 2,
 				    HV_PM_CTRL, phy_reg);
+			}
+		}
 		sc->phy.release(sc);
 		if (rv)
 			return;
 		if (sc->sc_type >= WM_T_PCH_SPT) {
 			uint16_t data, ptr_gap;
 			if (speed == STATUS_SPEED_1000) {
 				rv = sc->phy.acquire(sc);
 				if (rv)
 					return;
 				rv = sc->phy.readreg_locked(dev, 2,
 				    I82579_UNKNOWN1, &data);
 				if (rv) {
 					sc->phy.release(sc);
 					return;
+				}
 				ptr_gap = (data & (0x3ff << 2)) >> 2;
 				if (ptr_gap < 0x18) {
 					data &= ~(0x3ff << 2);
 					data |= (0x18 << 2);
 					rv = sc->phy.writereg_locked(dev,
 , I82579_UNKNOWN1, data);
+				}
 				sc->phy.release(sc);
 				if (rv)
 					return;
 			} else {
 				rv = sc->phy.acquire(sc);
 				if (rv)
 					return;
 				rv = sc->phy.writereg_locked(dev, 2,
 				    I82579_UNKNOWN1, 0xc023);
 				sc->phy.release(sc);
 				if (rv)
 					return;
+			}
+		}
+	}
 	/*
 	 * I217 Packet Loss issue:
 	 * ensure that FEXTNVM4 Beacon Duration is set correctly
 	 * on power up.
 	 * Set the Beacon Duration for I217 to 8 usec
 	 */
 	if (sc->sc_type >= WM_T_PCH_LPT) {
 		reg = CSR_READ(sc, WMREG_FEXTNVM4);
 		reg &= ~FEXTNVM4_BEACON_DURATION;
 		reg |= FEXTNVM4_BEACON_DURATION_8US;
 		CSR_WRITE(sc, WMREG_FEXTNVM4, reg);
+	}
 	/* Work-around I218 hang issue */
 	if ((sc->sc_pcidevid == PCI_PRODUCT_INTEL_I218_LM) ||
 	    (sc->sc_pcidevid == PCI_PRODUCT_INTEL_I218_V) ||
 	    (sc->sc_pcidevid == PCI_PRODUCT_INTEL_I218_LM3) ||
 	    (sc->sc_pcidevid == PCI_PRODUCT_INTEL_I218_V3))
 		wm_k1_workaround_lpt_lp(sc, link);
 	if (sc->sc_type >= WM_T_PCH_LPT) {
 		/*
 		 * Set platform power management values for Latency
 		 * Tolerance Reporting (LTR)
 		 */
 		wm_platform_pm_pch_lpt(sc,
 		    ((sc->sc_mii.mii_media_status & IFM_ACTIVE) != 0));
+	}
 	/* Clear link partner's EEE ability */
 	sc->eee_lp_ability = 0;
 	/* FEXTNVM6 K1-off workaround */
 	if (sc->sc_type == WM_T_PCH_SPT) {
 		reg = CSR_READ(sc, WMREG_FEXTNVM6);
 		if (CSR_READ(sc, WMREG_PCIEANACFG) & FEXTNVM6_K1_OFF_ENABLE)
 			reg |= FEXTNVM6_K1_OFF_ENABLE;
 		else
 			reg &= ~FEXTNVM6_K1_OFF_ENABLE;
 		CSR_WRITE(sc, WMREG_FEXTNVM6, reg);
+	}
 	if (!link)
 		return;
 	switch (sc->sc_type) {
 	case WM_T_PCH2:
 		wm_k1_workaround_lv(sc);
 		/* FALLTHROUGH */
 	case WM_T_PCH:
 		if (sc->sc_phytype == WMPHY_82578)
 			wm_link_stall_workaround_hv(sc);
 		break;
 	default:
 		break;
+	}
 	/* Enable/Disable EEE after link up */
 	if (sc->sc_phytype > WMPHY_82579)
 		wm_set_eee_pchlan(sc);
+}
 /*
  * wm_linkintr_tbi:
+ *
  *	Helper; handle link interrupts for TBI mode.
  */
 static void
 wm_linkintr_tbi(struct wm_softc *sc, uint32_t icr)
+{
 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
 	uint32_t status;
 	DPRINTF(sc, WM_DEBUG_LINK, ("%s: %s:\n", device_xname(sc->sc_dev),
 		__func__));
 	status = CSR_READ(sc, WMREG_STATUS);
 	if (icr & ICR_LSC) {
 		wm_check_for_link(sc);
 		if (status & STATUS_LU) {
 			DPRINTF(sc, WM_DEBUG_LINK, ("%s: LINK: LSC -> up %s\n",
 				device_xname(sc->sc_dev),
 				(status & STATUS_FD) ? "FDX" : "HDX"));
 			/*
 			 * NOTE: CTRL will update TFCE and RFCE automatically,
 			 * so we should update sc->sc_ctrl
 			 */
 			sc->sc_ctrl = CSR_READ(sc, WMREG_CTRL);
 			sc->sc_tctl &= ~TCTL_COLD(0x3ff);
 			sc->sc_fcrtl &= ~FCRTL_XONE;
 			if (status & STATUS_FD)
 				sc->sc_tctl |=
 				    TCTL_COLD(TX_COLLISION_DISTANCE_FDX);
 			else
 				sc->sc_tctl |=
 				    TCTL_COLD(TX_COLLISION_DISTANCE_HDX);
 			if (sc->sc_ctrl & CTRL_TFCE)
 				sc->sc_fcrtl |= FCRTL_XONE;
 			CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl);
 			CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ?
 			    WMREG_OLD_FCRTL : WMREG_FCRTL, sc->sc_fcrtl);
 			sc->sc_tbi_linkup = 1;
 			if_link_state_change(ifp, LINK_STATE_UP);
 		} else {
 			DPRINTF(sc, WM_DEBUG_LINK, ("%s: LINK: LSC -> down\n",
 				device_xname(sc->sc_dev)));
 			sc->sc_tbi_linkup = 0;
 			if_link_state_change(ifp, LINK_STATE_DOWN);
+		}
 		/* Update LED */
 		wm_tbi_serdes_set_linkled(sc);
 	} else if (icr & ICR_RXSEQ)
 		DPRINTF(sc, WM_DEBUG_LINK, ("%s: LINK: Receive sequence error\n",
 			device_xname(sc->sc_dev)));
+}
 /*
  * wm_linkintr_serdes:
+ *
  *	Helper; handle link interrupts for TBI mode.
  */
 static void
 wm_linkintr_serdes(struct wm_softc *sc, uint32_t icr)
+{
 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
 	struct mii_data *mii = &sc->sc_mii;
 	struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
 	uint32_t pcs_adv, pcs_lpab, reg;
 	DPRINTF(sc, WM_DEBUG_LINK, ("%s: %s:\n", device_xname(sc->sc_dev),
 		__func__));
 	if (icr & ICR_LSC) {
 		/* Check PCS */
 		reg = CSR_READ(sc, WMREG_PCS_LSTS);
 		if ((reg & PCS_LSTS_LINKOK) != 0) {
 			DPRINTF(sc, WM_DEBUG_LINK, ("%s: LINK: LSC -> up\n",
 				device_xname(sc->sc_dev)));
 			mii->mii_media_status |= IFM_ACTIVE;
 			sc->sc_tbi_linkup = 1;
 			if_link_state_change(ifp, LINK_STATE_UP);
 		} else {
 			DPRINTF(sc, WM_DEBUG_LINK, ("%s: LINK: LSC -> down\n",
 				device_xname(sc->sc_dev)));
 			mii->mii_media_status |= IFM_NONE;
 			sc->sc_tbi_linkup = 0;
 			if_link_state_change(ifp, LINK_STATE_DOWN);
 			wm_tbi_serdes_set_linkled(sc);
 			return;
+		}
 		mii->mii_media_active |= IFM_1000_SX;
 		if ((reg & PCS_LSTS_FDX) != 0)
 			mii->mii_media_active |= IFM_FDX;
 		else
 			mii->mii_media_active |= IFM_HDX;
 		if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) {
 			/* Check flow */
 			reg = CSR_READ(sc, WMREG_PCS_LSTS);
 			if ((reg & PCS_LSTS_AN_COMP) == 0) {
 				DPRINTF(sc, WM_DEBUG_LINK,
 				    ("XXX LINKOK but not ACOMP\n"));
 				return;
+			}
 			pcs_adv = CSR_READ(sc, WMREG_PCS_ANADV);
 			pcs_lpab = CSR_READ(sc, WMREG_PCS_LPAB);
 			DPRINTF(sc, WM_DEBUG_LINK,
 			    ("XXX AN result %08x, %08x\n", pcs_adv, pcs_lpab));
 			if ((pcs_adv & TXCW_SYM_PAUSE)
 			    && (pcs_lpab & TXCW_SYM_PAUSE)) {
 				mii->mii_media_active |= IFM_FLOW
 				    | IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE;
 			} else if (((pcs_adv & TXCW_SYM_PAUSE) == 0)
 			    && (pcs_adv & TXCW_ASYM_PAUSE)
 			    && (pcs_lpab & TXCW_SYM_PAUSE)
 			    && (pcs_lpab & TXCW_ASYM_PAUSE))
 				mii->mii_media_active |= IFM_FLOW
 				    | IFM_ETH_TXPAUSE;
 			else if ((pcs_adv & TXCW_SYM_PAUSE)
 			    && (pcs_adv & TXCW_ASYM_PAUSE)
 			    && ((pcs_lpab & TXCW_SYM_PAUSE) == 0)
 			    && (pcs_lpab & TXCW_ASYM_PAUSE))
 				mii->mii_media_active |= IFM_FLOW
 				    | IFM_ETH_RXPAUSE;
+		}
 		/* Update LED */
 		wm_tbi_serdes_set_linkled(sc);
 	} else
 		DPRINTF(sc, WM_DEBUG_LINK, ("%s: LINK: Receive sequence error\n",
 		    device_xname(sc->sc_dev)));
+}
 /*
  * wm_linkintr:
+ *
  *	Helper; handle link interrupts.
  */
 static void
 wm_linkintr(struct wm_softc *sc, uint32_t icr)
+{
 	KASSERT(WM_CORE_LOCKED(sc));
 	if (sc->sc_flags & WM_F_HAS_MII)
 		wm_linkintr_gmii(sc, icr);
 	else if ((sc->sc_mediatype == WM_MEDIATYPE_SERDES)
 	    && ((sc->sc_type >= WM_T_82575) && (sc->sc_type <= WM_T_I211)))
 		wm_linkintr_serdes(sc, icr);
 	else
 		wm_linkintr_tbi(sc, icr);
+}
 static inline void
 wm_sched_handle_queue(struct wm_softc *sc, struct wm_queue *wmq)
+{
 	if (wmq->wmq_txrx_use_workqueue)
 		workqueue_enqueue(sc->sc_queue_wq, &wmq->wmq_cookie, curcpu());
 	else
 		softint_schedule(wmq->wmq_si);
+}
 static inline void
 wm_legacy_intr_disable(struct wm_softc *sc)
+{
 	CSR_WRITE(sc, WMREG_IMC, 0xffffffffU);
+}
 static inline void
 wm_legacy_intr_enable(struct wm_softc *sc)
+{
 	CSR_WRITE(sc, WMREG_IMS, sc->sc_icr);
+}
 /*
  * wm_intr_legacy:
+ *
  *	Interrupt service routine for INTx and MSI.
  */
 static int
 wm_intr_legacy(void *arg)
+{
 	struct wm_softc *sc = arg;
 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
 	struct wm_queue *wmq = &sc->sc_queue[0];
 	struct wm_txqueue *txq = &wmq->wmq_txq;
 	struct wm_rxqueue *rxq = &wmq->wmq_rxq;
 	u_int txlimit = sc->sc_tx_intr_process_limit;
 	u_int rxlimit = sc->sc_rx_intr_process_limit;
 	uint32_t icr, rndval = 0;
 	bool more = false;
 	icr = CSR_READ(sc, WMREG_ICR);
 	if ((icr & sc->sc_icr) == 0)
 		return 0;
 	DPRINTF(sc, WM_DEBUG_TX,
 	    ("%s: INTx: got intr\n",device_xname(sc->sc_dev)));
 	if (rndval == 0)
 		rndval = icr;
 	mutex_enter(rxq->rxq_lock);
 	if (rxq->rxq_stopping) {
 		mutex_exit(rxq->rxq_lock);
 		return 1;
+	}
 #if defined(WM_DEBUG) || defined(WM_EVENT_COUNTERS)
 	if (icr & (ICR_RXDMT0 | ICR_RXT0)) {
 		DPRINTF(sc, WM_DEBUG_RX,
 		    ("%s: RX: got Rx intr 0x%08x\n",
 			device_xname(sc->sc_dev),
 			icr & (uint32_t)(ICR_RXDMT0 | ICR_RXT0)));
 		WM_Q_EVCNT_INCR(rxq, intr);
+	}
 #endif
 	/*
 	 * wm_rxeof() does *not* call upper layer functions directly,
 	 * as if_percpuq_enqueue() just call softint_schedule().
 	 * So, we can call wm_rxeof() in interrupt context.
 	 */
 	more = wm_rxeof(rxq, rxlimit);
 	mutex_exit(rxq->rxq_lock);
 	mutex_enter(txq->txq_lock);
 	if (txq->txq_stopping) {
 		mutex_exit(txq->txq_lock);
 		return 1;
+	}
 #if defined(WM_DEBUG) || defined(WM_EVENT_COUNTERS)
 	if (icr & ICR_TXDW) {
 		DPRINTF(sc, WM_DEBUG_TX,
 		    ("%s: TX: got TXDW interrupt\n",
 			device_xname(sc->sc_dev)));
 		WM_Q_EVCNT_INCR(txq, txdw);
+	}
 #endif
 	more |= wm_txeof(txq, txlimit);
 	if (!IF_IS_EMPTY(&ifp->if_snd))
 		more = true;
 	mutex_exit(txq->txq_lock);
 	WM_CORE_LOCK(sc);
 	if (sc->sc_core_stopping) {
 		WM_CORE_UNLOCK(sc);
 		return 1;
+	}
 	if (icr & (ICR_LSC | ICR_RXSEQ)) {
 		WM_EVCNT_INCR(&sc->sc_ev_linkintr);
 		wm_linkintr(sc, icr);
+	}
 	if ((icr & ICR_GPI(0)) != 0)
 		device_printf(sc->sc_dev, "got module interrupt\n");
 	WM_CORE_UNLOCK(sc);
 	if (icr & ICR_RXO) {
 #if defined(WM_DEBUG)
 		log(LOG_WARNING, "%s: Receive overrun\n",
 		    device_xname(sc->sc_dev));
 #endif /* defined(WM_DEBUG) */
+	}
 	rnd_add_uint32(&sc->rnd_source, rndval);
 	if (more) {
 		/* Try to get more packets going. */
 		wm_legacy_intr_disable(sc);
 		wmq->wmq_txrx_use_workqueue = sc->sc_txrx_use_workqueue;
 		wm_sched_handle_queue(sc, wmq);
+	}
 	return 1;
+}
 static inline void
 wm_txrxintr_disable(struct wm_queue *wmq)
+{
 	struct wm_softc *sc = wmq->wmq_txq.txq_sc;
 	if (__predict_false(!wm_is_using_msix(sc))) {
 		return wm_legacy_intr_disable(sc);
+	}
 	if (sc->sc_type == WM_T_82574)
 		CSR_WRITE(sc, WMREG_IMC,
 		    ICR_TXQ(wmq->wmq_id) | ICR_RXQ(wmq->wmq_id));
 	else if (sc->sc_type == WM_T_82575)
 		CSR_WRITE(sc, WMREG_EIMC,
 		    EITR_TX_QUEUE(wmq->wmq_id) | EITR_RX_QUEUE(wmq->wmq_id));
 	else
 		CSR_WRITE(sc, WMREG_EIMC, 1 << wmq->wmq_intr_idx);
+}
 static inline void
 wm_txrxintr_enable(struct wm_queue *wmq)
+{
 	struct wm_softc *sc = wmq->wmq_txq.txq_sc;
 	wm_itrs_calculate(sc, wmq);
 	if (__predict_false(!wm_is_using_msix(sc))) {
 		return wm_legacy_intr_enable(sc);
+	}
 	/*
 	 * ICR_OTHER which is disabled in wm_linkintr_msix() is enabled here.
 	 * There is no need to care about which of RXQ(0) and RXQ(1) enable
 	 * ICR_OTHER in first, because each RXQ/TXQ interrupt is disabled
 	 * while each wm_handle_queue(wmq) is runnig.
 	 */
 	if (sc->sc_type == WM_T_82574)
 		CSR_WRITE(sc, WMREG_IMS,
 		    ICR_TXQ(wmq->wmq_id) | ICR_RXQ(wmq->wmq_id) | ICR_OTHER);
 	else if (sc->sc_type == WM_T_82575)
 		CSR_WRITE(sc, WMREG_EIMS,
 		    EITR_TX_QUEUE(wmq->wmq_id) | EITR_RX_QUEUE(wmq->wmq_id));
 	else
 		CSR_WRITE(sc, WMREG_EIMS, 1 << wmq->wmq_intr_idx);
+}
 static int
 wm_txrxintr_msix(void *arg)
+{
 	struct wm_queue *wmq = arg;
 	struct wm_txqueue *txq = &wmq->wmq_txq;
 	struct wm_rxqueue *rxq = &wmq->wmq_rxq;
 	struct wm_softc *sc = txq->txq_sc;
 	u_int txlimit = sc->sc_tx_intr_process_limit;
 	u_int rxlimit = sc->sc_rx_intr_process_limit;
 	bool txmore;
 	bool rxmore;
 	KASSERT(wmq->wmq_intr_idx == wmq->wmq_id);
 	DPRINTF(sc, WM_DEBUG_TX,
 	    ("%s: TX: got Tx intr\n", device_xname(sc->sc_dev)));
 	wm_txrxintr_disable(wmq);
 	mutex_enter(txq->txq_lock);
 	if (txq->txq_stopping) {
 		mutex_exit(txq->txq_lock);
 		return 1;
+	}
 	WM_Q_EVCNT_INCR(txq, txdw);
 	txmore = wm_txeof(txq, txlimit);
 	/* wm_deferred start() is done in wm_handle_queue(). */
 	mutex_exit(txq->txq_lock);
 	DPRINTF(sc, WM_DEBUG_RX,
 	    ("%s: RX: got Rx intr\n", device_xname(sc->sc_dev)));
 	mutex_enter(rxq->rxq_lock);
 	if (rxq->rxq_stopping) {
 		mutex_exit(rxq->rxq_lock);
 		return 1;
+	}
 	WM_Q_EVCNT_INCR(rxq, intr);
 	rxmore = wm_rxeof(rxq, rxlimit);
 	mutex_exit(rxq->rxq_lock);
 	wm_itrs_writereg(sc, wmq);
 	if (txmore || rxmore) {
 		wmq->wmq_txrx_use_workqueue = sc->sc_txrx_use_workqueue;
 		wm_sched_handle_queue(sc, wmq);
 	} else
 		wm_txrxintr_enable(wmq);
 	return 1;
+}
 static void
 wm_handle_queue(void *arg)
+{
 	struct wm_queue *wmq = arg;
 	struct wm_txqueue *txq = &wmq->wmq_txq;
 	struct wm_rxqueue *rxq = &wmq->wmq_rxq;
 	struct wm_softc *sc = txq->txq_sc;
 	u_int txlimit = sc->sc_tx_process_limit;
 	u_int rxlimit = sc->sc_rx_process_limit;
 	bool txmore;
 	bool rxmore;
 	mutex_enter(txq->txq_lock);
 	if (txq->txq_stopping) {
 		mutex_exit(txq->txq_lock);
 		return;
+	}
 	txmore = wm_txeof(txq, txlimit);
 	wm_deferred_start_locked(txq);
 	mutex_exit(txq->txq_lock);
 	mutex_enter(rxq->rxq_lock);
 	if (rxq->rxq_stopping) {
 		mutex_exit(rxq->rxq_lock);
 		return;
+	}
 	WM_Q_EVCNT_INCR(rxq, defer);
 	rxmore = wm_rxeof(rxq, rxlimit);
 	mutex_exit(rxq->rxq_lock);
 	if (txmore || rxmore) {
 		wmq->wmq_txrx_use_workqueue = sc->sc_txrx_use_workqueue;
 		wm_sched_handle_queue(sc, wmq);
 	} else
 		wm_txrxintr_enable(wmq);
+}
 static void
 wm_handle_queue_work(struct work *wk, void *context)
+{
 	struct wm_queue *wmq = container_of(wk, struct wm_queue, wmq_cookie);
 	/*
 	 * "enqueued flag" is not required here.
 	 */
 	wm_handle_queue(wmq);
+}
 /*
  * wm_linkintr_msix:
+ *
  *	Interrupt service routine for link status change for MSI-X.
  */
 static int
 wm_linkintr_msix(void *arg)
+{
 	struct wm_softc *sc = arg;
 	uint32_t reg;
 	bool has_rxo;
 	reg = CSR_READ(sc, WMREG_ICR);
 	WM_CORE_LOCK(sc);
 	DPRINTF(sc, WM_DEBUG_LINK,
 	    ("%s: LINK: got link intr. ICR = %08x\n",
 		device_xname(sc->sc_dev), reg));
 	if (sc->sc_core_stopping)
 		goto out;
 	if ((reg & ICR_LSC) != 0) {
 		WM_EVCNT_INCR(&sc->sc_ev_linkintr);
 		wm_linkintr(sc, ICR_LSC);
+	}
 	if ((reg & ICR_GPI(0)) != 0)
 		device_printf(sc->sc_dev, "got module interrupt\n");
 	/*
 	 * XXX 82574 MSI-X mode workaround
+	 *
 	 * 82574 MSI-X mode causes receive overrun(RXO) interrupt as ICR_OTHER
 	 * MSI-X vector, furthermore it does not cause neigher ICR_RXQ(0) nor
 	 * ICR_RXQ(1) vector. So, we generate ICR_RXQ(0) and ICR_RXQ(1)
 	 * interrupts by writing WMREG_ICS to process receive packets.
 	 */
 	if (sc->sc_type == WM_T_82574 && ((reg & ICR_RXO) != 0)) {
 #if defined(WM_DEBUG)
 		log(LOG_WARNING, "%s: Receive overrun\n",
 		    device_xname(sc->sc_dev));
 #endif /* defined(WM_DEBUG) */
 		has_rxo = true;
 		/*
 		 * The RXO interrupt is very high rate when receive traffic is
 		 * high rate. We use polling mode for ICR_OTHER like Tx/Rx
 		 * interrupts. ICR_OTHER will be enabled at the end of
 		 * wm_txrxintr_msix() which is kicked by both ICR_RXQ(0) and
 		 * ICR_RXQ(1) interrupts.
 		 */
 		CSR_WRITE(sc, WMREG_IMC, ICR_OTHER);
 		CSR_WRITE(sc, WMREG_ICS, ICR_RXQ(0) | ICR_RXQ(1));
+	}
 out:
 	WM_CORE_UNLOCK(sc);
 	if (sc->sc_type == WM_T_82574) {
 		if (!has_rxo)
 			CSR_WRITE(sc, WMREG_IMS, ICR_OTHER | ICR_LSC);
 		else
 			CSR_WRITE(sc, WMREG_IMS, ICR_LSC);
 	} else if (sc->sc_type == WM_T_82575)
 		CSR_WRITE(sc, WMREG_EIMS, EITR_OTHER);
 	else
 		CSR_WRITE(sc, WMREG_EIMS, 1 << sc->sc_link_intr_idx);
 	return 1;
+}
 /*
  * Media related.
  * GMII, SGMII, TBI (and SERDES)
  */
 /* Common */
 /*
  * wm_tbi_serdes_set_linkled:
+ *
  *	Update the link LED on TBI and SERDES devices.
  */
 static void
 wm_tbi_serdes_set_linkled(struct wm_softc *sc)
+{
 	if (sc->sc_tbi_linkup)
 		sc->sc_ctrl |= CTRL_SWDPIN(0);
 	else
 		sc->sc_ctrl &= ~CTRL_SWDPIN(0);
 	/* 82540 or newer devices are active low */
 	sc->sc_ctrl ^= (sc->sc_type >= WM_T_82540) ? CTRL_SWDPIN(0) : 0;
 	CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
+}
 /* GMII related */
 /*
  * wm_gmii_reset:
+ *
  *	Reset the PHY.
  */
 static void
 wm_gmii_reset(struct wm_softc *sc)
+{
 	uint32_t reg;
 	int rv;
 	DPRINTF(sc, WM_DEBUG_INIT, ("%s: %s called\n",
 		device_xname(sc->sc_dev), __func__));
 	rv = sc->phy.acquire(sc);
 	if (rv != 0) {
 		aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n",
 		    __func__);
 		return;
+	}
 	switch (sc->sc_type) {
 	case WM_T_82542_2_0:
 	case WM_T_82542_2_1:
 		/* null */
 		break;
 	case WM_T_82543:
 		/*
 		 * With 82543, we need to force speed and duplex on the MAC
 		 * equal to what the PHY speed and duplex configuration is.
 		 * In addition, we need to perform a hardware reset on the PHY
 		 * to take it out of reset.
 		 */
 		sc->sc_ctrl |= CTRL_FRCSPD | CTRL_FRCFDX;
 		CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
 		/* The PHY reset pin is active-low. */
 		reg = CSR_READ(sc, WMREG_CTRL_EXT);
 		reg &= ~((CTRL_EXT_SWDPIO_MASK << CTRL_EXT_SWDPIO_SHIFT) |
 		    CTRL_EXT_SWDPIN(4));
 		reg |= CTRL_EXT_SWDPIO(4);
 		CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
 		CSR_WRITE_FLUSH(sc);
 		delay(10*1000);
 		CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_SWDPIN(4));
 		CSR_WRITE_FLUSH(sc);
 		delay(150);
 #if 0
 		sc->sc_ctrl_ext = reg | CTRL_EXT_SWDPIN(4);
 #endif
 		delay(20*1000);	/* XXX extra delay to get PHY ID? */
 		break;
 	case WM_T_82544:	/* Reset 10000us */
 	case WM_T_82540:
 	case WM_T_82545:
 	case WM_T_82545_3:
 	case WM_T_82546:
 	case WM_T_82546_3:
 	case WM_T_82541:
 	case WM_T_82541_2:
 	case WM_T_82547:
 	case WM_T_82547_2:
 	case WM_T_82571:	/* Reset 100us */
 	case WM_T_82572:
 	case WM_T_82573:
 	case WM_T_82574:
 	case WM_T_82575:
 	case WM_T_82576:
 	case WM_T_82580:
 	case WM_T_I350:
 	case WM_T_I354:
 	case WM_T_I210:
 	case WM_T_I211:
 	case WM_T_82583:
 	case WM_T_80003:
 		/* Generic reset */
 		CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl | CTRL_PHY_RESET);
 		CSR_WRITE_FLUSH(sc);
 		delay(20000);
 		CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
 		CSR_WRITE_FLUSH(sc);
 		delay(20000);
 		if ((sc->sc_type == WM_T_82541)
 		    || (sc->sc_type == WM_T_82541_2)
 		    || (sc->sc_type == WM_T_82547)
 		    || (sc->sc_type == WM_T_82547_2)) {
 			/* Workaround for igp are done in igp_reset() */
 			/* XXX add code to set LED after phy reset */
+		}
 		break;
 	case WM_T_ICH8:
 	case WM_T_ICH9:
 	case WM_T_ICH10:
 	case WM_T_PCH:
 	case WM_T_PCH2:
 	case WM_T_PCH_LPT:
 	case WM_T_PCH_SPT:
 	case WM_T_PCH_CNP:
 		/* Generic reset */
 		CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl | CTRL_PHY_RESET);
 		CSR_WRITE_FLUSH(sc);
 		delay(100);
 		CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
 		CSR_WRITE_FLUSH(sc);
 		delay(150);
 		break;
 	default:
 		panic("%s: %s: unknown type\n", device_xname(sc->sc_dev),
 		    __func__);
 		break;
+	}
 	sc->phy.release(sc);
 	/* get_cfg_done */
 	wm_get_cfg_done(sc);
 	/* Extra setup */
 	switch (sc->sc_type) {
 	case WM_T_82542_2_0:
 	case WM_T_82542_2_1:
 	case WM_T_82543:
 	case WM_T_82544:
 	case WM_T_82540:
 	case WM_T_82545:
 	case WM_T_82545_3:
 	case WM_T_82546:
 	case WM_T_82546_3:
 	case WM_T_82541_2:
 	case WM_T_82547_2:
 	case WM_T_82571:
 	case WM_T_82572:
 	case WM_T_82573:
 	case WM_T_82574:
 	case WM_T_82583:
 	case WM_T_82575:
 	case WM_T_82576:
 	case WM_T_82580:
 	case WM_T_I350:
 	case WM_T_I354:
 	case WM_T_I210:
 	case WM_T_I211:
 	case WM_T_80003:
 		/* Null */
 		break;
 	case WM_T_82541:
 	case WM_T_82547:
 		/* XXX Configure actively LED after PHY reset */
 		break;
 	case WM_T_ICH8:
 	case WM_T_ICH9:
 	case WM_T_ICH10:
 	case WM_T_PCH:
 	case WM_T_PCH2:
 	case WM_T_PCH_LPT:
 	case WM_T_PCH_SPT:
 	case WM_T_PCH_CNP:
 		wm_phy_post_reset(sc);
 		break;
 	default:
 		panic("%s: unknown type\n", __func__);
 		break;
+	}
+}
 /*
  * Setup sc_phytype and mii_{read|write}reg.
+ *
  *  To identify PHY type, correct read/write function should be selected.
  * To select correct read/write function, PCI ID or MAC type are required
  * without accessing PHY registers.
+ *
  *  On the first call of this function, PHY ID is not known yet. Check
  * PCI ID or MAC type. The list of the PCI ID may not be perfect, so the
  * result might be incorrect.
+ *
  *  In the second call, PHY OUI and model is used to identify PHY type.
  * It might not be perfect because of the lack of compared entry, but it
  * would be better than the first call.
+ *
  *  If the detected new result and previous assumption is different,
  * diagnous message will be printed.
  */
 static void
 wm_gmii_setup_phytype(struct wm_softc *sc, uint32_t phy_oui,
     uint16_t phy_model)
+{
 	device_t dev = sc->sc_dev;
 	struct mii_data *mii = &sc->sc_mii;
 	uint16_t new_phytype = WMPHY_UNKNOWN;
 	uint16_t doubt_phytype = WMPHY_UNKNOWN;
 	mii_readreg_t new_readreg;
 	mii_writereg_t new_writereg;
 	bool dodiag = true;
 	DPRINTF(sc, WM_DEBUG_INIT, ("%s: %s called\n",
 		device_xname(sc->sc_dev), __func__));
 	/*
 	 * 1000BASE-T SFP uses SGMII and the first asumed PHY type is always
 	 * incorrect. So don't print diag output when it's 2nd call.
 	 */
 	if ((sc->sc_sfptype != 0) && (phy_oui == 0) && (phy_model == 0))
 		dodiag = false;
 	if (mii->mii_readreg == NULL) {
 		/*
 		 *  This is the first call of this function. For ICH and PCH
 		 * variants, it's difficult to determine the PHY access method
 		 * by sc_type, so use the PCI product ID for some devices.
 		 */
 		switch (sc->sc_pcidevid) {
 		case PCI_PRODUCT_INTEL_PCH_M_LM:
 		case PCI_PRODUCT_INTEL_PCH_M_LC:
 			/* 82577 */
 			new_phytype = WMPHY_82577;
 			break;
 		case PCI_PRODUCT_INTEL_PCH_D_DM:
 		case PCI_PRODUCT_INTEL_PCH_D_DC:
 			/* 82578 */
 			new_phytype = WMPHY_82578;
 			break;
 		case PCI_PRODUCT_INTEL_PCH2_LV_LM:
 		case PCI_PRODUCT_INTEL_PCH2_LV_V:
 			/* 82579 */
 			new_phytype = WMPHY_82579;
 			break;
 		case PCI_PRODUCT_INTEL_82801H_82567V_3:
 		case PCI_PRODUCT_INTEL_82801I_BM:
 		case PCI_PRODUCT_INTEL_82801I_IGP_M_AMT: /* Not IGP but BM */
 		case PCI_PRODUCT_INTEL_82801J_R_BM_LM:
 		case PCI_PRODUCT_INTEL_82801J_R_BM_LF:
 		case PCI_PRODUCT_INTEL_82801J_D_BM_LM:
 		case PCI_PRODUCT_INTEL_82801J_D_BM_LF:
 		case PCI_PRODUCT_INTEL_82801J_R_BM_V:
 			/* ICH8, 9, 10 with 82567 */
 			new_phytype = WMPHY_BM;
 			break;
 		default:
 			break;
+		}
 	} else {
 		/* It's not the first call. Use PHY OUI and model */
 		switch (phy_oui) {
 		case MII_OUI_ATTANSIC: /* atphy(4) */
 			switch (phy_model) {
 			case MII_MODEL_ATTANSIC_AR8021:
 				new_phytype = WMPHY_82578;
 				break;
 			default:
 				break;
+			}
 			break;
 		case MII_OUI_xxMARVELL:
 			switch (phy_model) {
 			case MII_MODEL_xxMARVELL_I210:
 				new_phytype = WMPHY_I210;
 				break;
 			case MII_MODEL_xxMARVELL_E1011:
 			case MII_MODEL_xxMARVELL_E1000_3:
 			case MII_MODEL_xxMARVELL_E1000_5:
 			case MII_MODEL_xxMARVELL_E1112:
 				new_phytype = WMPHY_M88;
 				break;
 			case MII_MODEL_xxMARVELL_E1149:
 				new_phytype = WMPHY_BM;
 				break;
 			case MII_MODEL_xxMARVELL_E1111:
 			case MII_MODEL_xxMARVELL_I347:
 			case MII_MODEL_xxMARVELL_E1512:
 			case MII_MODEL_xxMARVELL_E1340M:
 			case MII_MODEL_xxMARVELL_E1543:
 				new_phytype = WMPHY_M88;
 				break;
 			case MII_MODEL_xxMARVELL_I82563:
 				new_phytype = WMPHY_GG82563;
 				break;
 			default:
 				break;
+			}
 			break;
 		case MII_OUI_INTEL:
 			switch (phy_model) {
 			case MII_MODEL_INTEL_I82577:
 				new_phytype = WMPHY_82577;
 				break;
 			case MII_MODEL_INTEL_I82579:
 				new_phytype = WMPHY_82579;
 				break;
 			case MII_MODEL_INTEL_I217:
 				new_phytype = WMPHY_I217;
 				break;
 			case MII_MODEL_INTEL_I82580:
 				new_phytype = WMPHY_82580;
 				break;
 			case MII_MODEL_INTEL_I350:
 				new_phytype = WMPHY_I350;
 				break;
 				break;
 			default:
 				break;
+			}
 			break;
 		case MII_OUI_yyINTEL:
 			switch (phy_model) {
 			case MII_MODEL_yyINTEL_I82562G:
 			case MII_MODEL_yyINTEL_I82562EM:
 			case MII_MODEL_yyINTEL_I82562ET:
 				new_phytype = WMPHY_IFE;
 				break;
 			case MII_MODEL_yyINTEL_IGP01E1000:
 				new_phytype = WMPHY_IGP;
 				break;
 			case MII_MODEL_yyINTEL_I82566:
 				new_phytype = WMPHY_IGP_3;
 				break;
 			default:
 				break;
+			}
 			break;
 		default:
 			break;
+		}
 		if (dodiag) {
 			if (new_phytype == WMPHY_UNKNOWN)
 				aprint_verbose_dev(dev,
 				    "%s: Unknown PHY model. OUI=%06x, "
 				    "model=%04x\n", __func__, phy_oui,
 				    phy_model);
 			if ((sc->sc_phytype != WMPHY_UNKNOWN)
 			    && (sc->sc_phytype != new_phytype)) {
 				aprint_error_dev(dev, "Previously assumed PHY "
 				    "type(%u) was incorrect. PHY type from PHY"
 				    "ID = %u\n", sc->sc_phytype, new_phytype);
+			}
+		}
+	}
 	/* Next, use sc->sc_flags and sc->sc_type to set read/write funcs. */
 	if (((sc->sc_flags & WM_F_SGMII) != 0) && !wm_sgmii_uses_mdio(sc)) {
 		/* SGMII */
 		new_readreg = wm_sgmii_readreg;
 		new_writereg = wm_sgmii_writereg;
 	} else if ((sc->sc_type == WM_T_82574) || (sc->sc_type == WM_T_82583)){
 		/* BM2 (phyaddr == 1) */
 		if ((sc->sc_phytype != WMPHY_UNKNOWN)
 		    && (new_phytype != WMPHY_BM)
 		    && (new_phytype != WMPHY_UNKNOWN))
 			doubt_phytype = new_phytype;
 		new_phytype = WMPHY_BM;
 		new_readreg = wm_gmii_bm_readreg;
 		new_writereg = wm_gmii_bm_writereg;
 	} else if (sc->sc_type >= WM_T_PCH) {
 		/* All PCH* use _hv_ */
 		new_readreg = wm_gmii_hv_readreg;
 		new_writereg = wm_gmii_hv_writereg;
 	} else if (sc->sc_type >= WM_T_ICH8) {
 		/* non-82567 ICH8, 9 and 10 */
 		new_readreg = wm_gmii_i82544_readreg;
 		new_writereg = wm_gmii_i82544_writereg;
 	} else if (sc->sc_type >= WM_T_80003) {
 		/* 80003 */
 		if ((sc->sc_phytype != WMPHY_UNKNOWN)
 		    && (new_phytype != WMPHY_GG82563)
 		    && (new_phytype != WMPHY_UNKNOWN))
 			doubt_phytype = new_phytype;
 		new_phytype = WMPHY_GG82563;
 		new_readreg = wm_gmii_i80003_readreg;
 		new_writereg = wm_gmii_i80003_writereg;
 	} else if (sc->sc_type >= WM_T_I210) {
 		/* I210 and I211 */
 		if ((sc->sc_phytype != WMPHY_UNKNOWN)
 		    && (new_phytype != WMPHY_I210)
 		    && (new_phytype != WMPHY_UNKNOWN))
 			doubt_phytype = new_phytype;
 		new_phytype = WMPHY_I210;
 		new_readreg = wm_gmii_gs40g_readreg;
 		new_writereg = wm_gmii_gs40g_writereg;
 	} else if (sc->sc_type >= WM_T_82580) {
 		/* 82580, I350 and I354 */
 		new_readreg = wm_gmii_82580_readreg;
 		new_writereg = wm_gmii_82580_writereg;
 	} else if (sc->sc_type >= WM_T_82544) {
 		/* 82544, 0, [56], [17], 8257[1234] and 82583 */
 		new_readreg = wm_gmii_i82544_readreg;
 		new_writereg = wm_gmii_i82544_writereg;
 	} else {
 		new_readreg = wm_gmii_i82543_readreg;
 		new_writereg = wm_gmii_i82543_writereg;
+	}
 	if (new_phytype == WMPHY_BM) {
 		/* All BM use _bm_ */
 		new_readreg = wm_gmii_bm_readreg;
 		new_writereg = wm_gmii_bm_writereg;
+	}
 	if ((sc->sc_type >= WM_T_PCH) && (sc->sc_type <= WM_T_PCH_CNP)) {
 		/* All PCH* use _hv_ */
 		new_readreg = wm_gmii_hv_readreg;
 		new_writereg = wm_gmii_hv_writereg;
+	}
 	/* Diag output */
 	if (dodiag) {
 		if (doubt_phytype != WMPHY_UNKNOWN)
 			aprint_error_dev(dev, "Assumed new PHY type was "
 			    "incorrect. old = %u, new = %u\n", sc->sc_phytype,
 			    new_phytype);
 		else if ((sc->sc_phytype != WMPHY_UNKNOWN)
 		    && (sc->sc_phytype != new_phytype))
 			aprint_error_dev(dev, "Previously assumed PHY type(%u)"
 			    "was incorrect. New PHY type = %u\n",
 			    sc->sc_phytype, new_phytype);
 		if ((mii->mii_readreg != NULL) &&
 		    (new_phytype == WMPHY_UNKNOWN))
 			aprint_error_dev(dev, "PHY type is still unknown.\n");
 		if ((mii->mii_readreg != NULL) &&
 		    (mii->mii_readreg != new_readreg))
 			aprint_error_dev(dev, "Previously assumed PHY "
 			    "read/write function was incorrect.\n");
+	}
 	/* Update now */
 	sc->sc_phytype = new_phytype;
 	mii->mii_readreg = new_readreg;
 	mii->mii_writereg = new_writereg;
 	if (new_readreg == wm_gmii_hv_readreg) {
 		sc->phy.readreg_locked = wm_gmii_hv_readreg_locked;
 		sc->phy.writereg_locked = wm_gmii_hv_writereg_locked;
 	} else if (new_readreg == wm_sgmii_readreg) {
 		sc->phy.readreg_locked = wm_sgmii_readreg_locked;
 		sc->phy.writereg_locked = wm_sgmii_writereg_locked;
 	} else if (new_readreg == wm_gmii_i82544_readreg) {
 		sc->phy.readreg_locked = wm_gmii_i82544_readreg_locked;
 		sc->phy.writereg_locked = wm_gmii_i82544_writereg_locked;
+	}
+}
 /*
  * wm_get_phy_id_82575:
+ *
  * Return PHY ID. Return -1 if it failed.
  */
 static int
 wm_get_phy_id_82575(struct wm_softc *sc)
+{
 	uint32_t reg;
 	int phyid = -1;
 	/* XXX */
 	if ((sc->sc_flags & WM_F_SGMII) == 0)
 		return -1;
 	if (wm_sgmii_uses_mdio(sc)) {
 		switch (sc->sc_type) {
 		case WM_T_82575:
 		case WM_T_82576:
 			reg = CSR_READ(sc, WMREG_MDIC);
 			phyid = (reg & MDIC_PHY_MASK) >> MDIC_PHY_SHIFT;
 			break;
 		case WM_T_82580:
 		case WM_T_I350:
 		case WM_T_I354:
 		case WM_T_I210:
 		case WM_T_I211:
 			reg = CSR_READ(sc, WMREG_MDICNFG);
 			phyid = (reg & MDICNFG_PHY_MASK) >> MDICNFG_PHY_SHIFT;
 			break;
 		default:
 			return -1;
+		}
+	}
 	return phyid;
+}
 /*
  * wm_gmii_mediainit:
+ *
  *	Initialize media for use on 1000BASE-T devices.
  */
 static void
 wm_gmii_mediainit(struct wm_softc *sc, pci_product_id_t prodid)
+{
 	device_t dev = sc->sc_dev;
 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
 	struct mii_data *mii = &sc->sc_mii;
 	DPRINTF(sc, WM_DEBUG_GMII, ("%s: %s called\n",
 		device_xname(sc->sc_dev), __func__));
 	/* We have GMII. */
 	sc->sc_flags |= WM_F_HAS_MII;
 	if (sc->sc_type == WM_T_80003)
 		sc->sc_tipg =  TIPG_1000T_80003_DFLT;
 	else
 		sc->sc_tipg = TIPG_1000T_DFLT;
 	/*
 	 * Let the chip set speed/duplex on its own based on
 	 * signals from the PHY.
 	 * XXXbouyer - I'm not sure this is right for the 80003,
 	 * the em driver only sets CTRL_SLU here - but it seems to work.
 	 */
 	sc->sc_ctrl |= CTRL_SLU;
 	CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
 	/* Initialize our media structures and probe the GMII. */
 	mii->mii_ifp = ifp;
 	mii->mii_statchg = wm_gmii_statchg;
 	/* get PHY control from SMBus to PCIe */
 	if ((sc->sc_type == WM_T_PCH) || (sc->sc_type == WM_T_PCH2)
 	    || (sc->sc_type == WM_T_PCH_LPT) || (sc->sc_type == WM_T_PCH_SPT)
 	    || (sc->sc_type == WM_T_PCH_CNP))
 		wm_init_phy_workarounds_pchlan(sc);
 	wm_gmii_reset(sc);
 	sc->sc_ethercom.ec_mii = &sc->sc_mii;
 	ifmedia_init_with_lock(&mii->mii_media, IFM_IMASK, wm_gmii_mediachange,
 	    wm_gmii_mediastatus, sc->sc_core_lock);
 	/* Setup internal SGMII PHY for SFP */
 	wm_sgmii_sfp_preconfig(sc);
 	if ((sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576)
 	    || (sc->sc_type == WM_T_82580)
 	    || (sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354)
 	    || (sc->sc_type == WM_T_I210) || (sc->sc_type == WM_T_I211)) {
 		if ((sc->sc_flags & WM_F_SGMII) == 0) {
 			/* Attach only one port */
 			mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, 1,
 			    MII_OFFSET_ANY, MIIF_DOPAUSE);
 		} else {
 			int i, id;
 			uint32_t ctrl_ext;
 			id = wm_get_phy_id_82575(sc);
 			if (id != -1) {
 				mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff,
 				    id, MII_OFFSET_ANY, MIIF_DOPAUSE);
+			}
 			if ((id == -1)
 			    || (LIST_FIRST(&mii->mii_phys) == NULL)) {
 				/* Power on sgmii phy if it is disabled */
 				ctrl_ext = CSR_READ(sc, WMREG_CTRL_EXT);
 				CSR_WRITE(sc, WMREG_CTRL_EXT,
 				    ctrl_ext &~ CTRL_EXT_SWDPIN(3));
 				CSR_WRITE_FLUSH(sc);
 				delay(300*1000); /* XXX too long */
 				/*
 				 * From 1 to 8.
+				 *
 				 * I2C access fails with I2C register's ERROR
 				 * bit set, so prevent error message while
 				 * scanning.
 				 */
 				sc->phy.no_errprint = true;
 				for (i = 1; i < 8; i++)
 					mii_attach(sc->sc_dev, &sc->sc_mii,
 xffffffff, i, MII_OFFSET_ANY,
 					    MIIF_DOPAUSE);
 				sc->phy.no_errprint = false;
 				/* Restore previous sfp cage power state */
 				CSR_WRITE(sc, WMREG_CTRL_EXT, ctrl_ext);
+			}
+		}
 	} else
 		mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY,
 		    MII_OFFSET_ANY, MIIF_DOPAUSE);
 	/*
 	 * If the MAC is PCH2 or PCH_LPT and failed to detect MII PHY, call
 	 * wm_set_mdio_slow_mode_hv() for a workaround and retry.
 	 */
 	if (((sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT)
 		|| (sc->sc_type == WM_T_PCH_SPT)
 		|| (sc->sc_type == WM_T_PCH_CNP))
 	    && (LIST_FIRST(&mii->mii_phys) == NULL)) {
 		wm_set_mdio_slow_mode_hv(sc);
 		mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY,
 		    MII_OFFSET_ANY, MIIF_DOPAUSE);
+	}
 	/*
 	 * (For ICH8 variants)
 	 * If PHY detection failed, use BM's r/w function and retry.
 	 */
 	if (LIST_FIRST(&mii->mii_phys) == NULL) {
 		/* if failed, retry with *_bm_* */
 		aprint_verbose_dev(dev, "Assumed PHY access function "
 		    "(type = %d) might be incorrect. Use BM and retry.\n",
 		    sc->sc_phytype);
 		sc->sc_phytype = WMPHY_BM;
 		mii->mii_readreg = wm_gmii_bm_readreg;
 		mii->mii_writereg = wm_gmii_bm_writereg;
 		mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY,
 		    MII_OFFSET_ANY, MIIF_DOPAUSE);
+	}
 	if (LIST_FIRST(&mii->mii_phys) == NULL) {
 		/* Any PHY wasn't find */
 		ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL);
 		ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE);
 		sc->sc_phytype = WMPHY_NONE;
 	} else {
 		struct mii_softc *child = LIST_FIRST(&mii->mii_phys);
 		/*
 		 * PHY Found! Check PHY type again by the second call of
 		 * wm_gmii_setup_phytype.
 		 */
 		wm_gmii_setup_phytype(sc, child->mii_mpd_oui,
 		    child->mii_mpd_model);
 		ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO);
+	}
+}
 /*
  * wm_gmii_mediachange:	[ifmedia interface function]
+ *
  *	Set hardware to newly-selected media on a 1000BASE-T device.
  */
 static int
 wm_gmii_mediachange(struct ifnet *ifp)
+{
 	struct wm_softc *sc = ifp->if_softc;
 	struct ifmedia_entry *ife = sc->sc_mii.mii_media.ifm_cur;
 	uint32_t reg;
 	int rc;
 	DPRINTF(sc, WM_DEBUG_GMII, ("%s: %s called\n",
 		device_xname(sc->sc_dev), __func__));
 	if ((ifp->if_flags & IFF_UP) == 0)
 		return 0;
 	/* XXX Not for I354? FreeBSD's e1000_82575.c doesn't include it */
 	if ((sc->sc_type == WM_T_82580)
 	    || (sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I210)
 	    || (sc->sc_type == WM_T_I211)) {
 		reg = CSR_READ(sc, WMREG_PHPM);
 		reg &= ~PHPM_GO_LINK_D;
 		CSR_WRITE(sc, WMREG_PHPM, reg);
+	}
 	/* Disable D0 LPLU. */
 	wm_lplu_d0_disable(sc);
 	sc->sc_ctrl &= ~(CTRL_SPEED_MASK | CTRL_FD);
 	sc->sc_ctrl |= CTRL_SLU;
 	if ((IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO)
 	    || (sc->sc_type > WM_T_82543)) {
 		sc->sc_ctrl &= ~(CTRL_FRCSPD | CTRL_FRCFDX);
 	} else {
 		sc->sc_ctrl &= ~CTRL_ASDE;
 		sc->sc_ctrl |= CTRL_FRCSPD | CTRL_FRCFDX;
 		if (ife->ifm_media & IFM_FDX)
 			sc->sc_ctrl |= CTRL_FD;
 		switch (IFM_SUBTYPE(ife->ifm_media)) {
 		case IFM_10_T:
 			sc->sc_ctrl |= CTRL_SPEED_10;
 			break;
 		case IFM_100_TX:
 			sc->sc_ctrl |= CTRL_SPEED_100;
 			break;
 		case IFM_1000_T:
 			sc->sc_ctrl |= CTRL_SPEED_1000;
 			break;
 		case IFM_NONE:
 			/* There is no specific setting for IFM_NONE */
 			break;
 		default:
 			panic("wm_gmii_mediachange: bad media 0x%x",
 			    ife->ifm_media);
+		}
+	}
 	CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
 	CSR_WRITE_FLUSH(sc);
 	if ((sc->sc_type >= WM_T_82575) && (sc->sc_type <= WM_T_I211))
 		wm_serdes_mediachange(ifp);
 	if (sc->sc_type <= WM_T_82543)
 		wm_gmii_reset(sc);
 	else if ((sc->sc_type >= WM_T_82575) && (sc->sc_type <= WM_T_I211)
 	    && ((sc->sc_flags & WM_F_SGMII) != 0)) {
 		/* allow time for SFP cage time to power up phy */
 		delay(300 * 1000);
 		wm_gmii_reset(sc);
+	}
 	if ((rc = mii_mediachg(&sc->sc_mii)) == ENXIO)
 		return 0;
 	return rc;
+}
 /*
  * wm_gmii_mediastatus:	[ifmedia interface function]
+ *
  *	Get the current interface media status on a 1000BASE-T device.
  */
 static void
 wm_gmii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
+{
 	struct wm_softc *sc = ifp->if_softc;
 	ether_mediastatus(ifp, ifmr);
 	ifmr->ifm_active = (ifmr->ifm_active & ~IFM_ETH_FMASK)
 	    | sc->sc_flowflags;
+}
 #define	MDI_IO		CTRL_SWDPIN(2)
 #define	MDI_DIR		CTRL_SWDPIO(2)	/* host -> PHY */
 #define	MDI_CLK		CTRL_SWDPIN(3)
 static void
 wm_i82543_mii_sendbits(struct wm_softc *sc, uint32_t data, int nbits)
+{
 	uint32_t i, v;
 	v = CSR_READ(sc, WMREG_CTRL);
 	v &= ~(MDI_IO | MDI_CLK | (CTRL_SWDPIO_MASK << CTRL_SWDPIO_SHIFT));
 	v |= MDI_DIR | CTRL_SWDPIO(3);
 	for (i = __BIT(nbits - 1); i != 0; i >>= 1) {
 		if (data & i)
 			v |= MDI_IO;
 		else
 			v &= ~MDI_IO;
 		CSR_WRITE(sc, WMREG_CTRL, v);
 		CSR_WRITE_FLUSH(sc);
 		delay(10);
 		CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK);
 		CSR_WRITE_FLUSH(sc);
 		delay(10);
 		CSR_WRITE(sc, WMREG_CTRL, v);
 		CSR_WRITE_FLUSH(sc);
 		delay(10);
+	}
+}
 static uint16_t
 wm_i82543_mii_recvbits(struct wm_softc *sc)
+{
 	uint32_t v, i;
 	uint16_t data = 0;
 	v = CSR_READ(sc, WMREG_CTRL);
 	v &= ~(MDI_IO | MDI_CLK | (CTRL_SWDPIO_MASK << CTRL_SWDPIO_SHIFT));
 	v |= CTRL_SWDPIO(3);
 	CSR_WRITE(sc, WMREG_CTRL, v);
 	CSR_WRITE_FLUSH(sc);
 	delay(10);
 	CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK);
 	CSR_WRITE_FLUSH(sc);
 	delay(10);
 	CSR_WRITE(sc, WMREG_CTRL, v);
 	CSR_WRITE_FLUSH(sc);
 	delay(10);
 	for (i = 0; i < 16; i++) {
 		data <<= 1;
 		CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK);
 		CSR_WRITE_FLUSH(sc);
 		delay(10);
 		if (CSR_READ(sc, WMREG_CTRL) & MDI_IO)
 			data |= 1;
 		CSR_WRITE(sc, WMREG_CTRL, v);
 		CSR_WRITE_FLUSH(sc);
 		delay(10);
+	}
 	CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK);
 	CSR_WRITE_FLUSH(sc);
 	delay(10);
 	CSR_WRITE(sc, WMREG_CTRL, v);
 	CSR_WRITE_FLUSH(sc);
 	delay(10);
 	return data;
+}
 #undef MDI_IO
 #undef MDI_DIR
 #undef MDI_CLK
 /*
  * wm_gmii_i82543_readreg:	[mii interface function]
+ *
  *	Read a PHY register on the GMII (i82543 version).
  */
 static int
 wm_gmii_i82543_readreg(device_t dev, int phy, int reg, uint16_t *val)
+{
 	struct wm_softc *sc = device_private(dev);
 	wm_i82543_mii_sendbits(sc, 0xffffffffU, 32);
 	wm_i82543_mii_sendbits(sc, reg | (phy << 5) |
 	    (MII_COMMAND_READ << 10) | (MII_COMMAND_START << 12), 14);
 	*val = wm_i82543_mii_recvbits(sc) & 0xffff;
 	DPRINTF(sc, WM_DEBUG_GMII, ("%s: GMII: read phy %d reg %d -> 0x%04hx\n",
 		device_xname(dev), phy, reg, *val));
 	return 0;
+}
 /*
  * wm_gmii_i82543_writereg:	[mii interface function]
+ *
  *	Write a PHY register on the GMII (i82543 version).
  */
 static int
 wm_gmii_i82543_writereg(device_t dev, int phy, int reg, uint16_t val)
+{
 	struct wm_softc *sc = device_private(dev);
 	wm_i82543_mii_sendbits(sc, 0xffffffffU, 32);
 	wm_i82543_mii_sendbits(sc, val | (MII_COMMAND_ACK << 16) |
 	    (reg << 18) | (phy << 23) | (MII_COMMAND_WRITE << 28) |
 	    (MII_COMMAND_START << 30), 32);
 	return 0;
+}
 /*
  * wm_gmii_mdic_readreg:	[mii interface function]
+ *
  *	Read a PHY register on the GMII.
  */
 static int
 wm_gmii_mdic_readreg(device_t dev, int phy, int reg, uint16_t *val)
+{
 	struct wm_softc *sc = device_private(dev);
 	uint32_t mdic = 0;
 	int i;
 	if ((sc->sc_phytype != WMPHY_82579) && (sc->sc_phytype != WMPHY_I217)
 	    && (reg > MII_ADDRMASK)) {
 		device_printf(dev, "%s: PHYTYPE = %d, addr 0x%x > 0x1f\n",
 		    __func__, sc->sc_phytype, reg);
 		reg &= MII_ADDRMASK;
+	}
 	CSR_WRITE(sc, WMREG_MDIC, MDIC_OP_READ | MDIC_PHYADD(phy) |
 	    MDIC_REGADD(reg));
 	for (i = 0; i < WM_GEN_POLL_TIMEOUT * 3; i++) {
 		delay(50);
 		mdic = CSR_READ(sc, WMREG_MDIC);
 		if (mdic & MDIC_READY)
 			break;
+	}
 	if ((mdic & MDIC_READY) == 0) {
 		DPRINTF(sc, WM_DEBUG_GMII,
 		    ("%s: MDIC read timed out: phy %d reg %d\n",
 			device_xname(dev), phy, reg));
 		return ETIMEDOUT;
 	} else if (mdic & MDIC_E) {
 		/* This is normal if no PHY is present. */
 		DPRINTF(sc, WM_DEBUG_GMII, ("%s: MDIC read error: phy %d reg %d\n",
 			device_xname(sc->sc_dev), phy, reg));
 		return -1;
 	} else
 		*val = MDIC_DATA(mdic);
 	/*
 	 * Allow some time after each MDIC transaction to avoid
 	 * reading duplicate data in the next MDIC transaction.
 	 */
 	if (sc->sc_type == WM_T_PCH2)
 		delay(100);
 	return 0;
+}
 /*
  * wm_gmii_mdic_writereg:	[mii interface function]
+ *
  *	Write a PHY register on the GMII.
  */
 static int
 wm_gmii_mdic_writereg(device_t dev, int phy, int reg, uint16_t val)
+{
 	struct wm_softc *sc = device_private(dev);
 	uint32_t mdic = 0;
 	int i;
 	if ((sc->sc_phytype != WMPHY_82579) && (sc->sc_phytype != WMPHY_I217)
 	    && (reg > MII_ADDRMASK)) {
 		device_printf(dev, "%s: PHYTYPE = %d, addr 0x%x > 0x1f\n",
 		    __func__, sc->sc_phytype, reg);
 		reg &= MII_ADDRMASK;
+	}
 	CSR_WRITE(sc, WMREG_MDIC, MDIC_OP_WRITE | MDIC_PHYADD(phy) |
 	    MDIC_REGADD(reg) | MDIC_DATA(val));
 	for (i = 0; i < WM_GEN_POLL_TIMEOUT * 3; i++) {
 		delay(50);
 		mdic = CSR_READ(sc, WMREG_MDIC);
 		if (mdic & MDIC_READY)
 			break;
+	}
 	if ((mdic & MDIC_READY) == 0) {
 		DPRINTF(sc, WM_DEBUG_GMII,
 		    ("%s: MDIC write timed out: phy %d reg %d\n",
 			device_xname(dev), phy, reg));
 		return ETIMEDOUT;
 	} else if (mdic & MDIC_E) {
 		DPRINTF(sc, WM_DEBUG_GMII,
 		    ("%s: MDIC write error: phy %d reg %d\n",
 			device_xname(dev), phy, reg));
 		return -1;
+	}
 	/*
 	 * Allow some time after each MDIC transaction to avoid
 	 * reading duplicate data in the next MDIC transaction.
 	 */
 	if (sc->sc_type == WM_T_PCH2)
 		delay(100);
 	return 0;
+}
 /*
  * wm_gmii_i82544_readreg:	[mii interface function]
+ *
  *	Read a PHY register on the GMII.
  */
 static int
 wm_gmii_i82544_readreg(device_t dev, int phy, int reg, uint16_t *val)
+{
 	struct wm_softc *sc = device_private(dev);
 	int rv;
 	if (sc->phy.acquire(sc)) {
 		device_printf(dev, "%s: failed to get semaphore\n", __func__);
 		return -1;
+	}
 	rv = wm_gmii_i82544_readreg_locked(dev, phy, reg, val);
 	sc->phy.release(sc);
 	return rv;
+}
 static int
 wm_gmii_i82544_readreg_locked(device_t dev, int phy, int reg, uint16_t *val)
+{
 	struct wm_softc *sc = device_private(dev);
 	int rv;
 	if (reg > BME1000_MAX_MULTI_PAGE_REG) {
 		switch (sc->sc_phytype) {
 		case WMPHY_IGP:
 		case WMPHY_IGP_2:
 		case WMPHY_IGP_3:
 			rv = wm_gmii_mdic_writereg(dev, phy,
 			    IGPHY_PAGE_SELECT, reg);
 			if (rv != 0)
 				return rv;
 			break;
 		default:
 #ifdef WM_DEBUG
 			device_printf(dev, "%s: PHYTYPE = 0x%x, addr = %02x\n",
 			    __func__, sc->sc_phytype, reg);
 #endif
 			break;
+		}
+	}
 	return wm_gmii_mdic_readreg(dev, phy, reg & MII_ADDRMASK, val);
+}
 /*
  * wm_gmii_i82544_writereg:	[mii interface function]
+ *
  *	Write a PHY register on the GMII.
  */
 static int
 wm_gmii_i82544_writereg(device_t dev, int phy, int reg, uint16_t val)
+{
 	struct wm_softc *sc = device_private(dev);
 	int rv;
 	if (sc->phy.acquire(sc)) {
 		device_printf(dev, "%s: failed to get semaphore\n", __func__);
 		return -1;
+	}
 	rv = wm_gmii_i82544_writereg_locked(dev, phy, reg & MII_ADDRMASK, val);
 	sc->phy.release(sc);
 	return rv;
+}
 static int
 wm_gmii_i82544_writereg_locked(device_t dev, int phy, int reg, uint16_t val)
+{
 	struct wm_softc *sc = device_private(dev);
 	int rv;
 	if (reg > BME1000_MAX_MULTI_PAGE_REG) {
 		switch (sc->sc_phytype) {
 		case WMPHY_IGP:
 		case WMPHY_IGP_2:
 		case WMPHY_IGP_3:
 			rv = wm_gmii_mdic_writereg(dev, phy,
 			    IGPHY_PAGE_SELECT, reg);
 			if (rv != 0)
 				return rv;
 			break;
 		default:
 #ifdef WM_DEBUG
 			device_printf(dev, "%s: PHYTYPE == 0x%x, addr = %02x",
 			    __func__, sc->sc_phytype, reg);
 #endif
 			break;
+		}
+	}
 	return wm_gmii_mdic_writereg(dev, phy, reg & MII_ADDRMASK, val);
+}
 /*
  * wm_gmii_i80003_readreg:	[mii interface function]
+ *
  *	Read a PHY register on the kumeran
  * This could be handled by the PHY layer if we didn't have to lock the
  * resource ...
  */
 static int
 wm_gmii_i80003_readreg(device_t dev, int phy, int reg, uint16_t *val)
+{
 	struct wm_softc *sc = device_private(dev);
 	int page_select;
 	uint16_t temp, temp2;
 	int rv = 0;
 	if (phy != 1) /* Only one PHY on kumeran bus */
 		return -1;
 	if (sc->phy.acquire(sc)) {
 		device_printf(dev, "%s: failed to get semaphore\n", __func__);
 		return -1;
+	}
 	if ((reg & MII_ADDRMASK) < GG82563_MIN_ALT_REG)
 		page_select = GG82563_PHY_PAGE_SELECT;
 	else {
 		/*
 		 * Use Alternative Page Select register to access registers
 		 * 30 and 31.
 		 */
 		page_select = GG82563_PHY_PAGE_SELECT_ALT;
+	}
 	temp = reg >> GG82563_PAGE_SHIFT;
 	if ((rv = wm_gmii_mdic_writereg(dev, phy, page_select, temp)) != 0)
 		goto out;
 	if ((sc->sc_flags & WM_F_80003_MDIC_WA) != 0) {
 		/*
 		 * Wait more 200us for a bug of the ready bit in the MDIC
 		 * register.
 		 */
 		delay(200);
 		rv = wm_gmii_mdic_readreg(dev, phy, page_select, &temp2);
 		if ((rv != 0) || (temp2 != temp)) {
 			device_printf(dev, "%s failed\n", __func__);
 			rv = -1;
 			goto out;
+		}
 		delay(200);
 		rv = wm_gmii_mdic_readreg(dev, phy, reg & MII_ADDRMASK, val);
 		delay(200);
 	} else
 		rv = wm_gmii_mdic_readreg(dev, phy, reg & MII_ADDRMASK, val);
 out:
 	sc->phy.release(sc);
 	return rv;
+}
 /*
  * wm_gmii_i80003_writereg:	[mii interface function]
+ *
  *	Write a PHY register on the kumeran.
  * This could be handled by the PHY layer if we didn't have to lock the
  * resource ...
  */
 static int
 wm_gmii_i80003_writereg(device_t dev, int phy, int reg, uint16_t val)
+{
 	struct wm_softc *sc = device_private(dev);
 	int page_select, rv;
 	uint16_t temp, temp2;
 	if (phy != 1) /* Only one PHY on kumeran bus */
 		return -1;
 	if (sc->phy.acquire(sc)) {
 		device_printf(dev, "%s: failed to get semaphore\n", __func__);
 		return -1;
+	}
 	if ((reg & MII_ADDRMASK) < GG82563_MIN_ALT_REG)
 		page_select = GG82563_PHY_PAGE_SELECT;
 	else {
 		/*
 		 * Use Alternative Page Select register to access registers
 		 * 30 and 31.
 		 */
 		page_select = GG82563_PHY_PAGE_SELECT_ALT;
+	}
 	temp = (uint16_t)reg >> GG82563_PAGE_SHIFT;
 	if ((rv = wm_gmii_mdic_writereg(dev, phy, page_select, temp)) != 0)
 		goto out;
 	if ((sc->sc_flags & WM_F_80003_MDIC_WA) != 0) {
 		/*
 		 * Wait more 200us for a bug of the ready bit in the MDIC
 		 * register.
 		 */
 		delay(200);
 		rv = wm_gmii_mdic_readreg(dev, phy, page_select, &temp2);
 		if ((rv != 0) || (temp2 != temp)) {
 			device_printf(dev, "%s failed\n", __func__);
 			rv = -1;
 			goto out;
+		}
 		delay(200);
 		rv = wm_gmii_mdic_writereg(dev, phy, reg & MII_ADDRMASK, val);
 		delay(200);
 	} else
 		rv = wm_gmii_mdic_writereg(dev, phy, reg & MII_ADDRMASK, val);
 out:
 	sc->phy.release(sc);
 	return rv;
+}
 /*
  * wm_gmii_bm_readreg:	[mii interface function]
+ *
  *	Read a PHY register on the kumeran
  * This could be handled by the PHY layer if we didn't have to lock the
  * resource ...
  */
 static int
 wm_gmii_bm_readreg(device_t dev, int phy, int reg, uint16_t *val)
+{
 	struct wm_softc *sc = device_private(dev);
 	uint16_t page = reg >> BME1000_PAGE_SHIFT;
 	int rv;
 	if (sc->phy.acquire(sc)) {
 		device_printf(dev, "%s: failed to get semaphore\n", __func__);
 		return -1;
+	}
 	if ((sc->sc_type != WM_T_82574) && (sc->sc_type != WM_T_82583))
 		phy = ((page >= 768) || ((page == 0) && (reg == 25))
 		    || (reg == 31)) ? 1 : phy;
 	/* Page 800 works differently than the rest so it has its own func */
 	if (page == BM_WUC_PAGE) {
 		rv = wm_access_phy_wakeup_reg_bm(dev, reg, val, true, false);
 		goto release;
+	}
 	if (reg > BME1000_MAX_MULTI_PAGE_REG) {
 		if ((phy == 1) && (sc->sc_type != WM_T_82574)
 		    && (sc->sc_type != WM_T_82583))
 			rv = wm_gmii_mdic_writereg(dev, phy,
 			    IGPHY_PAGE_SELECT, page << BME1000_PAGE_SHIFT);
 		else
 			rv = wm_gmii_mdic_writereg(dev, phy,
 			    BME1000_PHY_PAGE_SELECT, page);
 		if (rv != 0)
 			goto release;
+	}
 	rv = wm_gmii_mdic_readreg(dev, phy, reg & MII_ADDRMASK, val);
 release:
 	sc->phy.release(sc);
 	return rv;
+}
 /*
  * wm_gmii_bm_writereg:	[mii interface function]
+ *
  *	Write a PHY register on the kumeran.
  * This could be handled by the PHY layer if we didn't have to lock the
  * resource ...
  */
 static int
 wm_gmii_bm_writereg(device_t dev, int phy, int reg, uint16_t val)
+{
 	struct wm_softc *sc = device_private(dev);
 	uint16_t page = reg >> BME1000_PAGE_SHIFT;
 	int rv;
 	if (sc->phy.acquire(sc)) {
 		device_printf(dev, "%s: failed to get semaphore\n", __func__);
 		return -1;
+	}
 	if ((sc->sc_type != WM_T_82574) && (sc->sc_type != WM_T_82583))
 		phy = ((page >= 768) || ((page == 0) && (reg == 25))
 		    || (reg == 31)) ? 1 : phy;
 	/* Page 800 works differently than the rest so it has its own func */
 	if (page == BM_WUC_PAGE) {
 		rv = wm_access_phy_wakeup_reg_bm(dev, reg, &val, false, false);
 		goto release;
+	}
 	if (reg > BME1000_MAX_MULTI_PAGE_REG) {
 		if ((phy == 1) && (sc->sc_type != WM_T_82574)
 		    && (sc->sc_type != WM_T_82583))
 			rv = wm_gmii_mdic_writereg(dev, phy,
 			    IGPHY_PAGE_SELECT, page << BME1000_PAGE_SHIFT);
 		else
 			rv = wm_gmii_mdic_writereg(dev, phy,
 			    BME1000_PHY_PAGE_SELECT, page);
 		if (rv != 0)
 			goto release;
+	}
 	rv = wm_gmii_mdic_writereg(dev, phy, reg & MII_ADDRMASK, val);
 release:
 	sc->phy.release(sc);
 	return rv;
+}
 /*
  *  wm_enable_phy_wakeup_reg_access_bm - enable access to BM wakeup registers
  *  @dev: pointer to the HW structure
  *  @phy_reg: pointer to store original contents of BM_WUC_ENABLE_REG
+ *
  *  Assumes semaphore already acquired and phy_reg points to a valid memory
  *  address to store contents of the BM_WUC_ENABLE_REG register.
  */
 static int
 wm_enable_phy_wakeup_reg_access_bm(device_t dev, uint16_t *phy_regp)
+{
 #ifdef WM_DEBUG
 	struct wm_softc *sc = device_private(dev);
 #endif
 	uint16_t temp;
 	int rv;
 	DPRINTF(sc, WM_DEBUG_INIT, ("%s: %s called\n",
 		device_xname(dev), __func__));
 	if (!phy_regp)
 		return -1;
 	/* All page select, port ctrl and wakeup registers use phy address 1 */
 	/* Select Port Control Registers page */
 	rv = wm_gmii_mdic_writereg(dev, 1, IGPHY_PAGE_SELECT,
 	    BM_PORT_CTRL_PAGE << IGP3_PAGE_SHIFT);
 	if (rv != 0)
 		return rv;
 	/* Read WUCE and save it */
 	rv = wm_gmii_mdic_readreg(dev, 1, BM_WUC_ENABLE_REG, phy_regp);
 	if (rv != 0)
 		return rv;
 	/* Enable both PHY wakeup mode and Wakeup register page writes.
 	 * Prevent a power state change by disabling ME and Host PHY wakeup.
 	 */
 	temp = *phy_regp;
 	temp |= BM_WUC_ENABLE_BIT;
 	temp &= ~(BM_WUC_ME_WU_BIT | BM_WUC_HOST_WU_BIT);
 	if ((rv = wm_gmii_mdic_writereg(dev, 1, BM_WUC_ENABLE_REG, temp)) != 0)
 		return rv;