Sun Feb 20 18:56:01 2022 UTC ()
Convert assembly to something both gcc and clang understand.


(christos)
diff -r1.1 -r1.2 src/sys/arch/evbppc/dht/locore.S
cvs diff -r1.1 -r1.2 src/sys/arch/evbppc/dht/locore.S (expand / switch to unified diff)

--- src/sys/arch/evbppc/dht/locore.S 2021/04/02 07:00:33 1.1
+++ src/sys/arch/evbppc/dht/locore.S 2022/02/20 18:56:01 1.2
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: locore.S,v 1.1 2021/04/02 07:00:33 rin Exp $ */ 1/* $NetBSD: locore.S,v 1.2 2022/02/20 18:56:01 christos Exp $ */
2 2
3/* 3/*
4 * Taken from src/sys/arch/powerpc/ibm4xx/openbios/locore.s: 4 * Taken from src/sys/arch/powerpc/ibm4xx/openbios/locore.s:
5 * NetBSD: locore.S,v 1.17 2021/03/30 01:57:20 rin Exp 5 * NetBSD: locore.S,v 1.17 2021/03/30 01:57:20 rin Exp
6 */ 6 */
7 7
8/* 8/*
9 * Copyright 2001 Wasabi Systems, Inc. 9 * Copyright 2001 Wasabi Systems, Inc.
10 * All rights reserved. 10 * All rights reserved.
11 * 11 *
12 * Written by Eduardo Horvath and Simon Burge for Wasabi Systems, Inc. 12 * Written by Eduardo Horvath and Simon Burge for Wasabi Systems, Inc.
13 * 13 *
14 * Redistribution and use in source and binary forms, with or without 14 * Redistribution and use in source and binary forms, with or without
@@ -110,29 +110,29 @@ _C_LABEL(kernel_text): @@ -110,29 +110,29 @@ _C_LABEL(kernel_text):
110 .globl __start 110 .globl __start
111__start: 111__start:
112 li %r0,0 112 li %r0,0
113 mtmsr %r0 /* Disable FPU/MMU/exceptions */ 113 mtmsr %r0 /* Disable FPU/MMU/exceptions */
114 isync 114 isync
115 115
116 /* 116 /*
117 * Errata 213: Incorrect data may be flushed from the data cache. 117 * Errata 213: Incorrect data may be flushed from the data cache.
118 * Cores: PPC405D5X1, PPC405D5X2 118 * Cores: PPC405D5X1, PPC405D5X2
119 * Workaround: #1, CCR0 modification sequence #2 119 * Workaround: #1, CCR0 modification sequence #2
120 * Note: Meaning of bits we need to set is undocumented. 120 * Note: Meaning of bits we need to set is undocumented.
121 */ 121 */
122 sync 122 sync
123 mfccr0 %r0 123 mfspr %r0,947 /* mfccr0 %r0 */
124 oris %r0,%r0,0x50000000@h 124 oris %r0,%r0,0x50000000@h
125 mtccr0 %r0 125 mtspr 947,%r0 /* mtccr0 %r0 */
126 isync 126 isync
127 127
128 /* PPC405GP errata, item #58. 128 /* PPC405GP errata, item #58.
129 * Load string instructions may write incorrect data into the last GPR 129 * Load string instructions may write incorrect data into the last GPR
130 * targeted in the operation. 130 * targeted in the operation.
131 * Workaround: set OCM0_DSCNTL[DSEN]=0 and OCM0_DSCNTL[DOF]=0 */ 131 * Workaround: set OCM0_DSCNTL[DSEN]=0 and OCM0_DSCNTL[DOF]=0 */
132 li %r0,0 132 li %r0,0
133 mtdcr DCR_OCM0_DSCNTL, %r0 /* Disable Data access to OCM */ 133 mtdcr DCR_OCM0_DSCNTL, %r0 /* Disable Data access to OCM */
134 mtdcr DCR_OCM0_ISCNTL, %r0 /* Disable Instruction access to OCM. 134 mtdcr DCR_OCM0_ISCNTL, %r0 /* Disable Instruction access to OCM.
135 Just in case */ 135 Just in case */
136#ifdef PPC_4XX_NOCACHE 136#ifdef PPC_4XX_NOCACHE
137 /* Disable all caches for physical addresses */ 137 /* Disable all caches for physical addresses */
138 li %r0,0 138 li %r0,0