Sun Feb 27 19:22:12 2022 UTC ()
mips: Redefine BDSYNC as sync on Octeon, not syncw.

BDSYNC is used for membar_sync, which is supposed to be a full
sequential consistency barrier, which is not provided by syncw, so
this is necessary for correctness.

BDSYNC is not used for anything else, so this can't hurt performance,
except where it was necessary for correctness anyway or where the
semantic choice of membar_sync was too strong anyway.


(riastradh)
diff -r1.67 -r1.68 src/sys/arch/mips/include/asm.h

cvs diff -r1.67 -r1.68 src/sys/arch/mips/include/asm.h (expand / switch to context diff)
--- src/sys/arch/mips/include/asm.h 2022/02/27 19:22:02 1.67
+++ src/sys/arch/mips/include/asm.h 2022/02/27 19:22:12 1.68
@@ -1,4 +1,4 @@
-/*	$NetBSD: asm.h,v 1.67 2022/02/27 19:22:02 riastradh Exp $	*/
+/*	$NetBSD: asm.h,v 1.68 2022/02/27 19:22:12 riastradh Exp $	*/
 
 /*
  * Copyright (c) 1992, 1993
@@ -574,7 +574,7 @@
 #if defined(__OCTEON__)
 				/* early cnMIPS have erratum which means 2 */
 #define	LLSCSYNC	sync 4; sync 4
-#define	BDSYNC		sync 4		/* sync 4 == syncw - sync all writes */
+#define	BDSYNC		sync
 #define	BDSYNC_ACQ	sync
 #define	SYNC_ACQ	sync
 #define	SYNC_REL	sync