 @@ -1,741 +1,741 @@
-/* $NetBSD: cpu.c,v 1.68 2021/11/12 06:44:46 skrll Exp $ */
+/* $NetBSD: cpu.c,v 1.69 2022/03/03 06:26:05 riastradh Exp $ */
 /*
  * Copyright (c) 2017 Ryo Shimizu <ryo@nerv.org>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: cpu.c,v 1.68 2021/11/12 06:44:46 skrll Exp $");
+__KERNEL_RCSID(1, "$NetBSD: cpu.c,v 1.69 2022/03/03 06:26:05 riastradh Exp $");
 #include "locators.h"
 #include "opt_arm_debug.h"
 #include "opt_ddb.h"
 #include "opt_fdt.h"
 #include "opt_multiprocessor.h"
 #include <sys/param.h>
 #include <sys/atomic.h>
 #include <sys/cpu.h>
 #include <sys/device.h>
 #include <sys/kmem.h>
 #include <sys/reboot.h>
 #include <sys/rndsource.h>
 #include <sys/sysctl.h>
 #include <sys/systm.h>
 #include <crypto/aes/aes_impl.h>
 #include <crypto/aes/arch/arm/aes_armv8.h>
 #include <crypto/aes/arch/arm/aes_neon.h>
 #include <crypto/chacha/chacha_impl.h>
 #include <crypto/chacha/arch/arm/chacha_neon.h>
 #include <aarch64/armreg.h>
 #include <aarch64/cpu.h>
 #include <aarch64/cpu_counter.h>
 #ifdef DDB
 #include <aarch64/db_machdep.h>
 #endif
 #include <aarch64/machdep.h>
 #include <arm/cpufunc.h>
 #include <arm/cpu_topology.h>
 #ifdef FDT
 #include <arm/fdt/arm_fdtvar.h>
 #endif
 #ifdef VERBOSE_INIT_ARM
 #define VPRINTF(...)	printf(__VA_ARGS__)
 #else
 #define VPRINTF(...)	__nothing
 #endif
 void cpu_attach(device_t, cpuid_t);
 void cpu_setup_id(struct cpu_info *);
 static void identify_aarch64_model(uint32_t, char *, size_t);
 static void cpu_identify(device_t self, struct cpu_info *);
 static void cpu_identify1(device_t self, struct cpu_info *);
 static void cpu_identify2(device_t self, struct cpu_info *);
 static void cpu_init_counter(struct cpu_info *);
 static void cpu_setup_sysctl(device_t, struct cpu_info *);
 static void cpu_setup_rng(device_t, struct cpu_info *);
 static void cpu_setup_aes(device_t, struct cpu_info *);
 static void cpu_setup_chacha(device_t, struct cpu_info *);
 #ifdef MULTIPROCESSOR
 #define NCPUINFO	MAXCPUS
 #else
 #define NCPUINFO	1
 #endif /* MULTIPROCESSOR */
 /*
  * Our exported cpu_info structs; these will be first used by the
  * secondary cpus as part of cpu_mpstart and the hatching process.
  */
 struct cpu_info cpu_info_store[NCPUINFO] = {
 	[0] = {
 		.ci_cpl = IPL_HIGH,
 		.ci_curlwp = &lwp0
+	}
 };
 void
 cpu_attach(device_t dv, cpuid_t id)
+{
 	struct cpu_info *ci;
 	const int unit = device_unit(dv);
 	if (unit == 0) {
 		ci = curcpu();
 		ci->ci_cpuid = id;
 	} else {
 #ifdef MULTIPROCESSOR
 		if ((boothowto & RB_MD1) != 0) {
 			aprint_naive("\n");
 			aprint_normal(": multiprocessor boot disabled\n");
 			return;
+		}
 		KASSERT(unit < MAXCPUS);
 		ci = &cpu_info_store[unit];
 		ci->ci_cpl = IPL_HIGH;
 		ci->ci_cpuid = id;
 		/* ci_id is stored by own cpus when hatching */
 		cpu_info[ncpu] = ci;
 		if (cpu_hatched_p(unit) == 0) {
 			ci->ci_dev = dv;
-			dv->dv_private = ci;
+			device_set_private(dv, ci);
 			ci->ci_index = -1;
 			aprint_naive(": disabled\n");
 			aprint_normal(": disabled (unresponsive)\n");
 			return;
+		}
 #else /* MULTIPROCESSOR */
 		aprint_naive(": disabled\n");
 		aprint_normal(": disabled (uniprocessor kernel)\n");
 		return;
 #endif /* MULTIPROCESSOR */
+	}
 	ci->ci_dev = dv;
-	dv->dv_private = ci;
+	device_set_private(dv, ci);
 	ci->ci_kfpu_spl = -1;
 	arm_cpu_do_topology(ci);	// XXXNH move this after mi_cpu_attach
 	cpu_identify(dv, ci);
 	cpu_setup_sysctl(dv, ci);
 #ifdef MULTIPROCESSOR
 	if (unit != 0) {
 		mi_cpu_attach(ci);
 		pmap_tlb_info_attach(&pmap_tlb0_info, ci);
 		aarch64_parsecacheinfo(ci);
+	}
 #endif /* MULTIPROCESSOR */
 	fpu_attach(ci);
 	cpu_identify1(dv, ci);
 	aarch64_printcacheinfo(dv, ci);
 	cpu_identify2(dv, ci);
 	if (unit != 0) {
 	    return;
+	}
 	db_machdep_init(ci);
 	cpu_init_counter(ci);
 	/* These currently only check the BP. */
 	cpu_setup_rng(dv, ci);
 	cpu_setup_aes(dv, ci);
 	cpu_setup_chacha(dv, ci);
+}
 struct cpuidtab {
 	uint32_t cpu_partnum;
 	const char *cpu_name;
 	const char *cpu_vendor;
 	const char *cpu_architecture;
 };
 #define CPU_PARTMASK	(CPU_ID_IMPLEMENTOR_MASK | CPU_ID_PARTNO_MASK)
 const struct cpuidtab cpuids[] = {
 	{ CPU_ID_CORTEXA35R0 & CPU_PARTMASK, "Cortex-A35", "Arm", "v8-A" },
 	{ CPU_ID_CORTEXA53R0 & CPU_PARTMASK, "Cortex-A53", "Arm", "v8-A" },
 	{ CPU_ID_CORTEXA57R0 & CPU_PARTMASK, "Cortex-A57", "Arm", "v8-A" },
 	{ CPU_ID_CORTEXA55R1 & CPU_PARTMASK, "Cortex-A55", "Arm", "v8.2-A+" },
 	{ CPU_ID_CORTEXA65R0 & CPU_PARTMASK, "Cortex-A65", "Arm", "v8.2-A+" },
 	{ CPU_ID_CORTEXA72R0 & CPU_PARTMASK, "Cortex-A72", "Arm", "v8-A" },
 	{ CPU_ID_CORTEXA73R0 & CPU_PARTMASK, "Cortex-A73", "Arm", "v8-A" },
 	{ CPU_ID_CORTEXA75R2 & CPU_PARTMASK, "Cortex-A75", "Arm", "v8.2-A+" },
 	{ CPU_ID_CORTEXA76R3 & CPU_PARTMASK, "Cortex-A76", "Arm", "v8.2-A+" },
 	{ CPU_ID_CORTEXA76AER1 & CPU_PARTMASK, "Cortex-A76AE", "Arm", "v8.2-A+" },
 	{ CPU_ID_CORTEXA77R0 & CPU_PARTMASK, "Cortex-A77", "Arm", "v8.2-A+" },
 	{ CPU_ID_NVIDIADENVER2 & CPU_PARTMASK, "Denver2", "NVIDIA", "v8-A" },
 	{ CPU_ID_EMAG8180 & CPU_PARTMASK, "eMAG", "Ampere", "v8-A" },
 	{ CPU_ID_NEOVERSEE1R1 & CPU_PARTMASK, "Neoverse E1", "Arm", "v8.2-A+" },
 	{ CPU_ID_NEOVERSEN1R3 & CPU_PARTMASK, "Neoverse N1", "Arm", "v8.2-A+" },
 	{ CPU_ID_THUNDERXRX, "ThunderX", "Cavium", "v8-A" },
 	{ CPU_ID_THUNDERX81XXRX, "ThunderX CN81XX", "Cavium", "v8-A" },
 	{ CPU_ID_THUNDERX83XXRX, "ThunderX CN83XX", "Cavium", "v8-A" },
 	{ CPU_ID_THUNDERX2RX, "ThunderX2", "Marvell", "v8.1-A" },
 	{ CPU_ID_APPLE_M1_ICESTORM & CPU_PARTMASK, "M1 Icestorm", "Apple", "Apple Silicon" },
 	{ CPU_ID_APPLE_M1_FIRESTORM & CPU_PARTMASK, "M1 Firestorm", "Apple", "Apple Silicon" },
 };
 static void
 identify_aarch64_model(uint32_t cpuid, char *buf, size_t len)
+{
 	int i;
 	uint32_t cpupart, variant, revision;
 	cpupart = cpuid & CPU_PARTMASK;
 	variant = __SHIFTOUT(cpuid, CPU_ID_VARIANT_MASK);
 	revision = __SHIFTOUT(cpuid, CPU_ID_REVISION_MASK);
 	for (i = 0; i < __arraycount(cpuids); i++) {
 		if (cpupart == cpuids[i].cpu_partnum) {
 			snprintf(buf, len, "%s %s r%dp%d (%s)",
 			    cpuids[i].cpu_vendor, cpuids[i].cpu_name,
 			    variant, revision,
 			    cpuids[i].cpu_architecture);
 			return;
+		}
+	}
 	snprintf(buf, len, "unknown CPU (ID = 0x%08x)", cpuid);
+}
 static void
 cpu_identify(device_t self, struct cpu_info *ci)
+{
 	char model[128];
 	const char *m;
 	identify_aarch64_model(ci->ci_id.ac_midr, model, sizeof(model));
 	aprint_naive("\n");
 	aprint_normal(": %s, id 0x%lx\n", model, ci->ci_cpuid);
 	aprint_normal_dev(ci->ci_dev, "package %u, core %u, smt %u\n",
 	    ci->ci_package_id, ci->ci_core_id, ci->ci_smt_id);
 	if (ci->ci_index == 0) {
 		m = cpu_getmodel();
 		if (m == NULL || *m == 0)
 			cpu_setmodel("%s", model);
 		if (CPU_ID_ERRATA_CAVIUM_THUNDERX_1_1_P(ci->ci_id.ac_midr))
 			aprint_normal("WARNING: ThunderX Pass 1.1 detected.\n"
 			    "This has known hardware bugs that may cause the "
 			    "incorrect operation of atomic operations.\n");
+	}
+}
 static void
 cpu_identify1(device_t self, struct cpu_info *ci)
+{
 	struct aarch64_sysctl_cpu_id *id = &ci->ci_id;
 	uint64_t sctlr = ci->ci_sctlr_el1;
 	if (sctlr & SCTLR_I)
 		aprint_verbose_dev(self, "IC enabled");
 	else
 		aprint_verbose_dev(self, "IC disabled");
 	if (sctlr & SCTLR_C)
 		aprint_verbose(", DC enabled");
 	else
 		aprint_verbose(", DC disabled");
 	if (sctlr & SCTLR_A)
 		aprint_verbose(", Alignment check enabled\n");
 	else {
 		switch (sctlr & (SCTLR_SA | SCTLR_SA0)) {
 		case SCTLR_SA | SCTLR_SA0:
 			aprint_verbose(
 			    ", EL0/EL1 stack Alignment check enabled\n");
 			break;
 		case SCTLR_SA:
 			aprint_verbose(", EL1 stack Alignment check enabled\n");
 			break;
 		case SCTLR_SA0:
 			aprint_verbose(", EL0 stack Alignment check enabled\n");
 			break;
 		case 0:
 			aprint_verbose(", Alignment check disabled\n");
 			break;
+		}
+	}
 	/*
 	 * CTR - Cache Type Register
 	 */
 	const uint64_t ctr = id->ac_ctr;
 	const uint64_t clidr = id->ac_clidr;
 	aprint_verbose_dev(self, "Cache Writeback Granule %" PRIu64 "B,"
 	    " Exclusives Reservation Granule %" PRIu64 "B\n",
 	    __SHIFTOUT(ctr, CTR_EL0_CWG_LINE) * 4,
 	    __SHIFTOUT(ctr, CTR_EL0_ERG_LINE) * 4);
 	aprint_verbose_dev(self, "Dcache line %ld, Icache line %ld"
 	    ", DIC=%lu, IDC=%lu, LoUU=%lu, LoC=%lu, LoUIS=%lu\n",
 	    sizeof(int) << __SHIFTOUT(ctr, CTR_EL0_DMIN_LINE),
 	    sizeof(int) << __SHIFTOUT(ctr, CTR_EL0_IMIN_LINE),
 	    __SHIFTOUT(ctr, CTR_EL0_DIC),
 	    __SHIFTOUT(ctr, CTR_EL0_IDC),
 	    __SHIFTOUT(clidr, CLIDR_LOUU),
 	    __SHIFTOUT(clidr, CLIDR_LOC),
 	    __SHIFTOUT(clidr, CLIDR_LOUIS));
+}
 /*
  * identify vfp, etc.
  */
 static void
 cpu_identify2(device_t self, struct cpu_info *ci)
+{
 	struct aarch64_sysctl_cpu_id * const id = &ci->ci_id;
 	aprint_debug_dev(self, "midr=0x%" PRIx32 " mpidr=0x%" PRIx32 "\n",
 	    (uint32_t)id->ac_midr, (uint32_t)id->ac_mpidr);
 	aprint_verbose_dev(self, "revID=0x%" PRIx64, id->ac_revidr);
 	/* ID_AA64DFR0_EL1 */
 	switch (__SHIFTOUT(id->ac_aa64dfr0, ID_AA64DFR0_EL1_PMUVER)) {
 	case ID_AA64DFR0_EL1_PMUVER_V3:
 		aprint_verbose(", PMCv3");
 		break;
 	case ID_AA64DFR0_EL1_PMUVER_NOV3:
 		aprint_verbose(", PMC");
 		break;
+	}
 	/* ID_AA64MMFR0_EL1 */
 	switch (__SHIFTOUT(id->ac_aa64mmfr0, ID_AA64MMFR0_EL1_TGRAN4)) {
 	case ID_AA64MMFR0_EL1_TGRAN4_4KB:
 		aprint_verbose(", 4k table");
 		break;
+	}
 	switch (__SHIFTOUT(id->ac_aa64mmfr0, ID_AA64MMFR0_EL1_TGRAN16)) {
 	case ID_AA64MMFR0_EL1_TGRAN16_16KB:
 		aprint_verbose(", 16k table");
 		break;
+	}
 	switch (__SHIFTOUT(id->ac_aa64mmfr0, ID_AA64MMFR0_EL1_TGRAN64)) {
 	case ID_AA64MMFR0_EL1_TGRAN64_64KB:
 		aprint_verbose(", 64k table");
 		break;
+	}
 	switch (__SHIFTOUT(id->ac_aa64mmfr0, ID_AA64MMFR0_EL1_ASIDBITS)) {
 	case ID_AA64MMFR0_EL1_ASIDBITS_8BIT:
 		aprint_verbose(", 8bit ASID");
 		break;
 	case ID_AA64MMFR0_EL1_ASIDBITS_16BIT:
 		aprint_verbose(", 16bit ASID");
 		break;
+	}
 	aprint_verbose("\n");
 	aprint_verbose_dev(self, "auxID=0x%" PRIx64, ci->ci_id.ac_aa64isar0);
 	/* PFR0 */
 	switch (__SHIFTOUT(id->ac_aa64pfr0, ID_AA64PFR0_EL1_CSV3)) {
 	case ID_AA64PFR0_EL1_CSV3_IMPL:
 		aprint_verbose(", CSV3");
 		break;
+	}
 	switch (__SHIFTOUT(id->ac_aa64pfr0, ID_AA64PFR0_EL1_CSV2)) {
 	case ID_AA64PFR0_EL1_CSV2_IMPL:
 		aprint_verbose(", CSV2");
 		break;
+	}
 	switch (__SHIFTOUT(id->ac_aa64pfr0, ID_AA64PFR0_EL1_GIC)) {
 	case ID_AA64PFR0_EL1_GIC_CPUIF_EN:
 		aprint_verbose(", GICv3");
 		break;
+	}
 	switch (__SHIFTOUT(id->ac_aa64pfr0, ID_AA64PFR0_EL1_FP)) {
 	case ID_AA64PFR0_EL1_FP_NONE:
 		break;
 	default:
 		aprint_verbose(", FP");
 		break;
+	}
 	/* ISAR0 */
 	switch (__SHIFTOUT(id->ac_aa64isar0, ID_AA64ISAR0_EL1_CRC32)) {
 	case ID_AA64ISAR0_EL1_CRC32_CRC32X:
 		aprint_verbose(", CRC32");
 		break;
+	}
 	switch (__SHIFTOUT(id->ac_aa64isar0, ID_AA64ISAR0_EL1_SHA1)) {
 	case ID_AA64ISAR0_EL1_SHA1_SHA1CPMHSU:
 		aprint_verbose(", SHA1");
 		break;
+	}
 	switch (__SHIFTOUT(id->ac_aa64isar0, ID_AA64ISAR0_EL1_SHA2)) {
 	case ID_AA64ISAR0_EL1_SHA2_SHA256HSU:
 		aprint_verbose(", SHA256");
 		break;
+	}
 	switch (__SHIFTOUT(id->ac_aa64isar0, ID_AA64ISAR0_EL1_AES)) {
 	case ID_AA64ISAR0_EL1_AES_AES:
 		aprint_verbose(", AES");
 		break;
 	case ID_AA64ISAR0_EL1_AES_PMUL:
 		aprint_verbose(", AES+PMULL");
 		break;
+	}
 	switch (__SHIFTOUT(id->ac_aa64isar0, ID_AA64ISAR0_EL1_RNDR)) {
 	case ID_AA64ISAR0_EL1_RNDR_RNDRRS:
 		aprint_verbose(", RNDRRS");
 		break;
+	}
 	/* PFR0:DIT -- data-independent timing support */
 	switch (__SHIFTOUT(id->ac_aa64pfr0, ID_AA64PFR0_EL1_DIT)) {
 	case ID_AA64PFR0_EL1_DIT_IMPL:
 		aprint_verbose(", DIT");
 		break;
+	}
 	/* PFR0:AdvSIMD */
 	switch (__SHIFTOUT(id->ac_aa64pfr0, ID_AA64PFR0_EL1_ADVSIMD)) {
 	case ID_AA64PFR0_EL1_ADV_SIMD_NONE:
 		break;
 	default:
 		aprint_verbose(", NEON");
 		break;
+	}
 	/* MVFR0/MVFR1 */
 	switch (__SHIFTOUT(id->ac_mvfr0, MVFR0_FPROUND)) {
 	case MVFR0_FPROUND_ALL:
 		aprint_verbose(", rounding");
 		break;
+	}
 	switch (__SHIFTOUT(id->ac_mvfr0, MVFR0_FPTRAP)) {
 	case MVFR0_FPTRAP_TRAP:
 		aprint_verbose(", exceptions");
 		break;
+	}
 	switch (__SHIFTOUT(id->ac_mvfr1, MVFR1_FPDNAN)) {
 	case MVFR1_FPDNAN_NAN:
 		aprint_verbose(", NaN propagation");
 		break;
+	}
 	switch (__SHIFTOUT(id->ac_mvfr1, MVFR1_FPFTZ)) {
 	case MVFR1_FPFTZ_DENORMAL:
 		aprint_verbose(", denormals");
 		break;
+	}
 	switch (__SHIFTOUT(id->ac_mvfr0, MVFR0_SIMDREG)) {
 	case MVFR0_SIMDREG_16x64:
 		aprint_verbose(", 16x64bitRegs");
 		break;
 	case MVFR0_SIMDREG_32x64:
 		aprint_verbose(", 32x64bitRegs");
 		break;
+	}
 	switch (__SHIFTOUT(id->ac_mvfr1, MVFR1_SIMDFMAC)) {
 	case MVFR1_SIMDFMAC_FMAC:
 		aprint_verbose(", Fused Multiply-Add");
 		break;
+	}
 	aprint_verbose("\n");
+}
 /*
  * Enable the performance counter, then estimate frequency for
  * the current PE and store the result in cpu_cc_freq.
  */
 static void
 cpu_init_counter(struct cpu_info *ci)
+{
 	const uint64_t dfr0 = reg_id_aa64dfr0_el1_read();
 	const u_int pmuver = __SHIFTOUT(dfr0, ID_AA64DFR0_EL1_PMUVER);
 	if (pmuver == ID_AA64DFR0_EL1_PMUVER_NONE) {
 		/* Performance Monitors Extension not implemented. */
 		return;
+	}
 	if (pmuver == ID_AA64DFR0_EL1_PMUVER_IMPL) {
 		/* Non-standard Performance Monitors are not supported. */
 		return;
+	}
 	reg_pmcr_el0_write(PMCR_E | PMCR_C);
 	reg_pmcntenset_el0_write(PMCNTEN_C);
 	const uint32_t prev = cpu_counter32();
 	delay(100000);
 	ci->ci_data.cpu_cc_freq = (cpu_counter32() - prev) * 10;
+}
 /*
  * Fill in this CPUs id data.  Must be called on all cpus.
  */
 void __noasan
 cpu_setup_id(struct cpu_info *ci)
+{
 	struct aarch64_sysctl_cpu_id *id = &ci->ci_id;
 	/* SCTLR - System Control Register */
 	ci->ci_sctlr_el1 = reg_sctlr_el1_read();
 	memset(id, 0, sizeof *id);
 	id->ac_midr      = reg_midr_el1_read();
 	id->ac_revidr    = reg_revidr_el1_read();
 	id->ac_mpidr     = reg_mpidr_el1_read();
 	id->ac_aa64dfr0  = reg_id_aa64dfr0_el1_read();
 	id->ac_aa64dfr1  = reg_id_aa64dfr1_el1_read();
 	id->ac_aa64isar0 = reg_id_aa64isar0_el1_read();
 	id->ac_aa64isar1 = reg_id_aa64isar1_el1_read();
 	id->ac_aa64mmfr0 = reg_id_aa64mmfr0_el1_read();
 	id->ac_aa64mmfr1 = reg_id_aa64mmfr1_el1_read();
 	id->ac_aa64mmfr2 = reg_id_aa64mmfr2_el1_read();
 	id->ac_mvfr0     = reg_mvfr0_el1_read();
 	id->ac_mvfr1     = reg_mvfr1_el1_read();
 	id->ac_mvfr2     = reg_mvfr2_el1_read();
 	id->ac_clidr     = reg_clidr_el1_read();
 	id->ac_ctr       = reg_ctr_el0_read();
 	/* Only in ARMv8.2. */
 	id->ac_aa64zfr0  = 0 /* reg_id_aa64zfr0_el1_read() */;
 	id->ac_aa64pfr0  = reg_id_aa64pfr0_el1_read();
 	id->ac_aa64pfr1  = reg_id_aa64pfr1_el1_read();
+}
 /*
  * setup the per-cpu sysctl tree.
  */
 static void
 cpu_setup_sysctl(device_t dv, struct cpu_info *ci)
+{
 	const struct sysctlnode *cpunode = NULL;
 	sysctl_createv(NULL, 0, NULL, &cpunode,
 		       CTLFLAG_PERMANENT,
 		       CTLTYPE_NODE, device_xname(dv), NULL,
 		       NULL, 0, NULL, 0,
 		       CTL_MACHDEP,
 		       CTL_CREATE, CTL_EOL);
 	if (cpunode == NULL)
 		return;
 	sysctl_createv(NULL, 0, &cpunode, NULL,
 		       CTLFLAG_PERMANENT,
 		       CTLTYPE_STRUCT, "cpu_id", NULL,
 		       NULL, 0, &ci->ci_id, sizeof(ci->ci_id),
 		       CTL_CREATE, CTL_EOL);
+}
 static struct krndsource rndrrs_source;
 static void
 rndrrs_get(size_t nbytes, void *cookie)
+{
 	/* Entropy bits per data byte, wild-arse guess.  */
 	const unsigned bpb = 4;
 	size_t nbits = nbytes*NBBY;
 	uint64_t x;
 	int error;
 	while (nbits) {
 		/*
 		 * x := random 64-bit sample
 		 * error := Z bit, set to 1 if sample is bad
+		 *
 		 * XXX This should be done by marking the function
 		 * __attribute__((target("arch=armv8.5-a+rng"))) and
 		 * using `mrs %0, rndrrs', but:
+		 *
 		 * (a) the version of gcc we use doesn't support that,
 		 * and
 		 * (b) clang doesn't seem to like `rndrrs' itself.
+		 *
 		 * So we use the numeric encoding for now.
 		 */
 		__asm __volatile(""
 		    "mrs	%0, s3_3_c2_c4_1\n"
 		    "cset	%w1, eq"
 		    : "=r"(x), "=r"(error));
 		if (error)
 			break;
 		rnd_add_data_sync(&rndrrs_source, &x, sizeof(x),
 		    bpb*sizeof(x));
 		nbits -= MIN(nbits, bpb*sizeof(x));
+	}
 	explicit_memset(&x, 0, sizeof x);
+}
 /*
  * setup the RNDRRS entropy source
  */
 static void
 cpu_setup_rng(device_t dv, struct cpu_info *ci)
+{
 	struct aarch64_sysctl_cpu_id *id = &ci->ci_id;
 	/* Verify that it is supported.  */
 	switch (__SHIFTOUT(id->ac_aa64isar0, ID_AA64ISAR0_EL1_RNDR)) {
 	case ID_AA64ISAR0_EL1_RNDR_RNDRRS:
 		break;
 	default:
 		return;
+	}
 	/* Attach it.  */
 	rndsource_setcb(&rndrrs_source, rndrrs_get, NULL);
 	rnd_attach_source(&rndrrs_source, "rndrrs", RND_TYPE_RNG,
 	    RND_FLAG_DEFAULT|RND_FLAG_HASCB);
+}
 /*
  * setup the AES implementation
  */
 static void
 cpu_setup_aes(device_t dv, struct cpu_info *ci)
+{
 	struct aarch64_sysctl_cpu_id *id = &ci->ci_id;
 	/* Check for ARMv8.0-AES support.  */
 	switch (__SHIFTOUT(id->ac_aa64isar0, ID_AA64ISAR0_EL1_AES)) {
 	case ID_AA64ISAR0_EL1_AES_AES:
 	case ID_AA64ISAR0_EL1_AES_PMUL:
 		aes_md_init(&aes_armv8_impl);
 		return;
 	default:
 		break;
+	}
 	/* Failing that, check for SIMD support.  */
 	switch (__SHIFTOUT(id->ac_aa64pfr0, ID_AA64PFR0_EL1_ADVSIMD)) {
 	case ID_AA64PFR0_EL1_ADV_SIMD_IMPL:
 		aes_md_init(&aes_neon_impl);
 		return;
 	default:
 		break;
+	}
+}
 /*
  * setup the ChaCha implementation
  */
 static void
 cpu_setup_chacha(device_t dv, struct cpu_info *ci)
+{
 	struct aarch64_sysctl_cpu_id *id = &ci->ci_id;
 	/* Check for SIMD support.  */
 	switch (__SHIFTOUT(id->ac_aa64pfr0, ID_AA64PFR0_EL1_ADVSIMD)) {
 	case ID_AA64PFR0_EL1_ADV_SIMD_IMPL:
 		chacha_md_init(&chacha_neon_impl);
 		return;
 	default:
 		break;
+	}
+}
 #ifdef MULTIPROCESSOR
 /*
  * Initialise a secondary processor.
+ *
  * printf isn't available as kmutex(9) relies on curcpu which isn't setup yet.
+ *
  */
 void __noasan
 cpu_init_secondary_processor(int cpuindex)
+{
 	struct cpu_info * ci = &cpu_info_store[cpuindex];
 	struct aarch64_sysctl_cpu_id *id = &ci->ci_id;
 	aarch64_setcpufuncs(ci);
 	/* Sets ci->ci_{sctlr,midr,mpidr}, etc */
 	cpu_setup_id(ci);
 	arm_cpu_topology_set(ci, id->ac_mpidr);
 	aarch64_getcacheinfo(ci);
 	cpu_set_hatched(cpuindex);
 	/*
 	 * return to assembly to wait for cpu_boot_secondary_processors
 	 */
+}
 /*
  * When we are called, the MMU and caches are on and we are running on the stack
  * of the idlelwp for this cpu.
  */
 void
 cpu_hatch(struct cpu_info *ci)
+{
 	KASSERT(curcpu() == ci);
 	KASSERT((reg_tcr_el1_read() & TCR_EPD0) != 0);
 #ifdef DDB
 	db_machdep_cpu_init();
 #endif
 	cpu_init_counter(ci);
 	intr_cpu_init(ci);
 #ifdef FDT
 	arm_fdt_cpu_hatch(ci);
 #endif
 	/*
 	 * clear my bit of arm_cpu_mbox to tell cpu_boot_secondary_processors().
 	 * there are cpu0,1,2,3, and if cpu2 is unresponsive,
 	 * ci_index are each cpu0=0, cpu1=1, cpu2=undef, cpu3=2.
 	 * therefore we have to use device_unit instead of ci_index for mbox.
 	 */
 	cpu_clr_mbox(device_unit(ci->ci_dev));
+}
 #endif /* MULTIPROCESSOR */

 @@ -1,915 +1,915 @@
-/*	$NetBSD: cpu.c,v 1.152 2021/10/31 16:23:47 skrll Exp $	*/
+/*	$NetBSD: cpu.c,v 1.153 2022/03/03 06:26:05 riastradh Exp $	*/
 /*
  * Copyright (c) 1995 Mark Brinicombe.
  * Copyright (c) 1995 Brini.
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  * 3. All advertising materials mentioning features or use of this software
  *    must display the following acknowledgement:
  *	This product includes software developed by Brini.
  * 4. The name of the company nor the name of the author may be used to
  *    endorse or promote products derived from this software without specific
  *    prior written permission.
+ *
  * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
+ *
  * RiscBSD kernel project
+ *
  * cpu.c
+ *
  * Probing and configuration for the master CPU
+ *
  * Created      : 10/10/95
  */
 #include "opt_armfpe.h"
 #include "opt_cputypes.h"
 #include "opt_multiprocessor.h"
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.152 2021/10/31 16:23:47 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.153 2022/03/03 06:26:05 riastradh Exp $");
 #include <sys/param.h>
 #include <sys/conf.h>
 #include <sys/cpu.h>
 #include <sys/device.h>
 #include <sys/kmem.h>
 #include <sys/proc.h>
 #include <sys/reboot.h>
 #include <sys/systm.h>
 #include <uvm/uvm_extern.h>
 #include <arm/locore.h>
 #include <arm/undefined.h>
 #include <arm/cpu_topology.h>
 extern const char *cpu_arch;
 #ifdef MULTIPROCESSOR
 #ifdef MPDEBUG
 uint32_t arm_cpu_marker[2] __cacheline_aligned = { 0, 0 };
 #endif
 #endif
 /* Prototypes */
 void identify_arm_cpu(device_t, struct cpu_info *);
 void identify_features(device_t, struct cpu_info *);
 void identify_cortex_caches(device_t);
 /*
  * Identify the master (boot) CPU
  */
 void
 cpu_attach(device_t dv, cpuid_t id)
+{
 	const char * const xname = device_xname(dv);
 	const int unit = device_unit(dv);
 	struct cpu_info *ci;
 	if (unit == 0) {
 		ci = curcpu();
 		/* Read SCTLR from cpu */
 		ci->ci_ctrl = cpu_control(0, 0);
 		/* Get the CPU ID from coprocessor 15 */
 		ci->ci_cpuid = id;
 		ci->ci_arm_cpuid = cpu_idnum();
 		ci->ci_arm_cputype = ci->ci_arm_cpuid & CPU_ID_CPU_MASK;
 		ci->ci_arm_cpurev = ci->ci_arm_cpuid & CPU_ID_REVISION_MASK;
 		/*
 		 * Get other sysregs for BP. APs information is grabbed in
 		 * cpu_init_secondary_processor.
 		 */
 		ci->ci_actlr = armreg_auxctl_read();
 		ci->ci_revidr = armreg_revidr_read();
 	} else {
 #ifdef MULTIPROCESSOR
 		if ((boothowto & RB_MD1) != 0) {
 			aprint_naive("\n");
 			aprint_normal(": multiprocessor boot disabled\n");
 			return;
+		}
 		KASSERT(unit < MAXCPUS);
 		ci = &cpu_info_store[unit];
 		KASSERT(cpu_info[unit] == NULL);
 		ci->ci_cpl = IPL_HIGH;
 		ci->ci_cpuid = id;
 		ci->ci_data.cpu_cc_freq = cpu_info_store[0].ci_data.cpu_cc_freq;
 		ci->ci_undefsave[2] = cpu_info_store[0].ci_undefsave[2];
 		cpu_info[unit] = ci;
 		if (cpu_hatched_p(unit) == false) {
 			ci->ci_dev = dv;
-			dv->dv_private = ci;
+			device_set_private(dv, ci);
 			aprint_naive(": disabled\n");
 			aprint_normal(": disabled (unresponsive)\n");
 			return;
+		}
 #else
 		aprint_naive(": disabled\n");
 		aprint_normal(": disabled (uniprocessor kernel)\n");
 		return;
 #endif
+	}
 	ci->ci_dev = dv;
-	dv->dv_private = ci;
+	device_set_private(dv, ci);
 	arm_cpu_do_topology(ci);
 	evcnt_attach_dynamic(&ci->ci_arm700bugcount, EVCNT_TYPE_MISC,
 	    NULL, xname, "arm700swibug");
 	evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_WRTBUF_0], EVCNT_TYPE_TRAP,
 	    NULL, xname, "vector abort");
 	evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_WRTBUF_1], EVCNT_TYPE_TRAP,
 	    NULL, xname, "terminal abort");
 	evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_BUSERR_0], EVCNT_TYPE_TRAP,
 	    NULL, xname, "external linefetch abort (S)");
 	evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_BUSERR_1], EVCNT_TYPE_TRAP,
 	    NULL, xname, "external linefetch abort (P)");
 	evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_BUSERR_2], EVCNT_TYPE_TRAP,
 	    NULL, xname, "external non-linefetch abort (S)");
 	evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_BUSERR_3], EVCNT_TYPE_TRAP,
 	    NULL, xname, "external non-linefetch abort (P)");
 	evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_BUSTRNL1], EVCNT_TYPE_TRAP,
 	    NULL, xname, "external translation abort (L1)");
 	evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_BUSTRNL2], EVCNT_TYPE_TRAP,
 	    NULL, xname, "external translation abort (L2)");
 	evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_ALIGN_0], EVCNT_TYPE_TRAP,
 	    NULL, xname, "alignment abort (0)");
 	evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_ALIGN_1], EVCNT_TYPE_TRAP,
 	    NULL, xname, "alignment abort (1)");
 	evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_TRANS_S], EVCNT_TYPE_TRAP,
 	    NULL, xname, "translation abort (S)");
 	evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_TRANS_P], EVCNT_TYPE_TRAP,
 	    NULL, xname, "translation abort (P)");
 	evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_DOMAIN_S], EVCNT_TYPE_TRAP,
 	    NULL, xname, "domain abort (S)");
 	evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_DOMAIN_P], EVCNT_TYPE_TRAP,
 	    NULL, xname, "domain abort (P)");
 	evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_PERM_S], EVCNT_TYPE_TRAP,
 	    NULL, xname, "permission abort (S)");
 	evcnt_attach_dynamic_nozero(&ci->ci_abt_evs[FAULT_PERM_P], EVCNT_TYPE_TRAP,
 	    NULL, xname, "permission abort (P)");
 	evcnt_attach_dynamic_nozero(&ci->ci_und_ev, EVCNT_TYPE_TRAP,
 	    NULL, xname, "undefined insn traps");
 	evcnt_attach_dynamic_nozero(&ci->ci_und_cp15_ev, EVCNT_TYPE_TRAP,
 	    NULL, xname, "undefined cp15 insn traps");
 	ci->ci_kfpu_spl = -1;
 #ifdef MULTIPROCESSOR
 	if (unit != 0) {
 		mi_cpu_attach(ci);
 #ifdef ARM_MMU_EXTENDED
 		pmap_tlb_info_attach(&pmap_tlb0_info, ci);
 #endif
+	}
 #endif
 	identify_arm_cpu(dv, ci);
 #ifdef CPU_STRONGARM
 	if (ci->ci_arm_cputype == CPU_ID_SA110 &&
 	    ci->ci_arm_cpurev < 3) {
 		aprint_normal_dev(dv, "SA-110 with bugged STM^ instruction\n");
+	}
 #endif
 #ifdef CPU_ARM8
 	if ((ci->ci_arm_cpuid & CPU_ID_CPU_MASK) == CPU_ID_ARM810) {
 		int clock = arm8_clock_config(0, 0);
 		char *fclk;
 		aprint_normal_dev(dv, "ARM810 cp15=%02x", clock);
 		aprint_normal(" clock:%s", (clock & 1) ? " dynamic" : "");
 		aprint_normal("%s", (clock & 2) ? " sync" : "");
 		switch ((clock >> 2) & 3) {
 		case 0:
 			fclk = "bus clock";
 			break;
 		case 1:
 			fclk = "ref clock";
 			break;
 		case 3:
 			fclk = "pll";
 			break;
 		default:
 			fclk = "illegal";
 			break;
+		}
 		aprint_normal(" fclk source=%s\n", fclk);
+ 	}
 #endif
 	vfp_attach(ci);
+}
 enum cpu_class {
 	CPU_CLASS_NONE,
 	CPU_CLASS_ARM2,
 	CPU_CLASS_ARM2AS,
 	CPU_CLASS_ARM3,
 	CPU_CLASS_ARM6,
 	CPU_CLASS_ARM7,
 	CPU_CLASS_ARM7TDMI,
 	CPU_CLASS_ARM8,
 	CPU_CLASS_ARM9TDMI,
 	CPU_CLASS_ARM9ES,
 	CPU_CLASS_ARM9EJS,
 	CPU_CLASS_ARM10E,
 	CPU_CLASS_ARM10EJ,
 	CPU_CLASS_SA1,
 	CPU_CLASS_XSCALE,
 	CPU_CLASS_ARM11J,
 	CPU_CLASS_ARMV4,
 	CPU_CLASS_CORTEX,
 	CPU_CLASS_PJ4B,
 };
 static const char * const generic_steppings[16] = {
 	"rev 0",	"rev 1",	"rev 2",	"rev 3",
 	"rev 4",	"rev 5",	"rev 6",	"rev 7",
 	"rev 8",	"rev 9",	"rev 10",	"rev 11",
 	"rev 12",	"rev 13",	"rev 14",	"rev 15",
 };
 static const char * const pN_steppings[16] = {
 	"*p0",	"*p1",	"*p2",	"*p3",	"*p4",	"*p5",	"*p6",	"*p7",
 	"*p8",	"*p9",	"*p10",	"*p11",	"*p12",	"*p13",	"*p14",	"*p15",
 };
 static const char * const sa110_steppings[16] = {
 	"rev 0",	"step J",	"step K",	"step S",
 	"step T",	"rev 5",	"rev 6",	"rev 7",
 	"rev 8",	"rev 9",	"rev 10",	"rev 11",
 	"rev 12",	"rev 13",	"rev 14",	"rev 15",
 };
 static const char * const sa1100_steppings[16] = {
 	"rev 0",	"step B",	"step C",	"rev 3",
 	"rev 4",	"rev 5",	"rev 6",	"rev 7",
 	"step D",	"step E",	"rev 10"	"step G",
 	"rev 12",	"rev 13",	"rev 14",	"rev 15",
 };
 static const char * const sa1110_steppings[16] = {
 	"step A-0",	"rev 1",	"rev 2",	"rev 3",
 	"step B-0",	"step B-1",	"step B-2",	"step B-3",
 	"step B-4",	"step B-5",	"rev 10",	"rev 11",
 	"rev 12",	"rev 13",	"rev 14",	"rev 15",
 };
 static const char * const ixp12x0_steppings[16] = {
 	"(IXP1200 step A)",		"(IXP1200 step B)",
 	"rev 2",			"(IXP1200 step C)",
 	"(IXP1200 step D)",		"(IXP1240/1250 step A)",
 	"(IXP1240 step B)",		"(IXP1250 step B)",
 	"rev 8",	"rev 9",	"rev 10",	"rev 11",
 	"rev 12",	"rev 13",	"rev 14",	"rev 15",
 };
 static const char * const xscale_steppings[16] = {
 	"step A-0",	"step A-1",	"step B-0",	"step C-0",
 	"step D-0",	"rev 5",	"rev 6",	"rev 7",
 	"rev 8",	"rev 9",	"rev 10",	"rev 11",
 	"rev 12",	"rev 13",	"rev 14",	"rev 15",
 };
 static const char * const i80321_steppings[16] = {
 	"step A-0",	"step B-0",	"rev 2",	"rev 3",
 	"rev 4",	"rev 5",	"rev 6",	"rev 7",
 	"rev 8",	"rev 9",	"rev 10",	"rev 11",
 	"rev 12",	"rev 13",	"rev 14",	"rev 15",
 };
 static const char * const i80219_steppings[16] = {
 	"step A-0",	"rev 1",	"rev 2",	"rev 3",
 	"rev 4",	"rev 5",	"rev 6",	"rev 7",
 	"rev 8",	"rev 9",	"rev 10",	"rev 11",
 	"rev 12",	"rev 13",	"rev 14",	"rev 15",
 };
 /* Steppings for PXA2[15]0 */
 static const char * const pxa2x0_steppings[16] = {
 	"step A-0",	"step A-1",	"step B-0",	"step B-1",
 	"step B-2",	"step C-0",	"rev 6",	"rev 7",
 	"rev 8",	"rev 9",	"rev 10",	"rev 11",
 	"rev 12",	"rev 13",	"rev 14",	"rev 15",
 };
 /* Steppings for PXA255/26x.
  * rev 5: PXA26x B0, rev 6: PXA255 A0
  */
 static const char * const pxa255_steppings[16] = {
 	"rev 0",	"rev 1",	"rev 2",	"step A-0",
 	"rev 4",	"step B-0",	"step A-0",	"rev 7",
 	"rev 8",	"rev 9",	"rev 10",	"rev 11",
 	"rev 12",	"rev 13",	"rev 14",	"rev 15",
 };
 /* Stepping for PXA27x */
 static const char * const pxa27x_steppings[16] = {
 	"step A-0",	"step A-1",	"step B-0",	"step B-1",
 	"step C-0",	"rev 5",	"rev 6",	"rev 7",
 	"rev 8",	"rev 9",	"rev 10",	"rev 11",
 	"rev 12",	"rev 13",	"rev 14",	"rev 15",
 };
 static const char * const ixp425_steppings[16] = {
 	"step 0",	"rev 1",	"rev 2",	"rev 3",
 	"rev 4",	"rev 5",	"rev 6",	"rev 7",
 	"rev 8",	"rev 9",	"rev 10",	"rev 11",
 	"rev 12",	"rev 13",	"rev 14",	"rev 15",
 };
 struct cpuidtab {
 	uint32_t	cpuid;
 	enum		cpu_class cpu_class;
 	const char	*cpu_classname;
 	const char * const *cpu_steppings;
 	char		cpu_arch[8];
 };
 const struct cpuidtab cpuids[] = {
 	{ CPU_ID_ARM2,		CPU_CLASS_ARM2,		"ARM2",
 	  generic_steppings, "2" },
 	{ CPU_ID_ARM250,	CPU_CLASS_ARM2AS,	"ARM250",
 	  generic_steppings, "2" },
 	{ CPU_ID_ARM3,		CPU_CLASS_ARM3,		"ARM3",
 	  generic_steppings, "2A" },
 	{ CPU_ID_ARM600,	CPU_CLASS_ARM6,		"ARM600",
 	  generic_steppings, "3" },
 	{ CPU_ID_ARM610,	CPU_CLASS_ARM6,		"ARM610",
 	  generic_steppings, "3" },
 	{ CPU_ID_ARM620,	CPU_CLASS_ARM6,		"ARM620",
 	  generic_steppings, "3" },
 	{ CPU_ID_ARM700,	CPU_CLASS_ARM7,		"ARM700",
 	  generic_steppings, "3" },
 	{ CPU_ID_ARM710,	CPU_CLASS_ARM7,		"ARM710",
 	  generic_steppings, "3" },
 	{ CPU_ID_ARM7500,	CPU_CLASS_ARM7,		"ARM7500",
 	  generic_steppings, "3" },
 	{ CPU_ID_ARM710A,	CPU_CLASS_ARM7,		"ARM710a",
 	  generic_steppings, "3" },
 	{ CPU_ID_ARM7500FE,	CPU_CLASS_ARM7,		"ARM7500FE",
 	  generic_steppings, "3" },
 	{ CPU_ID_ARM810,	CPU_CLASS_ARM8,		"ARM810",
 	  generic_steppings, "4" },
 	{ CPU_ID_SA110,		CPU_CLASS_SA1,		"SA-110",
 	  sa110_steppings, "4" },
 	{ CPU_ID_SA1100,	CPU_CLASS_SA1,		"SA-1100",
 	  sa1100_steppings, "4" },
 	{ CPU_ID_SA1110,	CPU_CLASS_SA1,		"SA-1110",
 	  sa1110_steppings, "4" },
 	{ CPU_ID_FA526,		CPU_CLASS_ARMV4,	"FA526",
 	  generic_steppings, "4" },
 	{ CPU_ID_IXP1200,	CPU_CLASS_SA1,		"IXP1200",
 	  ixp12x0_steppings, "4" },
 	{ CPU_ID_ARM710T,	CPU_CLASS_ARM7TDMI,	"ARM710T",
 	  generic_steppings, "4T" },
 	{ CPU_ID_ARM720T,	CPU_CLASS_ARM7TDMI,	"ARM720T",
 	  generic_steppings, "4T" },
 	{ CPU_ID_ARM740T8K,	CPU_CLASS_ARM7TDMI, "ARM740T (8 KB cache)",
 	  generic_steppings, "4T" },
 	{ CPU_ID_ARM740T4K,	CPU_CLASS_ARM7TDMI, "ARM740T (4 KB cache)",
 	  generic_steppings, "4T" },
 	{ CPU_ID_ARM920T,	CPU_CLASS_ARM9TDMI,	"ARM920T",
 	  generic_steppings, "4T" },
 	{ CPU_ID_ARM922T,	CPU_CLASS_ARM9TDMI,	"ARM922T",
 	  generic_steppings, "4T" },
 	{ CPU_ID_ARM940T,	CPU_CLASS_ARM9TDMI,	"ARM940T",
 	  generic_steppings, "4T" },
 	{ CPU_ID_TI925T,	CPU_CLASS_ARM9TDMI,	"TI ARM925T",
 	  generic_steppings, "4T" },
 	{ CPU_ID_ARM946ES,	CPU_CLASS_ARM9ES,	"ARM946E-S",
 	  generic_steppings, "5TE" },
 	{ CPU_ID_ARM966ES,	CPU_CLASS_ARM9ES,	"ARM966E-S",
 	  generic_steppings, "5TE" },
 	{ CPU_ID_ARM966ESR1,	CPU_CLASS_ARM9ES,	"ARM966E-S",
 	  generic_steppings, "5TE" },
 	{ CPU_ID_MV88SV131,	CPU_CLASS_ARM9ES,	"Sheeva 88SV131",
 	  generic_steppings, "5TE" },
 	{ CPU_ID_MV88FR571_VD,	CPU_CLASS_ARM9ES,	"Sheeva 88FR571-vd",
 	  generic_steppings, "5TE" },
 	{ CPU_ID_80200,		CPU_CLASS_XSCALE,	"i80200",
 	  xscale_steppings, "5TE" },
 	{ CPU_ID_80321_400,	CPU_CLASS_XSCALE,	"i80321 400MHz",
 	  i80321_steppings, "5TE" },
 	{ CPU_ID_80321_600,	CPU_CLASS_XSCALE,	"i80321 600MHz",
 	  i80321_steppings, "5TE" },
 	{ CPU_ID_80321_400_B0,	CPU_CLASS_XSCALE,	"i80321 400MHz",
 	  i80321_steppings, "5TE" },
 	{ CPU_ID_80321_600_B0,	CPU_CLASS_XSCALE,	"i80321 600MHz",
 	  i80321_steppings, "5TE" },
 	{ CPU_ID_80219_400,	CPU_CLASS_XSCALE,	"i80219 400MHz",
 	  i80219_steppings, "5TE" },
 	{ CPU_ID_80219_600,	CPU_CLASS_XSCALE,	"i80219 600MHz",
 	  i80219_steppings, "5TE" },
 	{ CPU_ID_PXA27X,	CPU_CLASS_XSCALE,	"PXA27x",
 	  pxa27x_steppings, "5TE" },
 	{ CPU_ID_PXA250A,	CPU_CLASS_XSCALE,	"PXA250",
 	  pxa2x0_steppings, "5TE" },
 	{ CPU_ID_PXA210A,	CPU_CLASS_XSCALE,	"PXA210",
 	  pxa2x0_steppings, "5TE" },
 	{ CPU_ID_PXA250B,	CPU_CLASS_XSCALE,	"PXA250",
 	  pxa2x0_steppings, "5TE" },
 	{ CPU_ID_PXA210B,	CPU_CLASS_XSCALE,	"PXA210",
 	  pxa2x0_steppings, "5TE" },
 	{ CPU_ID_PXA250C, 	CPU_CLASS_XSCALE,	"PXA255/26x",
 	  pxa255_steppings, "5TE" },
 	{ CPU_ID_PXA210C, 	CPU_CLASS_XSCALE,	"PXA210",
 	  pxa2x0_steppings, "5TE" },
 	{ CPU_ID_IXP425_533,	CPU_CLASS_XSCALE,	"IXP425 533MHz",
 	  ixp425_steppings, "5TE" },
 	{ CPU_ID_IXP425_400,	CPU_CLASS_XSCALE,	"IXP425 400MHz",
 	  ixp425_steppings, "5TE" },
 	{ CPU_ID_IXP425_266,	CPU_CLASS_XSCALE,	"IXP425 266MHz",
 	  ixp425_steppings, "5TE" },
 	{ CPU_ID_ARM1020E,	CPU_CLASS_ARM10E,	"ARM1020E",
 	  generic_steppings, "5TE" },
 	{ CPU_ID_ARM1022ES,	CPU_CLASS_ARM10E,	"ARM1022E-S",
 	  generic_steppings, "5TE" },
 	{ CPU_ID_ARM1026EJS,	CPU_CLASS_ARM10EJ,	"ARM1026EJ-S",
 	  generic_steppings, "5TEJ" },
 	{ CPU_ID_ARM926EJS,	CPU_CLASS_ARM9EJS,	"ARM926EJ-S r0",
 	  pN_steppings, "5TEJ" },
 	{ CPU_ID_ARM1136JS,	CPU_CLASS_ARM11J,	"ARM1136J-S r0",
 	  pN_steppings, "6J" },
 	{ CPU_ID_ARM1136JSR1,	CPU_CLASS_ARM11J,	"ARM1136J-S r1",
 	  pN_steppings, "6J" },
 #if 0
 	/* The ARM1156T2-S only has a memory protection unit */
 	{ CPU_ID_ARM1156T2S,	CPU_CLASS_ARM11J,	"ARM1156T2-S r0",
 	  pN_steppings, "6T2" },
 #endif
 	{ CPU_ID_ARM1176JZS,	CPU_CLASS_ARM11J,	"ARM1176JZ-S r0",
 	  pN_steppings, "6ZK" },
 	{ CPU_ID_ARM11MPCORE,	CPU_CLASS_ARM11J, 	"ARM11 MPCore",
 	  generic_steppings, "6K" },
 	{ CPU_ID_CORTEXA5R0,	CPU_CLASS_CORTEX,	"Cortex-A5 r0",
 	  pN_steppings, "7A" },
 	{ CPU_ID_CORTEXA7R0,	CPU_CLASS_CORTEX,	"Cortex-A7 r0",
 	  pN_steppings, "7A" },
 	{ CPU_ID_CORTEXA8R1,	CPU_CLASS_CORTEX,	"Cortex-A8 r1",
 	  pN_steppings, "7A" },
 	{ CPU_ID_CORTEXA8R2,	CPU_CLASS_CORTEX,	"Cortex-A8 r2",
 	  pN_steppings, "7A" },
 	{ CPU_ID_CORTEXA8R3,	CPU_CLASS_CORTEX,	"Cortex-A8 r3",
 	  pN_steppings, "7A" },
 	{ CPU_ID_CORTEXA9R1,	CPU_CLASS_CORTEX,	"Cortex-A9 r1",
 	  pN_steppings, "7A" },
 	{ CPU_ID_CORTEXA9R2,	CPU_CLASS_CORTEX,	"Cortex-A9 r2",
 	  pN_steppings, "7A" },
 	{ CPU_ID_CORTEXA9R3,	CPU_CLASS_CORTEX,	"Cortex-A9 r3",
 	  pN_steppings, "7A" },
 	{ CPU_ID_CORTEXA9R4,	CPU_CLASS_CORTEX,	"Cortex-A9 r4",
 	  pN_steppings, "7A" },
 	{ CPU_ID_CORTEXA12R0,	CPU_CLASS_CORTEX,	"Cortex-A17(A12) r0",	/* A12 was rebranded A17 */
 	  pN_steppings, "7A" },
 	{ CPU_ID_CORTEXA15R2,	CPU_CLASS_CORTEX,	"Cortex-A15 r2",
 	  pN_steppings, "7A" },
 	{ CPU_ID_CORTEXA15R3,	CPU_CLASS_CORTEX,	"Cortex-A15 r3",
 	  pN_steppings, "7A" },
 	{ CPU_ID_CORTEXA15R4,	CPU_CLASS_CORTEX,	"Cortex-A15 r4",
 	  pN_steppings, "7A" },
 	{ CPU_ID_CORTEXA17R1,	CPU_CLASS_CORTEX,	"Cortex-A17 r1",
 	  pN_steppings, "7A" },
 	{ CPU_ID_CORTEXA35R0,	CPU_CLASS_CORTEX,	"Cortex-A35 r0",
 	  pN_steppings, "8A" },
 	{ CPU_ID_CORTEXA53R0,	CPU_CLASS_CORTEX,	"Cortex-A53 r0",
 	  pN_steppings, "8A" },
 	{ CPU_ID_CORTEXA57R0,	CPU_CLASS_CORTEX,	"Cortex-A57 r0",
 	  pN_steppings, "8A" },
 	{ CPU_ID_CORTEXA57R1,	CPU_CLASS_CORTEX,	"Cortex-A57 r1",
 	  pN_steppings, "8A" },
 	{ CPU_ID_CORTEXA72R0,	CPU_CLASS_CORTEX,	"Cortex-A72 r0",
 	  pN_steppings, "8A" },
 	{ CPU_ID_MV88SV581X_V6, CPU_CLASS_PJ4B,      "Sheeva 88SV581x",
 	  generic_steppings },
 	{ CPU_ID_ARM_88SV581X_V6, CPU_CLASS_PJ4B,    "Sheeva 88SV581x",
 	  generic_steppings },
 	{ CPU_ID_MV88SV581X_V7, CPU_CLASS_PJ4B,      "Sheeva 88SV581x",
 	  generic_steppings },
 	{ CPU_ID_ARM_88SV581X_V7, CPU_CLASS_PJ4B,    "Sheeva 88SV581x",
 	  generic_steppings },
 	{ CPU_ID_MV88SV584X_V6, CPU_CLASS_PJ4B,      "Sheeva 88SV584x",
 	  generic_steppings },
 	{ CPU_ID_ARM_88SV584X_V6, CPU_CLASS_PJ4B,    "Sheeva 88SV584x",
 	  generic_steppings },
 	{ CPU_ID_MV88SV584X_V7, CPU_CLASS_PJ4B,      "Sheeva 88SV584x",
 	  generic_steppings },
 	{ 0, CPU_CLASS_NONE, NULL, NULL, "" }
 };
 struct cpu_classtab {
 	const char	*class_name;
 	const char	*class_option;
 };
 const struct cpu_classtab cpu_classes[] = {
 	[CPU_CLASS_NONE] =	{ "unknown",	NULL },
 	[CPU_CLASS_ARM2] =	{ "ARM2",	"CPU_ARM2" },
 	[CPU_CLASS_ARM2AS] =	{ "ARM2as",	"CPU_ARM250" },
 	[CPU_CLASS_ARM3] =	{ "ARM3",	"CPU_ARM3" },
 	[CPU_CLASS_ARM6] =	{ "ARM6",	"CPU_ARM6" },
 	[CPU_CLASS_ARM7] =	{ "ARM7",	"CPU_ARM7" },
 	[CPU_CLASS_ARM7TDMI] =	{ "ARM7TDMI",	"CPU_ARM7TDMI" },
 	[CPU_CLASS_ARM8] =	{ "ARM8",	"CPU_ARM8" },
 	[CPU_CLASS_ARM9TDMI] =	{ "ARM9TDMI",	NULL },
 	[CPU_CLASS_ARM9ES] =	{ "ARM9E-S",	"CPU_ARM9E" },
 	[CPU_CLASS_ARM9EJS] =	{ "ARM9EJ-S",	"CPU_ARM9E" },
 	[CPU_CLASS_ARM10E] =	{ "ARM10E",	"CPU_ARM10" },
 	[CPU_CLASS_ARM10EJ] =	{ "ARM10EJ",	"CPU_ARM10" },
 	[CPU_CLASS_SA1] =	{ "SA-1",	"CPU_SA110" },
 	[CPU_CLASS_XSCALE] =	{ "XScale",	"CPU_XSCALE_..." },
 	[CPU_CLASS_ARM11J] =	{ "ARM11J",	"CPU_ARM11" },
 	[CPU_CLASS_ARMV4] =	{ "ARMv4",	"CPU_ARMV4" },
 	[CPU_CLASS_CORTEX] =	{ "Cortex",	"CPU_CORTEX" },
 	[CPU_CLASS_PJ4B] =	{ "Marvell",	"CPU_PJ4B" },
 };
 /*
  * Report the type of the specified arm processor. This uses the generic and
  * arm specific information in the CPU structure to identify the processor.
  * The remaining fields in the CPU structure are filled in appropriately.
  */
 static const char * const wtnames[] = {
 	"write-through",
 	"write-back",
 	"write-back",
 	"**unknown 3**",
 	"**unknown 4**",
 	"write-back-locking",		/* XXX XScale-specific? */
 	"write-back-locking-A",
 	"write-back-locking-B",
 	"**unknown 8**",
 	"**unknown 9**",
 	"**unknown 10**",
 	"**unknown 11**",
 	"write-back",
 	"write-back-locking-line",
 	"write-back-locking-C",
 	"write-back-locking-D",
 };
 static void
 print_cache_info(device_t dv, struct arm_cache_info *info, u_int level)
+{
 	if (info->cache_unified) {
 		aprint_normal_dev(dv, "L%u %dKB/%dB %d-way (%u set) %s %cI%cT Unified cache\n",
 		    level + 1,
 		    info->dcache_size / 1024,
 		    info->dcache_line_size, info->dcache_ways,
 		    info->dcache_sets ? info->dcache_sets :
 			info->dcache_size /
 			    (info->dcache_line_size * info->dcache_ways),
 		    wtnames[info->cache_type],
 		    info->dcache_type & CACHE_TYPE_PIxx ? 'P' : 'V',
 		    info->dcache_type & CACHE_TYPE_xxPT ? 'P' : 'V');
 	} else {
 		aprint_normal_dev(dv, "L%u %dKB/%dB %d-way (%u set) %cI%cT Instruction cache\n",
 		    level + 1,
 		    info->icache_size / 1024,
 		    info->icache_line_size, info->icache_ways,
 		    info->icache_sets ? info->icache_sets :
 			info->icache_size /
 			    (info->icache_line_size * info->icache_ways),
 		    info->icache_type & CACHE_TYPE_PIxx ? 'P' : 'V',
 		    info->icache_type & CACHE_TYPE_xxPT ? 'P' : 'V');
 		aprint_normal_dev(dv, "L%u %dKB/%dB %d-way (%u set) %s %cI%cT Data cache\n",
 		    level + 1,
 		    info->dcache_size / 1024,
 		    info->dcache_line_size, info->dcache_ways,
 		    info->dcache_sets ? info->dcache_sets :
 			info->dcache_size /
 			    (info->dcache_line_size * info->dcache_ways),
 		    wtnames[info->cache_type],
 		    info->dcache_type & CACHE_TYPE_PIxx ? 'P' : 'V',
 		    info->dcache_type & CACHE_TYPE_xxPT ? 'P' : 'V');
+	}
+}
 static enum cpu_class
 identify_arm_model(uint32_t cpuid, char *buf, size_t len)
+{
 	enum cpu_class cpu_class = CPU_CLASS_NONE;
 	for (const struct cpuidtab *id = cpuids; id->cpuid != 0; id++) {
 		if (id->cpuid == (cpuid & CPU_ID_CPU_MASK)) {
 			const char *steppingstr =
 			    id->cpu_steppings[cpuid & CPU_ID_REVISION_MASK];
 			cpu_arch = id->cpu_arch;
 			cpu_class = id->cpu_class;
 			snprintf(buf, len, "%s%s%s (%s V%s core)",
 			    id->cpu_classname,
 			    steppingstr[0] == '*' ? "" : " ",
 			    &steppingstr[steppingstr[0] == '*'],
 			    cpu_classes[cpu_class].class_name,
 			    cpu_arch);
 			return cpu_class;
+		}
+	}
 	snprintf(buf, len, "unknown CPU (ID = 0x%x)", cpuid);
 	return cpu_class;
+}
 void
 identify_arm_cpu(device_t dv, struct cpu_info *ci)
+{
 	const uint32_t arm_cpuid = ci->ci_arm_cpuid;
 	const char * const xname = device_xname(dv);
 	char model[128];
 	const char *m;
 	if (arm_cpuid == 0) {
 		aprint_error("Processor failed probe - no CPU ID\n");
 		return;
+	}
 	const enum cpu_class cpu_class = identify_arm_model(arm_cpuid,
 	     model, sizeof(model));
 	if (ci->ci_cpuid == 0) {
 		m = cpu_getmodel();
 		if (m == NULL || *m == 0)
 			cpu_setmodel("%s", model);
+	}
 	if (ci->ci_data.cpu_cc_freq != 0) {
 		char freqbuf[10];
 		humanize_number(freqbuf, sizeof(freqbuf), ci->ci_data.cpu_cc_freq,
 		    "Hz", 1000);
 		aprint_naive(": %s %s\n", freqbuf, model);
 		aprint_normal(": %s %s\n", freqbuf, model);
 	} else {
 		aprint_naive(": %s\n", model);
 		aprint_normal(": %s\n", model);
+	}
 	aprint_debug_dev(dv, "midr:   %#x\n", arm_cpuid);
 	aprint_normal("%s:", xname);
 	switch (cpu_class) {
 	case CPU_CLASS_ARM6:
 	case CPU_CLASS_ARM7:
 	case CPU_CLASS_ARM7TDMI:
 	case CPU_CLASS_ARM8:
 		if ((ci->ci_ctrl & CPU_CONTROL_IDC_ENABLE) == 0)
 			aprint_normal(" IDC disabled");
 		else
 			aprint_normal(" IDC enabled");
 		break;
 	case CPU_CLASS_ARM9TDMI:
 	case CPU_CLASS_ARM9ES:
 	case CPU_CLASS_ARM9EJS:
 	case CPU_CLASS_ARM10E:
 	case CPU_CLASS_ARM10EJ:
 	case CPU_CLASS_SA1:
 	case CPU_CLASS_XSCALE:
 	case CPU_CLASS_ARM11J:
 	case CPU_CLASS_ARMV4:
 	case CPU_CLASS_CORTEX:
 	case CPU_CLASS_PJ4B:
 		if ((ci->ci_ctrl & CPU_CONTROL_DC_ENABLE) == 0)
 			aprint_normal(" DC disabled");
 		else
 			aprint_normal(" DC enabled");
 		if ((ci->ci_ctrl & CPU_CONTROL_IC_ENABLE) == 0)
 			aprint_normal(" IC disabled");
 		else
 			aprint_normal(" IC enabled");
 		break;
 	default:
 		break;
+	}
 	if ((ci->ci_ctrl & CPU_CONTROL_WBUF_ENABLE) == 0)
 		aprint_normal(" WB disabled");
 	else
 		aprint_normal(" WB enabled");
 	if (ci->ci_ctrl & CPU_CONTROL_LABT_ENABLE)
 		aprint_normal(" LABT");
 	else
 		aprint_normal(" EABT");
 	if (ci->ci_ctrl & CPU_CONTROL_BPRD_ENABLE)
 		aprint_normal(" branch prediction enabled");
 	aprint_normal("\n");
 	if (CPU_ID_CORTEX_P(arm_cpuid) ||
 	    CPU_ID_ARM11_P(arm_cpuid) ||
 	    CPU_ID_MV88SV58XX_P(arm_cpuid)) {
 		if ((arm_cpuid & CPU_ID_CPU_MASK) != CPU_ID_ARM1136JS &&
 		    (arm_cpuid & CPU_ID_CPU_MASK) != CPU_ID_ARM1176JZS) {
 			identify_features(dv, ci);
+		}
+	}
 	/* Print cache info. */
 	if (arm_pcache.icache_line_size != 0 || arm_pcache.dcache_line_size != 0) {
 		print_cache_info(dv, &arm_pcache, 0);
+	}
 	if (arm_scache.icache_line_size != 0 || arm_scache.dcache_line_size != 0) {
 		print_cache_info(dv, &arm_scache, 1);
+	}
 	switch (cpu_class) {
 #ifdef CPU_ARM6
 	case CPU_CLASS_ARM6:
 #endif
 #ifdef CPU_ARM7
 	case CPU_CLASS_ARM7:
 #endif
 #ifdef CPU_ARM7TDMI
 	case CPU_CLASS_ARM7TDMI:
 #endif
 #ifdef CPU_ARM8
 	case CPU_CLASS_ARM8:
 #endif
 #ifdef CPU_ARM9
 	case CPU_CLASS_ARM9TDMI:
 #endif
 #if defined(CPU_ARM9E) || defined(CPU_SHEEVA)
 	case CPU_CLASS_ARM9ES:
 	case CPU_CLASS_ARM9EJS:
 #endif
 #ifdef CPU_ARM10
 	case CPU_CLASS_ARM10E:
 	case CPU_CLASS_ARM10EJ:
 #endif
 #if defined(CPU_SA110) || defined(CPU_SA1100) || \
     defined(CPU_SA1110) || defined(CPU_IXP12X0)
 	case CPU_CLASS_SA1:
 #endif
 #if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
     defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425)
 	case CPU_CLASS_XSCALE:
 #endif
 #if defined(CPU_ARM11)
 	case CPU_CLASS_ARM11J:
 #endif
 #if defined(CPU_CORTEX)
 	case CPU_CLASS_CORTEX:
 #endif
 #if defined(CPU_PJ4B)
 	case CPU_CLASS_PJ4B:
 #endif
 #if defined(CPU_FA526)
 	case CPU_CLASS_ARMV4:
 #endif
 		break;
 	default:
 		if (cpu_classes[cpu_class].class_option == NULL) {
 			aprint_error_dev(dv, "%s does not fully support this CPU.\n",
 			     ostype);
 		} else {
 			aprint_error_dev(dv, "This kernel does not fully support "
 			       "this CPU.\n");
 			aprint_normal_dev(dv, "Recompile with \"options %s\" to "
 			       "correct this.\n", cpu_classes[cpu_class].class_option);
+		}
 		break;
+	}
+}
 extern int cpu_instruction_set_attributes[6];
 extern int cpu_memory_model_features[4];
 extern int cpu_processor_features[2];
 extern int cpu_simd_present;
 extern int cpu_simdex_present;
 void
 identify_features(device_t dv, struct cpu_info *ci)
+{
 	const int unit = device_unit(dv);
 	aprint_debug_dev(dv, "sctlr:  %#x\n", ci->ci_ctrl);
 	aprint_debug_dev(dv, "actlr:  %#x\n", ci->ci_actlr);
 	aprint_debug_dev(dv, "revidr: %#x\n", ci->ci_revidr);
 #ifdef MULTIPROCESSOR
 	aprint_debug_dev(dv, "mpidr:  %#x\n", ci->ci_mpidr);
 #endif
 	if (unit != 0)
 		return;
 	cpu_instruction_set_attributes[0] = armreg_isar0_read();
 	cpu_instruction_set_attributes[1] = armreg_isar1_read();
 	cpu_instruction_set_attributes[2] = armreg_isar2_read();
 	cpu_instruction_set_attributes[3] = armreg_isar3_read();
 	cpu_instruction_set_attributes[4] = armreg_isar4_read();
 	cpu_instruction_set_attributes[5] = armreg_isar5_read();
 	cpu_hwdiv_present =
 	    ((cpu_instruction_set_attributes[0] >> 24) & 0x0f) >= 2;
 	cpu_simd_present =
 	    ((cpu_instruction_set_attributes[3] >> 4) & 0x0f) >= 3;
 	cpu_simdex_present = cpu_simd_present
 	    && ((cpu_instruction_set_attributes[1] >> 12) & 0x0f) >= 2;
 	cpu_synchprim_present =
 	    ((cpu_instruction_set_attributes[3] >> 8) & 0xf0)
 	    | ((cpu_instruction_set_attributes[4] >> 20) & 0x0f);
 	cpu_memory_model_features[0] = armreg_mmfr0_read();
 	cpu_memory_model_features[1] = armreg_mmfr1_read();
 	cpu_memory_model_features[2] = armreg_mmfr2_read();
 	cpu_memory_model_features[3] = armreg_mmfr3_read();
 #if 0
 	if (__SHIFTOUT(cpu_memory_model_features[3], __BITS(23,20))) {
 		/*
 		* Updates to the translation tables do not require a clean
 		* to the point of unification to ensure visibility by
 		* subsequent translation table walks.
 		*/
 		pmap_needs_pte_sync = 0;
+	}
 #endif
 	cpu_processor_features[0] = armreg_pfr0_read();
 	cpu_processor_features[1] = armreg_pfr1_read();
 	aprint_debug_dev(dv,
 	    "isar: [0]=%#x [1]=%#x [2]=%#x [3]=%#x, [4]=%#x, [5]=%#x\n",
 	    cpu_instruction_set_attributes[0],
 	    cpu_instruction_set_attributes[1],
 	    cpu_instruction_set_attributes[2],
 	    cpu_instruction_set_attributes[3],
 	    cpu_instruction_set_attributes[4],
 	    cpu_instruction_set_attributes[5]);
 	aprint_debug_dev(dv,
 	    "mmfr: [0]=%#x [1]=%#x [2]=%#x [3]=%#x\n",
 	    cpu_memory_model_features[0], cpu_memory_model_features[1],
 	    cpu_memory_model_features[2], cpu_memory_model_features[3]);
 	aprint_debug_dev(dv,
 	    "pfr: [0]=%#x [1]=%#x\n",
 	    cpu_processor_features[0], cpu_processor_features[1]);
+}
 #ifdef _ARM_ARCH_6
 int
 cpu_maxproc_hook(int nmaxproc)
+{
 #ifdef ARM_MMU_EXTENDED
 	return pmap_maxproc_set(nmaxproc);
 #else
 	return 0;
 #endif
+}
 #endif

 @@ -1,387 +1,378 @@
-/* $NetBSD: cpu_fdt.c,v 1.41 2021/08/30 23:16:17 jmcneill Exp $ */
+/* $NetBSD: cpu_fdt.c,v 1.42 2022/03/03 06:26:05 riastradh Exp $ */
 /*-
  * Copyright (c) 2017 Jared McNeill <jmcneill@invisible.ca>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 #include "opt_multiprocessor.h"
 #include "psci_fdt.h"
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpu_fdt.c,v 1.41 2021/08/30 23:16:17 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu_fdt.c,v 1.42 2022/03/03 06:26:05 riastradh Exp $");
 #include <sys/param.h>
 #include <sys/atomic.h>
 #include <sys/bus.h>
 #include <sys/device.h>
 #include <sys/lwp.h>
 #include <sys/systm.h>
 #include <sys/kernel.h>
 #include <dev/fdt/fdtvar.h>
 #include <arm/armreg.h>
 #include <arm/cpu.h>
 #include <arm/cpufunc.h>
 #include <arm/cpuvar.h>
 #include <arm/locore.h>
 #include <arm/arm/psci.h>
 #include <arm/fdt/arm_fdtvar.h>
 #include <arm/fdt/psci_fdtvar.h>
 #include <uvm/uvm_extern.h>
 static int	cpu_fdt_match(device_t, cfdata_t, void *);
 static void	cpu_fdt_attach(device_t, device_t, void *);
-struct cpu_fdt_softc {
+CFATTACH_DECL_NEW(cpu_fdt, 0,
 	device_t		sc_dev;
 	int			sc_phandle;
 };
 CFATTACH_DECL_NEW(cpu_fdt, sizeof(struct cpu_fdt_softc),
 	cpu_fdt_match, cpu_fdt_attach, NULL, NULL);
 static int
 cpu_fdt_match(device_t parent, cfdata_t cf, void *aux)
+{
 	struct fdt_attach_args * const faa = aux;
 	const int phandle = faa->faa_phandle;
 	const char *device_type;
 	device_type = fdtbus_get_string(phandle, "device_type");
 	return device_type != NULL && strcmp(device_type, "cpu") == 0;
+}
 static void
 cpu_fdt_attach(device_t parent, device_t self, void *aux)
+{
 	struct cpu_fdt_softc * const sc = device_private(self);
 	struct fdt_attach_args * const faa = aux;
 	const int phandle = faa->faa_phandle;
 	bus_addr_t cpuid;
 	const uint32_t *cap_ptr;
 	int len;
 	sc->sc_dev = self;
 	sc->sc_phandle = phandle;
  	cap_ptr = fdtbus_get_prop(phandle, "capacity-dmips-mhz", &len);
 	if (cap_ptr && len == 4) {
 		prop_dictionary_t dict = device_properties(self);
 		uint32_t capacity_dmips_mhz = be32toh(*cap_ptr);
 		prop_dictionary_set_uint32(dict, "capacity_dmips_mhz",
 		    capacity_dmips_mhz);
+	}
 	if (fdtbus_get_reg(phandle, 0, &cpuid, NULL) != 0)
 		cpuid = 0;
 	/* Attach the CPU */
 	cpu_attach(self, cpuid);
 	/* Attach CPU frequency scaling provider */
 	config_found(self, faa, NULL, CFARGS_NONE);
+}
 #if defined(MULTIPROCESSOR) && (NPSCI_FDT > 0 || defined(__aarch64__))
 static register_t
 cpu_fdt_mpstart_pa(void)
+{
 	bool ok __diagused;
 	paddr_t pa;
 	ok = pmap_extract(pmap_kernel(), (vaddr_t)cpu_mpstart, &pa);
 	KASSERT(ok);
 	return pa;
+}
 #endif
 #ifdef MULTIPROCESSOR
 static bool
 arm_fdt_cpu_okay(const int child)
+{
 	const char *s;
 	s = fdtbus_get_string(child, "device_type");
 	if (!s || strcmp(s, "cpu") != 0)
 		return false;
 	s = fdtbus_get_string(child, "status");
 	if (s) {
 		if (strcmp(s, "okay") == 0)
 			return false;
 		if (strcmp(s, "disabled") == 0)
 			return of_hasprop(child, "enable-method");
 		return false;
 	} else {
 		return true;
+	}
+}
 #endif /* MULTIPROCESSOR */
 void
 arm_fdt_cpu_bootstrap(void)
+{
 #ifdef MULTIPROCESSOR
 	uint64_t mpidr, bp_mpidr;
 	u_int cpuindex;
 	int child;
 	const int cpus = OF_finddevice("/cpus");
 	if (cpus == -1) {
 		aprint_error("%s: no /cpus node found\n", __func__);
 		arm_cpu_max = 1;
 		return;
+	}
 	/* Count CPUs */
 	arm_cpu_max = 0;
 	/* MPIDR affinity levels of boot processor. */
 	bp_mpidr = cpu_mpidr_aff_read();
 	/* Add APs to cpu_mpidr array */
 	cpuindex = 1;
 	for (child = OF_child(cpus); child; child = OF_peer(child)) {
 		if (!arm_fdt_cpu_okay(child))
 			continue;
 		arm_cpu_max++;
 		if (fdtbus_get_reg64(child, 0, &mpidr, NULL) != 0)
 			continue;
 		if (mpidr == bp_mpidr)
 			continue; 	/* BP already started */
 		KASSERT(cpuindex < MAXCPUS);
 		cpu_mpidr[cpuindex] = mpidr;
 		cpu_dcache_wb_range((vaddr_t)&cpu_mpidr[cpuindex],
 		    sizeof(cpu_mpidr[cpuindex]));
 		cpuindex++;
+	}
 #endif
+}
 #ifdef MULTIPROCESSOR
 static struct arm_cpu_method *
 arm_fdt_cpu_enable_method_byname(const char *method)
+{
 	__link_set_decl(arm_cpu_methods, struct arm_cpu_method);
 	struct arm_cpu_method * const *acmp;
 	__link_set_foreach(acmp, arm_cpu_methods) {
 		if (strcmp(method, (*acmp)->acm_compat) == 0)
 			return *acmp;
+	}
 	return NULL;
+}
 static struct arm_cpu_method *
 arm_fdt_cpu_enable_method(int phandle)
+{
 	const char *method;
  	method = fdtbus_get_string(phandle, "enable-method");
 	if (method == NULL)
 		return NULL;
 	return arm_fdt_cpu_enable_method_byname(method);
+}
 static int
 arm_fdt_cpu_enable(int phandle, struct arm_cpu_method *acm)
+{
 	return acm->acm_enable(phandle);
+}
 #endif
 int
 arm_fdt_cpu_mpstart(void)
+{
 	int ret = 0;
 #ifdef MULTIPROCESSOR
 	uint64_t mpidr, bp_mpidr;
 	u_int cpuindex, i;
 	int child, error;
 	struct arm_cpu_method *acm;
 	const int cpus = OF_finddevice("/cpus");
 	if (cpus == -1) {
 		aprint_error("%s: no /cpus node found\n", __func__);
 		return 0;
+	}
 	/* MPIDR affinity levels of boot processor. */
 	bp_mpidr = cpu_mpidr_aff_read();
 	/* Boot APs */
 	cpuindex = 1;
 	for (child = OF_child(cpus); child; child = OF_peer(child)) {
 		if (!arm_fdt_cpu_okay(child))
 			continue;
 		if (fdtbus_get_reg64(child, 0, &mpidr, NULL) != 0)
 			continue;
 		if (mpidr == bp_mpidr)
 			continue; 	/* BP already started */
 		acm = arm_fdt_cpu_enable_method(child);
 		if (acm == NULL)
 			acm = arm_fdt_cpu_enable_method(cpus);
 		if (acm == NULL)
 			acm = arm_fdt_cpu_enable_method_byname("psci");
 		if (acm == NULL)
 			continue;
 		error = arm_fdt_cpu_enable(child, acm);
 		if (error != 0) {
 			aprint_error("%s: failed to enable CPU %#" PRIx64 "\n",
 			    __func__, mpidr);
 			continue;
+		}
 		/* Wake up AP in case firmware has placed it in WFE state */
 		sev();
 		/* Wait for AP to start */
 		for (i = 0x10000000; i > 0; i--) {
 			if (cpu_hatched_p(cpuindex))
 				break;
+		}
 		if (i == 0) {
 			ret++;
 			aprint_error("cpu%d: WARNING: AP failed to start\n", cpuindex);
+		}
 		cpuindex++;
+	}
 #endif /* MULTIPROCESSOR */
 	return ret;
+}
 static int
 cpu_enable_nullop(int phandle)
+{
 	return ENXIO;
+}
 ARM_CPU_METHOD(default, "", cpu_enable_nullop);
 #if defined(MULTIPROCESSOR) && NPSCI_FDT > 0
 static int
 cpu_enable_psci(int phandle)
+{
 	static bool psci_probed, psci_p;
 	uint64_t mpidr;
 	int ret;
 	if (!psci_probed) {
 		psci_probed = true;
 		psci_p = psci_fdt_preinit() == 0;
+	}
 	if (!psci_p)
 		return ENXIO;
 	fdtbus_get_reg64(phandle, 0, &mpidr, NULL);
 #if !defined(AARCH64)
 	/*
 	 * not necessary on AARCH64. beside there it hangs the system
 	 * because cache ops are only functional after cpu_attach()
 	 * was called.
 	 */
 	cpu_dcache_wbinv_all();
 #endif
 	ret = psci_cpu_on(mpidr, cpu_fdt_mpstart_pa(), 0);
 	if (ret != PSCI_SUCCESS)
 		return EIO;
 	return 0;
+}
 ARM_CPU_METHOD(psci, "psci", cpu_enable_psci);
 #endif
 #if defined(MULTIPROCESSOR) && defined(__aarch64__)
 static int
 spintable_cpu_on(const int phandle, u_int cpuindex,
     paddr_t entry_point_address, paddr_t cpu_release_addr)
+{
 	/*
 	 * we need devmap for cpu-release-addr in advance.
 	 * __HAVE_MM_MD_DIRECT_MAPPED_PHYS nor pmap work at this point.
 	 */
 	if (pmap_devmap_find_pa(cpu_release_addr, sizeof(paddr_t)) == NULL) {
 		aprint_error("%s: devmap for cpu-release-addr"
 		    " 0x%08"PRIxPADDR" required\n", __func__, cpu_release_addr);
 		return -1;
 	} else {
 		extern struct bus_space arm_generic_bs_tag;
 		bus_space_handle_t ioh;
 		const int parent = OF_parent(phandle);
 		const int addr_cells = fdtbus_get_addr_cells(parent);
 		bus_space_map(&arm_generic_bs_tag, cpu_release_addr,
 		    sizeof(paddr_t), 0, &ioh);
 		if (addr_cells == 1) {
 			bus_space_write_4(&arm_generic_bs_tag, ioh, 0,
 			    entry_point_address);
 		} else {
 			bus_space_write_8(&arm_generic_bs_tag, ioh, 0,
 			    entry_point_address);
+		}
 		bus_space_unmap(&arm_generic_bs_tag, ioh, sizeof(paddr_t));
+	}
 	return 0;
+}
 static int
 cpu_enable_spin_table(int phandle)
+{
 	uint64_t mpidr, addr;
 	int ret;
 	fdtbus_get_reg64(phandle, 0, &mpidr, NULL);
 	if (of_getprop_uint64(phandle, "cpu-release-addr", &addr) != 0)
 		return ENXIO;
 	ret = spintable_cpu_on(phandle, mpidr, cpu_fdt_mpstart_pa(),
 	    (paddr_t)addr);
 	if (ret != 0)
 		return EIO;
 	return 0;
+}
 ARM_CPU_METHOD(spin_table, "spin-table", cpu_enable_spin_table);
 #endif