Wed Mar 16 09:48:23 2022 UTC ()
s/frmae/frame/


(andvar)
diff -r1.65 -r1.66 src/sys/arch/powerpc/powerpc/locore_subr.S
cvs diff -r1.65 -r1.66 src/sys/arch/powerpc/powerpc/locore_subr.S (expand / switch to unified diff)

--- src/sys/arch/powerpc/powerpc/locore_subr.S 2021/03/06 08:34:58 1.65
+++ src/sys/arch/powerpc/powerpc/locore_subr.S 2022/03/16 09:48:23 1.66
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: locore_subr.S,v 1.65 2021/03/06 08:34:58 rin Exp $ */ 1/* $NetBSD: locore_subr.S,v 1.66 2022/03/16 09:48:23 andvar Exp $ */
2 2
3/* 3/*
4 * Copyright (c) 2001 Wasabi Systems, Inc. 4 * Copyright (c) 2001 Wasabi Systems, Inc.
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * Written by Eduardo Horvath and Simon Burge for Wasabi Systems, Inc. 7 * Written by Eduardo Horvath and Simon Burge for Wasabi Systems, Inc.
8 * 8 *
9 * Redistribution and use in source and binary forms, with or without 9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions 10 * modification, are permitted provided that the following conditions
11 * are met: 11 * are met:
12 * 1. Redistributions of source code must retain the above copyright 12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer. 13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright 14 * 2. Redistributions in binary form must reproduce the above copyright
@@ -274,27 +274,27 @@ ENTRY(cpu_switchto) @@ -274,27 +274,27 @@ ENTRY(cpu_switchto)
274 mr %r3,%r30 274 mr %r3,%r30
275 mr %r4,%r31 275 mr %r4,%r31
276 276
277/* 277/*
278 * Note that callframe linkages are setup in cpu_lwp_fork(). 278 * Note that callframe linkages are setup in cpu_lwp_fork().
279 */ 279 */
280 ldreg %r31,CFRAME_R31(%r1) /* restore saved registers */ 280 ldreg %r31,CFRAME_R31(%r1) /* restore saved registers */
281 ldreg %r30,CFRAME_R30(%r1) 281 ldreg %r30,CFRAME_R30(%r1)
282 IBM405_ERRATA77_DCBT(0,%r1) 282 IBM405_ERRATA77_DCBT(0,%r1)
283 stwcx. %r1,0,%r1 /* clear reservation */ 283 stwcx. %r1,0,%r1 /* clear reservation */
284#if 1 284#if 1
285 addi %r1,%r1,CALLFRAMELEN 285 addi %r1,%r1,CALLFRAMELEN
286#else 286#else
287 ldreg %r1,CFRAME_SP(%r1) /* pop stack frmae */ 287 ldreg %r1,CFRAME_SP(%r1) /* pop stack frame */
288#endif 288#endif
289 ldreg %r0,CFRAME_LR(%r1) 289 ldreg %r0,CFRAME_LR(%r1)
290 mtlr %r0 290 mtlr %r0
291 blr /* CPUINIT needs a raw blr */ 291 blr /* CPUINIT needs a raw blr */
292 292
293ENTRY_NOPROFILE(emptyidlespin) 293ENTRY_NOPROFILE(emptyidlespin)
294#ifdef DIAGNOSTIC 294#ifdef DIAGNOSTIC
295 GET_CPUINFO(%r3) 295 GET_CPUINFO(%r3)
296 lbz %r4,CI_CPL(%r3) 296 lbz %r4,CI_CPL(%r3)
297 twnei %r4,IPL_NONE 297 twnei %r4,IPL_NONE
298 mfmsr %r5 298 mfmsr %r5
299 andi. %r5,%r5,PSL_EE@l 299 andi. %r5,%r5,PSL_EE@l
300 tweqi %r5,0 300 tweqi %r5,0