 @@ -1,14 +1,14 @@
-/*	$NetBSD: video.h,v 1.7 2009/10/20 19:10:11 snj Exp $	*/
+/*	$NetBSD: video.h,v 1.8 2022/07/03 11:30:48 andvar Exp $	*/
 /*
  * Copyright (c) 1995 Leo Weppelman.
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -102,27 +102,27 @@ struct video {
 /* values for vd_st_res: */
 #define	RES_LOW		0x00	/* 320x200, 16 colors			*/
 #define	RES_MID		0x01	/* 640x200,  4 colors			*/
 #define	RES_HIGH	0x02	/* 640x400, monochrome			*/
 /* masks for vd_tt_res: */
 #define	RES_STLOW	0x0000	/* 320x200, 16 colors			*/
 #define	RES_STMID	0x0100	/* 640x200,  4 colors			*/
 #define	RES_STHIGH	0x0200	/* 640x400, monochrome			*/
 #define	RES_TTMID	0x0400	/* 640x480, 16 colors			*/
 #define	RES_TTHIGH	0x0600	/* 1280x960, monochrome			*/
 #define	RES_TTLOW	0x0700	/* 320x480,  256 colors			*/
-#define TT_PALLET	0x000f	/* Pallette number			*/
+#define TT_PALLET	0x000f	/* Palette number			*/
 #define	TT_HYMONO	0x8000	/* Hyper mono mode			*/
 #define	TT_SHOLD	0x1000	/* Sample/hold mode			*/
 /* The falcon video modes */
 #define RES_FALAUTO	0	/* Falcon resolution dedected at boot	*/
 #define RES_VGA2	1	/* 640x480,   2 colors			*/
 #define RES_VGA4	2	/* 640x480,   4 colors			*/
 #define RES_VGA16	3	/* 640x480,  16 colors			*/
 #define RES_VGA256	4	/* 640x480, 256 colors			*/
 #define RES_DIRECT	5	/* 320x200, 65536 colors		*/
 #define RES_FAL_STLOW	6	/* 320x200,  16 colors			*/
 #define RES_FAL_STMID	7	/* 640x200,   4 colors			*/
 #define RES_FAL_STHIGH	8	/* 640x400,   2 colors			*/

 @@ -1,14 +1,14 @@
-/*	$NetBSD: sti_sgc.c,v 1.6 2021/08/07 16:18:53 thorpej Exp $	*/
+/*	$NetBSD: sti_sgc.c,v 1.7 2022/07/03 11:30:48 andvar Exp $	*/
 /*	$OpenBSD: sti_sgc.c,v 1.14 2007/05/26 00:36:03 krw Exp $	*/
 /*
  * Copyright (c) 2005, Miodrag Vallat
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -17,27 +17,27 @@
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
+ *
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: sti_sgc.c,v 1.6 2021/08/07 16:18:53 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: sti_sgc.c,v 1.7 2022/07/03 11:30:48 andvar Exp $");
 #include <sys/param.h>
 #include <sys/device.h>
 #include <sys/bus.h>
 #include <uvm/uvm_extern.h>
 #include <dev/wscons/wsconsio.h>
 #include <dev/wscons/wsdisplayvar.h>
 #include <dev/ic/stireg.h>
 #include <dev/ic/stivar.h>
 @@ -249,27 +249,27 @@ sti_sgc_probe(bus_space_tag_t iot, int s
 	bus_space_handle_t ioh;
 	int devtype;
 	if (bus_space_map(iot, (bus_addr_t)sgc_slottopa(slot),
 	    PAGE_SIZE, 0, &ioh))
 		return 0;
 	devtype = bus_space_read_1(iot, ioh, 3);
 	bus_space_unmap(iot, ioh, PAGE_SIZE);
 	/*
 	 * This might not be reliable enough. On the other hand, non-STI
-	 * SGC cards will apparently not initialize in an hp300, to the
+	 * SGC cards will apparently not initialize in the hp300, to the
 	 * point of not even answering bus probes (checked with an
 	 * Harmony/FDDI SGC card).
 	 */
 	if (devtype != STI_DEVTYPE1 && devtype != STI_DEVTYPE4)
 		return 0;
 	return 1;
+}
 static int
 sti_evrx_putcmap(struct sti_screen *scr, u_int index, u_int count)
+{
 	struct sti_rom *rom = scr->scr_rom;
 @@ -307,27 +307,27 @@ sti_evrx_resetramdac(struct sti_screen *
 	 * Initialize the Bt458.  When we write to control registers,
 	 * the address is not incremented automatically. So we specify
 	 * it ourselves for each control register.
 	 */
 	/* all planes will be read */
 	bus_space_write_1(bst, bsh, EVRX_BT458_ADDR, 0x04);
 	bus_space_write_1(bst, bsh, EVRX_BT458_CTRL, 0xff);
 	/* all planes have non-blink */
 	bus_space_write_1(bst, bsh, EVRX_BT458_ADDR, 0x05);
 	bus_space_write_1(bst, bsh, EVRX_BT458_CTRL, 0x00);
-	/* pallete enabled, ovly plane disabled */
+	/* palette enabled, ovly plane disabled */
 	bus_space_write_1(bst, bsh, EVRX_BT458_ADDR, 0x06);
 	bus_space_write_1(bst, bsh, EVRX_BT458_CTRL, 0x40);
 	/* no test mode */
 	bus_space_write_1(bst, bsh, EVRX_BT458_ADDR, 0x07);
 	bus_space_write_1(bst, bsh, EVRX_BT458_CTRL, 0x00);
 	/* magic initialization from HP-UX woodInitializeHardware() */
 	bus_space_write_4(bst, bsh, EVRX_MAGIC00, 0x00000001);
 	bus_space_write_4(bst, bsh, EVRX_MAGIC04, 0x00000001);
 	bus_space_write_4(bst, bsh, EVRX_MAGIC08, 0x00000001);
 	bus_space_write_4(bst, bsh, EVRX_MAGIC0C, 0x00000001);
 	bus_space_write_4(bst, bsh, EVRX_MAGIC18, 0xFFFFFFFF);

 @@ -1,14 +1,14 @@
-/*	$NetBSD: ite8181reg.h,v 1.4 2005/12/11 12:17:33 christos Exp $	*/
+/*	$NetBSD: ite8181reg.h,v 1.5 2022/07/03 11:30:48 andvar Exp $	*/
 /*-
  * Copyright (c) 2000 SATO Kazumi
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -28,38 +28,38 @@
  */
 /* ITE8181 configuration registers */
 #define ITE8181_CONF_OFFSET	((8192 -1) * 1024)	/* offset of config reg */
 #define ITE8181_ID       0x00	/* Device ID, Vender ID */
 #define		ITE8181_DATA_ID 0x81811283
 #define		ITE8181_PRODUCT_ID 0x8181
 #define		ITE8181_VENDER_ID 0x1283
 #define ITE8181_SCMD     0x04	/* Status, Command Reg. */
 #define ITE8181_CLASS    0x08	/* Class, Sub-class, PRG, revision */
 #define		ITE8181_DATA_CLASS      0x03800000
 #define		ITE8181_CLASS_MASK      0xffff0000
 #define		ITE8181_REV_MASK	0x000000ff
-#define ITE8181_MBA      0x10	/* Memory Base Address(4MB bounday) */
+#define ITE8181_MBA      0x10	/* Memory Base Address(4MB boundary) */
 #define ITE8181_GBA      0x14	/* GUI Base Address(32KB boundary) */
 #define ITE8181_SBA      0x18	/* Graphic Base Address (64KB boundary) */
 #define ITE8181_TEST     0x40	/* Test Reg. */
 #define ITE8181_STANDBY  0x44	/* Standby Reg. */
 #define 	ITE8181_DATA_PLL2_TEST		0xc0000	/* PLL2 is test mode */
 #define 	ITE8181_DATA_PLL1_TEST		0x30000	/* PLL1 is test mode */
 #define 	ITE8181_DATA_PLL2_RESET		0x8000	/* PLL2 reset */
 #define 	ITE8181_DATA_PLL1_RESET		0x4000	/* PLL1 reset */
 #define 	ITE8181_DATA_PLL2_PWDOWN	0x2000	/* PLL2 powerdown */
 #define 	ITE8181_DATA_PLL1_PWDOWN	0x1000	/* PLL1 powerdown */
-#define		ITE8181_DATA_PALETTESTBY	0x0200	/* Pallete RAM standby */
+#define		ITE8181_DATA_PALETTESTBY	0x0200	/* Palette RAM standby */
 #define		ITE8181_DATA_CURSORSTBY		0x0100	/* Cursor standby */
 #define		ITE8181_DATA_BITBLTSTBY		0x0080	/* BitBlt engine standby */
 #define		ITE8181_DATA_LINESTBY		0x0040	/* Line Draw standby */
 #define		ITE8181_DATA_DACCLKSTOP		0x0020	/* DAC Clock stop */
 #define		ITE8181_DATA_DACPOWERON		0x0010	/* DAC Power ON */
 #define		ITE8181_DATA_GATEPLL2IN		0x0008	/* Gate PLL2 input clock */
 #define		ITE8181_DATA_GATEPLL1IN		0x0004	/* Gate PLL1 input clock */
 #define		ITE8181_DATA_CLOCKSTOP		0x0001	/* 14.318MHZ CLock Stop */
 #define ITE8181_PLL1     0x48	/* PLL1 Reg. */
 #define ITE8181_PLL2     0x4c	/* PLL2 Reg. */
 /* ITE8181 GUI 32bit registers */
 #define ITE8181_GUI_BSLE	0x00	/* BitBlt src/Line Draw End */
 @@ -194,27 +194,27 @@
 #define		ITE8181_TRC_MASK	0x10	/* text reverse control */
 #define		ITE8181_TRC_NOTREVERSE	0x00
 #define		ITE8181_TRC_TREVERSE	0x10
 #define		ITE8181_CM_MASK		0x01	/* color to mono map */
 #define		ITE8181_CM_NTSC		0x00	/* NTSC weighting */
 #define		ITE8181_CM_GREEN	0x01	/* green only */
 #define ITE8181_EMA_FRCCOL	0xa2	/* FRC Color */
 #define		ITE8181_FRCCOL_MASK	0x80	/* FRC color option */
 #define		ITE8181_FRCCOL_8	0x80	/* option1, 8 color */
 #define		ITE8181_FRCCOL_16	0x00	/* option2, 16 color */
-#define ITE8181_EMA_FRCPAT	0xa3	/* select frame rate perttern */
+#define ITE8181_EMA_FRCPAT	0xa3	/* select frame rate pattern */
 #define		ITE8181_FRCPAT_PROGRAM	0x80
 #define		ITE8181_FRCPAT_CONSTANT	0x00
 #define ITE8181_EMA_FBADDR1	0xa8	/* FB addr1 [21:14] */
 #define ITE8181_EMA_FBADDR2	0xa9	/* FB addr2 [21:14] */
 #define ITE8181_EMA_FBADDR3	0xaa	/* FB addr3 [21:14] */
 #define ITE8181_EMA_REDBCOLOR	0xaa	/* Red Border color */
 #define ITE8181_EMA_GREENBCOLOR	0xab	/* Green Border color */
 #define ITE8181_EMA_BLUEBCOLOR	0xac	/* Blue Border color */
 #define ITE8181_EMA_DISPERSION1	0xb0	/* Dispersion-1 B0-B7 */
 #define ITE8181_EMA_DISPERSION2	0xb8	/* Dispersion-2 B8-BF */

 @@ -1,14 +1,14 @@
-/*	$NetBSD: hd64461video.c,v 1.56 2022/05/24 06:28:00 andvar Exp $	*/
+/*	$NetBSD: hd64461video.c,v 1.57 2022/07/03 11:30:48 andvar Exp $	*/
 /*-
  * Copyright (c) 2001, 2002, 2004 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by UCHIYAMA Yasushi.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
 @@ -20,27 +20,27 @@
  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: hd64461video.c,v 1.56 2022/05/24 06:28:00 andvar Exp $");
+__KERNEL_RCSID(0, "$NetBSD: hd64461video.c,v 1.57 2022/07/03 11:30:48 andvar Exp $");
 #include "opt_hd64461video.h"
 // #define HD64461VIDEO_HWACCEL
 #include <sys/param.h>
 #include <sys/kernel.h>
 #include <sys/systm.h>
 #include <sys/device.h>
 #include <sys/malloc.h>
 #include <sys/bus.h>
 #include <sys/conf.h> /* cdev_decl */
 #include <dev/cons.h> /* consdev */
 @@ -1117,51 +1117,51 @@ hd64461video_frame_buffer_size(struct hd
 	    *(volatile int *)(page + 4) != ~x)
 		return (0);
  fbend_found:
 	return (page - startaddr);
+}
 STATIC void
 hd64461video_set_clut(struct hd64461video_chip *vc, int idx, int cnt,
     uint8_t *r, uint8_t *g, uint8_t *b)
+{
 	KASSERT(r && g && b);
-	/* index pallete */
+	/* index palette */
 	hd64461_reg_write_2(HD64461_LCDCPTWAR_REG16,
 	    HD64461_LCDCPTWAR_SET(0, idx));
 	/* set data */
 	while (cnt && LEGAL_CLUT_INDEX(idx)) {
 		uint16_t v;
 #define	HD64461VIDEO_SET_CLUT(x)					\
 		v = (x >> 2) & 0x3f;					\
 		hd64461_reg_write_2(HD64461_LCDCPTWDR_REG16, v)
 		HD64461VIDEO_SET_CLUT(*r);
 		HD64461VIDEO_SET_CLUT(*g);
 		HD64461VIDEO_SET_CLUT(*b);
 #undef	HD64461VIDEO_SET_CLUT
 		r++, g++, b++;
 		idx++, cnt--;
+	}
+}
 STATIC void
 hd64461video_get_clut(struct hd64461video_chip *vc, int idx, int cnt,
     uint8_t *r, uint8_t *g, uint8_t *b)
+{
 	KASSERT(r && g && b);
-	/* index pallete */
+	/* index palette */
 	hd64461_reg_write_2(HD64461_LCDCPTRAR_REG16,
 	    HD64461_LCDCPTRAR_SET(0, idx));
 	/* get data */
 	while (cnt && LEGAL_CLUT_INDEX(idx)) {
 		uint16_t v;
 #define	HD64461VIDEO_GET_CLUT(x)					\
 	v = hd64461_reg_read_2(HD64461_LCDCPTRDR_REG16);		\
 	x = HD64461_LCDCPTRDR(v);					\
 	x <<= 2
 		HD64461VIDEO_GET_CLUT(*r);
 		HD64461VIDEO_GET_CLUT(*g);
 		HD64461VIDEO_GET_CLUT(*b);

 @@ -1,14 +1,14 @@
-/* $NetBSD: lunafb.c,v 1.43 2021/08/07 16:18:57 thorpej Exp $ */
+/* $NetBSD: lunafb.c,v 1.44 2022/07/03 11:30:48 andvar Exp $ */
 /*-
  * Copyright (c) 2000 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Tohru Nishimura.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
 @@ -21,27 +21,27 @@
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <sys/cdefs.h>			/* RCS ID & Copyright macro defns */
-__KERNEL_RCSID(0, "$NetBSD: lunafb.c,v 1.43 2021/08/07 16:18:57 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: lunafb.c,v 1.44 2022/07/03 11:30:48 andvar Exp $");
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/conf.h>
 #include <sys/device.h>
 #include <sys/ioctl.h>
 #include <sys/kmem.h>
 #include <sys/mman.h>
 #include <sys/proc.h>
 #include <sys/tty.h>
 #include <sys/errno.h>
 #include <sys/buf.h>
 @@ -420,27 +420,27 @@ omfb_resetcmap(struct om_hwdevconfig *dc
 	} else if (hwplanemask == 0xff) {
 		struct bt458 *ndac = (struct bt458 *)OMFB_RAMDAC;
 		/*
 		 * Initialize the Bt458.  When we write to control registers,
 		 * the address is not incremented automatically. So we specify
 		 * it ourselves for each control register.
 		 */
 		ndac->bt_addr = 0x04;
 		ndac->bt_ctrl = 0xff; /* all planes will be read */
 		ndac->bt_addr = 0x05;
 		ndac->bt_ctrl = 0x00; /* all planes have non-blink */
 		ndac->bt_addr = 0x06;
-		ndac->bt_ctrl = 0x40; /* pallete enabled, ovly plane disabled */
+		ndac->bt_ctrl = 0x40; /* palette enabled, ovly plane disabled */
 		ndac->bt_addr = 0x07;
 		ndac->bt_ctrl = 0x00; /* no test mode */
 		/*
 		 * Set ANSI 16 colors.  We only supports 4bpp console right
 		 * now, repeat 16 colors in 256 colormap.
 		 */
 		ndac->bt_addr = 0;
 		for (i = 0; i < 256; i++) {
 			ndac->bt_cmap = dc->dc_cmap.r[i] = ansicmap[i % 16].r;
 			ndac->bt_cmap = dc->dc_cmap.g[i] = ansicmap[i % 16].g;
 			ndac->bt_cmap = dc->dc_cmap.b[i] = ansicmap[i % 16].b;
+		}

 @@ -1,14 +1,14 @@
-/* $NetBSD: tgareg.h,v 1.6 2005/12/11 12:22:50 christos Exp $ */
+/* $NetBSD: tgareg.h,v 1.7 2022/07/03 11:30:48 andvar Exp $ */
 /*
  * Copyright (c) 1995, 1996 Carnegie-Mellon University.
  * All rights reserved.
+ *
  * Author: Chris G. Demetriou
+ *
  * Permission to use, copy, modify and distribute this software and
  * its documentation is hereby granted, provided that both the copyright
  * notice and this permission notice appear in all copies of the
  * software, derivative works or modified versions, and any portions
  * thereof, and that both notices appear in supporting documentation.
+ *
 @@ -101,27 +101,27 @@ typedef u_int32_t tga_reg_t;
 #define	TGA_REG_GBIR	0x023		/* Blue Increment */
 #define	TGA_REG_GZIR_L	0x024		/* Z-increment Low */
 #define	TGA_REG_GZIR_H	0x025		/* Z-Increment High */
 #define	TGA_REG_GDBR	0x026		/* DMA Base Address */
 #define	TGA_REG_GBWR	0x027		/* Bresenham Width */
 #define	TGA_REG_GZVR_L	0x028		/* Z-value Low */
 #define	TGA_REG_GZVR_H	0x029		/* Z-value High */
 #define	TGA_REG_GZBR	0x02a		/* Z-base address */
 /*	GADR alias	0x02b */
 #define	TGA_REG_GRVR	0x02c		/* Red Value */
 #define	TGA_REG_GGVR	0x02d		/* Green Value */
 #define	TGA_REG_GBVR	0x02e		/* Blue Value */
 #define	TGA_REG_GSWR	0x02f		/* Span Width */
-#define	TGA_REG_EPSR	0x030		/* Pallete and DAC Setup */
+#define	TGA_REG_EPSR	0x030		/* Palette and DAC Setup */
 /*	reserved	0x031 - 0x3f */
 #define	TGA_REG_GSNR0	0x040		/* Slope-no-go 0 */
 #define	TGA_REG_GSNR1	0x041		/* Slope-no-go 1 */
 #define	TGA_REG_GSNR2	0x042		/* Slope-no-go 2 */
 #define	TGA_REG_GSNR3	0x043		/* Slope-no-go 3 */
 #define	TGA_REG_GSNR4	0x044		/* Slope-no-go 4 */
 #define	TGA_REG_GSNR5	0x045		/* Slope-no-go 5 */
 #define	TGA_REG_GSNR6	0x046		/* Slope-no-go 6 */
 #define	TGA_REG_GSNR7	0x047		/* Slope-no-go 7 */
 #define	TGA_REG_GSLR0	0x048		/* Slope 0 */
 @@ -146,27 +146,27 @@ typedef u_int32_t tga_reg_t;
 #define	TGA_REG_GCDR	0x059		/* Copy 64 Destination */
 /*	GC[SD]R aliases 0x05a - 0x05f */
 /*	reserved	0x060 - 0x077 */
 #define	TGA_REG_ERWR	0x078		/* EEPROM write */
 /*	reserved	0x079 */
 #define	TGA_REG_ECGR	0x07a		/* Clock */
 /*	reserved	0x07b */
-#define	TGA_REG_EPDR	0x07c		/* Pallete and DAC Data */
+#define	TGA_REG_EPDR	0x07c		/* Palette and DAC Data */
 /*	reserved	0x07d */
 #define	TGA_REG_SCSR	0x07e		/* Command Status */
 /*	reserved	0x07f */
 /*
  * Video Valid Register
  */
 #define	VVR_VIDEOVALID	0x00000001	/* 0 VGA, 1 TGA2 (TGA2 only) */
 #define	VVR_BLANK	0x00000002	/* 0 active, 1 blank */
 #define	VVR_CURSOR	0x00000004	/* 0 disable, 1 enable (TGA2 R/O) */