Thu Jul 21 14:27:47 2022 UTC ()
s/Transration/Translation/


(andvar)
diff -r1.3 -r1.4 src/sys/arch/ia64/include/dig64.h
cvs diff -r1.3 -r1.4 src/sys/arch/ia64/include/dig64.h (expand / switch to unified diff)

--- src/sys/arch/ia64/include/dig64.h 2022/07/21 10:09:21 1.3
+++ src/sys/arch/ia64/include/dig64.h 2022/07/21 14:27:46 1.4
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: dig64.h,v 1.3 2022/07/21 10:09:21 andvar Exp $ */ 1/* $NetBSD: dig64.h,v 1.4 2022/07/21 14:27:46 andvar Exp $ */
2 2
3/*- 3/*-
4 * Copyright (c) 2002 Marcel Moolenaar 4 * Copyright (c) 2002 Marcel Moolenaar
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * Redistribution and use in source and binary forms, with or without 7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions 8 * modification, are permitted provided that the following conditions
9 * are met: 9 * are met:
10 * 10 *
11 * 1. Redistributions of source code must retain the above copyright 11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer. 12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright 13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the 14 * notice, this list of conditions and the following disclaimer in the
@@ -95,28 +95,28 @@ struct dig64_vga_spec { @@ -95,28 +95,28 @@ struct dig64_vga_spec {
95 uint8_t num; /*Number of Extended Address Space Descriptors*/ 95 uint8_t num; /*Number of Extended Address Space Descriptors*/
96 struct { 96 struct {
97 uint8_t data[56]; 97 uint8_t data[56];
98 } edesc[0]; 98 } edesc[0];
99} __packed; 99} __packed;
100 100
101 101
102/* Interconnect Specific Structure */ 102/* Interconnect Specific Structure */
103 103
104#define DIG64_FLAGS_INTR_LEVEL (0 << 0) /* Level Triggered */ 104#define DIG64_FLAGS_INTR_LEVEL (0 << 0) /* Level Triggered */
105#define DIG64_FLAGS_INTR_EDGE (1 << 0) /* Edge Triggered */ 105#define DIG64_FLAGS_INTR_EDGE (1 << 0) /* Edge Triggered */
106#define DIG64_FLAGS_INTR_ACTH (0 << 1) /* Intr Active High */ 106#define DIG64_FLAGS_INTR_ACTH (0 << 1) /* Intr Active High */
107#define DIG64_FLAGS_INTR_ACTL (1 << 1) /* Intr Active Low */ 107#define DIG64_FLAGS_INTR_ACTL (1 << 1) /* Intr Active Low */
108#define DIG64_FLAGS_TRANS_DENSE (0 << 3) /* Dense Transration */ 108#define DIG64_FLAGS_TRANS_DENSE (0 << 3) /* Dense Translation */
109#define DIG64_FLAGS_TRANS_SPARSE (1 << 3) /* Sparse Transration */ 109#define DIG64_FLAGS_TRANS_SPARSE (1 << 3) /* Sparse Translation */
110#define DIG64_FLAGS_TYPE_STATIC (0 << 4) /* Type Static */ 110#define DIG64_FLAGS_TYPE_STATIC (0 << 4) /* Type Static */
111#define DIG64_FLAGS_TYPE_TRANS (1 << 4) /* Type Translation */ 111#define DIG64_FLAGS_TYPE_TRANS (1 << 4) /* Type Translation */
112#define DIG64_FLAGS_INTR_SUPP (1 << 6) /* Interrupt supported */ 112#define DIG64_FLAGS_INTR_SUPP (1 << 6) /* Interrupt supported */
113#define DIG64_FLAGS_MMIO_TRA_VALID (1 << 8) 113#define DIG64_FLAGS_MMIO_TRA_VALID (1 << 8)
114#define DIG64_FLAGS_IOPORT_TRA_VALID (1 << 9) 114#define DIG64_FLAGS_IOPORT_TRA_VALID (1 << 9)
115 115
116struct dig64_acpi_spec { 116struct dig64_acpi_spec {
117 uint8_t type; /* = 0 indicating ACPI */ 117 uint8_t type; /* = 0 indicating ACPI */
118 uint8_t resv; /* must be 0 */ 118 uint8_t resv; /* must be 0 */
119 uint16_t length; /* of the ACPI Specific Structure */ 119 uint16_t length; /* of the ACPI Specific Structure */
120 uint32_t uid; 120 uint32_t uid;
121 uint32_t hid; 121 uint32_t hid;
122 uint32_t acpi_gsi; /* ACPI Global System Interrupt */ 122 uint32_t acpi_gsi; /* ACPI Global System Interrupt */