Thu Sep 15 14:25:28 2022 UTC ()
fnm{add,sub}{,s}: Do not negate NaN.


(rin)
diff -r1.57 -r1.58 src/sys/arch/powerpc/fpu/fpu_emu.c
cvs diff -r1.57 -r1.58 src/sys/arch/powerpc/fpu/fpu_emu.c (expand / switch to unified diff)

--- src/sys/arch/powerpc/fpu/fpu_emu.c 2022/09/15 14:24:00 1.57
+++ src/sys/arch/powerpc/fpu/fpu_emu.c 2022/09/15 14:25:28 1.58
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: fpu_emu.c,v 1.57 2022/09/15 14:24:00 rin Exp $ */ 1/* $NetBSD: fpu_emu.c,v 1.58 2022/09/15 14:25:28 rin Exp $ */
2 2
3/* 3/*
4 * Copyright 2001 Wasabi Systems, Inc. 4 * Copyright 2001 Wasabi Systems, Inc.
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * Written by Eduardo Horvath and Simon Burge for Wasabi Systems, Inc. 7 * Written by Eduardo Horvath and Simon Burge for Wasabi Systems, Inc.
8 * 8 *
9 * Redistribution and use in source and binary forms, with or without 9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions 10 * modification, are permitted provided that the following conditions
11 * are met: 11 * are met:
12 * 1. Redistributions of source code must retain the above copyright 12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer. 13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright 14 * 2. Redistributions in binary form must reproduce the above copyright
@@ -66,27 +66,27 @@ @@ -66,27 +66,27 @@
66 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 66 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
67 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 67 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
68 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 68 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
69 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 69 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
70 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 70 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
71 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 71 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
72 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 72 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
73 * SUCH DAMAGE. 73 * SUCH DAMAGE.
74 * 74 *
75 * @(#)fpu.c 8.1 (Berkeley) 6/11/93 75 * @(#)fpu.c 8.1 (Berkeley) 6/11/93
76 */ 76 */
77 77
78#include <sys/cdefs.h> 78#include <sys/cdefs.h>
79__KERNEL_RCSID(0, "$NetBSD: fpu_emu.c,v 1.57 2022/09/15 14:24:00 rin Exp $"); 79__KERNEL_RCSID(0, "$NetBSD: fpu_emu.c,v 1.58 2022/09/15 14:25:28 rin Exp $");
80 80
81#ifdef _KERNEL_OPT 81#ifdef _KERNEL_OPT
82#include "opt_ddb.h" 82#include "opt_ddb.h"
83#endif 83#endif
84 84
85#include <sys/param.h> 85#include <sys/param.h>
86#include <sys/systm.h> 86#include <sys/systm.h>
87#include <sys/evcnt.h> 87#include <sys/evcnt.h>
88#include <sys/proc.h> 88#include <sys/proc.h>
89#include <sys/siginfo.h> 89#include <sys/siginfo.h>
90#include <sys/signal.h> 90#include <sys/signal.h>
91#include <sys/signalvar.h> 91#include <sys/signalvar.h>
92#include <sys/syslog.h> 92#include <sys/syslog.h>
@@ -728,39 +728,41 @@ fpu_execute(struct trapframe *tf, struct @@ -728,39 +728,41 @@ fpu_execute(struct trapframe *tf, struct
728 fpu_explode(fe, &fe->fe_f2, type, FR(rb)); 728 fpu_explode(fe, &fe->fe_f2, type, FR(rb));
729 fp = fpu_add(fe); 729 fp = fpu_add(fe);
730 break; 730 break;
731 case OPC59_FNMSUBS: 731 case OPC59_FNMSUBS:
732 FPU_EMU_EVCNT_INCR(fnmsub); 732 FPU_EMU_EVCNT_INCR(fnmsub);
733 DPRINTF(FPE_INSN, ("fpu_execute: FNMSUB\n")); 733 DPRINTF(FPE_INSN, ("fpu_execute: FNMSUB\n"));
734 fpu_explode(fe, &fe->fe_f1, type, FR(ra)); 734 fpu_explode(fe, &fe->fe_f1, type, FR(ra));
735 fpu_explode(fe, &fe->fe_f2, type, FR(rc)); 735 fpu_explode(fe, &fe->fe_f2, type, FR(rc));
736 fp = fpu_mul(fe); 736 fp = fpu_mul(fe);
737 fe->fe_f1 = *fp; 737 fe->fe_f1 = *fp;
738 fpu_explode(fe, &fe->fe_f2, type, FR(rb)); 738 fpu_explode(fe, &fe->fe_f2, type, FR(rb));
739 fp = fpu_sub(fe); 739 fp = fpu_sub(fe);
740 /* Negate */ 740 /* Negate */
741 fp->fp_sign ^= 1; 741 if (!ISNAN(fp))
 742 fp->fp_sign ^= 1;
742 break; 743 break;
743 case OPC59_FNMADDS: 744 case OPC59_FNMADDS:
744 FPU_EMU_EVCNT_INCR(fnmadd); 745 FPU_EMU_EVCNT_INCR(fnmadd);
745 DPRINTF(FPE_INSN, ("fpu_execute: FNMADD\n")); 746 DPRINTF(FPE_INSN, ("fpu_execute: FNMADD\n"));
746 fpu_explode(fe, &fe->fe_f1, type, FR(ra)); 747 fpu_explode(fe, &fe->fe_f1, type, FR(ra));
747 fpu_explode(fe, &fe->fe_f2, type, FR(rc)); 748 fpu_explode(fe, &fe->fe_f2, type, FR(rc));
748 fp = fpu_mul(fe); 749 fp = fpu_mul(fe);
749 fe->fe_f1 = *fp; 750 fe->fe_f1 = *fp;
750 fpu_explode(fe, &fe->fe_f2, type, FR(rb)); 751 fpu_explode(fe, &fe->fe_f2, type, FR(rb));
751 fp = fpu_add(fe); 752 fp = fpu_add(fe);
752 /* Negate */ 753 /* Negate */
753 fp->fp_sign ^= 1; 754 if (!ISNAN(fp))
 755 fp->fp_sign ^= 1;
754 break; 756 break;
755 default: 757 default:
756 return (NOTFPU); 758 return (NOTFPU);
757 break; 759 break;
758 } 760 }
759 761
760 /* If the instruction was single precision, round */ 762 /* If the instruction was single precision, round */
761 if (!(instr.i_any.i_opcd & 0x4)) { 763 if (!(instr.i_any.i_opcd & 0x4)) {
762 fpu_implode(fe, fp, FTYPE_SNG | FTYPE_FPSCR, 764 fpu_implode(fe, fp, FTYPE_SNG | FTYPE_FPSCR,
763 &FR(rt)); 765 &FR(rt));
764 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_SNG, 766 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_SNG,
765 FR(rt)); 767 FR(rt));
766 } else 768 } else