Sat Jan 7 08:00:50 2023 UTC ()
Whitespace. No functional change.


(msaitoh)
diff -r1.5 -r1.6 src/sys/dev/ic/igpioreg.h
cvs diff -r1.5 -r1.6 src/sys/dev/ic/igpioreg.h (expand / switch to unified diff)

--- src/sys/dev/ic/igpioreg.h 2023/01/07 03:22:02 1.5
+++ src/sys/dev/ic/igpioreg.h 2023/01/07 08:00:50 1.6
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: igpioreg.h,v 1.5 2023/01/07 03:22:02 msaitoh Exp $ */ 1/* $NetBSD: igpioreg.h,v 1.6 2023/01/07 08:00:50 msaitoh Exp $ */
2 2
3/* 3/*
4 * Copyright (c) 2021 Emmanuel Dreyfus 4 * Copyright (c) 2021 Emmanuel Dreyfus
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * Redistribution and use in source and binary forms, with or without 7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions 8 * modification, are permitted provided that the following conditions
9 * are met: 9 * are met:
10 * 1. Redistributions of source code must retain the above copyright 10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer. 11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright 12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the 13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution. 14 * documentation and/or other materials provided with the distribution.
@@ -345,61 +345,61 @@ struct igpio_pin_group igpio_pin_group[] @@ -345,61 +345,61 @@ struct igpio_pin_group igpio_pin_group[]
345 { "INT34C5", 2, 129, "GPP_S" }, 345 { "INT34C5", 2, 129, "GPP_S" },
346 { "INT34C5", 3, 137, "GPP_G" }, 346 { "INT34C5", 3, 137, "GPP_G" },
347 { "INT34C5", 4, 154, "vGPIO" }, 347 { "INT34C5", 4, 154, "vGPIO" },
348 { "INT34C5", 0, 181, "GPP_E" }, 348 { "INT34C5", 0, 181, "GPP_E" },
349 { "INT34C5", 1, 194, "GPP_F" }, 349 { "INT34C5", 1, 194, "GPP_F" },
350 { "INT34C5", 0, 218, "GPP_H" }, 350 { "INT34C5", 0, 218, "GPP_H" },
351 { "INT34C5", 1, 242, "GPP_J" }, 351 { "INT34C5", 1, 242, "GPP_J" },
352 { "INT34C5", 2, 252, "GPP_K" }, 352 { "INT34C5", 2, 252, "GPP_K" },
353 { "INT34C5", 0, 267, "GPP_I" }, 353 { "INT34C5", 0, 267, "GPP_I" },
354 { "INT34C5", 1, 282, "JTAG" }, 354 { "INT34C5", 1, 282, "JTAG" },
355 355
356 356
357 /* Alder Lake-P (Same as Tigerlake-LP(INT34C5)) */ 357 /* Alder Lake-P (Same as Tigerlake-LP(INT34C5)) */
358 { "INTC1055", 0, 0, "GPP_A" }, 358 { "INTC1055", 0, 0, "GPP_A" },
359 { "INTC1055", 1, 25, "GPP_R" }, 359 { "INTC1055", 1, 25, "GPP_R" },
360 { "INTC1055", 2, 45, "GPP_B" }, 360 { "INTC1055", 2, 45, "GPP_B" },
361 { "INTC1055", 3, 71, "vGPIO_0" }, 361 { "INTC1055", 3, 71, "vGPIO_0" },
362 { "INTC1055", 0, 79, "GPP_D" }, 362 { "INTC1055", 0, 79, "GPP_D" },
363 { "INTC1055", 1, 105, "GPP_C" }, 363 { "INTC1055", 1, 105, "GPP_C" },
364 { "INTC1055", 2, 129, "GPP_S" }, 364 { "INTC1055", 2, 129, "GPP_S" },
365 { "INTC1055", 3, 137, "GPP_G" }, 365 { "INTC1055", 3, 137, "GPP_G" },
366 { "INTC1055", 4, 154, "vGPIO" }, 366 { "INTC1055", 4, 154, "vGPIO" },
367 { "INTC1055", 0, 181, "GPP_E" }, 367 { "INTC1055", 0, 181, "GPP_E" },
368 { "INTC1055", 1, 194, "GPP_F" }, 368 { "INTC1055", 1, 194, "GPP_F" },
369 { "INTC1055", 0, 218, "GPP_H" }, 369 { "INTC1055", 0, 218, "GPP_H" },
370 { "INTC1055", 1, 242, "GPP_J" }, 370 { "INTC1055", 1, 242, "GPP_J" },
371 { "INTC1055", 2, 252, "GPP_K" }, 371 { "INTC1055", 2, 252, "GPP_K" },
372 { "INTC1055", 0, 267, "GPP_I" }, 372 { "INTC1055", 0, 267, "GPP_I" },
373 { "INTC1055", 1, 282, "JTAG" }, 373 { "INTC1055", 1, 282, "JTAG" },
374 374
375 375
376 /* Tiger Lake-LP */ 376 /* Tiger Lake-LP */
377 { "INTC1057", 0, 0, "GPP_A" }, 377 { "INTC1057", 0, 0, "GPP_A" },
378 { "INTC1057", 1, 25, "GPP_R" }, 378 { "INTC1057", 1, 25, "GPP_R" },
379 { "INTC1057", 2, 45, "GPP_B" }, 379 { "INTC1057", 2, 45, "GPP_B" },
380 { "INTC1057", 3, 71, "vGPIO_0" }, 380 { "INTC1057", 3, 71, "vGPIO_0" },
381 { "INTC1057", 0, 79, "GPP_D" }, 381 { "INTC1057", 0, 79, "GPP_D" },
382 { "INTC1057", 1, 105, "GPP_C" }, 382 { "INTC1057", 1, 105, "GPP_C" },
383 { "INTC1057", 2, 129, "GPP_S" }, 383 { "INTC1057", 2, 129, "GPP_S" },
384 { "INTC1057", 3, 137, "GPP_G" }, 384 { "INTC1057", 3, 137, "GPP_G" },
385 { "INTC1057", 4, 154, "vGPIO" }, 385 { "INTC1057", 4, 154, "vGPIO" },
386 { "INTC1057", 0, 181, "GPP_E" }, 386 { "INTC1057", 0, 181, "GPP_E" },
387 { "INTC1057", 1, 194, "GPP_F" }, 387 { "INTC1057", 1, 194, "GPP_F" },
388 { "INTC1057", 0, 218, "GPP_H" }, 388 { "INTC1057", 0, 218, "GPP_H" },
389 { "INTC1057", 1, 242, "GPP_J" }, 389 { "INTC1057", 1, 242, "GPP_J" },
390 { "INTC1057", 2, 252, "GPP_K" }, 390 { "INTC1057", 2, 252, "GPP_K" },
391 { "INTC1057", 0, 267, "GPP_I" }, 391 { "INTC1057", 0, 267, "GPP_I" },
392 { "INTC1057", 1, 282, "JTAG" }, 392 { "INTC1057", 1, 282, "JTAG" },
393 393
394 /* Tiger Lake-H */ 394 /* Tiger Lake-H */
395 { "INT34C6", 0, 0, "GPP_B" }, 395 { "INT34C6", 0, 0, "GPP_B" },
396 { "INT34C6", 1, 26, "GPP_T" }, 396 { "INT34C6", 1, 26, "GPP_T" },
397 { "INT34C6", 2, 42, "GPP_A" }, 397 { "INT34C6", 2, 42, "GPP_A" },
398 { "INT34C6", 0, 67, "GPP_S" }, 398 { "INT34C6", 0, 67, "GPP_S" },
399 { "INT34C6", 1, 75, "GPP_H" }, 399 { "INT34C6", 1, 75, "GPP_H" },
400 { "INT34C6", 2, 99, "GPP_D" }, 400 { "INT34C6", 2, 99, "GPP_D" },
401 { "INT34C6", 3, 120, "GPP_U" }, 401 { "INT34C6", 3, 120, "GPP_U" },
402 { "INT34C6", 4, 144, "vGPIO" }, 402 { "INT34C6", 4, 144, "vGPIO" },
403 { "INT34C6", 0, 171, "GPP_C" }, 403 { "INT34C6", 0, 171, "GPP_C" },
404 { "INT34C6", 1, 195, "GPP_F" }, 404 { "INT34C6", 1, 195, "GPP_F" },
405 { "INT34C6", 2, 220, "HVCMOS" }, 405 { "INT34C6", 2, 220, "HVCMOS" },