| @@ -1,1451 +1,1452 @@ | | | @@ -1,1451 +1,1452 @@ |
1 | /* $NetBSD: specialreg.h,v 1.204 2023/03/25 21:47:10 andvar Exp $ */ | | 1 | /* $NetBSD: specialreg.h,v 1.205 2023/04/11 02:44:06 msaitoh Exp $ */ |
2 | | | 2 | |
3 | /* | | 3 | /* |
4 | * Copyright (c) 2014-2020 The NetBSD Foundation, Inc. | | 4 | * Copyright (c) 2014-2020 The NetBSD Foundation, Inc. |
5 | * All rights reserved. | | 5 | * All rights reserved. |
6 | * | | 6 | * |
7 | * Redistribution and use in source and binary forms, with or without | | 7 | * Redistribution and use in source and binary forms, with or without |
8 | * modification, are permitted provided that the following conditions | | 8 | * modification, are permitted provided that the following conditions |
9 | * are met: | | 9 | * are met: |
10 | * 1. Redistributions of source code must retain the above copyright | | 10 | * 1. Redistributions of source code must retain the above copyright |
11 | * notice, this list of conditions and the following disclaimer. | | 11 | * notice, this list of conditions and the following disclaimer. |
12 | * 2. Redistributions in binary form must reproduce the above copyright | | 12 | * 2. Redistributions in binary form must reproduce the above copyright |
13 | * notice, this list of conditions and the following disclaimer in the | | 13 | * notice, this list of conditions and the following disclaimer in the |
14 | * documentation and/or other materials provided with the distribution. | | 14 | * documentation and/or other materials provided with the distribution. |
15 | * | | 15 | * |
16 | * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS | | 16 | * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS |
17 | * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED | | 17 | * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED |
18 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR | | 18 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
19 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS | | 19 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS |
20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | | 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | | 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | | 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
23 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | | 23 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
24 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | | 24 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
25 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | | 25 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
26 | * POSSIBILITY OF SUCH DAMAGE. | | 26 | * POSSIBILITY OF SUCH DAMAGE. |
27 | */ | | 27 | */ |
28 | | | 28 | |
29 | /* | | 29 | /* |
30 | * Copyright (c) 1991 The Regents of the University of California. | | 30 | * Copyright (c) 1991 The Regents of the University of California. |
31 | * All rights reserved. | | 31 | * All rights reserved. |
32 | * | | 32 | * |
33 | * Redistribution and use in source and binary forms, with or without | | 33 | * Redistribution and use in source and binary forms, with or without |
34 | * modification, are permitted provided that the following conditions | | 34 | * modification, are permitted provided that the following conditions |
35 | * are met: | | 35 | * are met: |
36 | * 1. Redistributions of source code must retain the above copyright | | 36 | * 1. Redistributions of source code must retain the above copyright |
37 | * notice, this list of conditions and the following disclaimer. | | 37 | * notice, this list of conditions and the following disclaimer. |
38 | * 2. Redistributions in binary form must reproduce the above copyright | | 38 | * 2. Redistributions in binary form must reproduce the above copyright |
39 | * notice, this list of conditions and the following disclaimer in the | | 39 | * notice, this list of conditions and the following disclaimer in the |
40 | * documentation and/or other materials provided with the distribution. | | 40 | * documentation and/or other materials provided with the distribution. |
41 | * 3. Neither the name of the University nor the names of its contributors | | 41 | * 3. Neither the name of the University nor the names of its contributors |
42 | * may be used to endorse or promote products derived from this software | | 42 | * may be used to endorse or promote products derived from this software |
43 | * without specific prior written permission. | | 43 | * without specific prior written permission. |
44 | * | | 44 | * |
45 | * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND | | 45 | * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND |
46 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | | 46 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
47 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | | 47 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
48 | * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE | | 48 | * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE |
49 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | | 49 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
50 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS | | 50 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
51 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) | | 51 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
52 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT | | 52 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
53 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY | | 53 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
54 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF | | 54 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
55 | * SUCH DAMAGE. | | 55 | * SUCH DAMAGE. |
56 | * | | 56 | * |
57 | * @(#)specialreg.h 7.1 (Berkeley) 5/9/91 | | 57 | * @(#)specialreg.h 7.1 (Berkeley) 5/9/91 |
58 | */ | | 58 | */ |
59 | | | 59 | |
60 | /* | | 60 | /* |
61 | * CR0 | | 61 | * CR0 |
62 | */ | | 62 | */ |
63 | #define CR0_PE 0x00000001 /* Protected mode Enable */ | | 63 | #define CR0_PE 0x00000001 /* Protected mode Enable */ |
64 | #define CR0_MP 0x00000002 /* "Math" Present (NPX or NPX emulator) */ | | 64 | #define CR0_MP 0x00000002 /* "Math" Present (NPX or NPX emulator) */ |
65 | #define CR0_EM 0x00000004 /* EMulate non-NPX coproc. (trap ESC only) */ | | 65 | #define CR0_EM 0x00000004 /* EMulate non-NPX coproc. (trap ESC only) */ |
66 | #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */ | | 66 | #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */ |
67 | #define CR0_ET 0x00000010 /* Extension Type (387 (if set) vs 287) */ | | 67 | #define CR0_ET 0x00000010 /* Extension Type (387 (if set) vs 287) */ |
68 | #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ | | 68 | #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ |
69 | #define CR0_WP 0x00010000 /* Write Protect (honor PTE_W in all modes) */ | | 69 | #define CR0_WP 0x00010000 /* Write Protect (honor PTE_W in all modes) */ |
70 | #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ | | 70 | #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ |
71 | #define CR0_NW 0x20000000 /* Not Write-through */ | | 71 | #define CR0_NW 0x20000000 /* Not Write-through */ |
72 | #define CR0_CD 0x40000000 /* Cache Disable */ | | 72 | #define CR0_CD 0x40000000 /* Cache Disable */ |
73 | #define CR0_PG 0x80000000 /* PaGing enable */ | | 73 | #define CR0_PG 0x80000000 /* PaGing enable */ |
74 | | | 74 | |
75 | /* | | 75 | /* |
76 | * Cyrix 486 DLC special registers, accessible as IO ports | | 76 | * Cyrix 486 DLC special registers, accessible as IO ports |
77 | */ | | 77 | */ |
78 | #define CCR0 0xc0 /* configuration control register 0 */ | | 78 | #define CCR0 0xc0 /* configuration control register 0 */ |
79 | #define CCR0_NC0 0x01 /* first 64K of each 1M memory region is non-cacheable */ | | 79 | #define CCR0_NC0 0x01 /* first 64K of each 1M memory region is non-cacheable */ |
80 | #define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */ | | 80 | #define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */ |
81 | #define CCR0_A20M 0x04 /* enables A20M# input pin */ | | 81 | #define CCR0_A20M 0x04 /* enables A20M# input pin */ |
82 | #define CCR0_KEN 0x08 /* enables KEN# input pin */ | | 82 | #define CCR0_KEN 0x08 /* enables KEN# input pin */ |
83 | #define CCR0_FLUSH 0x10 /* enables FLUSH# input pin */ | | 83 | #define CCR0_FLUSH 0x10 /* enables FLUSH# input pin */ |
84 | #define CCR0_BARB 0x20 /* flushes internal cache when entering hold state */ | | 84 | #define CCR0_BARB 0x20 /* flushes internal cache when entering hold state */ |
85 | #define CCR0_CO 0x40 /* cache org: 1=direct mapped, 0=2x set assoc */ | | 85 | #define CCR0_CO 0x40 /* cache org: 1=direct mapped, 0=2x set assoc */ |
86 | #define CCR0_SUSPEND 0x80 /* enables SUSP# and SUSPA# pins */ | | 86 | #define CCR0_SUSPEND 0x80 /* enables SUSP# and SUSPA# pins */ |
87 | #define CCR1 0xc1 /* configuration control register 1 */ | | 87 | #define CCR1 0xc1 /* configuration control register 1 */ |
88 | #define CCR1_RPL 0x01 /* enables RPLSET and RPLVAL# pins */ | | 88 | #define CCR1_RPL 0x01 /* enables RPLSET and RPLVAL# pins */ |
89 | | | 89 | |
90 | /* | | 90 | /* |
91 | * CR3 | | 91 | * CR3 |
92 | */ | | 92 | */ |
93 | #define CR3_PCID __BITS(11,0) | | 93 | #define CR3_PCID __BITS(11,0) |
94 | #define CR3_PA __BITS(62,12) | | 94 | #define CR3_PA __BITS(62,12) |
95 | #define CR3_NO_TLB_FLUSH __BIT(63) | | 95 | #define CR3_NO_TLB_FLUSH __BIT(63) |
96 | | | 96 | |
97 | /* | | 97 | /* |
98 | * CR4 | | 98 | * CR4 |
99 | */ | | 99 | */ |
100 | #define CR4_VME 0x00000001 /* Virtual 8086 mode extension enable */ | | 100 | #define CR4_VME 0x00000001 /* Virtual 8086 mode extension enable */ |
101 | #define CR4_PVI 0x00000002 /* Protected mode virtual interrupt enable */ | | 101 | #define CR4_PVI 0x00000002 /* Protected mode virtual interrupt enable */ |
102 | #define CR4_TSD 0x00000004 /* Restrict RDTSC instruction to cpl 0 */ | | 102 | #define CR4_TSD 0x00000004 /* Restrict RDTSC instruction to cpl 0 */ |
103 | #define CR4_DE 0x00000008 /* Debugging extension */ | | 103 | #define CR4_DE 0x00000008 /* Debugging extension */ |
104 | #define CR4_PSE 0x00000010 /* Large (4MB) page size enable */ | | 104 | #define CR4_PSE 0x00000010 /* Large (4MB) page size enable */ |
105 | #define CR4_PAE 0x00000020 /* Physical address extension enable */ | | 105 | #define CR4_PAE 0x00000020 /* Physical address extension enable */ |
106 | #define CR4_MCE 0x00000040 /* Machine check enable */ | | 106 | #define CR4_MCE 0x00000040 /* Machine check enable */ |
107 | #define CR4_PGE 0x00000080 /* Page global enable */ | | 107 | #define CR4_PGE 0x00000080 /* Page global enable */ |
108 | #define CR4_PCE 0x00000100 /* Enable RDPMC instruction for all cpls */ | | 108 | #define CR4_PCE 0x00000100 /* Enable RDPMC instruction for all cpls */ |
109 | #define CR4_OSFXSR 0x00000200 /* Enable fxsave/fxrestor and SSE */ | | 109 | #define CR4_OSFXSR 0x00000200 /* Enable fxsave/fxrestor and SSE */ |
110 | #define CR4_OSXMMEXCPT 0x00000400 /* Enable unmasked SSE exceptions */ | | 110 | #define CR4_OSXMMEXCPT 0x00000400 /* Enable unmasked SSE exceptions */ |
111 | #define CR4_UMIP 0x00000800 /* User Mode Instruction Prevention */ | | 111 | #define CR4_UMIP 0x00000800 /* User Mode Instruction Prevention */ |
112 | #define CR4_LA57 0x00001000 /* 57-bit linear addresses */ | | 112 | #define CR4_LA57 0x00001000 /* 57-bit linear addresses */ |
113 | #define CR4_VMXE 0x00002000 /* Enable VMX operations */ | | 113 | #define CR4_VMXE 0x00002000 /* Enable VMX operations */ |
114 | #define CR4_SMXE 0x00004000 /* Enable SMX operations */ | | 114 | #define CR4_SMXE 0x00004000 /* Enable SMX operations */ |
115 | #define CR4_FSGSBASE 0x00010000 /* Enable *FSBASE and *GSBASE instructions */ | | 115 | #define CR4_FSGSBASE 0x00010000 /* Enable *FSBASE and *GSBASE instructions */ |
116 | #define CR4_PCIDE 0x00020000 /* Enable Process Context IDentifiers */ | | 116 | #define CR4_PCIDE 0x00020000 /* Enable Process Context IDentifiers */ |
117 | #define CR4_OSXSAVE 0x00040000 /* Enable xsave and xrestore */ | | 117 | #define CR4_OSXSAVE 0x00040000 /* Enable xsave and xrestore */ |
118 | #define CR4_SMEP 0x00100000 /* Enable SMEP support */ | | 118 | #define CR4_SMEP 0x00100000 /* Enable SMEP support */ |
119 | #define CR4_SMAP 0x00200000 /* Enable SMAP support */ | | 119 | #define CR4_SMAP 0x00200000 /* Enable SMAP support */ |
120 | #define CR4_PKE 0x00400000 /* Enable Protection Keys for user pages */ | | 120 | #define CR4_PKE 0x00400000 /* Enable Protection Keys for user pages */ |
121 | #define CR4_CET 0x00800000 /* Enable CET */ | | 121 | #define CR4_CET 0x00800000 /* Enable CET */ |
122 | #define CR4_PKS 0x01000000 /* Enable Protection Keys for kern pages */ | | 122 | #define CR4_PKS 0x01000000 /* Enable Protection Keys for kern pages */ |
123 | | | 123 | |
124 | /* | | 124 | /* |
125 | * Extended Control Register XCR0 | | 125 | * Extended Control Register XCR0 |
126 | */ | | 126 | */ |
127 | #define XCR0_X87 __BIT(0) /* x87 FPU/MMX state */ | | 127 | #define XCR0_X87 __BIT(0) /* x87 FPU/MMX state */ |
128 | #define XCR0_SSE __BIT(1) /* SSE state */ | | 128 | #define XCR0_SSE __BIT(1) /* SSE state */ |
129 | #define XCR0_YMM_Hi128 __BIT(2) /* AVX-256 (ymmn registers) */ | | 129 | #define XCR0_YMM_Hi128 __BIT(2) /* AVX-256 (ymmn registers) */ |
130 | #define XCR0_BNDREGS __BIT(3) /* Memory protection ext bounds */ | | 130 | #define XCR0_BNDREGS __BIT(3) /* Memory protection ext bounds */ |
131 | #define XCR0_BNDCSR __BIT(4) /* Memory protection ext state */ | | 131 | #define XCR0_BNDCSR __BIT(4) /* Memory protection ext state */ |
132 | #define XCR0_Opmask __BIT(5) /* AVX-512 Opmask */ | | 132 | #define XCR0_Opmask __BIT(5) /* AVX-512 Opmask */ |
133 | #define XCR0_ZMM_Hi256 __BIT(6) /* AVX-512 upper 256 bits low regs */ | | 133 | #define XCR0_ZMM_Hi256 __BIT(6) /* AVX-512 upper 256 bits low regs */ |
134 | #define XCR0_Hi16_ZMM __BIT(7) /* AVX-512 512 bits upper registers */ | | 134 | #define XCR0_Hi16_ZMM __BIT(7) /* AVX-512 512 bits upper registers */ |
135 | #define XCR0_PT __BIT(8) /* Processor Trace state */ | | 135 | #define XCR0_PT __BIT(8) /* Processor Trace state */ |
136 | #define XCR0_PKRU __BIT(9) /* Protection Key state */ | | 136 | #define XCR0_PKRU __BIT(9) /* Protection Key state */ |
137 | #define XCR0_CET_U __BIT(11) /* User CET state */ | | 137 | #define XCR0_CET_U __BIT(11) /* User CET state */ |
138 | #define XCR0_CET_S __BIT(12) /* Kern CET state */ | | 138 | #define XCR0_CET_S __BIT(12) /* Kern CET state */ |
139 | #define XCR0_HDC __BIT(13) /* Hardware Duty Cycle state */ | | 139 | #define XCR0_HDC __BIT(13) /* Hardware Duty Cycle state */ |
140 | #define XCR0_LBR __BIT(15) /* Last Branch Record */ | | 140 | #define XCR0_LBR __BIT(15) /* Last Branch Record */ |
141 | #define XCR0_HWP __BIT(16) /* Hardware P-states */ | | 141 | #define XCR0_HWP __BIT(16) /* Hardware P-states */ |
142 | | | 142 | |
143 | #define XCR0_FLAGS1 "\20" \ | | 143 | #define XCR0_FLAGS1 "\20" \ |
144 | "\1" "x87" "\2" "SSE" "\3" "AVX" "\4" "BNDREGS" \ | | 144 | "\1" "x87" "\2" "SSE" "\3" "AVX" "\4" "BNDREGS" \ |
145 | "\5" "BNDCSR" "\6" "Opmask" "\7" "ZMM_Hi256" "\10" "Hi16_ZMM" \ | | 145 | "\5" "BNDCSR" "\6" "Opmask" "\7" "ZMM_Hi256" "\10" "Hi16_ZMM" \ |
146 | "\11" "PT" "\12" "PKRU" "\14" "CET_U" \ | | 146 | "\11" "PT" "\12" "PKRU" "\14" "CET_U" \ |
147 | "\15" "CET_S" "\16" "HDC" "\20" "LBR" \ | | 147 | "\15" "CET_S" "\16" "HDC" "\20" "LBR" \ |
148 | "\21" "HWP" | | 148 | "\21" "HWP" |
149 | | | 149 | |
150 | /* | | 150 | /* |
151 | * Known FPU bits, only these get enabled. The save area is sized for all the | | 151 | * Known FPU bits, only these get enabled. The save area is sized for all the |
152 | * fields below. | | 152 | * fields below. |
153 | */ | | 153 | */ |
154 | #define XCR0_FPU (XCR0_X87 | XCR0_SSE | XCR0_YMM_Hi128 | \ | | 154 | #define XCR0_FPU (XCR0_X87 | XCR0_SSE | XCR0_YMM_Hi128 | \ |
155 | XCR0_Opmask | XCR0_ZMM_Hi256 | XCR0_Hi16_ZMM) | | 155 | XCR0_Opmask | XCR0_ZMM_Hi256 | XCR0_Hi16_ZMM) |
156 | | | 156 | |
157 | /* | | 157 | /* |
158 | * XSAVE component indices, internal to NetBSD. | | 158 | * XSAVE component indices, internal to NetBSD. |
159 | */ | | 159 | */ |
160 | #define XSAVE_X87 0 | | 160 | #define XSAVE_X87 0 |
161 | #define XSAVE_SSE 1 | | 161 | #define XSAVE_SSE 1 |
162 | #define XSAVE_YMM_Hi128 2 | | 162 | #define XSAVE_YMM_Hi128 2 |
163 | #define XSAVE_BNDREGS 3 | | 163 | #define XSAVE_BNDREGS 3 |
164 | #define XSAVE_BNDCSR 4 | | 164 | #define XSAVE_BNDCSR 4 |
165 | #define XSAVE_Opmask 5 | | 165 | #define XSAVE_Opmask 5 |
166 | #define XSAVE_ZMM_Hi256 6 | | 166 | #define XSAVE_ZMM_Hi256 6 |
167 | #define XSAVE_Hi16_ZMM 7 | | 167 | #define XSAVE_Hi16_ZMM 7 |
168 | | | 168 | |
169 | /* | | 169 | /* |
170 | * Highest XSAVE component enabled by XCR0_FPU. | | 170 | * Highest XSAVE component enabled by XCR0_FPU. |
171 | */ | | 171 | */ |
172 | #define XSAVE_MAX_COMPONENT XSAVE_Hi16_ZMM | | 172 | #define XSAVE_MAX_COMPONENT XSAVE_Hi16_ZMM |
173 | | | 173 | |
174 | /* | | 174 | /* |
175 | * "features" bits. | | 175 | * "features" bits. |
176 | * CPUID Fn00000001 | | 176 | * CPUID Fn00000001 |
177 | */ | | 177 | */ |
178 | /* %edx */ | | 178 | /* %edx */ |
179 | #define CPUID_FPU 0x00000001 /* processor has an FPU? */ | | 179 | #define CPUID_FPU 0x00000001 /* processor has an FPU? */ |
180 | #define CPUID_VME 0x00000002 /* has virtual mode (%cr4's VME/PVI) */ | | 180 | #define CPUID_VME 0x00000002 /* has virtual mode (%cr4's VME/PVI) */ |
181 | #define CPUID_DE 0x00000004 /* has debugging extension */ | | 181 | #define CPUID_DE 0x00000004 /* has debugging extension */ |
182 | #define CPUID_PSE 0x00000008 /* has 4MB page size extension */ | | 182 | #define CPUID_PSE 0x00000008 /* has 4MB page size extension */ |
183 | #define CPUID_TSC 0x00000010 /* has time stamp counter */ | | 183 | #define CPUID_TSC 0x00000010 /* has time stamp counter */ |
184 | #define CPUID_MSR 0x00000020 /* has model specific registers */ | | 184 | #define CPUID_MSR 0x00000020 /* has model specific registers */ |
185 | #define CPUID_PAE 0x00000040 /* has physical address extension */ | | 185 | #define CPUID_PAE 0x00000040 /* has physical address extension */ |
186 | #define CPUID_MCE 0x00000080 /* has machine check exception */ | | 186 | #define CPUID_MCE 0x00000080 /* has machine check exception */ |
187 | #define CPUID_CX8 0x00000100 /* has CMPXCHG8B instruction */ | | 187 | #define CPUID_CX8 0x00000100 /* has CMPXCHG8B instruction */ |
188 | #define CPUID_APIC 0x00000200 /* has enabled APIC */ | | 188 | #define CPUID_APIC 0x00000200 /* has enabled APIC */ |
189 | #define CPUID_SEP 0x00000800 /* has SYSENTER/SYSEXIT extension */ | | 189 | #define CPUID_SEP 0x00000800 /* has SYSENTER/SYSEXIT extension */ |
190 | #define CPUID_MTRR 0x00001000 /* has memory type range register */ | | 190 | #define CPUID_MTRR 0x00001000 /* has memory type range register */ |
191 | #define CPUID_PGE 0x00002000 /* has page global extension */ | | 191 | #define CPUID_PGE 0x00002000 /* has page global extension */ |
192 | #define CPUID_MCA 0x00004000 /* has machine check architecture */ | | 192 | #define CPUID_MCA 0x00004000 /* has machine check architecture */ |
193 | #define CPUID_CMOV 0x00008000 /* has CMOVcc instruction */ | | 193 | #define CPUID_CMOV 0x00008000 /* has CMOVcc instruction */ |
194 | #define CPUID_PAT 0x00010000 /* Page Attribute Table */ | | 194 | #define CPUID_PAT 0x00010000 /* Page Attribute Table */ |
195 | #define CPUID_PSE36 0x00020000 /* 36-bit PSE */ | | 195 | #define CPUID_PSE36 0x00020000 /* 36-bit PSE */ |
196 | #define CPUID_PSN 0x00040000 /* Processor Serial Number */ | | 196 | #define CPUID_PSN 0x00040000 /* Processor Serial Number */ |
197 | #define CPUID_CLFSH 0x00080000 /* CLFLUSH instruction supported */ | | 197 | #define CPUID_CLFSH 0x00080000 /* CLFLUSH instruction supported */ |
198 | #define CPUID_DS 0x00200000 /* Debug Store */ | | 198 | #define CPUID_DS 0x00200000 /* Debug Store */ |
199 | #define CPUID_ACPI 0x00400000 /* ACPI performance modulation regs */ | | 199 | #define CPUID_ACPI 0x00400000 /* ACPI performance modulation regs */ |
200 | #define CPUID_MMX 0x00800000 /* MMX supported */ | | 200 | #define CPUID_MMX 0x00800000 /* MMX supported */ |
201 | #define CPUID_FXSR 0x01000000 /* Fast FP/MMX Save/Restore */ | | 201 | #define CPUID_FXSR 0x01000000 /* Fast FP/MMX Save/Restore */ |
202 | #define CPUID_SSE 0x02000000 /* Streaming SIMD Extensions */ | | 202 | #define CPUID_SSE 0x02000000 /* Streaming SIMD Extensions */ |
203 | #define CPUID_SSE2 0x04000000 /* Streaming SIMD Extensions #2 */ | | 203 | #define CPUID_SSE2 0x04000000 /* Streaming SIMD Extensions #2 */ |
204 | #define CPUID_SS 0x08000000 /* Self-Snoop */ | | 204 | #define CPUID_SS 0x08000000 /* Self-Snoop */ |
205 | #define CPUID_HTT 0x10000000 /* Hyper-Threading Technology */ | | 205 | #define CPUID_HTT 0x10000000 /* Hyper-Threading Technology */ |
206 | #define CPUID_TM 0x20000000 /* Thermal Monitor (TCC) */ | | 206 | #define CPUID_TM 0x20000000 /* Thermal Monitor (TCC) */ |
207 | #define CPUID_PBE 0x80000000 /* Pending Break Enable */ | | 207 | #define CPUID_PBE 0x80000000 /* Pending Break Enable */ |
208 | | | 208 | |
209 | #define CPUID_FLAGS1 "\20" \ | | 209 | #define CPUID_FLAGS1 "\20" \ |
210 | "\1" "FPU" "\2" "VME" "\3" "DE" "\4" "PSE" \ | | 210 | "\1" "FPU" "\2" "VME" "\3" "DE" "\4" "PSE" \ |
211 | "\5" "TSC" "\6" "MSR" "\7" "PAE" "\10" "MCE" \ | | 211 | "\5" "TSC" "\6" "MSR" "\7" "PAE" "\10" "MCE" \ |
212 | "\11" "CX8" "\12" "APIC" "\13" "B10" "\14" "SEP" \ | | 212 | "\11" "CX8" "\12" "APIC" "\13" "B10" "\14" "SEP" \ |
213 | "\15" "MTRR" "\16" "PGE" "\17" "MCA" "\20" "CMOV" \ | | 213 | "\15" "MTRR" "\16" "PGE" "\17" "MCA" "\20" "CMOV" \ |
214 | "\21" "PAT" "\22" "PSE36" "\23" "PN" "\24" "CLFSH" \ | | 214 | "\21" "PAT" "\22" "PSE36" "\23" "PN" "\24" "CLFSH" \ |
215 | "\25" "B20" "\26" "DS" "\27" "ACPI" "\30" "MMX" \ | | 215 | "\25" "B20" "\26" "DS" "\27" "ACPI" "\30" "MMX" \ |
216 | "\31" "FXSR" "\32" "SSE" "\33" "SSE2" "\34" "SS" \ | | 216 | "\31" "FXSR" "\32" "SSE" "\33" "SSE2" "\34" "SS" \ |
217 | "\35" "HTT" "\36" "TM" "\37" "IA64" "\40" "PBE" | | 217 | "\35" "HTT" "\36" "TM" "\37" "IA64" "\40" "PBE" |
218 | | | 218 | |
219 | /* Blacklists of CPUID flags - used to mask certain features */ | | 219 | /* Blacklists of CPUID flags - used to mask certain features */ |
220 | #ifdef XENPV | | 220 | #ifdef XENPV |
221 | #define CPUID_FEAT_BLACKLIST (CPUID_PGE|CPUID_PSE|CPUID_MTRR) | | 221 | #define CPUID_FEAT_BLACKLIST (CPUID_PGE|CPUID_PSE|CPUID_MTRR) |
222 | #else | | 222 | #else |
223 | #define CPUID_FEAT_BLACKLIST 0 | | 223 | #define CPUID_FEAT_BLACKLIST 0 |
224 | #endif | | 224 | #endif |
225 | | | 225 | |
226 | /* %ecx */ | | 226 | /* %ecx */ |
227 | #define CPUID2_SSE3 __BIT(0) /* Streaming SIMD Extensions 3 */ | | 227 | #define CPUID2_SSE3 __BIT(0) /* Streaming SIMD Extensions 3 */ |
228 | #define CPUID2_PCLMULQDQ __BIT(1) /* PCLMULQDQ instructions */ | | 228 | #define CPUID2_PCLMULQDQ __BIT(1) /* PCLMULQDQ instructions */ |
229 | #define CPUID2_DTES64 __BIT(2) /* 64-bit Debug Trace */ | | 229 | #define CPUID2_DTES64 __BIT(2) /* 64-bit Debug Trace */ |
230 | #define CPUID2_MONITOR __BIT(3) /* MONITOR/MWAIT instructions */ | | 230 | #define CPUID2_MONITOR __BIT(3) /* MONITOR/MWAIT instructions */ |
231 | #define CPUID2_DS_CPL __BIT(4) /* CPL Qualified Debug Store */ | | 231 | #define CPUID2_DS_CPL __BIT(4) /* CPL Qualified Debug Store */ |
232 | #define CPUID2_VMX __BIT(5) /* Virtual Machine eXtensions */ | | 232 | #define CPUID2_VMX __BIT(5) /* Virtual Machine eXtensions */ |
233 | #define CPUID2_SMX __BIT(6) /* Safer Mode eXtensions */ | | 233 | #define CPUID2_SMX __BIT(6) /* Safer Mode eXtensions */ |
234 | #define CPUID2_EST __BIT(7) /* Enhanced SpeedStep Technology */ | | 234 | #define CPUID2_EST __BIT(7) /* Enhanced SpeedStep Technology */ |
235 | #define CPUID2_TM2 __BIT(8) /* Thermal Monitor 2 */ | | 235 | #define CPUID2_TM2 __BIT(8) /* Thermal Monitor 2 */ |
236 | #define CPUID2_SSSE3 __BIT(9) /* Supplemental SSE3 */ | | 236 | #define CPUID2_SSSE3 __BIT(9) /* Supplemental SSE3 */ |
237 | #define CPUID2_CNXTID __BIT(10) /* Context ID */ | | 237 | #define CPUID2_CNXTID __BIT(10) /* Context ID */ |
238 | #define CPUID2_SDBG __BIT(11) /* Silicon Debug */ | | 238 | #define CPUID2_SDBG __BIT(11) /* Silicon Debug */ |
239 | #define CPUID2_FMA __BIT(12) /* Fused Multiply Add */ | | 239 | #define CPUID2_FMA __BIT(12) /* Fused Multiply Add */ |
240 | #define CPUID2_CX16 __BIT(13) /* CMPXCHG16B instruction */ | | 240 | #define CPUID2_CX16 __BIT(13) /* CMPXCHG16B instruction */ |
241 | #define CPUID2_XTPR __BIT(14) /* Task Priority Messages disabled? */ | | 241 | #define CPUID2_XTPR __BIT(14) /* Task Priority Messages disabled? */ |
242 | #define CPUID2_PDCM __BIT(15) /* Perf/Debug Capability MSR */ | | 242 | #define CPUID2_PDCM __BIT(15) /* Perf/Debug Capability MSR */ |
243 | /* bit 16 unused __BIT(16) */ | | 243 | /* bit 16 unused __BIT(16) */ |
244 | #define CPUID2_PCID __BIT(17) /* Process Context ID */ | | 244 | #define CPUID2_PCID __BIT(17) /* Process Context ID */ |
245 | #define CPUID2_DCA __BIT(18) /* Direct Cache Access */ | | 245 | #define CPUID2_DCA __BIT(18) /* Direct Cache Access */ |
246 | #define CPUID2_SSE41 __BIT(19) /* Streaming SIMD Extensions 4.1 */ | | 246 | #define CPUID2_SSE41 __BIT(19) /* Streaming SIMD Extensions 4.1 */ |
247 | #define CPUID2_SSE42 __BIT(20) /* Streaming SIMD Extensions 4.2 */ | | 247 | #define CPUID2_SSE42 __BIT(20) /* Streaming SIMD Extensions 4.2 */ |
248 | #define CPUID2_X2APIC __BIT(21) /* xAPIC Extensions */ | | 248 | #define CPUID2_X2APIC __BIT(21) /* xAPIC Extensions */ |
249 | #define CPUID2_MOVBE __BIT(22) /* MOVBE (move after byteswap) */ | | 249 | #define CPUID2_MOVBE __BIT(22) /* MOVBE (move after byteswap) */ |
250 | #define CPUID2_POPCNT __BIT(23) /* POPCNT instruction available */ | | 250 | #define CPUID2_POPCNT __BIT(23) /* POPCNT instruction available */ |
251 | #define CPUID2_DEADLINE __BIT(24) /* APIC Timer supports TSC Deadline */ | | 251 | #define CPUID2_DEADLINE __BIT(24) /* APIC Timer supports TSC Deadline */ |
252 | #define CPUID2_AESNI __BIT(25) /* AES instructions */ | | 252 | #define CPUID2_AESNI __BIT(25) /* AES instructions */ |
253 | #define CPUID2_XSAVE __BIT(26) /* XSAVE instructions */ | | 253 | #define CPUID2_XSAVE __BIT(26) /* XSAVE instructions */ |
254 | #define CPUID2_OSXSAVE __BIT(27) /* XGETBV/XSETBV instructions */ | | 254 | #define CPUID2_OSXSAVE __BIT(27) /* XGETBV/XSETBV instructions */ |
255 | #define CPUID2_AVX __BIT(28) /* AVX instructions */ | | 255 | #define CPUID2_AVX __BIT(28) /* AVX instructions */ |
256 | #define CPUID2_F16C __BIT(29) /* half precision conversion */ | | 256 | #define CPUID2_F16C __BIT(29) /* half precision conversion */ |
257 | #define CPUID2_RDRAND __BIT(30) /* RDRAND (hardware random number) */ | | 257 | #define CPUID2_RDRAND __BIT(30) /* RDRAND (hardware random number) */ |
258 | #define CPUID2_RAZ __BIT(31) /* RAZ. Indicates guest state. */ | | 258 | #define CPUID2_RAZ __BIT(31) /* RAZ. Indicates guest state. */ |
259 | | | 259 | |
260 | #define CPUID2_FLAGS1 "\20" \ | | 260 | #define CPUID2_FLAGS1 "\20" \ |
261 | "\1" "SSE3" "\2" "PCLMULQDQ" "\3" "DTES64" "\4" "MONITOR" \ | | 261 | "\1" "SSE3" "\2" "PCLMULQDQ" "\3" "DTES64" "\4" "MONITOR" \ |
262 | "\5" "DS-CPL" "\6" "VMX" "\7" "SMX" "\10" "EST" \ | | 262 | "\5" "DS-CPL" "\6" "VMX" "\7" "SMX" "\10" "EST" \ |
263 | "\11" "TM2" "\12" "SSSE3" "\13" "CID" "\14" "SDBG" \ | | 263 | "\11" "TM2" "\12" "SSSE3" "\13" "CID" "\14" "SDBG" \ |
264 | "\15" "FMA" "\16" "CX16" "\17" "xTPR" "\20" "PDCM" \ | | 264 | "\15" "FMA" "\16" "CX16" "\17" "xTPR" "\20" "PDCM" \ |
265 | "\21" "B16" "\22" "PCID" "\23" "DCA" "\24" "SSE41" \ | | 265 | "\21" "B16" "\22" "PCID" "\23" "DCA" "\24" "SSE41" \ |
266 | "\25" "SSE42" "\26" "X2APIC" "\27" "MOVBE" "\30" "POPCNT" \ | | 266 | "\25" "SSE42" "\26" "X2APIC" "\27" "MOVBE" "\30" "POPCNT" \ |
267 | "\31" "DEADLINE" "\32" "AES" "\33" "XSAVE" "\34" "OSXSAVE" \ | | 267 | "\31" "DEADLINE" "\32" "AES" "\33" "XSAVE" "\34" "OSXSAVE" \ |
268 | "\35" "AVX" "\36" "F16C" "\37" "RDRAND" "\40" "RAZ" | | 268 | "\35" "AVX" "\36" "F16C" "\37" "RDRAND" "\40" "RAZ" |
269 | | | 269 | |
270 | /* %eax */ | | 270 | /* %eax */ |
271 | #define CPUID_TO_BASEFAMILY(cpuid) (((cpuid) >> 8) & 0xf) | | 271 | #define CPUID_TO_BASEFAMILY(cpuid) (((cpuid) >> 8) & 0xf) |
272 | #define CPUID_TO_BASEMODEL(cpuid) (((cpuid) >> 4) & 0xf) | | 272 | #define CPUID_TO_BASEMODEL(cpuid) (((cpuid) >> 4) & 0xf) |
273 | #define CPUID_TO_STEPPING(cpuid) ((cpuid) & 0xf) | | 273 | #define CPUID_TO_STEPPING(cpuid) ((cpuid) & 0xf) |
274 | | | 274 | |
275 | /* | | 275 | /* |
276 | * The Extended family bits should only be inspected when CPUID_TO_BASEFAMILY() | | 276 | * The Extended family bits should only be inspected when CPUID_TO_BASEFAMILY() |
277 | * returns 15. They are use to encode family value 16 to 270 (add 15). | | 277 | * returns 15. They are use to encode family value 16 to 270 (add 15). |
278 | * The Extended model bits are the high 4 bits of the model. | | 278 | * The Extended model bits are the high 4 bits of the model. |
279 | * They are only valid for family >= 15 or family 6 (intel, but all amd | | 279 | * They are only valid for family >= 15 or family 6 (intel, but all amd |
280 | * family 6 are documented to return zero bits for them). | | 280 | * family 6 are documented to return zero bits for them). |
281 | */ | | 281 | */ |
282 | #define CPUID_TO_EXTFAMILY(cpuid) (((cpuid) >> 20) & 0xff) | | 282 | #define CPUID_TO_EXTFAMILY(cpuid) (((cpuid) >> 20) & 0xff) |
283 | #define CPUID_TO_EXTMODEL(cpuid) (((cpuid) >> 16) & 0xf) | | 283 | #define CPUID_TO_EXTMODEL(cpuid) (((cpuid) >> 16) & 0xf) |
284 | | | 284 | |
285 | /* The macros for the Display Family and the Display Model */ | | 285 | /* The macros for the Display Family and the Display Model */ |
286 | #define CPUID_TO_FAMILY(cpuid) (CPUID_TO_BASEFAMILY(cpuid) \ | | 286 | #define CPUID_TO_FAMILY(cpuid) (CPUID_TO_BASEFAMILY(cpuid) \ |
287 | + ((CPUID_TO_BASEFAMILY(cpuid) != 0x0f) \ | | 287 | + ((CPUID_TO_BASEFAMILY(cpuid) != 0x0f) \ |
288 | ? 0 : CPUID_TO_EXTFAMILY(cpuid))) | | 288 | ? 0 : CPUID_TO_EXTFAMILY(cpuid))) |
289 | #define CPUID_TO_MODEL(cpuid) (CPUID_TO_BASEMODEL(cpuid) \ | | 289 | #define CPUID_TO_MODEL(cpuid) (CPUID_TO_BASEMODEL(cpuid) \ |
290 | | ((CPUID_TO_BASEFAMILY(cpuid) != 0x0f) \ | | 290 | | ((CPUID_TO_BASEFAMILY(cpuid) != 0x0f) \ |
291 | && (CPUID_TO_BASEFAMILY(cpuid) != 0x06) \ | | 291 | && (CPUID_TO_BASEFAMILY(cpuid) != 0x06) \ |
292 | ? 0 : (CPUID_TO_EXTMODEL(cpuid) << 4))) | | 292 | ? 0 : (CPUID_TO_EXTMODEL(cpuid) << 4))) |
293 | | | 293 | |
294 | /* %ebx */ | | 294 | /* %ebx */ |
295 | #define CPUID_BRAND_INDEX __BITS(7,0) | | 295 | #define CPUID_BRAND_INDEX __BITS(7,0) |
296 | #define CPUID_CLFLUSH_SIZE __BITS(15,8) | | 296 | #define CPUID_CLFLUSH_SIZE __BITS(15,8) |
297 | #define CPUID_HTT_CORES __BITS(23,16) | | 297 | #define CPUID_HTT_CORES __BITS(23,16) |
298 | #define CPUID_LOCAL_APIC_ID __BITS(31,24) | | 298 | #define CPUID_LOCAL_APIC_ID __BITS(31,24) |
299 | | | 299 | |
300 | /* | | 300 | /* |
301 | * Intel Deterministic Cache Parameter. | | 301 | * Intel Deterministic Cache Parameter. |
302 | * CPUID Fn0000_0004 | | 302 | * CPUID Fn0000_0004 |
303 | */ | | 303 | */ |
304 | | | 304 | |
305 | /* %eax */ | | 305 | /* %eax */ |
306 | #define CPUID_DCP_CACHETYPE __BITS(4, 0) /* Cache type */ | | 306 | #define CPUID_DCP_CACHETYPE __BITS(4, 0) /* Cache type */ |
307 | #define CPUID_DCP_CACHETYPE_N 0 /* NULL */ | | 307 | #define CPUID_DCP_CACHETYPE_N 0 /* NULL */ |
308 | #define CPUID_DCP_CACHETYPE_D 1 /* Data cache */ | | 308 | #define CPUID_DCP_CACHETYPE_D 1 /* Data cache */ |
309 | #define CPUID_DCP_CACHETYPE_I 2 /* Instruction cache */ | | 309 | #define CPUID_DCP_CACHETYPE_I 2 /* Instruction cache */ |
310 | #define CPUID_DCP_CACHETYPE_U 3 /* Unified cache */ | | 310 | #define CPUID_DCP_CACHETYPE_U 3 /* Unified cache */ |
311 | #define CPUID_DCP_CACHELEVEL __BITS(7, 5) /* Cache level (start at 1) */ | | 311 | #define CPUID_DCP_CACHELEVEL __BITS(7, 5) /* Cache level (start at 1) */ |
312 | #define CPUID_DCP_SELFINITCL __BIT(8) /* Self initializing cachelvl*/ | | 312 | #define CPUID_DCP_SELFINITCL __BIT(8) /* Self initializing cachelvl*/ |
313 | #define CPUID_DCP_FULLASSOC __BIT(9) /* Full associative */ | | 313 | #define CPUID_DCP_FULLASSOC __BIT(9) /* Full associative */ |
314 | #define CPUID_DCP_SHARING __BITS(25, 14) /* sharing */ | | 314 | #define CPUID_DCP_SHARING __BITS(25, 14) /* sharing */ |
315 | #define CPUID_DCP_CORE_P_PKG __BITS(31, 26) /* Cores/package */ | | 315 | #define CPUID_DCP_CORE_P_PKG __BITS(31, 26) /* Cores/package */ |
316 | | | 316 | |
317 | /* %ebx */ | | 317 | /* %ebx */ |
318 | #define CPUID_DCP_LINESIZE __BITS(11, 0) /* System coherency linesize */ | | 318 | #define CPUID_DCP_LINESIZE __BITS(11, 0) /* System coherency linesize */ |
319 | #define CPUID_DCP_PARTITIONS __BITS(21, 12) /* Physical line partitions */ | | 319 | #define CPUID_DCP_PARTITIONS __BITS(21, 12) /* Physical line partitions */ |
320 | #define CPUID_DCP_WAYS __BITS(31, 22) /* Ways of associativity */ | | 320 | #define CPUID_DCP_WAYS __BITS(31, 22) /* Ways of associativity */ |
321 | | | 321 | |
322 | /* %ecx: Number of sets */ | | 322 | /* %ecx: Number of sets */ |
323 | | | 323 | |
324 | /* %edx */ | | 324 | /* %edx */ |
325 | #define CPUID_DCP_INVALIDATE __BIT(0) /* WB invalidate/invalidate */ | | 325 | #define CPUID_DCP_INVALIDATE __BIT(0) /* WB invalidate/invalidate */ |
326 | #define CPUID_DCP_INCLUSIVE __BIT(1) /* Cache inclusiveness */ | | 326 | #define CPUID_DCP_INCLUSIVE __BIT(1) /* Cache inclusiveness */ |
327 | #define CPUID_DCP_COMPLEX __BIT(2) /* Complex cache indexing */ | | 327 | #define CPUID_DCP_COMPLEX __BIT(2) /* Complex cache indexing */ |
328 | | | 328 | |
329 | /* | | 329 | /* |
330 | * Intel/AMD MONITOR/MWAIT. | | 330 | * Intel/AMD MONITOR/MWAIT. |
331 | * CPUID Fn0000_0005 | | 331 | * CPUID Fn0000_0005 |
332 | */ | | 332 | */ |
333 | /* %eax */ | | 333 | /* %eax */ |
334 | #define CPUID_MON_MINSIZE __BITS(15, 0) /* Smallest monitor-line size */ | | 334 | #define CPUID_MON_MINSIZE __BITS(15, 0) /* Smallest monitor-line size */ |
335 | /* %ebx */ | | 335 | /* %ebx */ |
336 | #define CPUID_MON_MAXSIZE __BITS(15, 0) /* Largest monitor-line size */ | | 336 | #define CPUID_MON_MAXSIZE __BITS(15, 0) /* Largest monitor-line size */ |
337 | /* %ecx */ | | 337 | /* %ecx */ |
338 | #define CPUID_MON_EMX __BIT(0) /* MONITOR/MWAIT Extensions */ | | 338 | #define CPUID_MON_EMX __BIT(0) /* MONITOR/MWAIT Extensions */ |
339 | #define CPUID_MON_IBE __BIT(1) /* Interrupt as Break Event */ | | 339 | #define CPUID_MON_IBE __BIT(1) /* Interrupt as Break Event */ |
340 | | | 340 | |
341 | #define CPUID_MON_FLAGS "\20" \ | | 341 | #define CPUID_MON_FLAGS "\20" \ |
342 | "\1" "EMX" "\2" "IBE" | | 342 | "\1" "EMX" "\2" "IBE" |
343 | | | 343 | |
344 | /* %edx: number of substates for specific C-state */ | | 344 | /* %edx: number of substates for specific C-state */ |
345 | #define CPUID_MON_SUBSTATE(edx, cstate) (((edx) >> (cstate * 4)) & 0x0000000f) | | 345 | #define CPUID_MON_SUBSTATE(edx, cstate) (((edx) >> (cstate * 4)) & 0x0000000f) |
346 | | | 346 | |
347 | /* | | 347 | /* |
348 | * Intel/AMD Digital Thermal Sensor and Power Management. | | 348 | * Intel/AMD Digital Thermal Sensor and Power Management. |
349 | * CPUID Fn0000_0006 | | 349 | * CPUID Fn0000_0006 |
350 | */ | | 350 | */ |
351 | /* %eax */ | | 351 | /* %eax */ |
352 | #define CPUID_DSPM_DTS __BIT(0) /* Digital Thermal Sensor */ | | 352 | #define CPUID_DSPM_DTS __BIT(0) /* Digital Thermal Sensor */ |
353 | #define CPUID_DSPM_IDA __BIT(1) /* Intel Dynamic Acceleration */ | | 353 | #define CPUID_DSPM_IDA __BIT(1) /* Intel Dynamic Acceleration */ |
354 | #define CPUID_DSPM_ARAT __BIT(2) /* Always Running APIC Timer */ | | 354 | #define CPUID_DSPM_ARAT __BIT(2) /* Always Running APIC Timer */ |
355 | #define CPUID_DSPM_PLN __BIT(4) /* Power Limit Notification */ | | 355 | #define CPUID_DSPM_PLN __BIT(4) /* Power Limit Notification */ |
356 | #define CPUID_DSPM_ECMD __BIT(5) /* Clock Modulation Extension */ | | 356 | #define CPUID_DSPM_ECMD __BIT(5) /* Clock Modulation Extension */ |
357 | #define CPUID_DSPM_PTM __BIT(6) /* Package Level Thermal Management */ | | 357 | #define CPUID_DSPM_PTM __BIT(6) /* Package Level Thermal Management */ |
358 | #define CPUID_DSPM_HWP __BIT(7) /* HWP */ | | 358 | #define CPUID_DSPM_HWP __BIT(7) /* HWP */ |
359 | #define CPUID_DSPM_HWP_NOTIFY __BIT(8) /* HWP Notification */ | | 359 | #define CPUID_DSPM_HWP_NOTIFY __BIT(8) /* HWP Notification */ |
360 | #define CPUID_DSPM_HWP_ACTWIN __BIT(9) /* HWP Activity Window */ | | 360 | #define CPUID_DSPM_HWP_ACTWIN __BIT(9) /* HWP Activity Window */ |
361 | #define CPUID_DSPM_HWP_EPP __BIT(10) /* HWP Energy Performance Preference */ | | 361 | #define CPUID_DSPM_HWP_EPP __BIT(10) /* HWP Energy Performance Preference */ |
362 | #define CPUID_DSPM_HWP_PLR __BIT(11) /* HWP Package Level Request */ | | 362 | #define CPUID_DSPM_HWP_PLR __BIT(11) /* HWP Package Level Request */ |
363 | #define CPUID_DSPM_HDC __BIT(13) /* Hardware Duty Cycling */ | | 363 | #define CPUID_DSPM_HDC __BIT(13) /* Hardware Duty Cycling */ |
364 | #define CPUID_DSPM_TBMT3 __BIT(14) /* Turbo Boost Max Technology 3.0 */ | | 364 | #define CPUID_DSPM_TBMT3 __BIT(14) /* Turbo Boost Max Technology 3.0 */ |
365 | #define CPUID_DSPM_HWP_CAP __BIT(15) /* HWP Capabilities */ | | 365 | #define CPUID_DSPM_HWP_CAP __BIT(15) /* HWP Capabilities */ |
366 | #define CPUID_DSPM_HWP_PECI __BIT(16) /* HWP PECI override */ | | 366 | #define CPUID_DSPM_HWP_PECI __BIT(16) /* HWP PECI override */ |
367 | #define CPUID_DSPM_HWP_FLEX __BIT(17) /* Flexible HWP */ | | 367 | #define CPUID_DSPM_HWP_FLEX __BIT(17) /* Flexible HWP */ |
368 | #define CPUID_DSPM_HWP_FAST __BIT(18) /* Fast access for IA32_HWP_REQUEST */ | | 368 | #define CPUID_DSPM_HWP_FAST __BIT(18) /* Fast access for IA32_HWP_REQUEST */ |
369 | #define CPUID_DSPM_HFI __BIT(19) /* Hardware Feedback Interface */ | | 369 | #define CPUID_DSPM_HFI __BIT(19) /* Hardware Feedback Interface */ |
370 | #define CPUID_DSPM_HWP_IGNIDL __BIT(20) /* Ignore Idle Logical Processor HWP */ | | 370 | #define CPUID_DSPM_HWP_IGNIDL __BIT(20) /* Ignore Idle Logical Processor HWP */ |
371 | #define CPUID_DSPM_TD __BIT(23) /* Thread Director */ | | 371 | #define CPUID_DSPM_TD __BIT(23) /* Thread Director */ |
372 | #define CPUID_DSPM_THERMI_HFN __BIT(24) /* THERM_INTERRUPT MSR HFN bit */ | | 372 | #define CPUID_DSPM_THERMI_HFN __BIT(24) /* THERM_INTERRUPT MSR HFN bit */ |
373 | | | 373 | |
374 | #define CPUID_DSPM_FLAGS "\20" \ | | 374 | #define CPUID_DSPM_FLAGS "\20" \ |
375 | "\1" "DTS" "\2" "IDA" "\3" "ARAT" \ | | 375 | "\1" "DTS" "\2" "IDA" "\3" "ARAT" \ |
376 | "\5" "PLN" "\6" "ECMD" "\7" "PTM" "\10" "HWP" \ | | 376 | "\5" "PLN" "\6" "ECMD" "\7" "PTM" "\10" "HWP" \ |
377 | "\11" "HWP_NOTIFY" "\12" "HWP_ACTWIN" "\13" "HWP_EPP" "\14" "HWP_PLR" \ | | 377 | "\11" "HWP_NOTIFY" "\12" "HWP_ACTWIN" "\13" "HWP_EPP" "\14" "HWP_PLR" \ |
378 | "\16" "HDC" "\17" "TBM3" "\20" "HWP_CAP" \ | | 378 | "\16" "HDC" "\17" "TBM3" "\20" "HWP_CAP" \ |
379 | "\21" "HWP_PECI" "\22" "HWP_FLEX" "\23" "HWP_FAST" "\24HFI" \ | | 379 | "\21" "HWP_PECI" "\22" "HWP_FLEX" "\23" "HWP_FAST" "\24HFI" \ |
380 | "\25" "HWP_IGNIDL" "\30" "TD" \ | | 380 | "\25" "HWP_IGNIDL" "\30" "TD" \ |
381 | "\31" "THERMI_HFN" | | 381 | "\31" "THERMI_HFN" |
382 | | | 382 | |
383 | /* %ecx */ | | 383 | /* %ecx */ |
384 | #define CPUID_DSPM_HWF __BIT(0) /* MSR_APERF/MSR_MPERF available */ | | 384 | #define CPUID_DSPM_HWF __BIT(0) /* MSR_APERF/MSR_MPERF available */ |
385 | #define CPUID_DSPM_EPB __BIT(3) /* Energy Performance Bias */ | | 385 | #define CPUID_DSPM_EPB __BIT(3) /* Energy Performance Bias */ |
386 | #define CPUID_DSPM_NTDC __BITS(15, 8) /* Number of Thread Director Classes */ | | 386 | #define CPUID_DSPM_NTDC __BITS(15, 8) /* Number of Thread Director Classes */ |
387 | | | 387 | |
388 | #define CPUID_DSPM_FLAGS1 "\177\20" \ | | 388 | #define CPUID_DSPM_FLAGS1 "\177\20" \ |
389 | "b\0HWF\0" "b\3EPB\0" \ | | 389 | "b\0HWF\0" "b\3EPB\0" \ |
390 | "f\10\10NTDC\0" | | 390 | "f\10\10NTDC\0" |
391 | | | 391 | |
392 | /* | | 392 | /* |
393 | * Intel/AMD Structured Extended Feature. | | 393 | * Intel/AMD Structured Extended Feature. |
394 | * CPUID Fn0000_0007 | | 394 | * CPUID Fn0000_0007 |
395 | * %ecx == 0: Subleaf 0 | | 395 | * %ecx == 0: Subleaf 0 |
396 | * %eax: The Maximum input value for supported subleaf. | | 396 | * %eax: The Maximum input value for supported subleaf. |
397 | * %ebx: Feature bits. | | 397 | * %ebx: Feature bits. |
398 | * %ecx: Feature bits. | | 398 | * %ecx: Feature bits. |
399 | * %edx: Feature bits. | | 399 | * %edx: Feature bits. |
400 | * | | 400 | * |
401 | * %ecx == 1: Structure Extendede Feature Enumeration Sub-leaf | | 401 | * %ecx == 1: Structure Extendede Feature Enumeration Sub-leaf |
402 | * %eax: See below. | | 402 | * %eax: See below. |
403 | */ | | 403 | */ |
404 | | | 404 | |
405 | /* %ecx = 0, %ebx */ | | 405 | /* %ecx = 0, %ebx */ |
406 | #define CPUID_SEF_FSGSBASE __BIT(0) /* {RD,WR}{FS,GS}BASE */ | | 406 | #define CPUID_SEF_FSGSBASE __BIT(0) /* {RD,WR}{FS,GS}BASE */ |
407 | #define CPUID_SEF_TSC_ADJUST __BIT(1) /* IA32_TSC_ADJUST MSR support */ | | 407 | #define CPUID_SEF_TSC_ADJUST __BIT(1) /* IA32_TSC_ADJUST MSR support */ |
408 | #define CPUID_SEF_SGX __BIT(2) /* Software Guard Extensions */ | | 408 | #define CPUID_SEF_SGX __BIT(2) /* Software Guard Extensions */ |
409 | #define CPUID_SEF_BMI1 __BIT(3) /* Advanced bit manipulation ext. 1st grp */ | | 409 | #define CPUID_SEF_BMI1 __BIT(3) /* Advanced bit manipulation ext. 1st grp */ |
410 | #define CPUID_SEF_HLE __BIT(4) /* Hardware Lock Elision */ | | 410 | #define CPUID_SEF_HLE __BIT(4) /* Hardware Lock Elision */ |
411 | #define CPUID_SEF_AVX2 __BIT(5) /* Advanced Vector Extensions 2 */ | | 411 | #define CPUID_SEF_AVX2 __BIT(5) /* Advanced Vector Extensions 2 */ |
412 | #define CPUID_SEF_FDPEXONLY __BIT(6) /* x87FPU Data ptr updated only on x87exp */ | | 412 | #define CPUID_SEF_FDPEXONLY __BIT(6) /* x87FPU Data ptr updated only on x87exp */ |
413 | #define CPUID_SEF_SMEP __BIT(7) /* Supervisor-Mode Execution Prevention */ | | 413 | #define CPUID_SEF_SMEP __BIT(7) /* Supervisor-Mode Execution Prevention */ |
414 | #define CPUID_SEF_BMI2 __BIT(8) /* Advanced bit manipulation ext. 2nd grp */ | | 414 | #define CPUID_SEF_BMI2 __BIT(8) /* Advanced bit manipulation ext. 2nd grp */ |
415 | #define CPUID_SEF_ERMS __BIT(9) /* Enhanced REP MOVSB/STOSB */ | | 415 | #define CPUID_SEF_ERMS __BIT(9) /* Enhanced REP MOVSB/STOSB */ |
416 | #define CPUID_SEF_INVPCID __BIT(10) /* INVPCID instruction */ | | 416 | #define CPUID_SEF_INVPCID __BIT(10) /* INVPCID instruction */ |
417 | #define CPUID_SEF_RTM __BIT(11) /* Restricted Transactional Memory */ | | 417 | #define CPUID_SEF_RTM __BIT(11) /* Restricted Transactional Memory */ |
418 | #define CPUID_SEF_QM __BIT(12) /* Resource Director Technology Monitoring */ | | 418 | #define CPUID_SEF_QM __BIT(12) /* Resource Director Technology Monitoring */ |
419 | #define CPUID_SEF_FPUCSDS __BIT(13) /* Deprecate FPU CS and FPU DS values */ | | 419 | #define CPUID_SEF_FPUCSDS __BIT(13) /* Deprecate FPU CS and FPU DS values */ |
420 | #define CPUID_SEF_MPX __BIT(14) /* Memory Protection Extensions */ | | 420 | #define CPUID_SEF_MPX __BIT(14) /* Memory Protection Extensions */ |
421 | #define CPUID_SEF_PQE __BIT(15) /* Resource Director Technology Allocation */ | | 421 | #define CPUID_SEF_PQE __BIT(15) /* Resource Director Technology Allocation */ |
422 | #define CPUID_SEF_AVX512F __BIT(16) /* AVX-512 Foundation */ | | 422 | #define CPUID_SEF_AVX512F __BIT(16) /* AVX-512 Foundation */ |
423 | #define CPUID_SEF_AVX512DQ __BIT(17) /* AVX-512 Double/Quadword */ | | 423 | #define CPUID_SEF_AVX512DQ __BIT(17) /* AVX-512 Double/Quadword */ |
424 | #define CPUID_SEF_RDSEED __BIT(18) /* RDSEED instruction */ | | 424 | #define CPUID_SEF_RDSEED __BIT(18) /* RDSEED instruction */ |
425 | #define CPUID_SEF_ADX __BIT(19) /* ADCX/ADOX instructions */ | | 425 | #define CPUID_SEF_ADX __BIT(19) /* ADCX/ADOX instructions */ |
426 | #define CPUID_SEF_SMAP __BIT(20) /* Supervisor-Mode Access Prevention */ | | 426 | #define CPUID_SEF_SMAP __BIT(20) /* Supervisor-Mode Access Prevention */ |
427 | #define CPUID_SEF_AVX512_IFMA __BIT(21) /* AVX-512 Integer Fused Multiply Add */ | | 427 | #define CPUID_SEF_AVX512_IFMA __BIT(21) /* AVX-512 Integer Fused Multiply Add */ |
428 | /* Bit 22 was PCOMMIT */ | | 428 | /* Bit 22 was PCOMMIT */ |
429 | #define CPUID_SEF_CLFLUSHOPT __BIT(23) /* Cache Line FLUSH OPTimized */ | | 429 | #define CPUID_SEF_CLFLUSHOPT __BIT(23) /* Cache Line FLUSH OPTimized */ |
430 | #define CPUID_SEF_CLWB __BIT(24) /* Cache Line Write Back */ | | 430 | #define CPUID_SEF_CLWB __BIT(24) /* Cache Line Write Back */ |
431 | #define CPUID_SEF_PT __BIT(25) /* Processor Trace */ | | 431 | #define CPUID_SEF_PT __BIT(25) /* Processor Trace */ |
432 | #define CPUID_SEF_AVX512PF __BIT(26) /* AVX-512 PreFetch */ | | 432 | #define CPUID_SEF_AVX512PF __BIT(26) /* AVX-512 PreFetch */ |
433 | #define CPUID_SEF_AVX512ER __BIT(27) /* AVX-512 Exponential and Reciprocal */ | | 433 | #define CPUID_SEF_AVX512ER __BIT(27) /* AVX-512 Exponential and Reciprocal */ |
434 | #define CPUID_SEF_AVX512CD __BIT(28) /* AVX-512 Conflict Detection */ | | 434 | #define CPUID_SEF_AVX512CD __BIT(28) /* AVX-512 Conflict Detection */ |
435 | #define CPUID_SEF_SHA __BIT(29) /* SHA Extensions */ | | 435 | #define CPUID_SEF_SHA __BIT(29) /* SHA Extensions */ |
436 | #define CPUID_SEF_AVX512BW __BIT(30) /* AVX-512 Byte and Word */ | | 436 | #define CPUID_SEF_AVX512BW __BIT(30) /* AVX-512 Byte and Word */ |
437 | #define CPUID_SEF_AVX512VL __BIT(31) /* AVX-512 Vector Length */ | | 437 | #define CPUID_SEF_AVX512VL __BIT(31) /* AVX-512 Vector Length */ |
438 | | | 438 | |
439 | #define CPUID_SEF_FLAGS "\20" \ | | 439 | #define CPUID_SEF_FLAGS "\20" \ |
440 | "\1" "FSGSBASE" "\2" "TSCADJUST" "\3" "SGX" "\4" "BMI1" \ | | 440 | "\1" "FSGSBASE" "\2" "TSCADJUST" "\3" "SGX" "\4" "BMI1" \ |
441 | "\5" "HLE" "\6" "AVX2" "\7" "FDPEXONLY" "\10" "SMEP" \ | | 441 | "\5" "HLE" "\6" "AVX2" "\7" "FDPEXONLY" "\10" "SMEP" \ |
442 | "\11" "BMI2" "\12" "ERMS" "\13" "INVPCID" "\14" "RTM" \ | | 442 | "\11" "BMI2" "\12" "ERMS" "\13" "INVPCID" "\14" "RTM" \ |
443 | "\15" "QM" "\16" "FPUCSDS" "\17" "MPX" "\20" "PQE" \ | | 443 | "\15" "QM" "\16" "FPUCSDS" "\17" "MPX" "\20" "PQE" \ |
444 | "\21" "AVX512F" "\22" "AVX512DQ" "\23" "RDSEED" "\24" "ADX" \ | | 444 | "\21" "AVX512F" "\22" "AVX512DQ" "\23" "RDSEED" "\24" "ADX" \ |
445 | "\25" "SMAP" "\26" "AVX512_IFMA" "\30" "CLFLUSHOPT" \ | | 445 | "\25" "SMAP" "\26" "AVX512_IFMA" "\30" "CLFLUSHOPT" \ |
446 | "\31" "CLWB" "\32" "PT" "\33" "AVX512PF" "\34" "AVX512ER" \ | | 446 | "\31" "CLWB" "\32" "PT" "\33" "AVX512PF" "\34" "AVX512ER" \ |
447 | "\35" "AVX512CD""\36" "SHA" "\37" "AVX512BW" "\40" "AVX512VL" | | 447 | "\35" "AVX512CD""\36" "SHA" "\37" "AVX512BW" "\40" "AVX512VL" |
448 | | | 448 | |
449 | /* %ecx = 0, %ecx */ | | 449 | /* %ecx = 0, %ecx */ |
450 | #define CPUID_SEF_PREFETCHWT1 __BIT(0) /* PREFETCHWT1 instruction */ | | 450 | #define CPUID_SEF_PREFETCHWT1 __BIT(0) /* PREFETCHWT1 instruction */ |
451 | #define CPUID_SEF_AVX512_VBMI __BIT(1) /* AVX-512 Vector Byte Manipulation */ | | 451 | #define CPUID_SEF_AVX512_VBMI __BIT(1) /* AVX-512 Vector Byte Manipulation */ |
452 | #define CPUID_SEF_UMIP __BIT(2) /* User-Mode Instruction prevention */ | | 452 | #define CPUID_SEF_UMIP __BIT(2) /* User-Mode Instruction prevention */ |
453 | #define CPUID_SEF_PKU __BIT(3) /* Protection Keys for User-mode pages */ | | 453 | #define CPUID_SEF_PKU __BIT(3) /* Protection Keys for User-mode pages */ |
454 | #define CPUID_SEF_OSPKE __BIT(4) /* OS has set CR4.PKE to ena. protec. keys */ | | 454 | #define CPUID_SEF_OSPKE __BIT(4) /* OS has set CR4.PKE to ena. protec. keys */ |
455 | #define CPUID_SEF_WAITPKG __BIT(5) /* TPAUSE,UMONITOR,UMWAIT */ | | 455 | #define CPUID_SEF_WAITPKG __BIT(5) /* TPAUSE,UMONITOR,UMWAIT */ |
456 | #define CPUID_SEF_AVX512_VBMI2 __BIT(6) /* AVX-512 Vector Byte Manipulation 2 */ | | 456 | #define CPUID_SEF_AVX512_VBMI2 __BIT(6) /* AVX-512 Vector Byte Manipulation 2 */ |
457 | #define CPUID_SEF_CET_SS __BIT(7) /* CET Shadow Stack */ | | 457 | #define CPUID_SEF_CET_SS __BIT(7) /* CET Shadow Stack */ |
458 | #define CPUID_SEF_GFNI __BIT(8) /* Galois Field instructions */ | | 458 | #define CPUID_SEF_GFNI __BIT(8) /* Galois Field instructions */ |
459 | #define CPUID_SEF_VAES __BIT(9) /* Vector AES instruction set */ | | 459 | #define CPUID_SEF_VAES __BIT(9) /* Vector AES instruction set */ |
460 | #define CPUID_SEF_VPCLMULQDQ __BIT(10) /* CLMUL instruction set */ | | 460 | #define CPUID_SEF_VPCLMULQDQ __BIT(10) /* CLMUL instruction set */ |
461 | #define CPUID_SEF_AVX512_VNNI __BIT(11) /* Vector Neural Network Instruction */ | | 461 | #define CPUID_SEF_AVX512_VNNI __BIT(11) /* Vector Neural Network Instruction */ |
462 | #define CPUID_SEF_AVX512_BITALG __BIT(12) /* BITALG instructions */ | | 462 | #define CPUID_SEF_AVX512_BITALG __BIT(12) /* BITALG instructions */ |
463 | #define CPUID_SEF_TME_EN __BIT(13) /* Total Memory Encryption */ | | 463 | #define CPUID_SEF_TME_EN __BIT(13) /* Total Memory Encryption */ |
464 | #define CPUID_SEF_AVX512_VPOPCNTDQ __BIT(14) /* Vector Population Count D/Q */ | | 464 | #define CPUID_SEF_AVX512_VPOPCNTDQ __BIT(14) /* Vector Population Count D/Q */ |
465 | #define CPUID_SEF_LA57 __BIT(16) /* 57bit linear addr & 5LVL paging */ | | 465 | #define CPUID_SEF_LA57 __BIT(16) /* 57bit linear addr & 5LVL paging */ |
466 | #define CPUID_SEF_MAWAU __BITS(21, 17) /* MAWAU for BND{LD,ST}X */ | | 466 | #define CPUID_SEF_MAWAU __BITS(21, 17) /* MAWAU for BND{LD,ST}X */ |
467 | #define CPUID_SEF_RDPID __BIT(22) /* RDPID and IA32_TSC_AUX */ | | 467 | #define CPUID_SEF_RDPID __BIT(22) /* RDPID and IA32_TSC_AUX */ |
468 | #define CPUID_SEF_KL __BIT(23) /* Key Locker */ | | 468 | #define CPUID_SEF_KL __BIT(23) /* Key Locker */ |
| | | 469 | #define CPUID_SEF_BUS_LOCK_DETECT __BIT(24) /* OS bus-lock detection */ |
469 | #define CPUID_SEF_CLDEMOTE __BIT(25) /* Cache line demote */ | | 470 | #define CPUID_SEF_CLDEMOTE __BIT(25) /* Cache line demote */ |
470 | #define CPUID_SEF_MOVDIRI __BIT(27) /* MOVDIRI instruction */ | | 471 | #define CPUID_SEF_MOVDIRI __BIT(27) /* MOVDIRI instruction */ |
471 | #define CPUID_SEF_MOVDIR64B __BIT(28) /* MOVDIR64B instruction */ | | 472 | #define CPUID_SEF_MOVDIR64B __BIT(28) /* MOVDIR64B instruction */ |
472 | #define CPUID_SEF_ENQCMD __BIT(29) /* Enqueue Stores */ | | 473 | #define CPUID_SEF_ENQCMD __BIT(29) /* Enqueue Stores */ |
473 | #define CPUID_SEF_SGXLC __BIT(30) /* SGX Launch Configuration */ | | 474 | #define CPUID_SEF_SGXLC __BIT(30) /* SGX Launch Configuration */ |
474 | #define CPUID_SEF_PKS __BIT(31) /* Protection Keys for kern-mode pages */ | | 475 | #define CPUID_SEF_PKS __BIT(31) /* Protection Keys for kern-mode pages */ |
475 | | | 476 | |
476 | #define CPUID_SEF_FLAGS1 "\177\20" \ | | 477 | #define CPUID_SEF_FLAGS1 "\177\20" \ |
477 | "b\0PREFETCHWT1\0" "b\1AVX512_VBMI\0" "b\2UMIP\0" "b\3PKU\0" \ | | 478 | "b\0PREFETCHWT1\0" "b\1AVX512_VBMI\0" "b\2UMIP\0" "b\3PKU\0" \ |
478 | "b\4OSPKE\0" "b\5WAITPKG\0" "b\6AVX512_VBMI2\0" "b\7CET_SS\0" \ | | 479 | "b\4OSPKE\0" "b\5WAITPKG\0" "b\6AVX512_VBMI2\0" "b\7CET_SS\0" \ |
479 | "b\10GFNI\0" "b\11VAES\0" "b\12VPCLMULQDQ\0" "b\13AVX512_VNNI\0"\ | | 480 | "b\10GFNI\0" "b\11VAES\0" "b\12VPCLMULQDQ\0" "b\13AVX512_VNNI\0"\ |
480 | "b\14AVX512_BITALG\0" "b\15TME_EN\0" "b\16AVX512_VPOPCNTDQ\0" \ | | 481 | "b\14AVX512_BITALG\0" "b\15TME_EN\0" "b\16AVX512_VPOPCNTDQ\0" \ |
481 | "b\20LA57\0" \ | | 482 | "b\20LA57\0" \ |
482 | "f\21\5MAWAU\0" "b\26RDPID\0" "b\27KL\0" \ | | 483 | "f\21\5MAWAU\0" "b\26RDPID\0" "b\27KL\0" \ |
483 | "b\31CLDEMOTE\0" "b\33MOVDIRI\0" \ | | 484 | "b\30\BUS_LOCK_DETECT" "b\31CLDEMOTE\0" "b\33MOVDIRI\0" \ |
484 | "b\34MOVDIR64B\0" "b\35ENQCMD\0" "b\36SGXLC\0" "b\37PKS\0" | | 485 | "b\34MOVDIR64B\0" "b\35ENQCMD\0" "b\36SGXLC\0" "b\37PKS\0" |
485 | | | 486 | |
486 | /* %ecx = 0, %edx */ | | 487 | /* %ecx = 0, %edx */ |
487 | #define CPUID_SEF_SGX_KEYS __BIT(1) /* Attestation support for SGX */ | | 488 | #define CPUID_SEF_SGX_KEYS __BIT(1) /* Attestation support for SGX */ |
488 | #define CPUID_SEF_AVX512_4VNNIW __BIT(2) /* AVX512 4-reg Neural Network ins */ | | 489 | #define CPUID_SEF_AVX512_4VNNIW __BIT(2) /* AVX512 4-reg Neural Network ins */ |
489 | #define CPUID_SEF_AVX512_4FMAPS __BIT(3) /* AVX512 4-reg Mult Accum Single precision */ | | 490 | #define CPUID_SEF_AVX512_4FMAPS __BIT(3) /* AVX512 4-reg Mult Accum Single precision */ |
490 | #define CPUID_SEF_FSRM __BIT(4) /* Fast Short Rep Move */ | | 491 | #define CPUID_SEF_FSRM __BIT(4) /* Fast Short Rep Move */ |
491 | #define CPUID_SEF_UINTR __BIT(5) /* User Interrupts */ | | 492 | #define CPUID_SEF_UINTR __BIT(5) /* User Interrupts */ |
492 | #define CPUID_SEF_AVX512_VP2INTERSECT __BIT(8) /* AVX512 VP2INTERSECT */ | | 493 | #define CPUID_SEF_AVX512_VP2INTERSECT __BIT(8) /* AVX512 VP2INTERSECT */ |
493 | #define CPUID_SEF_SRBDS_CTRL __BIT(9) /* IA32_MCU_OPT_CTRL */ | | 494 | #define CPUID_SEF_SRBDS_CTRL __BIT(9) /* IA32_MCU_OPT_CTRL */ |
494 | #define CPUID_SEF_MD_CLEAR __BIT(10) /* VERW clears CPU buffers */ | | 495 | #define CPUID_SEF_MD_CLEAR __BIT(10) /* VERW clears CPU buffers */ |
495 | #define CPUID_SEF_RTM_ALWAYS_ABORT __BIT(11) /* XBEGIN immediately abort */ | | 496 | #define CPUID_SEF_RTM_ALWAYS_ABORT __BIT(11) /* XBEGIN immediately abort */ |
496 | #define CPUID_SEF_RTM_FORCE_ABORT __BIT(13) /* MSR_TSX_FORCE_ABORT bit 0 */ | | 497 | #define CPUID_SEF_RTM_FORCE_ABORT __BIT(13) /* MSR_TSX_FORCE_ABORT bit 0 */ |
497 | #define CPUID_SEF_SERIALIZE __BIT(14) /* SERIALIZE instruction */ | | 498 | #define CPUID_SEF_SERIALIZE __BIT(14) /* SERIALIZE instruction */ |
498 | #define CPUID_SEF_HYBRID __BIT(15) /* Hybrid part */ | | 499 | #define CPUID_SEF_HYBRID __BIT(15) /* Hybrid part */ |
499 | #define CPUID_SEF_TSXLDTRK __BIT(16) /* TSX suspend load addr tracking */ | | 500 | #define CPUID_SEF_TSXLDTRK __BIT(16) /* TSX suspend load addr tracking */ |
500 | #define CPUID_SEF_PCONFIG __BIT(18) /* Platform CONFIGuration */ | | 501 | #define CPUID_SEF_PCONFIG __BIT(18) /* Platform CONFIGuration */ |
501 | #define CPUID_SEF_ARCH_LBR __BIT(19) /* Architectural LBR */ | | 502 | #define CPUID_SEF_ARCH_LBR __BIT(19) /* Architectural LBR */ |
502 | #define CPUID_SEF_CET_IBT __BIT(20) /* CET Indirect Branch Tracking */ | | 503 | #define CPUID_SEF_CET_IBT __BIT(20) /* CET Indirect Branch Tracking */ |
503 | #define CPUID_SEF_AMX_BF16 __BIT(22) /* AMX bfloat16 */ | | 504 | #define CPUID_SEF_AMX_BF16 __BIT(22) /* AMX bfloat16 */ |
504 | #define CPUID_SEF_AVX512_FP16 __BIT(23) /* AVX512 FP16 */ | | 505 | #define CPUID_SEF_AVX512_FP16 __BIT(23) /* AVX512 FP16 */ |
505 | #define CPUID_SEF_AMX_TILE __BIT(24) /* Tile architecture */ | | 506 | #define CPUID_SEF_AMX_TILE __BIT(24) /* Tile architecture */ |
506 | #define CPUID_SEF_AMX_INT8 __BIT(25) /* AMX 8bit interger */ | | 507 | #define CPUID_SEF_AMX_INT8 __BIT(25) /* AMX 8bit interger */ |
507 | #define CPUID_SEF_IBRS __BIT(26) /* IBRS / IBPB Speculation Control */ | | 508 | #define CPUID_SEF_IBRS __BIT(26) /* IBRS / IBPB Speculation Control */ |
508 | #define CPUID_SEF_STIBP __BIT(27) /* STIBP Speculation Control */ | | 509 | #define CPUID_SEF_STIBP __BIT(27) /* STIBP Speculation Control */ |
509 | #define CPUID_SEF_L1D_FLUSH __BIT(28) /* IA32_FLUSH_CMD MSR */ | | 510 | #define CPUID_SEF_L1D_FLUSH __BIT(28) /* IA32_FLUSH_CMD MSR */ |
510 | #define CPUID_SEF_ARCH_CAP __BIT(29) /* IA32_ARCH_CAPABILITIES */ | | 511 | #define CPUID_SEF_ARCH_CAP __BIT(29) /* IA32_ARCH_CAPABILITIES */ |
511 | #define CPUID_SEF_CORE_CAP __BIT(30) /* IA32_CORE_CAPABILITIES */ | | 512 | #define CPUID_SEF_CORE_CAP __BIT(30) /* IA32_CORE_CAPABILITIES */ |
512 | #define CPUID_SEF_SSBD __BIT(31) /* Speculative Store Bypass Disable */ | | 513 | #define CPUID_SEF_SSBD __BIT(31) /* Speculative Store Bypass Disable */ |
513 | | | 514 | |
514 | #define CPUID_SEF_FLAGS2 "\20" \ | | 515 | #define CPUID_SEF_FLAGS2 "\20" \ |
515 | "\2SGX_KEYS" "\3AVX512_4VNNIW" "\4AVX512_4FMAPS" \ | | 516 | "\2SGX_KEYS" "\3AVX512_4VNNIW" "\4AVX512_4FMAPS" \ |
516 | "\5FSRM" "\6UINTR" \ | | 517 | "\5FSRM" "\6UINTR" \ |
517 | "\11VP2INTERSECT" "\12SRBDS_CTRL" "\13MD_CLEAR" "\14RTM_ALWAYS_ABORT" \ | | 518 | "\11VP2INTERSECT" "\12SRBDS_CTRL" "\13MD_CLEAR" "\14RTM_ALWAYS_ABORT" \ |
518 | "\16RTM_FORCE_ABORT" "\17SERIALIZE" "\20HYBRID" \ | | 519 | "\16RTM_FORCE_ABORT" "\17SERIALIZE" "\20HYBRID" \ |
519 | "\21" "TSXLDTRK" "\23" "PCONFIG" "\24" "ARCH_LBR" \ | | 520 | "\21" "TSXLDTRK" "\23" "PCONFIG" "\24" "ARCH_LBR" \ |
520 | "\25CET_IBT" "\27AMX_BF16" "\30AVX512_FP16" \ | | 521 | "\25CET_IBT" "\27AMX_BF16" "\30AVX512_FP16" \ |
521 | "\31AMX_TILE" "\32AMX_INT8" "\33IBRS" "\34STIBP" \ | | 522 | "\31AMX_TILE" "\32AMX_INT8" "\33IBRS" "\34STIBP" \ |
522 | "\35" "L1D_FLUSH" "\36" "ARCH_CAP" "\37CORE_CAP" "\40" "SSBD" | | 523 | "\35" "L1D_FLUSH" "\36" "ARCH_CAP" "\37CORE_CAP" "\40" "SSBD" |
523 | | | 524 | |
524 | /* %ecx = 1, %eax */ | | 525 | /* %ecx = 1, %eax */ |
525 | #define CPUID_SEF_AVXVNNI __BIT(4) /* AVX version of VNNI */ | | 526 | #define CPUID_SEF_AVXVNNI __BIT(4) /* AVX version of VNNI */ |
526 | #define CPUID_SEF_AVX512_BF16 __BIT(5) | | 527 | #define CPUID_SEF_AVX512_BF16 __BIT(5) |
527 | #define CPUID_SEF_FZLRMS __BIT(10) /* fast zero-length REP MOVSB */ | | 528 | #define CPUID_SEF_FZLRMS __BIT(10) /* fast zero-length REP MOVSB */ |
528 | #define CPUID_SEF_FSRSB __BIT(11) /* fast short REP STOSB */ | | 529 | #define CPUID_SEF_FSRSB __BIT(11) /* fast short REP STOSB */ |
529 | #define CPUID_SEF_FSRCS __BIT(12) /* fast short REP CMPSB, REP SCASB */ | | 530 | #define CPUID_SEF_FSRCS __BIT(12) /* fast short REP CMPSB, REP SCASB */ |
530 | #define CPUID_SEF_HRESET __BIT(22) /* HREST & IA32_HRESET_ENABLE MSR */ | | 531 | #define CPUID_SEF_HRESET __BIT(22) /* HREST & IA32_HRESET_ENABLE MSR */ |
531 | #define CPUID_SEF_LAM __BIT(26) /* Linear Address Masking */ | | 532 | #define CPUID_SEF_LAM __BIT(26) /* Linear Address Masking */ |
532 | | | 533 | |
533 | #define CPUID_SEF1_FLAGS_A "\20" \ | | 534 | #define CPUID_SEF1_FLAGS_A "\20" \ |
534 | "\5" "AVXVNNI" "\6" "AVX512_BF16" \ | | 535 | "\5" "AVXVNNI" "\6" "AVX512_BF16" \ |
535 | "\13" "FZLRMS" "\14" "FSRSB" \ | | 536 | "\13" "FZLRMS" "\14" "FSRSB" \ |
536 | "\15" "FSRCS" "\27" "HRESET" \ | | 537 | "\15" "FSRCS" "\27" "HRESET" \ |
537 | "\31" "LAM" | | 538 | "\31" "LAM" |
538 | | | 539 | |
539 | /* %ecx = 1, %ebx */ | | 540 | /* %ecx = 1, %ebx */ |
540 | #define CPUID_SEF_INTEL_PPIN __BIT(0) /* IA32_PPIN & IA32_PPIN_CTL MSRs */ | | 541 | #define CPUID_SEF_INTEL_PPIN __BIT(0) /* IA32_PPIN & IA32_PPIN_CTL MSRs */ |
541 | | | 542 | |
542 | #define CPUID_SEF1_FLAGS_B "\20" \ | | 543 | #define CPUID_SEF1_FLAGS_B "\20" \ |
543 | "\1" "PPIN" | | 544 | "\1" "PPIN" |
544 | | | 545 | |
545 | /* %ecx = 1, %edx */ | | 546 | /* %ecx = 1, %edx */ |
546 | #define CPUID_SEF_CET_SSS __BIT(18) /* CET Supervisor Shadow Stack */ | | 547 | #define CPUID_SEF_CET_SSS __BIT(18) /* CET Supervisor Shadow Stack */ |
547 | | | 548 | |
548 | #define CPUID_SEF1_FLAGS_D "\20" \ | | 549 | #define CPUID_SEF1_FLAGS_D "\20" \ |
549 | "\23CET_SSS" | | 550 | "\23CET_SSS" |
550 | | | 551 | |
551 | /* %ecx = 2, %edx */ | | 552 | /* %ecx = 2, %edx */ |
552 | #define CPUID_SEF_PSFD __BIT(0) /* Fast Forwarding Predictor Dis. */ | | 553 | #define CPUID_SEF_PSFD __BIT(0) /* Fast Forwarding Predictor Dis. */ |
553 | #define CPUID_SEF_IPRED_CTRL __BIT(1) /* IPRED_DIS */ | | 554 | #define CPUID_SEF_IPRED_CTRL __BIT(1) /* IPRED_DIS */ |
554 | #define CPUID_SEF_RRSBA_CTRL __BIT(2) /* RRSBA for CPL3 */ | | 555 | #define CPUID_SEF_RRSBA_CTRL __BIT(2) /* RRSBA for CPL3 */ |
555 | #define CPUID_SEF_DDPD_U __BIT(3) /* Data Dependent Prefetcher */ | | 556 | #define CPUID_SEF_DDPD_U __BIT(3) /* Data Dependent Prefetcher */ |
556 | #define CPUID_SEF_BHI_CTRL __BIT(4) /* BHI_DIS_S */ | | 557 | #define CPUID_SEF_BHI_CTRL __BIT(4) /* BHI_DIS_S */ |
557 | #define CPUID_SEF_MCDT_NO __BIT(5) /* !MXCSR Config Dependent Timing */ | | 558 | #define CPUID_SEF_MCDT_NO __BIT(5) /* !MXCSR Config Dependent Timing */ |
558 | | | 559 | |
559 | #define CPUID_SEF2_FLAGS_D "\20" \ | | 560 | #define CPUID_SEF2_FLAGS_D "\20" \ |
560 | "\1PSFD" "\2IPRED_CTRL" "\3RRSBA_CTRL" "\4DDPD_U" \ | | 561 | "\1PSFD" "\2IPRED_CTRL" "\3RRSBA_CTRL" "\4DDPD_U" \ |
561 | "\5BHI_CTRL" "\6MCDT_NO" | | 562 | "\5BHI_CTRL" "\6MCDT_NO" |
562 | | | 563 | |
563 | /* | | 564 | /* |
564 | * Intel CPUID Architectural Performance Monitoring. | | 565 | * Intel CPUID Architectural Performance Monitoring. |
565 | * CPUID Fn0000000a | | 566 | * CPUID Fn0000000a |
566 | * | | 567 | * |
567 | * See also src/usr.sbin/tprof/arch/tprof_x86.c | | 568 | * See also src/usr.sbin/tprof/arch/tprof_x86.c |
568 | */ | | 569 | */ |
569 | | | 570 | |
570 | /* %eax */ | | 571 | /* %eax */ |
571 | #define CPUID_PERF_VERSION __BITS(7, 0) /* Version ID */ | | 572 | #define CPUID_PERF_VERSION __BITS(7, 0) /* Version ID */ |
572 | #define CPUID_PERF_NGPPC __BITS(15, 8) /* Num of G.P. perf counter */ | | 573 | #define CPUID_PERF_NGPPC __BITS(15, 8) /* Num of G.P. perf counter */ |
573 | #define CPUID_PERF_NBWGPPC __BITS(23, 16) /* Bit width of G.P. perfcnt */ | | 574 | #define CPUID_PERF_NBWGPPC __BITS(23, 16) /* Bit width of G.P. perfcnt */ |
574 | #define CPUID_PERF_BVECLEN __BITS(31, 24) /* Length of EBX bit vector */ | | 575 | #define CPUID_PERF_BVECLEN __BITS(31, 24) /* Length of EBX bit vector */ |
575 | | | 576 | |
576 | #define CPUID_PERF_FLAGS0 "\177\20" \ | | 577 | #define CPUID_PERF_FLAGS0 "\177\20" \ |
577 | "f\0\10VERSION\0" "f\10\10GPCounter\0" \ | | 578 | "f\0\10VERSION\0" "f\10\10GPCounter\0" \ |
578 | "f\20\10GPBitwidth\0" "f\30\10Vectorlen\0" | | 579 | "f\20\10GPBitwidth\0" "f\30\10Vectorlen\0" |
579 | | | 580 | |
580 | /* %ebx */ | | 581 | /* %ebx */ |
581 | #define CPUID_PERF_CORECYCL __BIT(0) /* No core cycle */ | | 582 | #define CPUID_PERF_CORECYCL __BIT(0) /* No core cycle */ |
582 | #define CPUID_PERF_INSTRETRY __BIT(1) /* No instruction retried */ | | 583 | #define CPUID_PERF_INSTRETRY __BIT(1) /* No instruction retried */ |
583 | #define CPUID_PERF_REFCYCL __BIT(2) /* No reference cycles */ | | 584 | #define CPUID_PERF_REFCYCL __BIT(2) /* No reference cycles */ |
584 | #define CPUID_PERF_LLCREF __BIT(3) /* No LLCache reference */ | | 585 | #define CPUID_PERF_LLCREF __BIT(3) /* No LLCache reference */ |
585 | #define CPUID_PERF_LLCMISS __BIT(4) /* No LLCache miss */ | | 586 | #define CPUID_PERF_LLCMISS __BIT(4) /* No LLCache miss */ |
586 | #define CPUID_PERF_BRINSRETR __BIT(5) /* No branch inst. retried */ | | 587 | #define CPUID_PERF_BRINSRETR __BIT(5) /* No branch inst. retried */ |
587 | #define CPUID_PERF_BRMISPRRETR __BIT(6) /* No branch mispredict retry */ | | 588 | #define CPUID_PERF_BRMISPRRETR __BIT(6) /* No branch mispredict retry */ |
588 | #define CPUID_PERF_TOPDOWNSLOT __BIT(7) /* No top-down slots */ | | 589 | #define CPUID_PERF_TOPDOWNSLOT __BIT(7) /* No top-down slots */ |
589 | | | 590 | |
590 | #define CPUID_PERF_FLAGS1 "\177\20" \ | | 591 | #define CPUID_PERF_FLAGS1 "\177\20" \ |
591 | "b\0CORECYCL\0" "b\1INST\0" "b\2REFCYCL\0" "b\3LLCREF\0" \ | | 592 | "b\0CORECYCL\0" "b\1INST\0" "b\2REFCYCL\0" "b\3LLCREF\0" \ |
592 | "b\4LLCMISS\0" "b\5BRINST\0" "b\6BRMISPR\0" "b\7TOPDOWNSLOT\0" | | 593 | "b\4LLCMISS\0" "b\5BRINST\0" "b\6BRMISPR\0" "b\7TOPDOWNSLOT\0" |
593 | | | 594 | |
594 | /* %ecx */ | | 595 | /* %ecx */ |
595 | | | 596 | |
596 | #define CPUID_PERF_FLAGS2 "\177\20" \ | | 597 | #define CPUID_PERF_FLAGS2 "\177\20" \ |
597 | "b\0INST\0" "b\1CLK_CORETHREAD\0" "b\2CLK_REF_TSC\0" "b\3TOPDOWNSLOT\0" | | 598 | "b\0INST\0" "b\1CLK_CORETHREAD\0" "b\2CLK_REF_TSC\0" "b\3TOPDOWNSLOT\0" |
598 | | | 599 | |
599 | /* %edx */ | | 600 | /* %edx */ |
600 | #define CPUID_PERF_NFFPC __BITS(4, 0) /* Num of fixed-funct perfcnt */ | | 601 | #define CPUID_PERF_NFFPC __BITS(4, 0) /* Num of fixed-funct perfcnt */ |
601 | #define CPUID_PERF_NBWFFPC __BITS(12, 5) /* Bit width of fixed-func pc */ | | 602 | #define CPUID_PERF_NBWFFPC __BITS(12, 5) /* Bit width of fixed-func pc */ |
602 | #define CPUID_PERF_ANYTHREADDEPR __BIT(15) /* Any Thread deprecation */ | | 603 | #define CPUID_PERF_ANYTHREADDEPR __BIT(15) /* Any Thread deprecation */ |
603 | | | 604 | |
604 | #define CPUID_PERF_FLAGS3 "\177\20" \ | | 605 | #define CPUID_PERF_FLAGS3 "\177\20" \ |
605 | "f\0\5FixedFunc\0" "f\5\10FFBitwidth\0" "b\17ANYTHREADDEPR\0" | | 606 | "f\0\5FixedFunc\0" "f\5\10FFBitwidth\0" "b\17ANYTHREADDEPR\0" |
606 | | | 607 | |
607 | /* | | 608 | /* |
608 | * Intel/AMD CPUID Extended Topology Enumeration. | | 609 | * Intel/AMD CPUID Extended Topology Enumeration. |
609 | * CPUID Fn0000000b | | 610 | * CPUID Fn0000000b |
610 | * %ecx == level number | | 611 | * %ecx == level number |
611 | * %eax: See below. | | 612 | * %eax: See below. |
612 | * %ebx: Number of logical processors at this level. | | 613 | * %ebx: Number of logical processors at this level. |
613 | * %ecx: See below. | | 614 | * %ecx: See below. |
614 | * %edx: x2APIC ID of the current logical processor. | | 615 | * %edx: x2APIC ID of the current logical processor. |
615 | */ | | 616 | */ |
616 | /* %eax */ | | 617 | /* %eax */ |
617 | #define CPUID_TOP_SHIFTNUM __BITS(4, 0) /* Topology ID shift value */ | | 618 | #define CPUID_TOP_SHIFTNUM __BITS(4, 0) /* Topology ID shift value */ |
618 | /* %ecx */ | | 619 | /* %ecx */ |
619 | #define CPUID_TOP_LVLNUM __BITS(7, 0) /* Level number */ | | 620 | #define CPUID_TOP_LVLNUM __BITS(7, 0) /* Level number */ |
620 | #define CPUID_TOP_LVLTYPE __BITS(15, 8) /* Level type */ | | 621 | #define CPUID_TOP_LVLTYPE __BITS(15, 8) /* Level type */ |
621 | #define CPUID_TOP_LVLTYPE_INVAL 0 /* Invalid */ | | 622 | #define CPUID_TOP_LVLTYPE_INVAL 0 /* Invalid */ |
622 | #define CPUID_TOP_LVLTYPE_SMT 1 /* SMT */ | | 623 | #define CPUID_TOP_LVLTYPE_SMT 1 /* SMT */ |
623 | #define CPUID_TOP_LVLTYPE_CORE 2 /* Core */ | | 624 | #define CPUID_TOP_LVLTYPE_CORE 2 /* Core */ |
624 | | | 625 | |
625 | /* | | 626 | /* |
626 | * Intel/AMD CPUID Processor extended state Enumeration. | | 627 | * Intel/AMD CPUID Processor extended state Enumeration. |
627 | * CPUID Fn0000000d | | 628 | * CPUID Fn0000000d |
628 | * | | 629 | * |
629 | * %ecx == 0: supported features info: | | 630 | * %ecx == 0: supported features info: |
630 | * %eax: Valid bits of lower 32bits of XCR0 | | 631 | * %eax: Valid bits of lower 32bits of XCR0 |
631 | * %ebx: Maximum save area size for features enabled in XCR0 | | 632 | * %ebx: Maximum save area size for features enabled in XCR0 |
632 | * %ecx: Maximum save area size for all cpu features | | 633 | * %ecx: Maximum save area size for all cpu features |
633 | * %edx: Valid bits of upper 32bits of XCR0 | | 634 | * %edx: Valid bits of upper 32bits of XCR0 |
634 | * | | 635 | * |
635 | * %ecx == 1: | | 636 | * %ecx == 1: |
636 | * %eax: See below | | 637 | * %eax: See below |
637 | * %ebx: Save area size for features enabled by XCR0 | IA32_XSS | | 638 | * %ebx: Save area size for features enabled by XCR0 | IA32_XSS |
638 | * %ecx: Valid bits of lower 32bits of IA32_XSS | | 639 | * %ecx: Valid bits of lower 32bits of IA32_XSS |
639 | * %edx: Valid bits of upper 32bits of IA32_XSS | | 640 | * %edx: Valid bits of upper 32bits of IA32_XSS |
640 | * | | 641 | * |
641 | * %ecx >= 2: Save area details for XCR0 bit n | | 642 | * %ecx >= 2: Save area details for XCR0 bit n |
642 | * %eax: size of save area for this feature | | 643 | * %eax: size of save area for this feature |
643 | * %ebx: offset of save area for this feature | | 644 | * %ebx: offset of save area for this feature |
644 | * %ecx, %edx: reserved | | 645 | * %ecx, %edx: reserved |
645 | * All of %eax, %ebx, %ecx and %edx are zero for unsupported features. | | 646 | * All of %eax, %ebx, %ecx and %edx are zero for unsupported features. |
646 | */ | | 647 | */ |
647 | | | 648 | |
648 | /* %ecx = 1, %eax */ | | 649 | /* %ecx = 1, %eax */ |
649 | #define CPUID_PES1_XSAVEOPT __BIT(0) /* xsaveopt instruction */ | | 650 | #define CPUID_PES1_XSAVEOPT __BIT(0) /* xsaveopt instruction */ |
650 | #define CPUID_PES1_XSAVEC __BIT(1) /* xsavec & compacted XRSTOR */ | | 651 | #define CPUID_PES1_XSAVEC __BIT(1) /* xsavec & compacted XRSTOR */ |
651 | #define CPUID_PES1_XGETBV __BIT(2) /* xgetbv with ECX = 1 */ | | 652 | #define CPUID_PES1_XGETBV __BIT(2) /* xgetbv with ECX = 1 */ |
652 | #define CPUID_PES1_XSAVES __BIT(3) /* xsaves/xrstors, IA32_XSS */ | | 653 | #define CPUID_PES1_XSAVES __BIT(3) /* xsaves/xrstors, IA32_XSS */ |
653 | #define CPUID_PES1_XFD __BIT(4) /* eXtened Feature Disable */ | | 654 | #define CPUID_PES1_XFD __BIT(4) /* eXtened Feature Disable */ |
654 | | | 655 | |
655 | #define CPUID_PES1_FLAGS "\20" \ | | 656 | #define CPUID_PES1_FLAGS "\20" \ |
656 | "\1XSAVEOPT" "\2XSAVEC" "\3XGETBV" "\4XSAVES" \ | | 657 | "\1XSAVEOPT" "\2XSAVEC" "\3XGETBV" "\4XSAVES" \ |
657 | "\5XFD" | | 658 | "\5XFD" |
658 | | | 659 | |
659 | /* | | 660 | /* |
660 | * Intel Deterministic Address Translation Parameter. | | 661 | * Intel Deterministic Address Translation Parameter. |
661 | * CPUID Fn0000_0018 | | 662 | * CPUID Fn0000_0018 |
662 | */ | | 663 | */ |
663 | | | 664 | |
664 | /* %ecx=0 %eax __BITS(31, 0): the maximum input value of supported sub-leaf */ | | 665 | /* %ecx=0 %eax __BITS(31, 0): the maximum input value of supported sub-leaf */ |
665 | | | 666 | |
666 | /* %ebx */ | | 667 | /* %ebx */ |
667 | #define CPUID_DATP_PGSIZE __BITS(3, 0) /* page size */ | | 668 | #define CPUID_DATP_PGSIZE __BITS(3, 0) /* page size */ |
668 | #define CPUID_DATP_PGSIZE_4KB __BIT(0) /* 4KB page support */ | | 669 | #define CPUID_DATP_PGSIZE_4KB __BIT(0) /* 4KB page support */ |
669 | #define CPUID_DATP_PGSIZE_2MB __BIT(1) /* 2MB page support */ | | 670 | #define CPUID_DATP_PGSIZE_2MB __BIT(1) /* 2MB page support */ |
670 | #define CPUID_DATP_PGSIZE_4MB __BIT(2) /* 4MB page support */ | | 671 | #define CPUID_DATP_PGSIZE_4MB __BIT(2) /* 4MB page support */ |
671 | #define CPUID_DATP_PGSIZE_1GB __BIT(3) /* 1GB page support */ | | 672 | #define CPUID_DATP_PGSIZE_1GB __BIT(3) /* 1GB page support */ |
672 | #define CPUID_DATP_PARTITIONING __BITS(10, 8) /* Partitioning */ | | 673 | #define CPUID_DATP_PARTITIONING __BITS(10, 8) /* Partitioning */ |
673 | #define CPUID_DATP_WAYS __BITS(31, 16) /* Ways of associativity */ | | 674 | #define CPUID_DATP_WAYS __BITS(31, 16) /* Ways of associativity */ |
674 | | | 675 | |
675 | /* Number of sets: %ecx */ | | 676 | /* Number of sets: %ecx */ |
676 | | | 677 | |
677 | /* %edx */ | | 678 | /* %edx */ |
678 | #define CPUID_DATP_TCTYPE __BITS(4, 0) /* Translation Cache type */ | | 679 | #define CPUID_DATP_TCTYPE __BITS(4, 0) /* Translation Cache type */ |
679 | #define CPUID_DATP_TCTYPE_N 0 /* NULL (not valid) */ | | 680 | #define CPUID_DATP_TCTYPE_N 0 /* NULL (not valid) */ |
680 | #define CPUID_DATP_TCTYPE_D 1 /* Data TLB */ | | 681 | #define CPUID_DATP_TCTYPE_D 1 /* Data TLB */ |
681 | #define CPUID_DATP_TCTYPE_I 2 /* Instruction TLB */ | | 682 | #define CPUID_DATP_TCTYPE_I 2 /* Instruction TLB */ |
682 | #define CPUID_DATP_TCTYPE_U 3 /* Unified TLB */ | | 683 | #define CPUID_DATP_TCTYPE_U 3 /* Unified TLB */ |
683 | #define CPUID_DATP_TCTYPE_L 4 /* Load only TLB */ | | 684 | #define CPUID_DATP_TCTYPE_L 4 /* Load only TLB */ |
684 | #define CPUID_DATP_TCTYPE_S 5 /* Store only TLB */ | | 685 | #define CPUID_DATP_TCTYPE_S 5 /* Store only TLB */ |
685 | #define CPUID_DATP_TCLEVEL __BITS(7, 5) /* TLB level (start at 1) */ | | 686 | #define CPUID_DATP_TCLEVEL __BITS(7, 5) /* TLB level (start at 1) */ |
686 | #define CPUID_DATP_FULLASSOC __BIT(8) /* Full associative */ | | 687 | #define CPUID_DATP_FULLASSOC __BIT(8) /* Full associative */ |
687 | #define CPUID_DATP_SHARING __BITS(25, 14) /* sharing */ | | 688 | #define CPUID_DATP_SHARING __BITS(25, 14) /* sharing */ |
688 | | | 689 | |
689 | /* | | 690 | /* |
690 | * Intel Native Model ID Information Enumeration. | | 691 | * Intel Native Model ID Information Enumeration. |
691 | * CPUID Fn0000_001a | | 692 | * CPUID Fn0000_001a |
692 | */ | | 693 | */ |
693 | /* %eax */ | | 694 | /* %eax */ |
694 | #define CPUID_HYBRID_NATIVEID __BITS(23, 0) /* Native model ID */ | | 695 | #define CPUID_HYBRID_NATIVEID __BITS(23, 0) /* Native model ID */ |
695 | #define CPUID_HYBRID_CORETYPE __BITS(31, 24) /* Core type */ | | 696 | #define CPUID_HYBRID_CORETYPE __BITS(31, 24) /* Core type */ |
696 | #define CPUID_HYBRID_CORETYPE_ATOM 0x20 /* Atom */ | | 697 | #define CPUID_HYBRID_CORETYPE_ATOM 0x20 /* Atom */ |
697 | #define CPUID_HYBRID_CORETYPE_CORE 0x40 /* Core */ | | 698 | #define CPUID_HYBRID_CORETYPE_CORE 0x40 /* Core */ |
698 | | | 699 | |
699 | /* | | 700 | /* |
700 | * Intel Tile Information | | 701 | * Intel Tile Information |
701 | * CPUID Fn0000_001d | | 702 | * CPUID Fn0000_001d |
702 | * %ecx == 0: Main leaf | | 703 | * %ecx == 0: Main leaf |
703 | * %eax: max_palette | | 704 | * %eax: max_palette |
704 | * %ecx == 1: Tile Palette1 Sub-leaf | | 705 | * %ecx == 1: Tile Palette1 Sub-leaf |
705 | * Tile palette 1 | | 706 | * Tile palette 1 |
706 | */ | | 707 | */ |
707 | | | 708 | |
708 | /* %ecx */ | | 709 | /* %ecx */ |
709 | #define CPUID_TILE_P1_TOTAL_B __BITS(15, 0) | | 710 | #define CPUID_TILE_P1_TOTAL_B __BITS(15, 0) |
710 | #define CPUID_TILE_P1_B_PERTILE __BITS(31, 16) | | 711 | #define CPUID_TILE_P1_B_PERTILE __BITS(31, 16) |
711 | #define CPUID_TILE_P1_B_PERLOW __BITS(15, 0) | | 712 | #define CPUID_TILE_P1_B_PERLOW __BITS(15, 0) |
712 | #define CPUID_TILE_P1_MAXNAMES __BITS(31, 16) | | 713 | #define CPUID_TILE_P1_MAXNAMES __BITS(31, 16) |
713 | #define CPUID_TILE_P1_MAXROWS __BITS(15, 0) | | 714 | #define CPUID_TILE_P1_MAXROWS __BITS(15, 0) |
714 | | | 715 | |
715 | /* | | 716 | /* |
716 | * Intel TMUL Information | | 717 | * Intel TMUL Information |
717 | * CPUID Fn0000_001e | | 718 | * CPUID Fn0000_001e |
718 | */ | | 719 | */ |
719 | | | 720 | |
720 | /* %ebx */ | | 721 | /* %ebx */ |
721 | #define CPUID_TMUL_MAXK __BITS(7, 0) /* Rows or columns */ | | 722 | #define CPUID_TMUL_MAXK __BITS(7, 0) /* Rows or columns */ |
722 | #define CPUID_TMUL_MAXN __BITS(23, 8) /* Column bytes */ | | 723 | #define CPUID_TMUL_MAXN __BITS(23, 8) /* Column bytes */ |
723 | | | 724 | |
724 | /* | | 725 | /* |
725 | * Intel extended features. | | 726 | * Intel extended features. |
726 | * CPUID Fn80000001 | | 727 | * CPUID Fn80000001 |
727 | */ | | 728 | */ |
728 | /* %edx */ | | 729 | /* %edx */ |
729 | #define CPUID_SYSCALL __BIT(11) /* SYSCALL/SYSRET */ | | 730 | #define CPUID_SYSCALL __BIT(11) /* SYSCALL/SYSRET */ |
730 | #define CPUID_XD __BIT(20) /* Execute Disable (like CPUID_NOX) */ | | 731 | #define CPUID_XD __BIT(20) /* Execute Disable (like CPUID_NOX) */ |
731 | #define CPUID_PAGE1GB __BIT(26) /* 1GB Large Page Support */ | | 732 | #define CPUID_PAGE1GB __BIT(26) /* 1GB Large Page Support */ |
732 | #define CPUID_RDTSCP __BIT(27) /* Read TSC Pair Instruction */ | | 733 | #define CPUID_RDTSCP __BIT(27) /* Read TSC Pair Instruction */ |
733 | #define CPUID_EM64T __BIT(29) /* Intel EM64T */ | | 734 | #define CPUID_EM64T __BIT(29) /* Intel EM64T */ |
734 | | | 735 | |
735 | #define CPUID_INTEL_EXT_FLAGS "\20" \ | | 736 | #define CPUID_INTEL_EXT_FLAGS "\20" \ |
736 | "\14" "SYSCALL/SYSRET" "\25" "XD" "\33" "P1GB" \ | | 737 | "\14" "SYSCALL/SYSRET" "\25" "XD" "\33" "P1GB" \ |
737 | "\34" "RDTSCP" "\36" "EM64T" | | 738 | "\34" "RDTSCP" "\36" "EM64T" |
738 | | | 739 | |
739 | /* %ecx */ | | 740 | /* %ecx */ |
740 | #define CPUID_LAHF __BIT(0) /* LAHF/SAHF in IA-32e mode, 64bit sub*/ | | 741 | #define CPUID_LAHF __BIT(0) /* LAHF/SAHF in IA-32e mode, 64bit sub*/ |
741 | /* __BIT(5) */ /* LZCNT. Same as AMD's CPUID_ABM */ | | 742 | /* __BIT(5) */ /* LZCNT. Same as AMD's CPUID_ABM */ |
742 | #define CPUID_PREFETCHW __BIT(8) /* PREFETCHW */ | | 743 | #define CPUID_PREFETCHW __BIT(8) /* PREFETCHW */ |
743 | | | 744 | |
744 | #define CPUID_INTEL_FLAGS4 "\20" \ | | 745 | #define CPUID_INTEL_FLAGS4 "\20" \ |
745 | "\1" "LAHF" "\02" "B01" "\03" "B02" \ | | 746 | "\1" "LAHF" "\02" "B01" "\03" "B02" \ |
746 | "\06" "LZCNT" \ | | 747 | "\06" "LZCNT" \ |
747 | "\11" "PREFETCHW" | | 748 | "\11" "PREFETCHW" |
748 | | | 749 | |
749 | | | 750 | |
750 | /* | | 751 | /* |
751 | * AMD/VIA extended features. | | 752 | * AMD/VIA extended features. |
752 | * CPUID Fn80000001 | | 753 | * CPUID Fn80000001 |
753 | */ | | 754 | */ |
754 | /* %edx */ | | 755 | /* %edx */ |
755 | /* CPUID_SYSCALL SYSCALL/SYSRET */ | | 756 | /* CPUID_SYSCALL SYSCALL/SYSRET */ |
756 | #define CPUID_MPC 0x00080000 /* Multiprocessing Capable */ | | 757 | #define CPUID_MPC 0x00080000 /* Multiprocessing Capable */ |
757 | #define CPUID_NOX 0x00100000 /* No Execute Page Protection */ | | 758 | #define CPUID_NOX 0x00100000 /* No Execute Page Protection */ |
758 | #define CPUID_MMXX 0x00400000 /* AMD MMX Extensions */ | | 759 | #define CPUID_MMXX 0x00400000 /* AMD MMX Extensions */ |
759 | /* CPUID_MMX MMX supported */ | | 760 | /* CPUID_MMX MMX supported */ |
760 | /* CPUID_FXSR fast FP/MMX save/restore */ | | 761 | /* CPUID_FXSR fast FP/MMX save/restore */ |
761 | #define CPUID_FFXSR 0x02000000 /* FXSAVE/FXSTOR Extensions */ | | 762 | #define CPUID_FFXSR 0x02000000 /* FXSAVE/FXSTOR Extensions */ |
762 | /* CPUID_PAGE1GB 1GB Large Page Support */ | | 763 | /* CPUID_PAGE1GB 1GB Large Page Support */ |
763 | /* CPUID_RDTSCP Read TSC Pair Instruction */ | | 764 | /* CPUID_RDTSCP Read TSC Pair Instruction */ |
764 | /* CPUID_EM64T Long mode */ | | 765 | /* CPUID_EM64T Long mode */ |
765 | #define CPUID_3DNOW2 0x40000000 /* 3DNow! Instruction Extension */ | | 766 | #define CPUID_3DNOW2 0x40000000 /* 3DNow! Instruction Extension */ |
766 | #define CPUID_3DNOW 0x80000000 /* 3DNow! Instructions */ | | 767 | #define CPUID_3DNOW 0x80000000 /* 3DNow! Instructions */ |
767 | | | 768 | |
768 | #define CPUID_EXT_FLAGS "\20" \ | | 769 | #define CPUID_EXT_FLAGS "\20" \ |
769 | "\14" "SYSCALL/SYSRET" \ | | 770 | "\14" "SYSCALL/SYSRET" \ |
770 | "\24" "MPC" \ | | 771 | "\24" "MPC" \ |
771 | "\25" "NOX" "\27" "MMXX" "\30" "MMX" \ | | 772 | "\25" "NOX" "\27" "MMXX" "\30" "MMX" \ |
772 | "\31" "FXSR" "\32" "FFXSR" "\33" "P1GB" "\34" "RDTSCP" \ | | 773 | "\31" "FXSR" "\32" "FFXSR" "\33" "P1GB" "\34" "RDTSCP" \ |
773 | "\36" "LONG" "\37" "3DNOW2" "\40" "3DNOW" | | 774 | "\36" "LONG" "\37" "3DNOW2" "\40" "3DNOW" |
774 | | | 775 | |
775 | /* %ecx (AMD) */ | | 776 | /* %ecx (AMD) */ |
776 | /* CPUID_LAHF LAHF/SAHF instruction */ | | 777 | /* CPUID_LAHF LAHF/SAHF instruction */ |
777 | #define CPUID_CMPLEGACY __BIT(1) /* Compare Legacy */ | | 778 | #define CPUID_CMPLEGACY __BIT(1) /* Compare Legacy */ |
778 | #define CPUID_SVM __BIT(2) /* Secure Virtual Machine */ | | 779 | #define CPUID_SVM __BIT(2) /* Secure Virtual Machine */ |
779 | #define CPUID_EAPIC __BIT(3) /* Extended APIC space */ | | 780 | #define CPUID_EAPIC __BIT(3) /* Extended APIC space */ |
780 | #define CPUID_ALTMOVCR0 __BIT(4) /* Lock Mov Cr0 */ | | 781 | #define CPUID_ALTMOVCR0 __BIT(4) /* Lock Mov Cr0 */ |
781 | #define CPUID_ABM __BIT(5) /* LZCNT instruction */ | | 782 | #define CPUID_ABM __BIT(5) /* LZCNT instruction */ |
782 | #define CPUID_SSE4A __BIT(6) /* SSE4A instruction set */ | | 783 | #define CPUID_SSE4A __BIT(6) /* SSE4A instruction set */ |
783 | #define CPUID_MISALIGNSSE __BIT(7) /* Misaligned SSE */ | | 784 | #define CPUID_MISALIGNSSE __BIT(7) /* Misaligned SSE */ |
784 | #define CPUID_3DNOWPF __BIT(8) /* 3DNow Prefetch */ | | 785 | #define CPUID_3DNOWPF __BIT(8) /* 3DNow Prefetch */ |
785 | #define CPUID_OSVW __BIT(9) /* OS visible workarounds */ | | 786 | #define CPUID_OSVW __BIT(9) /* OS visible workarounds */ |
786 | #define CPUID_IBS __BIT(10) /* Instruction Based Sampling */ | | 787 | #define CPUID_IBS __BIT(10) /* Instruction Based Sampling */ |
787 | #define CPUID_XOP __BIT(11) /* XOP instruction set */ | | 788 | #define CPUID_XOP __BIT(11) /* XOP instruction set */ |
788 | #define CPUID_SKINIT __BIT(12) /* SKINIT */ | | 789 | #define CPUID_SKINIT __BIT(12) /* SKINIT */ |
789 | #define CPUID_WDT __BIT(13) /* watchdog timer support */ | | 790 | #define CPUID_WDT __BIT(13) /* watchdog timer support */ |
790 | #define CPUID_LWP __BIT(15) /* Light Weight Profiling */ | | 791 | #define CPUID_LWP __BIT(15) /* Light Weight Profiling */ |
791 | #define CPUID_FMA4 __BIT(16) /* FMA4 instructions */ | | 792 | #define CPUID_FMA4 __BIT(16) /* FMA4 instructions */ |
792 | #define CPUID_TCE __BIT(17) /* Translation cache Extension */ | | 793 | #define CPUID_TCE __BIT(17) /* Translation cache Extension */ |
793 | #define CPUID_NODEID __BIT(19) /* NodeID MSR available */ | | 794 | #define CPUID_NODEID __BIT(19) /* NodeID MSR available */ |
794 | #define CPUID_TBM __BIT(21) /* TBM instructions */ | | 795 | #define CPUID_TBM __BIT(21) /* TBM instructions */ |
795 | #define CPUID_TOPOEXT __BIT(22) /* cpuid Topology Extension */ | | 796 | #define CPUID_TOPOEXT __BIT(22) /* cpuid Topology Extension */ |
796 | #define CPUID_PCEC __BIT(23) /* Perf Ctr Ext Core */ | | 797 | #define CPUID_PCEC __BIT(23) /* Perf Ctr Ext Core */ |
797 | #define CPUID_PCENB __BIT(24) /* Perf Ctr Ext NB */ | | 798 | #define CPUID_PCENB __BIT(24) /* Perf Ctr Ext NB */ |
798 | #define CPUID_SPM __BIT(25) /* Stream Perf Mon */ | | 799 | #define CPUID_SPM __BIT(25) /* Stream Perf Mon */ |
799 | #define CPUID_DBE __BIT(26) /* Data Breakpoint Extension */ | | 800 | #define CPUID_DBE __BIT(26) /* Data Breakpoint Extension */ |
800 | #define CPUID_PTSC __BIT(27) /* PerfTsc */ | | 801 | #define CPUID_PTSC __BIT(27) /* PerfTsc */ |
801 | #define CPUID_L2IPERFC __BIT(28) /* L2I performance counter Extension */ | | 802 | #define CPUID_L2IPERFC __BIT(28) /* L2I performance counter Extension */ |
802 | #define CPUID_MWAITX __BIT(29) /* MWAITX/MONITORX support */ | | 803 | #define CPUID_MWAITX __BIT(29) /* MWAITX/MONITORX support */ |
803 | #define CPUID_ADDRMASKEXT __BIT(30) /* Breakpoint Addressing Mask ext. */ | | 804 | #define CPUID_ADDRMASKEXT __BIT(30) /* Breakpoint Addressing Mask ext. */ |
804 | | | 805 | |
805 | #define CPUID_AMD_FLAGS4 "\20" \ | | 806 | #define CPUID_AMD_FLAGS4 "\20" \ |
806 | "\1" "LAHF" "\2" "CMPLEGACY" "\3" "SVM" "\4" "EAPIC" \ | | 807 | "\1" "LAHF" "\2" "CMPLEGACY" "\3" "SVM" "\4" "EAPIC" \ |
807 | "\5" "ALTMOVCR0" "\6" "LZCNT" "\7" "SSE4A" "\10" "MISALIGNSSE" \ | | 808 | "\5" "ALTMOVCR0" "\6" "LZCNT" "\7" "SSE4A" "\10" "MISALIGNSSE" \ |
808 | "\11" "3DNOWPREFETCH" \ | | 809 | "\11" "3DNOWPREFETCH" \ |
809 | "\12" "OSVW" "\13" "IBS" "\14" "XOP" \ | | 810 | "\12" "OSVW" "\13" "IBS" "\14" "XOP" \ |
810 | "\15" "SKINIT" "\16" "WDT" "\17" "B14" "\20" "LWP" \ | | 811 | "\15" "SKINIT" "\16" "WDT" "\17" "B14" "\20" "LWP" \ |
811 | "\21" "FMA4" "\22" "TCE" "\23" "B18" "\24" "NodeID" \ | | 812 | "\21" "FMA4" "\22" "TCE" "\23" "B18" "\24" "NodeID" \ |
812 | "\25" "B20" "\26" "TBM" "\27" "TopoExt" "\30" "PCExtC" \ | | 813 | "\25" "B20" "\26" "TBM" "\27" "TopoExt" "\30" "PCExtC" \ |
813 | "\31" "PCExtNB" "\32" "StrmPM" "\33" "DBExt" "\34" "PerfTsc" \ | | 814 | "\31" "PCExtNB" "\32" "StrmPM" "\33" "DBExt" "\34" "PerfTsc" \ |
814 | "\35" "L2IPERFC" "\36" "MWAITX" "\37" "AddrMaskExt" "\40" "B31" | | 815 | "\35" "L2IPERFC" "\36" "MWAITX" "\37" "AddrMaskExt" "\40" "B31" |
815 | | | 816 | |
816 | /* | | 817 | /* |
817 | * Advanced Power Management and RAS. | | 818 | * Advanced Power Management and RAS. |
818 | * CPUID Fn8000_0007 | | 819 | * CPUID Fn8000_0007 |
819 | * | | 820 | * |
820 | * Only ITSC is for both Intel and AMD. Others are only for AMD. | | 821 | * Only ITSC is for both Intel and AMD. Others are only for AMD. |
821 | * | | 822 | * |
822 | * %ebx: RAS capabilities. See below. | | 823 | * %ebx: RAS capabilities. See below. |
823 | * %ecx: Processor Power Monitoring Interface. | | 824 | * %ecx: Processor Power Monitoring Interface. |
824 | * %edx: See below. | | 825 | * %edx: See below. |
825 | * | | 826 | * |
826 | */ | | 827 | */ |
827 | /* %ebx */ | | 828 | /* %ebx */ |
828 | #define CPUID_RAS_OVFL_RECOV __BIT(0) /* MCA Overflow Recovery */ | | 829 | #define CPUID_RAS_OVFL_RECOV __BIT(0) /* MCA Overflow Recovery */ |
829 | #define CPUID_RAS_SUCCOR __BIT(1) /* Sw UnCorr. err. COntainment & Recovery */ | | 830 | #define CPUID_RAS_SUCCOR __BIT(1) /* Sw UnCorr. err. COntainment & Recovery */ |
830 | #define CPUID_RAS_MCAX __BIT(3) /* MCA Extension */ | | 831 | #define CPUID_RAS_MCAX __BIT(3) /* MCA Extension */ |
831 | | | 832 | |
832 | #define CPUID_RAS_FLAGS "\20" \ | | 833 | #define CPUID_RAS_FLAGS "\20" \ |
833 | "\1OVFL_RECOV" "\2SUCCOR" "\4" "MCAX" | | 834 | "\1OVFL_RECOV" "\2SUCCOR" "\4" "MCAX" |
834 | | | 835 | |
835 | /* %edx */ | | 836 | /* %edx */ |
836 | #define CPUID_APM_TS __BIT(0) /* Temperature Sensor */ | | 837 | #define CPUID_APM_TS __BIT(0) /* Temperature Sensor */ |
837 | #define CPUID_APM_FID __BIT(1) /* Frequency ID control */ | | 838 | #define CPUID_APM_FID __BIT(1) /* Frequency ID control */ |
838 | #define CPUID_APM_VID __BIT(2) /* Voltage ID control */ | | 839 | #define CPUID_APM_VID __BIT(2) /* Voltage ID control */ |
839 | #define CPUID_APM_TTP __BIT(3) /* THERMTRIP (PCI F3xE4 register) */ | | 840 | #define CPUID_APM_TTP __BIT(3) /* THERMTRIP (PCI F3xE4 register) */ |
840 | #define CPUID_APM_HTC __BIT(4) /* Hardware thermal control (HTC) */ | | 841 | #define CPUID_APM_HTC __BIT(4) /* Hardware thermal control (HTC) */ |
841 | #define CPUID_APM_STC __BIT(5) /* Software thermal control (STC) */ | | 842 | #define CPUID_APM_STC __BIT(5) /* Software thermal control (STC) */ |
842 | #define CPUID_APM_100 __BIT(6) /* 100MHz multiplier control */ | | 843 | #define CPUID_APM_100 __BIT(6) /* 100MHz multiplier control */ |
843 | #define CPUID_APM_HWP __BIT(7) /* HW P-State control */ | | 844 | #define CPUID_APM_HWP __BIT(7) /* HW P-State control */ |
844 | #define CPUID_APM_ITSC __BIT(8) /* Invariant TSC */ | | 845 | #define CPUID_APM_ITSC __BIT(8) /* Invariant TSC */ |
845 | #define CPUID_APM_CPB __BIT(9) /* Core Performance Boost */ | | 846 | #define CPUID_APM_CPB __BIT(9) /* Core Performance Boost */ |
846 | #define CPUID_APM_EFF __BIT(10) /* Effective Frequency (read-only) */ | | 847 | #define CPUID_APM_EFF __BIT(10) /* Effective Frequency (read-only) */ |
847 | #define CPUID_APM_PROCFI __BIT(11) /* Processor Feedback Interface */ | | 848 | #define CPUID_APM_PROCFI __BIT(11) /* Processor Feedback Interface */ |
848 | #define CPUID_APM_PROCPR __BIT(12) /* Processor Power Reporting */ | | 849 | #define CPUID_APM_PROCPR __BIT(12) /* Processor Power Reporting */ |
849 | #define CPUID_APM_CONNSTBY __BIT(13) /* Connected Standby */ | | 850 | #define CPUID_APM_CONNSTBY __BIT(13) /* Connected Standby */ |
850 | #define CPUID_APM_RAPL __BIT(14) /* Running Average Power Limit */ | | 851 | #define CPUID_APM_RAPL __BIT(14) /* Running Average Power Limit */ |
851 | | | 852 | |
852 | #define CPUID_APM_FLAGS "\20" \ | | 853 | #define CPUID_APM_FLAGS "\20" \ |
853 | "\1" "TS" "\2" "FID" "\3" "VID" "\4" "TTP" \ | | 854 | "\1" "TS" "\2" "FID" "\3" "VID" "\4" "TTP" \ |
854 | "\5" "HTC" "\6" "STC" "\7" "100" "\10" "HWP" \ | | 855 | "\5" "HTC" "\6" "STC" "\7" "100" "\10" "HWP" \ |
855 | "\11" "ITSC" "\12" "CPB" "\13" "EffFreq" "\14" "PROCFI" \ | | 856 | "\11" "ITSC" "\12" "CPB" "\13" "EffFreq" "\14" "PROCFI" \ |
856 | "\15" "PROCPR" "\16" "CONNSTBY" "\17" "RAPL" | | 857 | "\15" "PROCPR" "\16" "CONNSTBY" "\17" "RAPL" |
857 | | | 858 | |
858 | /* | | 859 | /* |
859 | * AMD Processor Capacity Parameters and Extended Features. | | 860 | * AMD Processor Capacity Parameters and Extended Features. |
860 | * CPUID Fn8000_0008 | | 861 | * CPUID Fn8000_0008 |
861 | * %eax: Long Mode Size Identifiers | | 862 | * %eax: Long Mode Size Identifiers |
862 | * %ebx: Extended Feature Identifiers | | 863 | * %ebx: Extended Feature Identifiers |
863 | * %ecx: Size Identifiers | | 864 | * %ecx: Size Identifiers |
864 | * %edx: RDPRU Register Identifier Range | | 865 | * %edx: RDPRU Register Identifier Range |
865 | */ | | 866 | */ |
866 | | | 867 | |
867 | /* %ebx */ | | 868 | /* %ebx */ |
868 | #define CPUID_CAPEX_CLZERO __BIT(0) /* CLZERO instruction */ | | 869 | #define CPUID_CAPEX_CLZERO __BIT(0) /* CLZERO instruction */ |
869 | #define CPUID_CAPEX_IRPERF __BIT(1) /* InstRetCntMsr */ | | 870 | #define CPUID_CAPEX_IRPERF __BIT(1) /* InstRetCntMsr */ |
870 | #define CPUID_CAPEX_XSAVEERPTR __BIT(2) /* RstrFpErrPtrs by XRSTOR */ | | 871 | #define CPUID_CAPEX_XSAVEERPTR __BIT(2) /* RstrFpErrPtrs by XRSTOR */ |
871 | #define CPUID_CAPEX_INVLPGB __BIT(3) /* INVLPGB instruction */ | | 872 | #define CPUID_CAPEX_INVLPGB __BIT(3) /* INVLPGB instruction */ |
872 | #define CPUID_CAPEX_RDPRU __BIT(4) /* RDPRU instruction */ | | 873 | #define CPUID_CAPEX_RDPRU __BIT(4) /* RDPRU instruction */ |
873 | #define CPUID_CAPEX_MBE __BIT(6) /* Memory Bandwidth Enforcement */ | | 874 | #define CPUID_CAPEX_MBE __BIT(6) /* Memory Bandwidth Enforcement */ |
874 | #define CPUID_CAPEX_MCOMMIT __BIT(8) /* MCOMMIT instruction */ | | 875 | #define CPUID_CAPEX_MCOMMIT __BIT(8) /* MCOMMIT instruction */ |
875 | #define CPUID_CAPEX_WBNOINVD __BIT(9) /* WBNOINVD instruction */ | | 876 | #define CPUID_CAPEX_WBNOINVD __BIT(9) /* WBNOINVD instruction */ |
876 | #define CPUID_CAPEX_IBPB __BIT(12) /* Speculation Control IBPB */ | | 877 | #define CPUID_CAPEX_IBPB __BIT(12) /* Speculation Control IBPB */ |
877 | #define CPUID_CAPEX_INT_WBINVD __BIT(13) /* Interruptable WB[NO]INVD */ | | 878 | #define CPUID_CAPEX_INT_WBINVD __BIT(13) /* Interruptable WB[NO]INVD */ |
878 | #define CPUID_CAPEX_IBRS __BIT(14) /* Speculation Control IBRS */ | | 879 | #define CPUID_CAPEX_IBRS __BIT(14) /* Speculation Control IBRS */ |
879 | #define CPUID_CAPEX_STIBP __BIT(15) /* Speculation Control STIBP */ | | 880 | #define CPUID_CAPEX_STIBP __BIT(15) /* Speculation Control STIBP */ |
880 | #define CPUID_CAPEX_IBRS_ALWAYSON __BIT(16) /* IBRS always on mode */ | | 881 | #define CPUID_CAPEX_IBRS_ALWAYSON __BIT(16) /* IBRS always on mode */ |
881 | #define CPUID_CAPEX_STIBP_ALWAYSON __BIT(17) /* STIBP always on mode */ | | 882 | #define CPUID_CAPEX_STIBP_ALWAYSON __BIT(17) /* STIBP always on mode */ |
882 | #define CPUID_CAPEX_PREFER_IBRS __BIT(18) /* IBRS preferred */ | | 883 | #define CPUID_CAPEX_PREFER_IBRS __BIT(18) /* IBRS preferred */ |
883 | #define CPUID_CAPEX_IBRS_SAMEMODE __BIT(19) /* IBRS same speculation limits */ | | 884 | #define CPUID_CAPEX_IBRS_SAMEMODE __BIT(19) /* IBRS same speculation limits */ |
884 | #define CPUID_CAPEX_EFER_LSMSLE_UN __BIT(20) /* EFER.LMSLE is unsupported */ | | 885 | #define CPUID_CAPEX_EFER_LSMSLE_UN __BIT(20) /* EFER.LMSLE is unsupported */ |
885 | #define CPUID_CAPEX_AMD_PPIN __BIT(23) /* Protected Processor Inventory Number */ | | 886 | #define CPUID_CAPEX_AMD_PPIN __BIT(23) /* Protected Processor Inventory Number */ |
886 | #define CPUID_CAPEX_SSBD __BIT(24) /* Speculation Control SSBD */ | | 887 | #define CPUID_CAPEX_SSBD __BIT(24) /* Speculation Control SSBD */ |
887 | #define CPUID_CAPEX_VIRT_SSBD __BIT(25) /* Virt Spec Control SSBD */ | | 888 | #define CPUID_CAPEX_VIRT_SSBD __BIT(25) /* Virt Spec Control SSBD */ |
888 | #define CPUID_CAPEX_SSB_NO __BIT(26) /* SSBD not required */ | | 889 | #define CPUID_CAPEX_SSB_NO __BIT(26) /* SSBD not required */ |
889 | #define CPUID_CAPEX_CPPC __BIT(27) /* Collaborative Processor Perf. Control */ | | 890 | #define CPUID_CAPEX_CPPC __BIT(27) /* Collaborative Processor Perf. Control */ |
890 | #define CPUID_CAPEX_PSFD __BIT(28) /* Predictive Store Forward Dis */ | | 891 | #define CPUID_CAPEX_PSFD __BIT(28) /* Predictive Store Forward Dis */ |
891 | #define CPUID_CAPEX_BTC_NO __BIT(29) /* Branch Type Confusion NO */ | | 892 | #define CPUID_CAPEX_BTC_NO __BIT(29) /* Branch Type Confusion NO */ |
892 | | | 893 | |
893 | #define CPUID_CAPEX_FLAGS "\20" \ | | 894 | #define CPUID_CAPEX_FLAGS "\20" \ |
894 | "\1CLZERO" "\2IRPERF" "\3XSAVEERPTR" "\4INVLPGB" \ | | 895 | "\1CLZERO" "\2IRPERF" "\3XSAVEERPTR" "\4INVLPGB" \ |
895 | "\5RDPRU" "\7MBE" \ | | 896 | "\5RDPRU" "\7MBE" \ |
896 | "\11MCOMMIT" "\12WBNOINVD" "\13B10" \ | | 897 | "\11MCOMMIT" "\12WBNOINVD" "\13B10" \ |
897 | "\15IBPB" "\16INT_WBINVD" "\17IBRS" "\20STIBP" \ | | 898 | "\15IBPB" "\16INT_WBINVD" "\17IBRS" "\20STIBP" \ |
898 | "\21IBRS_ALWAYSON" "\22STIBP_ALWAYSON" "\23PREFER_IBRS" \ | | 899 | "\21IBRS_ALWAYSON" "\22STIBP_ALWAYSON" "\23PREFER_IBRS" \ |
899 | "\24IBRS_SAMEMODE" \ | | 900 | "\24IBRS_SAMEMODE" \ |
900 | "\25EFER_LSMSLE_UN" "\30PPIN" \ | | 901 | "\25EFER_LSMSLE_UN" "\30PPIN" \ |
901 | "\31SSBD" "\32VIRT_SSBD" "\33SSB_NO" "\34CPPC" \ | | 902 | "\31SSBD" "\32VIRT_SSBD" "\33SSB_NO" "\34CPPC" \ |
902 | "\35PSFD" "\36BTC_NO" | | 903 | "\35PSFD" "\36BTC_NO" |
903 | | | 904 | |
904 | /* %ecx */ | | 905 | /* %ecx */ |
905 | #define CPUID_CAPEX_PerfTscSize __BITS(17,16) /* Perf. tstamp counter size */ | | 906 | #define CPUID_CAPEX_PerfTscSize __BITS(17,16) /* Perf. tstamp counter size */ |
906 | #define CPUID_CAPEX_ApicIdSize __BITS(15,12) /* APIC ID Size */ | | 907 | #define CPUID_CAPEX_ApicIdSize __BITS(15,12) /* APIC ID Size */ |
907 | #define CPUID_CAPEX_NC __BITS(7,0) /* Number of threads - 1 */ | | 908 | #define CPUID_CAPEX_NC __BITS(7,0) /* Number of threads - 1 */ |
908 | | | 909 | |
909 | /* | | 910 | /* |
910 | * AMD SVM Revision and Feature. | | 911 | * AMD SVM Revision and Feature. |
911 | * CPUID Fn8000_000a | | 912 | * CPUID Fn8000_000a |
912 | */ | | 913 | */ |
913 | | | 914 | |
914 | /* %eax: SVM revision */ | | 915 | /* %eax: SVM revision */ |
915 | #define CPUID_AMD_SVM_REV __BITS(7,0) | | 916 | #define CPUID_AMD_SVM_REV __BITS(7,0) |
916 | | | 917 | |
917 | /* %edx: SVM features */ | | 918 | /* %edx: SVM features */ |
918 | #define CPUID_AMD_SVM_NP __BIT(0) /* Nested Paging */ | | 919 | #define CPUID_AMD_SVM_NP __BIT(0) /* Nested Paging */ |
919 | #define CPUID_AMD_SVM_LbrVirt __BIT(1) /* LBR virtualization */ | | 920 | #define CPUID_AMD_SVM_LbrVirt __BIT(1) /* LBR virtualization */ |
920 | #define CPUID_AMD_SVM_SVML __BIT(2) /* SVM Lock */ | | 921 | #define CPUID_AMD_SVM_SVML __BIT(2) /* SVM Lock */ |
921 | #define CPUID_AMD_SVM_NRIPS __BIT(3) /* NRIP Save on #VMEXIT */ | | 922 | #define CPUID_AMD_SVM_NRIPS __BIT(3) /* NRIP Save on #VMEXIT */ |
922 | #define CPUID_AMD_SVM_TSCRateCtrl __BIT(4) /* MSR-based TSC rate ctrl */ | | 923 | #define CPUID_AMD_SVM_TSCRateCtrl __BIT(4) /* MSR-based TSC rate ctrl */ |
923 | #define CPUID_AMD_SVM_VMCBCleanBits __BIT(5) /* VMCB Clean Bits support */ | | 924 | #define CPUID_AMD_SVM_VMCBCleanBits __BIT(5) /* VMCB Clean Bits support */ |
924 | #define CPUID_AMD_SVM_FlushByASID __BIT(6) /* Flush by ASID */ | | 925 | #define CPUID_AMD_SVM_FlushByASID __BIT(6) /* Flush by ASID */ |
925 | #define CPUID_AMD_SVM_DecodeAssist __BIT(7) /* Decode Assists support */ | | 926 | #define CPUID_AMD_SVM_DecodeAssist __BIT(7) /* Decode Assists support */ |
926 | #define CPUID_AMD_SVM_PauseFilter __BIT(10) /* PAUSE intercept filter */ | | 927 | #define CPUID_AMD_SVM_PauseFilter __BIT(10) /* PAUSE intercept filter */ |
927 | #define CPUID_AMD_SVM_PFThreshold __BIT(12) /* PAUSE filter threshold */ | | 928 | #define CPUID_AMD_SVM_PFThreshold __BIT(12) /* PAUSE filter threshold */ |
928 | #define CPUID_AMD_SVM_AVIC __BIT(13) /* Advanced Virt. Intr. Ctrl */ | | 929 | #define CPUID_AMD_SVM_AVIC __BIT(13) /* Advanced Virt. Intr. Ctrl */ |
929 | #define CPUID_AMD_SVM_V_VMSAVE_VMLOAD __BIT(15) /* Virtual VM{SAVE/LOAD} */ | | 930 | #define CPUID_AMD_SVM_V_VMSAVE_VMLOAD __BIT(15) /* Virtual VM{SAVE/LOAD} */ |
930 | #define CPUID_AMD_SVM_vGIF __BIT(16) /* Virtualized GIF */ | | 931 | #define CPUID_AMD_SVM_vGIF __BIT(16) /* Virtualized GIF */ |
931 | #define CPUID_AMD_SVM_GMET __BIT(17) /* Guest Mode Execution Trap */ | | 932 | #define CPUID_AMD_SVM_GMET __BIT(17) /* Guest Mode Execution Trap */ |
932 | #define CPUID_AMD_SVM_X2AVIC __BIT(18) /* Virt. Intr. Ctrl 4 x2APIC */ | | 933 | #define CPUID_AMD_SVM_X2AVIC __BIT(18) /* Virt. Intr. Ctrl 4 x2APIC */ |
933 | #define CPUID_AMD_SVM_SSSCHECK __BIT(19) /* Shadow Stack restrictions */ | | 934 | #define CPUID_AMD_SVM_SSSCHECK __BIT(19) /* Shadow Stack restrictions */ |
934 | #define CPUID_AMD_SVM_SPEC_CTRL __BIT(20) /* SPEC_CTRL virtualization */ | | 935 | #define CPUID_AMD_SVM_SPEC_CTRL __BIT(20) /* SPEC_CTRL virtualization */ |
935 | #define CPUID_AMD_SVM_ROGPT __BIT(21) /* Read-Only Guest PTable */ | | 936 | #define CPUID_AMD_SVM_ROGPT __BIT(21) /* Read-Only Guest PTable */ |
936 | #define CPUID_AMD_SVM_HOST_MCE_OVERRIDE __BIT(23) /* #MC intercept */ | | 937 | #define CPUID_AMD_SVM_HOST_MCE_OVERRIDE __BIT(23) /* #MC intercept */ |
937 | #define CPUID_AMD_SVM_TLBICTL __BIT(24) /* TLB Intercept Control */ | | 938 | #define CPUID_AMD_SVM_TLBICTL __BIT(24) /* TLB Intercept Control */ |
938 | #define CPUID_AMD_SVM_VNMI __BIT(25) /* NMI Virtualization */ | | 939 | #define CPUID_AMD_SVM_VNMI __BIT(25) /* NMI Virtualization */ |
939 | #define CPUID_AMD_SVM_IBSVIRT __BIT(26) /* IBS Virtualization */ | | 940 | #define CPUID_AMD_SVM_IBSVIRT __BIT(26) /* IBS Virtualization */ |
940 | #define CPUID_AMD_SVM_XLVTOFFFLTCHG __BIT(27) /* Ext LVToffset FLT changed */ | | 941 | #define CPUID_AMD_SVM_XLVTOFFFLTCHG __BIT(27) /* Ext LVToffset FLT changed */ |
941 | #define CPUID_AMD_SVM_VMCBADRCHKCHG __BIT(28) /* VMCB addr check changed */ | | 942 | #define CPUID_AMD_SVM_VMCBADRCHKCHG __BIT(28) /* VMCB addr check changed */ |
942 | | | 943 | |
943 | | | 944 | |
944 | #define CPUID_AMD_SVM_FLAGS "\20" \ | | 945 | #define CPUID_AMD_SVM_FLAGS "\20" \ |
945 | "\1" "NP" "\2" "LbrVirt" "\3" "SVML" "\4" "NRIPS" \ | | 946 | "\1" "NP" "\2" "LbrVirt" "\3" "SVML" "\4" "NRIPS" \ |
946 | "\5" "TSCRate" "\6" "VMCBCleanBits" \ | | 947 | "\5" "TSCRate" "\6" "VMCBCleanBits" \ |
947 | "\7" "FlushByASID" "\10" "DecodeAssist" \ | | 948 | "\7" "FlushByASID" "\10" "DecodeAssist" \ |
948 | "\11" "B08" "\12" "B09" "\13" "PauseFilter" "\14" "B11" \ | | 949 | "\11" "B08" "\12" "B09" "\13" "PauseFilter" "\14" "B11" \ |
949 | "\15" "PFThreshold" "\16" "AVIC" "\17" "B14" \ | | 950 | "\15" "PFThreshold" "\16" "AVIC" "\17" "B14" \ |
950 | "\20" "V_VMSAVE_VMLOAD" \ | | 951 | "\20" "V_VMSAVE_VMLOAD" \ |
951 | "\21" "VGIF" "\22" "GMET" "\23x2AVIC" "\24SSSCHECK" \ | | 952 | "\21" "VGIF" "\22" "GMET" "\23x2AVIC" "\24SSSCHECK" \ |
952 | "\25" "SPEC_CTRL" "\26" "ROGPT" "\30HOST_MCE_OVERRIDE" \ | | 953 | "\25" "SPEC_CTRL" "\26" "ROGPT" "\30HOST_MCE_OVERRIDE" \ |
953 | "\31" "TLBICTL" "\32VNMI" "\33IBSVIRT" "\34ExtLvtOffsetFaultChg" \ | | 954 | "\31" "TLBICTL" "\32VNMI" "\33IBSVIRT" "\34ExtLvtOffsetFaultChg" \ |
954 | "\35VmcbAddrChkChg" | | 955 | "\35VmcbAddrChkChg" |
955 | | | 956 | |
956 | /* | | 957 | /* |
957 | * AMD Instruction-Based Sampling Capabilities. | | 958 | * AMD Instruction-Based Sampling Capabilities. |
958 | * CPUID Fn8000_001b | | 959 | * CPUID Fn8000_001b |
959 | */ | | 960 | */ |
960 | /* %eax */ | | 961 | /* %eax */ |
961 | #define CPUID_IBS_FFV __BIT(0) /* Feature Flags Valid */ | | 962 | #define CPUID_IBS_FFV __BIT(0) /* Feature Flags Valid */ |
962 | #define CPUID_IBS_FETCHSUM __BIT(1) /* Fetch Sampling */ | | 963 | #define CPUID_IBS_FETCHSUM __BIT(1) /* Fetch Sampling */ |
963 | #define CPUID_IBS_OPSAM __BIT(2) /* execution SAMpling */ | | 964 | #define CPUID_IBS_OPSAM __BIT(2) /* execution SAMpling */ |
964 | #define CPUID_IBS_RDWROPCNT __BIT(3) /* Read Write of Op Counter */ | | 965 | #define CPUID_IBS_RDWROPCNT __BIT(3) /* Read Write of Op Counter */ |
965 | #define CPUID_IBS_OPCNT __BIT(4) /* OP CouNTing mode */ | | 966 | #define CPUID_IBS_OPCNT __BIT(4) /* OP CouNTing mode */ |
966 | #define CPUID_IBS_BRNTRGT __BIT(5) /* Branch Target */ | | 967 | #define CPUID_IBS_BRNTRGT __BIT(5) /* Branch Target */ |
967 | #define CPUID_IBS_OPCNTEXT __BIT(6) /* OpCurCnt and OpMaxCnt extended */ | | 968 | #define CPUID_IBS_OPCNTEXT __BIT(6) /* OpCurCnt and OpMaxCnt extended */ |
968 | #define CPUID_IBS_RIPINVALIDCHK __BIT(7) /* Invalid RIP indication */ | | 969 | #define CPUID_IBS_RIPINVALIDCHK __BIT(7) /* Invalid RIP indication */ |
969 | #define CPUID_IBS_OPBRNFUSE __BIT(8) /* Fused branch micro-op indicate */ | | 970 | #define CPUID_IBS_OPBRNFUSE __BIT(8) /* Fused branch micro-op indicate */ |
970 | #define CPUID_IBS_FETCHCTLEXTD __BIT(9) /* IC_IBS_EXTD_CTL MSR */ | | 971 | #define CPUID_IBS_FETCHCTLEXTD __BIT(9) /* IC_IBS_EXTD_CTL MSR */ |
971 | #define CPUID_IBS_OPDATA4 __BIT(10) /* IBS op data 4 MSR */ | | 972 | #define CPUID_IBS_OPDATA4 __BIT(10) /* IBS op data 4 MSR */ |
972 | #define CPUID_IBS_L3MISSFILT __BIT(11) /* L3 Miss Filtering */ | | 973 | #define CPUID_IBS_L3MISSFILT __BIT(11) /* L3 Miss Filtering */ |
973 | | | 974 | |
974 | #define CPUID_IBS_FLAGS "\20" \ | | 975 | #define CPUID_IBS_FLAGS "\20" \ |
975 | "\1IBSFFV" "\2FetchSam" "\3OpSam" "\4RdWrOpCnt" \ | | 976 | "\1IBSFFV" "\2FetchSam" "\3OpSam" "\4RdWrOpCnt" \ |
976 | "\5OpCnt" "\6BrnTrgt" "\7OpCntExt" "\10RipInvalidChk" \ | | 977 | "\5OpCnt" "\6BrnTrgt" "\7OpCntExt" "\10RipInvalidChk" \ |
977 | "\11OpBrnFuse" "\12IbsFetchCtlExtd" "\13IbsOpData4" \ | | 978 | "\11OpBrnFuse" "\12IbsFetchCtlExtd" "\13IbsOpData4" \ |
978 | "\14IbsL3MissFiltering" | | 979 | "\14IbsL3MissFiltering" |
979 | | | 980 | |
980 | /* | | 981 | /* |
981 | * AMD Cache Topology Information. | | 982 | * AMD Cache Topology Information. |
982 | * CPUID Fn8000_001d | | 983 | * CPUID Fn8000_001d |
983 | * It's almost the same as Intel Deterministic Cache Parameter Leaf(0x04) | | 984 | * It's almost the same as Intel Deterministic Cache Parameter Leaf(0x04) |
984 | * except the following: | | 985 | * except the following: |
985 | * No Cores/package (%eax bit 31..26) | | 986 | * No Cores/package (%eax bit 31..26) |
986 | * No Complex cache indexing (%edx bit 2) | | 987 | * No Complex cache indexing (%edx bit 2) |
987 | */ | | 988 | */ |
988 | | | 989 | |
989 | /* | | 990 | /* |
990 | * AMD Processor Topology Information. | | 991 | * AMD Processor Topology Information. |
991 | * CPUID Fn8000_001e | | 992 | * CPUID Fn8000_001e |
992 | * %eax: Extended APIC ID. | | 993 | * %eax: Extended APIC ID. |
993 | * %ebx: Core Identifiers. | | 994 | * %ebx: Core Identifiers. |
994 | * %ecx: Node Identifiers. | | 995 | * %ecx: Node Identifiers. |
995 | */ | | 996 | */ |
996 | | | 997 | |
997 | /* %ebx */ | | 998 | /* %ebx */ |
998 | #define CPUID_AMD_PROCT_COREID __BITS(7,0) /* Core ID */ | | 999 | #define CPUID_AMD_PROCT_COREID __BITS(7,0) /* Core ID */ |
999 | #define CPUID_AMD_PROCT_THREADS_PER_CORE __BITS(15,8) /* Threads/Core - 1 */ | | 1000 | #define CPUID_AMD_PROCT_THREADS_PER_CORE __BITS(15,8) /* Threads/Core - 1 */ |
1000 | | | 1001 | |
1001 | /* %ecx */ | | 1002 | /* %ecx */ |
1002 | #define CPUID_AMD_PROCT_NODEID __BITS(7,0) /* Node ID */ | | 1003 | #define CPUID_AMD_PROCT_NODEID __BITS(7,0) /* Node ID */ |
1003 | #define CPUID_AMD_PROCT_NODE_PER_PROCESSOR __BITS(10,8) /* Node/Processor -1 */ | | 1004 | #define CPUID_AMD_PROCT_NODE_PER_PROCESSOR __BITS(10,8) /* Node/Processor -1 */ |
1004 | | | 1005 | |
1005 | /* | | 1006 | /* |
1006 | * AMD Encrypted Memory Capabilities. | | 1007 | * AMD Encrypted Memory Capabilities. |
1007 | * CPUID Fn8000_001f | | 1008 | * CPUID Fn8000_001f |
1008 | * %eax: flags | | 1009 | * %eax: flags |
1009 | * %ebx: 5-0: Cbit Position | | 1010 | * %ebx: 5-0: Cbit Position |
1010 | * 11-6: PhysAddrReduction | | 1011 | * 11-6: PhysAddrReduction |
1011 | * 15-12: NumVMPL | | 1012 | * 15-12: NumVMPL |
1012 | * %ecx: 31-0: NumEncryptedGuests | | 1013 | * %ecx: 31-0: NumEncryptedGuests |
1013 | * %edx: 31-0: MinSevNoEsAsid | | 1014 | * %edx: 31-0: MinSevNoEsAsid |
1014 | */ | | 1015 | */ |
1015 | #define CPUID_AMD_ENCMEM_SME __BIT(0) /* Secure Memory Encryption */ | | 1016 | #define CPUID_AMD_ENCMEM_SME __BIT(0) /* Secure Memory Encryption */ |
1016 | #define CPUID_AMD_ENCMEM_SEV __BIT(1) /* Secure Encrypted Virtualiz. */ | | 1017 | #define CPUID_AMD_ENCMEM_SEV __BIT(1) /* Secure Encrypted Virtualiz. */ |
1017 | #define CPUID_AMD_ENCMEM_PGFLMSR __BIT(2) /* Page Flush MSR */ | | 1018 | #define CPUID_AMD_ENCMEM_PGFLMSR __BIT(2) /* Page Flush MSR */ |
1018 | #define CPUID_AMD_ENCMEM_SEVES __BIT(3) /* SEV Encrypted State */ | | 1019 | #define CPUID_AMD_ENCMEM_SEVES __BIT(3) /* SEV Encrypted State */ |
1019 | #define CPUID_AMD_ENCMEM_SEV_SNP __BIT(4) /* Secure Nested Paging */ | | 1020 | #define CPUID_AMD_ENCMEM_SEV_SNP __BIT(4) /* Secure Nested Paging */ |
1020 | #define CPUID_AMD_ENCMEM_VMPL __BIT(5) /* Virtual Machine Privilege Lvl */ | | 1021 | #define CPUID_AMD_ENCMEM_VMPL __BIT(5) /* Virtual Machine Privilege Lvl */ |
1021 | #define CPUID_AMD_ENCMEM_RPMQUERY __BIT(6) /* RMPQUERY instruction */ | | 1022 | #define CPUID_AMD_ENCMEM_RPMQUERY __BIT(6) /* RMPQUERY instruction */ |
1022 | #define CPUID_AMD_ENCMEM_VMPLSSS __BIT(7) /* VMPL Secure Shadow Stack */ | | 1023 | #define CPUID_AMD_ENCMEM_VMPLSSS __BIT(7) /* VMPL Secure Shadow Stack */ |
1023 | #define CPUID_AMD_ENCMEM_SECTSC __BIT(8) /* Secure TSC */ | | 1024 | #define CPUID_AMD_ENCMEM_SECTSC __BIT(8) /* Secure TSC */ |
1024 | #define CPUID_AMD_ENCMEM_TSCAUX_V __BIT(9) /* TSC AUX Virtualization */ | | 1025 | #define CPUID_AMD_ENCMEM_TSCAUX_V __BIT(9) /* TSC AUX Virtualization */ |
1025 | #define CPUID_AMD_ENCMEM_HECC __BIT(10) /* HW Enf Cache Coh across enc dom */ | | 1026 | #define CPUID_AMD_ENCMEM_HECC __BIT(10) /* HW Enf Cache Coh across enc dom */ |
1026 | #define CPUID_AMD_ENCMEM_64BH __BIT(11) /* 64Bit Host */ | | 1027 | #define CPUID_AMD_ENCMEM_64BH __BIT(11) /* 64Bit Host */ |
1027 | #define CPUID_AMD_ENCMEM_RSTRINJ __BIT(12) /* Restricted Injection */ | | 1028 | #define CPUID_AMD_ENCMEM_RSTRINJ __BIT(12) /* Restricted Injection */ |
1028 | #define CPUID_AMD_ENCMEM_ALTINJ __BIT(13) /* Alternate Injection */ | | 1029 | #define CPUID_AMD_ENCMEM_ALTINJ __BIT(13) /* Alternate Injection */ |
1029 | #define CPUID_AMD_ENCMEM_DBGSWAP __BIT(14) /* Debug Swap */ | | 1030 | #define CPUID_AMD_ENCMEM_DBGSWAP __BIT(14) /* Debug Swap */ |
1030 | #define CPUID_AMD_ENCMEM_PREVHOSTIBS __BIT(15) /* Prevent Host IBS */ | | 1031 | #define CPUID_AMD_ENCMEM_PREVHOSTIBS __BIT(15) /* Prevent Host IBS */ |
1031 | #define CPUID_AMD_ENCMEM_VTE __BIT(16) /* Virtual Transparent Encryption */ | | 1032 | #define CPUID_AMD_ENCMEM_VTE __BIT(16) /* Virtual Transparent Encryption */ |
1032 | | | 1033 | |
1033 | #define CPUID_AMD_ENCMEM_VMGEXITP __BIT(17) /* VMGEXIT Parameter */ | | 1034 | #define CPUID_AMD_ENCMEM_VMGEXITP __BIT(17) /* VMGEXIT Parameter */ |
1034 | #define CPUID_AMD_ENCMEM_VIRTTOM __BIT(18) /* Virtual TOM MSR */ | | 1035 | #define CPUID_AMD_ENCMEM_VIRTTOM __BIT(18) /* Virtual TOM MSR */ |
1035 | #define CPUID_AMD_ENCMEM_IBSVGUEST __BIT(19) /* IBS Virt. for SEV-ES guest */ | | 1036 | #define CPUID_AMD_ENCMEM_IBSVGUEST __BIT(19) /* IBS Virt. for SEV-ES guest */ |
1036 | #define CPUID_AMD_ENCMEM_VMSA_REGPROT __BIT(24) /* VmsaRegProt */ | | 1037 | #define CPUID_AMD_ENCMEM_VMSA_REGPROT __BIT(24) /* VmsaRegProt */ |
1037 | #define CPUID_AMD_ENCMEM_SMTPROTECT __BIT(25) /* SMT Protection */ | | 1038 | #define CPUID_AMD_ENCMEM_SMTPROTECT __BIT(25) /* SMT Protection */ |
1038 | #define CPUID_AMD_ENCMEM_SVSM_COMMPAGE __BIT(28) /* SVSM Communication Page */ | | 1039 | #define CPUID_AMD_ENCMEM_SVSM_COMMPAGE __BIT(28) /* SVSM Communication Page */ |
1039 | #define CPUID_AMD_ENCMEM_NESTED_VSMP __BIT(29) /* VIRT_{RMPUPDATE,PSMASH} */ | | 1040 | #define CPUID_AMD_ENCMEM_NESTED_VSMP __BIT(29) /* VIRT_{RMPUPDATE,PSMASH} */ |
1040 | | | 1041 | |
1041 | #define CPUID_AMD_ENCMEM_FLAGS "\20" \ | | 1042 | #define CPUID_AMD_ENCMEM_FLAGS "\20" \ |
1042 | "\1" "SME" "\2" "SEV" "\3" "PageFlushMsr" "\4" "SEV-ES" \ | | 1043 | "\1" "SME" "\2" "SEV" "\3" "PageFlushMsr" "\4" "SEV-ES" \ |
1043 | "\5" "SEV-SNP" "\6" "VMPL" "\7RMPQUERY" "\10VmplSSS" \ | | 1044 | "\5" "SEV-SNP" "\6" "VMPL" "\7RMPQUERY" "\10VmplSSS" \ |
1044 | "\11SecureTSC" "\12TscAuxVirt" "\13HwEnfCacheCoh" "\14" "64BitHost" \ | | 1045 | "\11SecureTSC" "\12TscAuxVirt" "\13HwEnfCacheCoh" "\14" "64BitHost" \ |
1045 | "\15" "RSTRINJ" "\16" "ALTINJ" "\17" "DebugSwap" "\20PreventHostIbs" \ | | 1046 | "\15" "RSTRINJ" "\16" "ALTINJ" "\17" "DebugSwap" "\20PreventHostIbs" \ |
1046 | "\21VTE" "\22VmgexitParam" "\23VirtualTomMsr" "\24IbsVirtGuest" \ | | 1047 | "\21VTE" "\22VmgexitParam" "\23VirtualTomMsr" "\24IbsVirtGuest" \ |
1047 | "\31VmsaRegProt" "\32SmtProtection" \ | | 1048 | "\31VmsaRegProt" "\32SmtProtection" \ |
1048 | "\35SvsmCommPageMSR" "\36NestedVirtSnpMsr" | | 1049 | "\35SvsmCommPageMSR" "\36NestedVirtSnpMsr" |
1049 | | | 1050 | |
1050 | /* | | 1051 | /* |
1051 | * AMD Extended Features 2. | | 1052 | * AMD Extended Features 2. |
1052 | * CPUID Fn8000_0021 | | 1053 | * CPUID Fn8000_0021 |
1053 | */ | | 1054 | */ |
1054 | | | 1055 | |
1055 | /* %eax */ | | 1056 | /* %eax */ |
1056 | #define CPUID_AMDEXT2_NONESTEDDBP __BIT(0) /* No nested data breakpoints */ | | 1057 | #define CPUID_AMDEXT2_NONESTEDDBP __BIT(0) /* No nested data breakpoints */ |
1057 | #define CPUID_AMDEXT2_FGKBNOSERIAL __BIT(1) /* {FS,GS,K}BASE WRMSR !serializ */ | | 1058 | #define CPUID_AMDEXT2_FGKBNOSERIAL __BIT(1) /* {FS,GS,K}BASE WRMSR !serializ */ |
1058 | #define CPUID_AMDEXT2_LFENCESERIAL __BIT(2) /* LFENCE always serializing */ | | 1059 | #define CPUID_AMDEXT2_LFENCESERIAL __BIT(2) /* LFENCE always serializing */ |
1059 | #define CPUID_AMDEXT2_SMMPGCFGLCK __BIT(3) /* SMM Paging configuration lock */ | | 1060 | #define CPUID_AMDEXT2_SMMPGCFGLCK __BIT(3) /* SMM Paging configuration lock */ |
1060 | #define CPUID_AMDEXT2_NULLSELCLRB __BIT(6) /* Null segment selector clr base */ | | 1061 | #define CPUID_AMDEXT2_NULLSELCLRB __BIT(6) /* Null segment selector clr base */ |
1061 | #define CPUID_AMDEXT2_UPADDRIGN __BIT(7) /* Upper Address Ignore */ | | 1062 | #define CPUID_AMDEXT2_UPADDRIGN __BIT(7) /* Upper Address Ignore */ |
1062 | #define CPUID_AMDEXT2_AUTOIBRS __BIT(8) /* Automatic IBRS */ | | 1063 | #define CPUID_AMDEXT2_AUTOIBRS __BIT(8) /* Automatic IBRS */ |
1063 | #define CPUID_AMDEXT2_NOSMMCTL __BIT(9) /* SMM_CTL MSR is not supported */ | | 1064 | #define CPUID_AMDEXT2_NOSMMCTL __BIT(9) /* SMM_CTL MSR is not supported */ |
1064 | #define CPUID_AMDEXT2_FSRS __BIT(10) /* Fast Short Rep Stosb */ | | 1065 | #define CPUID_AMDEXT2_FSRS __BIT(10) /* Fast Short Rep Stosb */ |
1065 | #define CPUID_AMDEXT2_FSRC __BIT(11) /* Fast Short Rep Cmpsb */ | | 1066 | #define CPUID_AMDEXT2_FSRC __BIT(11) /* Fast Short Rep Cmpsb */ |
1066 | #define CPUID_AMDEXT2_PREFETCHCTL __BIT(13) /* Prefetch control MSR */ | | 1067 | #define CPUID_AMDEXT2_PREFETCHCTL __BIT(13) /* Prefetch control MSR */ |
1067 | #define CPUID_AMDEXT2_CPUIDUSRDIS __BIT(17) /* CPUID dis. for non-priv. soft */ | | 1068 | #define CPUID_AMDEXT2_CPUIDUSRDIS __BIT(17) /* CPUID dis. for non-priv. soft */ |
1068 | #define CPUID_AMDEXT2_EPSF __BIT(18) /* Enhanced Predictive Store Fwd */ | | 1069 | #define CPUID_AMDEXT2_EPSF __BIT(18) /* Enhanced Predictive Store Fwd */ |
1069 | | | 1070 | |
1070 | #define CPUID_AMDEXT2_FLAGS "\20" \ | | 1071 | #define CPUID_AMDEXT2_FLAGS "\20" \ |
1071 | "\1NoNestedDataBp" "\2FsGsKernelGsBaseNonSerializing" \ | | 1072 | "\1NoNestedDataBp" "\2FsGsKernelGsBaseNonSerializing" \ |
1072 | "\3LfenceAlwaysSerialize" "\4SmmPgCfgLock" \ | | 1073 | "\3LfenceAlwaysSerialize" "\4SmmPgCfgLock" \ |
1073 | "\7NullSelectClearsBase" "\10UpperAddressIgnore" \ | | 1074 | "\7NullSelectClearsBase" "\10UpperAddressIgnore" \ |
1074 | "\11AutomaticIBRS" "\12NoSmmCtlMSR" "\13FSRS" "\14FSRC" \ | | 1075 | "\11AutomaticIBRS" "\12NoSmmCtlMSR" "\13FSRS" "\14FSRC" \ |
1075 | "\16PrefetchCtlMSR" \ | | 1076 | "\16PrefetchCtlMSR" \ |
1076 | "\22CpuidUserDis" "\23EPSF" | | 1077 | "\22CpuidUserDis" "\23EPSF" |
1077 | | | 1078 | |
1078 | /* | | 1079 | /* |
1079 | * AMD Extended Performance Monitoring and Debug | | 1080 | * AMD Extended Performance Monitoring and Debug |
1080 | * CPUID Fn8000_0022 | | 1081 | * CPUID Fn8000_0022 |
1081 | */ | | 1082 | */ |
1082 | | | 1083 | |
1083 | /* %eax */ | | 1084 | /* %eax */ |
1084 | #define CPUID_AXPERF_PERFMONV2 __BIT(0) /* Version 2 */ | | 1085 | #define CPUID_AXPERF_PERFMONV2 __BIT(0) /* Version 2 */ |
1085 | #define CPUID_AXPERF_LBRSTACK __BIT(1) /* Last Branch Record Stack */ | | 1086 | #define CPUID_AXPERF_LBRSTACK __BIT(1) /* Last Branch Record Stack */ |
1086 | #define CPUID_AXPERF_LBRPMCFREEZE __BIT(2) /* Freezing LBR and PMC */ | | 1087 | #define CPUID_AXPERF_LBRPMCFREEZE __BIT(2) /* Freezing LBR and PMC */ |
1087 | | | 1088 | |
1088 | #define CPUID_AXPERF_FLAGS "\20" \ | | 1089 | #define CPUID_AXPERF_FLAGS "\20" \ |
1089 | "\1PerfMonV2" "\2LbrStack" "\3LbrAndPmcFreeze" | | 1090 | "\1PerfMonV2" "\2LbrStack" "\3LbrAndPmcFreeze" |
1090 | | | 1091 | |
1091 | /* %ebx */ | | 1092 | /* %ebx */ |
1092 | #define CPUID_AXPERF_NCPC __BITS(3, 0) /* Num of Core PMC counters */ | | 1093 | #define CPUID_AXPERF_NCPC __BITS(3, 0) /* Num of Core PMC counters */ |
1093 | #define CPUID_AXPERF_NLBRSTACK __BITS(9, 4) /* Num of LBR Stack entries */ | | 1094 | #define CPUID_AXPERF_NLBRSTACK __BITS(9, 4) /* Num of LBR Stack entries */ |
1094 | #define CPUID_AXPERF_NNBPC __BITS(15, 10) /* Num of NorthBridge PMCs */ | | 1095 | #define CPUID_AXPERF_NNBPC __BITS(15, 10) /* Num of NorthBridge PMCs */ |
1095 | #define CPUID_AXPERF_NUMCPC __BITS(21, 16) /* Num of UMC PMCs */ | | 1096 | #define CPUID_AXPERF_NUMCPC __BITS(21, 16) /* Num of UMC PMCs */ |
1096 | | | 1097 | |
1097 | /* | | 1098 | /* |
1098 | * Centaur Extended Feature flags. | | 1099 | * Centaur Extended Feature flags. |
1099 | * CPUID FnC000_0001 | | 1100 | * CPUID FnC000_0001 |
1100 | */ | | 1101 | */ |
1101 | #define CPUID_VIA_HAS_RNG __BIT(2) /* Random number generator */ | | 1102 | #define CPUID_VIA_HAS_RNG __BIT(2) /* Random number generator */ |
1102 | #define CPUID_VIA_DO_RNG __BIT(3) | | 1103 | #define CPUID_VIA_DO_RNG __BIT(3) |
1103 | #define CPUID_VIA_HAS_ACE __BIT(6) /* AES Encryption */ | | 1104 | #define CPUID_VIA_HAS_ACE __BIT(6) /* AES Encryption */ |
1104 | #define CPUID_VIA_DO_ACE __BIT(7) | | 1105 | #define CPUID_VIA_DO_ACE __BIT(7) |
1105 | #define CPUID_VIA_HAS_ACE2 __BIT(8) /* AES+CTR instructions */ | | 1106 | #define CPUID_VIA_HAS_ACE2 __BIT(8) /* AES+CTR instructions */ |
1106 | #define CPUID_VIA_DO_ACE2 __BIT(9) | | 1107 | #define CPUID_VIA_DO_ACE2 __BIT(9) |
1107 | #define CPUID_VIA_HAS_PHE __BIT(10) /* SHA1+SHA256 HMAC */ | | 1108 | #define CPUID_VIA_HAS_PHE __BIT(10) /* SHA1+SHA256 HMAC */ |
1108 | #define CPUID_VIA_DO_PHE __BIT(11) | | 1109 | #define CPUID_VIA_DO_PHE __BIT(11) |
1109 | #define CPUID_VIA_HAS_PMM __BIT(12) /* RSA Instructions */ | | 1110 | #define CPUID_VIA_HAS_PMM __BIT(12) /* RSA Instructions */ |
1110 | #define CPUID_VIA_DO_PMM __BIT(13) | | 1111 | #define CPUID_VIA_DO_PMM __BIT(13) |
1111 | | | 1112 | |
1112 | #define CPUID_FLAGS_PADLOCK "\20" \ | | 1113 | #define CPUID_FLAGS_PADLOCK "\20" \ |
1113 | "\3" "RNG" "\7" "AES" "\11" "AES/CTR" "\13" "SHA1/SHA256" \ | | 1114 | "\3" "RNG" "\7" "AES" "\11" "AES/CTR" "\13" "SHA1/SHA256" \ |
1114 | "\15" "RSA" | | 1115 | "\15" "RSA" |
1115 | | | 1116 | |
1116 | /* | | 1117 | /* |
1117 | * Model-Specific Registers | | 1118 | * Model-Specific Registers |
1118 | */ | | 1119 | */ |
1119 | #define MSR_TSC 0x010 | | 1120 | #define MSR_TSC 0x010 |
1120 | #define MSR_IA32_PLATFORM_ID 0x017 | | 1121 | #define MSR_IA32_PLATFORM_ID 0x017 |
1121 | #define MSR_APICBASE 0x01b | | 1122 | #define MSR_APICBASE 0x01b |
1122 | #define APICBASE_BSP 0x00000100 /* boot processor */ | | 1123 | #define APICBASE_BSP 0x00000100 /* boot processor */ |
1123 | #define APICBASE_EXTD 0x00000400 /* x2APIC mode */ | | 1124 | #define APICBASE_EXTD 0x00000400 /* x2APIC mode */ |
1124 | #define APICBASE_EN 0x00000800 /* software enable */ | | 1125 | #define APICBASE_EN 0x00000800 /* software enable */ |
1125 | /* | | 1126 | /* |
1126 | * APICBASE_PHYSADDR is actually variable-sized on some CPUs. But we're | | 1127 | * APICBASE_PHYSADDR is actually variable-sized on some CPUs. But we're |
1127 | * only interested in the initial value, which is guaranteed to fit the | | 1128 | * only interested in the initial value, which is guaranteed to fit the |
1128 | * first 32 bits. So this macro is fine. | | 1129 | * first 32 bits. So this macro is fine. |
1129 | */ | | 1130 | */ |
1130 | #define APICBASE_PHYSADDR 0xfffff000 /* physical address */ | | 1131 | #define APICBASE_PHYSADDR 0xfffff000 /* physical address */ |
1131 | #define MSR_EBL_CR_POWERON 0x02a | | 1132 | #define MSR_EBL_CR_POWERON 0x02a |
1132 | #define MSR_EBC_FREQUENCY_ID 0x02c /* PIV only */ | | 1133 | #define MSR_EBC_FREQUENCY_ID 0x02c /* PIV only */ |
1133 | #define MSR_IA32_SPEC_CTRL 0x048 | | 1134 | #define MSR_IA32_SPEC_CTRL 0x048 |
1134 | #define IA32_SPEC_CTRL_IBRS 0x01 | | 1135 | #define IA32_SPEC_CTRL_IBRS 0x01 |
1135 | #define IA32_SPEC_CTRL_STIBP 0x02 | | 1136 | #define IA32_SPEC_CTRL_STIBP 0x02 |
1136 | #define IA32_SPEC_CTRL_SSBD 0x04 | | 1137 | #define IA32_SPEC_CTRL_SSBD 0x04 |
1137 | #define MSR_IA32_PRED_CMD 0x049 | | 1138 | #define MSR_IA32_PRED_CMD 0x049 |
1138 | #define IA32_PRED_CMD_IBPB 0x01 | | 1139 | #define IA32_PRED_CMD_IBPB 0x01 |
1139 | #define MSR_BIOS_UPDT_TRIG 0x079 | | 1140 | #define MSR_BIOS_UPDT_TRIG 0x079 |
1140 | #define MSR_BIOS_SIGN 0x08b | | 1141 | #define MSR_BIOS_SIGN 0x08b |
1141 | #define MSR_PERFCTR0 0x0c1 | | 1142 | #define MSR_PERFCTR0 0x0c1 |
1142 | #define MSR_PERFCTR1 0x0c2 | | 1143 | #define MSR_PERFCTR1 0x0c2 |
1143 | #define MSR_FSB_FREQ 0x0cd /* Core Duo/Solo only */ | | 1144 | #define MSR_FSB_FREQ 0x0cd /* Core Duo/Solo only */ |
1144 | #define MSR_MPERF 0x0e7 | | 1145 | #define MSR_MPERF 0x0e7 |
1145 | #define MSR_APERF 0x0e8 | | 1146 | #define MSR_APERF 0x0e8 |
1146 | #define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */ | | 1147 | #define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */ |
1147 | #define MSR_MTRRcap 0x0fe | | 1148 | #define MSR_MTRRcap 0x0fe |
1148 | #define MSR_IA32_ARCH_CAPABILITIES 0x10a | | 1149 | #define MSR_IA32_ARCH_CAPABILITIES 0x10a |
1149 | #define IA32_ARCH_RDCL_NO 0x01 | | 1150 | #define IA32_ARCH_RDCL_NO 0x01 |
1150 | #define IA32_ARCH_IBRS_ALL 0x02 | | 1151 | #define IA32_ARCH_IBRS_ALL 0x02 |
1151 | #define IA32_ARCH_RSBA 0x04 | | 1152 | #define IA32_ARCH_RSBA 0x04 |
1152 | #define IA32_ARCH_SKIP_L1DFL_VMENTRY 0x08 | | 1153 | #define IA32_ARCH_SKIP_L1DFL_VMENTRY 0x08 |
1153 | #define IA32_ARCH_SSB_NO 0x10 | | 1154 | #define IA32_ARCH_SSB_NO 0x10 |
1154 | #define IA32_ARCH_MDS_NO 0x20 | | 1155 | #define IA32_ARCH_MDS_NO 0x20 |
1155 | #define IA32_ARCH_IF_PSCHANGE_MC_NO 0x40 | | 1156 | #define IA32_ARCH_IF_PSCHANGE_MC_NO 0x40 |
1156 | #define IA32_ARCH_TSX_CTRL 0x80 | | 1157 | #define IA32_ARCH_TSX_CTRL 0x80 |
1157 | #define IA32_ARCH_TAA_NO 0x100 | | 1158 | #define IA32_ARCH_TAA_NO 0x100 |
1158 | #define MSR_IA32_FLUSH_CMD 0x10b | | 1159 | #define MSR_IA32_FLUSH_CMD 0x10b |
1159 | #define IA32_FLUSH_CMD_L1D_FLUSH 0x01 | | 1160 | #define IA32_FLUSH_CMD_L1D_FLUSH 0x01 |
1160 | #define MSR_TSX_FORCE_ABORT 0x10f | | 1161 | #define MSR_TSX_FORCE_ABORT 0x10f |
1161 | #define MSR_IA32_TSX_CTRL 0x122 | | 1162 | #define MSR_IA32_TSX_CTRL 0x122 |
1162 | #define IA32_TSX_CTRL_RTM_DISABLE __BIT(0) | | 1163 | #define IA32_TSX_CTRL_RTM_DISABLE __BIT(0) |
1163 | #define IA32_TSX_CTRL_TSX_CPUID_CLEAR __BIT(1) | | 1164 | #define IA32_TSX_CTRL_TSX_CPUID_CLEAR __BIT(1) |
1164 | #define MSR_SYSENTER_CS 0x174 /* PII+ only */ | | 1165 | #define MSR_SYSENTER_CS 0x174 /* PII+ only */ |
1165 | #define MSR_SYSENTER_ESP 0x175 /* PII+ only */ | | 1166 | #define MSR_SYSENTER_ESP 0x175 /* PII+ only */ |
1166 | #define MSR_SYSENTER_EIP 0x176 /* PII+ only */ | | 1167 | #define MSR_SYSENTER_EIP 0x176 /* PII+ only */ |
1167 | #define MSR_MCG_CAP 0x179 | | 1168 | #define MSR_MCG_CAP 0x179 |
1168 | #define MSR_MCG_STATUS 0x17a | | 1169 | #define MSR_MCG_STATUS 0x17a |
1169 | #define MSR_MCG_CTL 0x17b | | 1170 | #define MSR_MCG_CTL 0x17b |
1170 | #define MSR_EVNTSEL0 0x186 | | 1171 | #define MSR_EVNTSEL0 0x186 |
1171 | #define MSR_EVNTSEL1 0x187 | | 1172 | #define MSR_EVNTSEL1 0x187 |
1172 | #define MSR_PERF_STATUS 0x198 /* Pentium M */ | | 1173 | #define MSR_PERF_STATUS 0x198 /* Pentium M */ |
1173 | #define MSR_PERF_CTL 0x199 /* Pentium M */ | | 1174 | #define MSR_PERF_CTL 0x199 /* Pentium M */ |
1174 | #define MSR_THERM_CONTROL 0x19a | | 1175 | #define MSR_THERM_CONTROL 0x19a |
1175 | #define MSR_THERM_INTERRUPT 0x19b | | 1176 | #define MSR_THERM_INTERRUPT 0x19b |
1176 | #define MSR_THERM_STATUS 0x19c | | 1177 | #define MSR_THERM_STATUS 0x19c |
1177 | #define MSR_THERM2_CTL 0x19d /* Pentium M */ | | 1178 | #define MSR_THERM2_CTL 0x19d /* Pentium M */ |
1178 | #define MSR_MISC_ENABLE 0x1a0 | | 1179 | #define MSR_MISC_ENABLE 0x1a0 |
1179 | #define IA32_MISC_FAST_STR_EN __BIT(0) | | 1180 | #define IA32_MISC_FAST_STR_EN __BIT(0) |
1180 | #define IA32_MISC_ATCC_EN __BIT(3) | | 1181 | #define IA32_MISC_ATCC_EN __BIT(3) |
1181 | #define IA32_MISC_PERFMON_EN __BIT(7) | | 1182 | #define IA32_MISC_PERFMON_EN __BIT(7) |
1182 | #define IA32_MISC_BTS_UNAVAIL __BIT(11) | | 1183 | #define IA32_MISC_BTS_UNAVAIL __BIT(11) |
1183 | #define IA32_MISC_PEBS_UNAVAIL __BIT(12) | | 1184 | #define IA32_MISC_PEBS_UNAVAIL __BIT(12) |
1184 | #define IA32_MISC_EISST_EN __BIT(16) | | 1185 | #define IA32_MISC_EISST_EN __BIT(16) |
1185 | #define IA32_MISC_MWAIT_EN __BIT(18) | | 1186 | #define IA32_MISC_MWAIT_EN __BIT(18) |
1186 | #define IA32_MISC_LIMIT_CPUID __BIT(22) | | 1187 | #define IA32_MISC_LIMIT_CPUID __BIT(22) |
1187 | #define IA32_MISC_XTPR_DIS __BIT(23) | | 1188 | #define IA32_MISC_XTPR_DIS __BIT(23) |
1188 | #define IA32_MISC_XD_DIS __BIT(34) | | 1189 | #define IA32_MISC_XD_DIS __BIT(34) |
1189 | #define MSR_TEMPERATURE_TARGET 0x1a2 | | 1190 | #define MSR_TEMPERATURE_TARGET 0x1a2 |
1190 | #define MSR_DEBUGCTLMSR 0x1d9 | | 1191 | #define MSR_DEBUGCTLMSR 0x1d9 |
1191 | #define MSR_LASTBRANCHFROMIP 0x1db | | 1192 | #define MSR_LASTBRANCHFROMIP 0x1db |
1192 | #define MSR_LASTBRANCHTOIP 0x1dc | | 1193 | #define MSR_LASTBRANCHTOIP 0x1dc |
1193 | #define MSR_LASTINTFROMIP 0x1dd | | 1194 | #define MSR_LASTINTFROMIP 0x1dd |
1194 | #define MSR_LASTINTTOIP 0x1de | | 1195 | #define MSR_LASTINTTOIP 0x1de |
1195 | #define MSR_ROB_CR_BKUPTMPDR6 0x1e0 | | 1196 | #define MSR_ROB_CR_BKUPTMPDR6 0x1e0 |
1196 | #define MSR_MTRRphysBase0 0x200 | | 1197 | #define MSR_MTRRphysBase0 0x200 |
1197 | #define MSR_MTRRphysMask0 0x201 | | 1198 | #define MSR_MTRRphysMask0 0x201 |
1198 | #define MSR_MTRRphysBase1 0x202 | | 1199 | #define MSR_MTRRphysBase1 0x202 |
1199 | #define MSR_MTRRphysMask1 0x203 | | 1200 | #define MSR_MTRRphysMask1 0x203 |
1200 | #define MSR_MTRRphysBase2 0x204 | | 1201 | #define MSR_MTRRphysBase2 0x204 |
1201 | #define MSR_MTRRphysMask2 0x205 | | 1202 | #define MSR_MTRRphysMask2 0x205 |
1202 | #define MSR_MTRRphysBase3 0x206 | | 1203 | #define MSR_MTRRphysBase3 0x206 |
1203 | #define MSR_MTRRphysMask3 0x207 | | 1204 | #define MSR_MTRRphysMask3 0x207 |
1204 | #define MSR_MTRRphysBase4 0x208 | | 1205 | #define MSR_MTRRphysBase4 0x208 |
1205 | #define MSR_MTRRphysMask4 0x209 | | 1206 | #define MSR_MTRRphysMask4 0x209 |
1206 | #define MSR_MTRRphysBase5 0x20a | | 1207 | #define MSR_MTRRphysBase5 0x20a |
1207 | #define MSR_MTRRphysMask5 0x20b | | 1208 | #define MSR_MTRRphysMask5 0x20b |
1208 | #define MSR_MTRRphysBase6 0x20c | | 1209 | #define MSR_MTRRphysBase6 0x20c |
1209 | #define MSR_MTRRphysMask6 0x20d | | 1210 | #define MSR_MTRRphysMask6 0x20d |
1210 | #define MSR_MTRRphysBase7 0x20e | | 1211 | #define MSR_MTRRphysBase7 0x20e |
1211 | #define MSR_MTRRphysMask7 0x20f | | 1212 | #define MSR_MTRRphysMask7 0x20f |
1212 | #define MSR_MTRRphysBase8 0x210 | | 1213 | #define MSR_MTRRphysBase8 0x210 |
1213 | #define MSR_MTRRphysMask8 0x211 | | 1214 | #define MSR_MTRRphysMask8 0x211 |
1214 | #define MSR_MTRRphysBase9 0x212 | | 1215 | #define MSR_MTRRphysBase9 0x212 |
1215 | #define MSR_MTRRphysMask9 0x213 | | 1216 | #define MSR_MTRRphysMask9 0x213 |
1216 | #define MSR_MTRRphysBase10 0x214 | | 1217 | #define MSR_MTRRphysBase10 0x214 |
1217 | #define MSR_MTRRphysMask10 0x215 | | 1218 | #define MSR_MTRRphysMask10 0x215 |
1218 | #define MSR_MTRRphysBase11 0x216 | | 1219 | #define MSR_MTRRphysBase11 0x216 |
1219 | #define MSR_MTRRphysMask11 0x217 | | 1220 | #define MSR_MTRRphysMask11 0x217 |
1220 | #define MSR_MTRRphysBase12 0x218 | | 1221 | #define MSR_MTRRphysBase12 0x218 |
1221 | #define MSR_MTRRphysMask12 0x219 | | 1222 | #define MSR_MTRRphysMask12 0x219 |
1222 | #define MSR_MTRRphysBase13 0x21a | | 1223 | #define MSR_MTRRphysBase13 0x21a |
1223 | #define MSR_MTRRphysMask13 0x21b | | 1224 | #define MSR_MTRRphysMask13 0x21b |
1224 | #define MSR_MTRRphysBase14 0x21c | | 1225 | #define MSR_MTRRphysBase14 0x21c |
1225 | #define MSR_MTRRphysMask14 0x21d | | 1226 | #define MSR_MTRRphysMask14 0x21d |
1226 | #define MSR_MTRRphysBase15 0x21e | | 1227 | #define MSR_MTRRphysBase15 0x21e |
1227 | #define MSR_MTRRphysMask15 0x21f | | 1228 | #define MSR_MTRRphysMask15 0x21f |
1228 | #define MSR_MTRRfix64K_00000 0x250 | | 1229 | #define MSR_MTRRfix64K_00000 0x250 |
1229 | #define MSR_MTRRfix16K_80000 0x258 | | 1230 | #define MSR_MTRRfix16K_80000 0x258 |
1230 | #define MSR_MTRRfix16K_A0000 0x259 | | 1231 | #define MSR_MTRRfix16K_A0000 0x259 |
1231 | #define MSR_MTRRfix4K_C0000 0x268 | | 1232 | #define MSR_MTRRfix4K_C0000 0x268 |
1232 | #define MSR_MTRRfix4K_C8000 0x269 | | 1233 | #define MSR_MTRRfix4K_C8000 0x269 |
1233 | #define MSR_MTRRfix4K_D0000 0x26a | | 1234 | #define MSR_MTRRfix4K_D0000 0x26a |
1234 | #define MSR_MTRRfix4K_D8000 0x26b | | 1235 | #define MSR_MTRRfix4K_D8000 0x26b |
1235 | #define MSR_MTRRfix4K_E0000 0x26c | | 1236 | #define MSR_MTRRfix4K_E0000 0x26c |
1236 | #define MSR_MTRRfix4K_E8000 0x26d | | 1237 | #define MSR_MTRRfix4K_E8000 0x26d |
1237 | #define MSR_MTRRfix4K_F0000 0x26e | | 1238 | #define MSR_MTRRfix4K_F0000 0x26e |
1238 | #define MSR_MTRRfix4K_F8000 0x26f | | 1239 | #define MSR_MTRRfix4K_F8000 0x26f |
1239 | #define MSR_CR_PAT 0x277 | | 1240 | #define MSR_CR_PAT 0x277 |
1240 | #define MSR_MTRRdefType 0x2ff | | 1241 | #define MSR_MTRRdefType 0x2ff |
1241 | #define MSR_MC0_CTL 0x400 | | 1242 | #define MSR_MC0_CTL 0x400 |
1242 | #define MSR_MC0_STATUS 0x401 | | 1243 | #define MSR_MC0_STATUS 0x401 |
1243 | #define MSR_MC0_ADDR 0x402 | | 1244 | #define MSR_MC0_ADDR 0x402 |
1244 | #define MSR_MC0_MISC 0x403 | | 1245 | #define MSR_MC0_MISC 0x403 |
1245 | #define MSR_MC1_CTL 0x404 | | 1246 | #define MSR_MC1_CTL 0x404 |
1246 | #define MSR_MC1_STATUS 0x405 | | 1247 | #define MSR_MC1_STATUS 0x405 |
1247 | #define MSR_MC1_ADDR 0x406 | | 1248 | #define MSR_MC1_ADDR 0x406 |
1248 | #define MSR_MC1_MISC 0x407 | | 1249 | #define MSR_MC1_MISC 0x407 |
1249 | #define MSR_MC2_CTL 0x408 | | 1250 | #define MSR_MC2_CTL 0x408 |
1250 | #define MSR_MC2_STATUS 0x409 | | 1251 | #define MSR_MC2_STATUS 0x409 |
1251 | #define MSR_MC2_ADDR 0x40a | | 1252 | #define MSR_MC2_ADDR 0x40a |
1252 | #define MSR_MC2_MISC 0x40b | | 1253 | #define MSR_MC2_MISC 0x40b |
1253 | #define MSR_MC3_CTL 0x40c | | 1254 | #define MSR_MC3_CTL 0x40c |
1254 | #define MSR_MC3_STATUS 0x40d | | 1255 | #define MSR_MC3_STATUS 0x40d |
1255 | #define MSR_MC3_ADDR 0x40e | | 1256 | #define MSR_MC3_ADDR 0x40e |
1256 | #define MSR_MC3_MISC 0x40f | | 1257 | #define MSR_MC3_MISC 0x40f |
1257 | #define MSR_MC4_CTL 0x410 | | 1258 | #define MSR_MC4_CTL 0x410 |
1258 | #define MSR_MC4_STATUS 0x411 | | 1259 | #define MSR_MC4_STATUS 0x411 |
1259 | #define MSR_MC4_ADDR 0x412 | | 1260 | #define MSR_MC4_ADDR 0x412 |
1260 | #define MSR_MC4_MISC 0x413 | | 1261 | #define MSR_MC4_MISC 0x413 |
1261 | /* 0x480 - 0x490 VMX */ | | 1262 | /* 0x480 - 0x490 VMX */ |
1262 | #define MSR_X2APIC_BASE 0x800 /* 0x800 - 0xBFF */ | | 1263 | #define MSR_X2APIC_BASE 0x800 /* 0x800 - 0xBFF */ |
1263 | #define MSR_X2APIC_ID 0x002 /* x2APIC ID. (RO) */ | | 1264 | #define MSR_X2APIC_ID 0x002 /* x2APIC ID. (RO) */ |
1264 | #define MSR_X2APIC_VERS 0x003 /* Version. (RO) */ | | 1265 | #define MSR_X2APIC_VERS 0x003 /* Version. (RO) */ |
1265 | #define MSR_X2APIC_TPRI 0x008 /* Task Prio. (RW) */ | | 1266 | #define MSR_X2APIC_TPRI 0x008 /* Task Prio. (RW) */ |
1266 | #define MSR_X2APIC_PPRI 0x00a /* Processor prio. (RO) */ | | 1267 | #define MSR_X2APIC_PPRI 0x00a /* Processor prio. (RO) */ |
1267 | #define MSR_X2APIC_EOI 0x00b /* End Int. (W) */ | | 1268 | #define MSR_X2APIC_EOI 0x00b /* End Int. (W) */ |
1268 | #define MSR_X2APIC_LDR 0x00d /* Logical dest. (RO) */ | | 1269 | #define MSR_X2APIC_LDR 0x00d /* Logical dest. (RO) */ |
1269 | #define MSR_X2APIC_SVR 0x00f /* Spurious intvec (RW) */ | | 1270 | #define MSR_X2APIC_SVR 0x00f /* Spurious intvec (RW) */ |
1270 | #define MSR_X2APIC_ISR 0x010 /* In-Service Status (RO) */ | | 1271 | #define MSR_X2APIC_ISR 0x010 /* In-Service Status (RO) */ |
1271 | #define MSR_X2APIC_TMR 0x018 /* Trigger Mode (RO) */ | | 1272 | #define MSR_X2APIC_TMR 0x018 /* Trigger Mode (RO) */ |
1272 | #define MSR_X2APIC_IRR 0x020 /* Interrupt Req (RO) */ | | 1273 | #define MSR_X2APIC_IRR 0x020 /* Interrupt Req (RO) */ |
1273 | #define MSR_X2APIC_ESR 0x028 /* Err status. (RW) */ | | 1274 | #define MSR_X2APIC_ESR 0x028 /* Err status. (RW) */ |
1274 | #define MSR_X2APIC_LVT_CMCI 0x02f /* LVT CMCI (RW) */ | | 1275 | #define MSR_X2APIC_LVT_CMCI 0x02f /* LVT CMCI (RW) */ |
1275 | #define MSR_X2APIC_ICRLO 0x030 /* Int. cmd. (RW64) */ | | 1276 | #define MSR_X2APIC_ICRLO 0x030 /* Int. cmd. (RW64) */ |
1276 | #define MSR_X2APIC_LVTT 0x032 /* Loc.vec.(timer) (RW) */ | | 1277 | #define MSR_X2APIC_LVTT 0x032 /* Loc.vec.(timer) (RW) */ |
1277 | #define MSR_X2APIC_TMINT 0x033 /* Loc.vec (Thermal) (RW) */ | | 1278 | #define MSR_X2APIC_TMINT 0x033 /* Loc.vec (Thermal) (RW) */ |
1278 | #define MSR_X2APIC_PCINT 0x034 /* Loc.vec (Perf Mon) (RW) */ | | 1279 | #define MSR_X2APIC_PCINT 0x034 /* Loc.vec (Perf Mon) (RW) */ |
1279 | #define MSR_X2APIC_LVINT0 0x035 /* Loc.vec (LINT0) (RW) */ | | 1280 | #define MSR_X2APIC_LVINT0 0x035 /* Loc.vec (LINT0) (RW) */ |
1280 | #define MSR_X2APIC_LVINT1 0x036 /* Loc.vec (LINT1) (RW) */ | | 1281 | #define MSR_X2APIC_LVINT1 0x036 /* Loc.vec (LINT1) (RW) */ |
1281 | #define MSR_X2APIC_LVERR 0x037 /* Loc.vec (ERROR) (RW) */ | | 1282 | #define MSR_X2APIC_LVERR 0x037 /* Loc.vec (ERROR) (RW) */ |
1282 | #define MSR_X2APIC_ICR_TIMER 0x038 /* Initial count (RW) */ | | 1283 | #define MSR_X2APIC_ICR_TIMER 0x038 /* Initial count (RW) */ |
1283 | #define MSR_X2APIC_CCR_TIMER 0x039 /* Current count (RO) */ | | 1284 | #define MSR_X2APIC_CCR_TIMER 0x039 /* Current count (RO) */ |
1284 | #define MSR_X2APIC_DCR_TIMER 0x03e /* Divisor config (RW) */ | | 1285 | #define MSR_X2APIC_DCR_TIMER 0x03e /* Divisor config (RW) */ |
1285 | #define MSR_X2APIC_SELF_IPI 0x03f /* SELF IPI (W) */ | | 1286 | #define MSR_X2APIC_SELF_IPI 0x03f /* SELF IPI (W) */ |
1286 | | | 1287 | |
1287 | /* | | 1288 | /* |
1288 | * VIA "Nehemiah" MSRs | | 1289 | * VIA "Nehemiah" MSRs |
1289 | */ | | 1290 | */ |
1290 | #define MSR_VIA_RNG 0x0000110b | | 1291 | #define MSR_VIA_RNG 0x0000110b |
1291 | #define MSR_VIA_RNG_ENABLE 0x00000040 | | 1292 | #define MSR_VIA_RNG_ENABLE 0x00000040 |
1292 | #define MSR_VIA_RNG_NOISE_MASK 0x00000300 | | 1293 | #define MSR_VIA_RNG_NOISE_MASK 0x00000300 |
1293 | #define MSR_VIA_RNG_NOISE_A 0x00000000 | | 1294 | #define MSR_VIA_RNG_NOISE_A 0x00000000 |
1294 | #define MSR_VIA_RNG_NOISE_B 0x00000100 | | 1295 | #define MSR_VIA_RNG_NOISE_B 0x00000100 |
1295 | #define MSR_VIA_RNG_2NOISE 0x00000300 | | 1296 | #define MSR_VIA_RNG_2NOISE 0x00000300 |
1296 | #define MSR_VIA_ACE 0x00001107 | | 1297 | #define MSR_VIA_ACE 0x00001107 |
1297 | #define VIA_ACE_ALTINST 0x00000001 | | 1298 | #define VIA_ACE_ALTINST 0x00000001 |
1298 | #define VIA_ACE_ECX8 0x00000002 | | 1299 | #define VIA_ACE_ECX8 0x00000002 |
1299 | #define VIA_ACE_ENABLE 0x10000000 | | 1300 | #define VIA_ACE_ENABLE 0x10000000 |
1300 | | | 1301 | |
1301 | /* | | 1302 | /* |
1302 | * VIA "Eden" MSRs | | 1303 | * VIA "Eden" MSRs |
1303 | */ | | 1304 | */ |
1304 | #define MSR_VIA_FCR MSR_VIA_ACE | | 1305 | #define MSR_VIA_FCR MSR_VIA_ACE |
1305 | | | 1306 | |
1306 | /* | | 1307 | /* |
1307 | * AMD K6/K7 MSRs. | | 1308 | * AMD K6/K7 MSRs. |
1308 | */ | | 1309 | */ |
1309 | #define MSR_K6_UWCCR 0xc0000085 | | 1310 | #define MSR_K6_UWCCR 0xc0000085 |
1310 | #define MSR_K7_EVNTSEL0 0xc0010000 | | 1311 | #define MSR_K7_EVNTSEL0 0xc0010000 |
1311 | #define MSR_K7_EVNTSEL1 0xc0010001 | | 1312 | #define MSR_K7_EVNTSEL1 0xc0010001 |
1312 | #define MSR_K7_EVNTSEL2 0xc0010002 | | 1313 | #define MSR_K7_EVNTSEL2 0xc0010002 |
1313 | #define MSR_K7_EVNTSEL3 0xc0010003 | | 1314 | #define MSR_K7_EVNTSEL3 0xc0010003 |
1314 | #define MSR_K7_PERFCTR0 0xc0010004 | | 1315 | #define MSR_K7_PERFCTR0 0xc0010004 |
1315 | #define MSR_K7_PERFCTR1 0xc0010005 | | 1316 | #define MSR_K7_PERFCTR1 0xc0010005 |
1316 | #define MSR_K7_PERFCTR2 0xc0010006 | | 1317 | #define MSR_K7_PERFCTR2 0xc0010006 |
1317 | #define MSR_K7_PERFCTR3 0xc0010007 | | 1318 | #define MSR_K7_PERFCTR3 0xc0010007 |
1318 | | | 1319 | |
1319 | /* | | 1320 | /* |
1320 | * AMD K8 (Opteron) MSRs. | | 1321 | * AMD K8 (Opteron) MSRs. |
1321 | */ | | 1322 | */ |
1322 | #define MSR_SYSCFG 0xc0010010 | | 1323 | #define MSR_SYSCFG 0xc0010010 |
1323 | | | 1324 | |
1324 | #define MSR_EFER 0xc0000080 /* Extended feature enable */ | | 1325 | #define MSR_EFER 0xc0000080 /* Extended feature enable */ |
1325 | #define EFER_SCE 0x00000001 /* SYSCALL extension */ | | 1326 | #define EFER_SCE 0x00000001 /* SYSCALL extension */ |
1326 | #define EFER_LME 0x00000100 /* Long Mode Enable */ | | 1327 | #define EFER_LME 0x00000100 /* Long Mode Enable */ |
1327 | #define EFER_LMA 0x00000400 /* Long Mode Active */ | | 1328 | #define EFER_LMA 0x00000400 /* Long Mode Active */ |
1328 | #define EFER_NXE 0x00000800 /* No-Execute Enabled */ | | 1329 | #define EFER_NXE 0x00000800 /* No-Execute Enabled */ |
1329 | #define EFER_SVME 0x00001000 /* Secure Virtual Machine En. */ | | 1330 | #define EFER_SVME 0x00001000 /* Secure Virtual Machine En. */ |
1330 | #define EFER_LMSLE 0x00002000 /* Long Mode Segment Limit E. */ | | 1331 | #define EFER_LMSLE 0x00002000 /* Long Mode Segment Limit E. */ |
1331 | #define EFER_FFXSR 0x00004000 /* Fast FXSAVE/FXRSTOR En. */ | | 1332 | #define EFER_FFXSR 0x00004000 /* Fast FXSAVE/FXRSTOR En. */ |
1332 | #define EFER_TCE 0x00008000 /* Translation Cache Ext. */ | | 1333 | #define EFER_TCE 0x00008000 /* Translation Cache Ext. */ |
1333 | | | 1334 | |
1334 | #define MSR_STAR 0xc0000081 /* 32 bit syscall gate addr */ | | 1335 | #define MSR_STAR 0xc0000081 /* 32 bit syscall gate addr */ |
1335 | #define MSR_LSTAR 0xc0000082 /* 64 bit syscall gate addr */ | | 1336 | #define MSR_LSTAR 0xc0000082 /* 64 bit syscall gate addr */ |
1336 | #define MSR_CSTAR 0xc0000083 /* compat syscall gate addr */ | | 1337 | #define MSR_CSTAR 0xc0000083 /* compat syscall gate addr */ |
1337 | #define MSR_SFMASK 0xc0000084 /* flags to clear on syscall */ | | 1338 | #define MSR_SFMASK 0xc0000084 /* flags to clear on syscall */ |
1338 | | | 1339 | |
1339 | #define MSR_FSBASE 0xc0000100 /* 64bit offset for fs: */ | | 1340 | #define MSR_FSBASE 0xc0000100 /* 64bit offset for fs: */ |
1340 | #define MSR_GSBASE 0xc0000101 /* 64bit offset for gs: */ | | 1341 | #define MSR_GSBASE 0xc0000101 /* 64bit offset for gs: */ |
1341 | #define MSR_KERNELGSBASE 0xc0000102 /* storage for swapgs ins */ | | 1342 | #define MSR_KERNELGSBASE 0xc0000102 /* storage for swapgs ins */ |
1342 | | | 1343 | |
1343 | #define MSR_VMCR 0xc0010114 /* Virtual Machine Control Register */ | | 1344 | #define MSR_VMCR 0xc0010114 /* Virtual Machine Control Register */ |
1344 | #define VMCR_DPD 0x00000001 /* Debug port disable */ | | 1345 | #define VMCR_DPD 0x00000001 /* Debug port disable */ |
1345 | #define VMCR_RINIT 0x00000002 /* intercept init */ | | 1346 | #define VMCR_RINIT 0x00000002 /* intercept init */ |
1346 | #define VMCR_DISA20 0x00000004 /* Disable A20 masking */ | | 1347 | #define VMCR_DISA20 0x00000004 /* Disable A20 masking */ |
1347 | #define VMCR_LOCK 0x00000008 /* SVM Lock */ | | 1348 | #define VMCR_LOCK 0x00000008 /* SVM Lock */ |
1348 | #define VMCR_SVMED 0x00000010 /* SVME Disable */ | | 1349 | #define VMCR_SVMED 0x00000010 /* SVME Disable */ |
1349 | #define MSR_SVMLOCK 0xc0010118 /* SVM Lock key */ | | 1350 | #define MSR_SVMLOCK 0xc0010118 /* SVM Lock key */ |
1350 | | | 1351 | |
1351 | /* | | 1352 | /* |
1352 | * These require a 'passcode' for access. See cpufunc.h. | | 1353 | * These require a 'passcode' for access. See cpufunc.h. |
1353 | */ | | 1354 | */ |
1354 | #define MSR_HWCR 0xc0010015 | | 1355 | #define MSR_HWCR 0xc0010015 |
1355 | #define HWCR_TLBCACHEDIS 0x00000008 | | 1356 | #define HWCR_TLBCACHEDIS 0x00000008 |
1356 | #define HWCR_FFDIS 0x00000040 | | 1357 | #define HWCR_FFDIS 0x00000040 |
1357 | | | 1358 | |
1358 | #define MSR_NB_CFG 0xc001001f | | 1359 | #define MSR_NB_CFG 0xc001001f |
1359 | #define NB_CFG_DISIOREQLOCK 0x0000000000000008ULL | | 1360 | #define NB_CFG_DISIOREQLOCK 0x0000000000000008ULL |
1360 | #define NB_CFG_DISDATMSK 0x0000001000000000ULL | | 1361 | #define NB_CFG_DISDATMSK 0x0000001000000000ULL |
1361 | #define NB_CFG_INITAPICCPUIDLO (1ULL << 54) | | 1362 | #define NB_CFG_INITAPICCPUIDLO (1ULL << 54) |
1362 | | | 1363 | |
1363 | #define MSR_LS_CFG 0xc0011020 | | 1364 | #define MSR_LS_CFG 0xc0011020 |
1364 | #define LS_CFG_ERRATA_1033 __BIT(4) | | 1365 | #define LS_CFG_ERRATA_1033 __BIT(4) |
1365 | #define LS_CFG_ERRATA_793 __BIT(15) | | 1366 | #define LS_CFG_ERRATA_793 __BIT(15) |
1366 | #define LS_CFG_ERRATA_1095 __BIT(57) | | 1367 | #define LS_CFG_ERRATA_1095 __BIT(57) |
1367 | #define LS_CFG_DIS_LS2_SQUISH 0x02000000 | | 1368 | #define LS_CFG_DIS_LS2_SQUISH 0x02000000 |
1368 | #define LS_CFG_DIS_SSB_F15H 0x0040000000000000ULL | | 1369 | #define LS_CFG_DIS_SSB_F15H 0x0040000000000000ULL |
1369 | #define LS_CFG_DIS_SSB_F16H 0x0000000200000000ULL | | 1370 | #define LS_CFG_DIS_SSB_F16H 0x0000000200000000ULL |
1370 | #define LS_CFG_DIS_SSB_F17H 0x0000000000000400ULL | | 1371 | #define LS_CFG_DIS_SSB_F17H 0x0000000000000400ULL |
1371 | | | 1372 | |
1372 | #define MSR_IC_CFG 0xc0011021 | | 1373 | #define MSR_IC_CFG 0xc0011021 |
1373 | #define IC_CFG_DIS_SEQ_PREFETCH 0x00000800 | | 1374 | #define IC_CFG_DIS_SEQ_PREFETCH 0x00000800 |
1374 | #define IC_CFG_DIS_IND 0x00004000 | | 1375 | #define IC_CFG_DIS_IND 0x00004000 |
1375 | #define IC_CFG_ERRATA_776 __BIT(26) | | 1376 | #define IC_CFG_ERRATA_776 __BIT(26) |
1376 | | | 1377 | |
1377 | #define MSR_DC_CFG 0xc0011022 | | 1378 | #define MSR_DC_CFG 0xc0011022 |
1378 | #define DC_CFG_DIS_CNV_WC_SSO 0x00000008 | | 1379 | #define DC_CFG_DIS_CNV_WC_SSO 0x00000008 |
1379 | #define DC_CFG_DIS_SMC_CHK_BUF 0x00000400 | | 1380 | #define DC_CFG_DIS_SMC_CHK_BUF 0x00000400 |
1380 | #define DC_CFG_ERRATA_261 0x01000000 | | 1381 | #define DC_CFG_ERRATA_261 0x01000000 |
1381 | | | 1382 | |
1382 | #define MSR_BU_CFG 0xc0011023 | | 1383 | #define MSR_BU_CFG 0xc0011023 |
1383 | #define BU_CFG_ERRATA_298 0x0000000000000002ULL | | 1384 | #define BU_CFG_ERRATA_298 0x0000000000000002ULL |
1384 | #define BU_CFG_ERRATA_254 0x0000000000200000ULL | | 1385 | #define BU_CFG_ERRATA_254 0x0000000000200000ULL |
1385 | #define BU_CFG_ERRATA_309 0x0000000000800000ULL | | 1386 | #define BU_CFG_ERRATA_309 0x0000000000800000ULL |
1386 | #define BU_CFG_THRL2IDXCMPDIS 0x0000080000000000ULL | | 1387 | #define BU_CFG_THRL2IDXCMPDIS 0x0000080000000000ULL |
1387 | #define BU_CFG_WBPFSMCCHKDIS 0x0000200000000000ULL | | 1388 | #define BU_CFG_WBPFSMCCHKDIS 0x0000200000000000ULL |
1388 | #define BU_CFG_WBENHWSBDIS 0x0001000000000000ULL | | 1389 | #define BU_CFG_WBENHWSBDIS 0x0001000000000000ULL |
1389 | | | 1390 | |
1390 | #define MSR_FP_CFG 0xc0011028 | | 1391 | #define MSR_FP_CFG 0xc0011028 |
1391 | #define FP_CFG_ERRATA_1049 __BIT(4) | | 1392 | #define FP_CFG_ERRATA_1049 __BIT(4) |
1392 | | | 1393 | |
1393 | #define MSR_DE_CFG 0xc0011029 | | 1394 | #define MSR_DE_CFG 0xc0011029 |
1394 | #define DE_CFG_ERRATA_721 0x00000001 | | 1395 | #define DE_CFG_ERRATA_721 0x00000001 |
1395 | #define DE_CFG_LFENCE_SERIALIZE __BIT(1) | | 1396 | #define DE_CFG_LFENCE_SERIALIZE __BIT(1) |
1396 | #define DE_CFG_ERRATA_1021 __BIT(13) | | 1397 | #define DE_CFG_ERRATA_1021 __BIT(13) |
1397 | | | 1398 | |
1398 | #define MSR_BU_CFG2 0xc001102a | | 1399 | #define MSR_BU_CFG2 0xc001102a |
1399 | #define BU_CFG2_CWPLUS_DIS __BIT(24) | | 1400 | #define BU_CFG2_CWPLUS_DIS __BIT(24) |
1400 | | | 1401 | |
1401 | #define MSR_LS_CFG2 0xc001102d | | 1402 | #define MSR_LS_CFG2 0xc001102d |
1402 | #define LS_CFG2_ERRATA_1091 __BIT(34) | | 1403 | #define LS_CFG2_ERRATA_1091 __BIT(34) |
1403 | | | 1404 | |
1404 | /* AMD Family10h MSRs */ | | 1405 | /* AMD Family10h MSRs */ |
1405 | #define MSR_OSVW_ID_LENGTH 0xc0010140 | | 1406 | #define MSR_OSVW_ID_LENGTH 0xc0010140 |
1406 | #define MSR_OSVW_STATUS 0xc0010141 | | 1407 | #define MSR_OSVW_STATUS 0xc0010141 |
1407 | #define MSR_UCODE_AMD_PATCHLEVEL 0x0000008b | | 1408 | #define MSR_UCODE_AMD_PATCHLEVEL 0x0000008b |
1408 | #define MSR_UCODE_AMD_PATCHLOADER 0xc0010020 | | 1409 | #define MSR_UCODE_AMD_PATCHLOADER 0xc0010020 |
1409 | | | 1410 | |
1410 | /* X86 MSRs */ | | 1411 | /* X86 MSRs */ |
1411 | #define MSR_RDTSCP_AUX 0xc0000103 | | 1412 | #define MSR_RDTSCP_AUX 0xc0000103 |
1412 | | | 1413 | |
1413 | /* | | 1414 | /* |
1414 | * Constants related to MTRRs | | 1415 | * Constants related to MTRRs |
1415 | */ | | 1416 | */ |
1416 | #define MTRR_N64K 8 /* numbers of fixed-size entries */ | | 1417 | #define MTRR_N64K 8 /* numbers of fixed-size entries */ |
1417 | #define MTRR_N16K 16 | | 1418 | #define MTRR_N16K 16 |
1418 | #define MTRR_N4K 64 | | 1419 | #define MTRR_N4K 64 |
1419 | | | 1420 | |
1420 | /* | | 1421 | /* |
1421 | * the following four 3-byte registers control the non-cacheable regions. | | 1422 | * the following four 3-byte registers control the non-cacheable regions. |
1422 | * These registers must be written as three separate bytes. | | 1423 | * These registers must be written as three separate bytes. |
1423 | * | | 1424 | * |
1424 | * NCRx+0: A31-A24 of starting address | | 1425 | * NCRx+0: A31-A24 of starting address |
1425 | * NCRx+1: A23-A16 of starting address | | 1426 | * NCRx+1: A23-A16 of starting address |
1426 | * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx. | | 1427 | * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx. |
1427 | * | | 1428 | * |
1428 | * The non-cacheable region's starting address must be aligned to the | | 1429 | * The non-cacheable region's starting address must be aligned to the |
1429 | * size indicated by the NCR_SIZE_xx field. | | 1430 | * size indicated by the NCR_SIZE_xx field. |
1430 | */ | | 1431 | */ |
1431 | #define NCR1 0xc4 | | 1432 | #define NCR1 0xc4 |
1432 | #define NCR2 0xc7 | | 1433 | #define NCR2 0xc7 |
1433 | #define NCR3 0xca | | 1434 | #define NCR3 0xca |
1434 | #define NCR4 0xcd | | 1435 | #define NCR4 0xcd |
1435 | | | 1436 | |
1436 | #define NCR_SIZE_0K 0 | | 1437 | #define NCR_SIZE_0K 0 |
1437 | #define NCR_SIZE_4K 1 | | 1438 | #define NCR_SIZE_4K 1 |
1438 | #define NCR_SIZE_8K 2 | | 1439 | #define NCR_SIZE_8K 2 |
1439 | #define NCR_SIZE_16K 3 | | 1440 | #define NCR_SIZE_16K 3 |
1440 | #define NCR_SIZE_32K 4 | | 1441 | #define NCR_SIZE_32K 4 |
1441 | #define NCR_SIZE_64K 5 | | 1442 | #define NCR_SIZE_64K 5 |
1442 | #define NCR_SIZE_128K 6 | | 1443 | #define NCR_SIZE_128K 6 |
1443 | #define NCR_SIZE_256K 7 | | 1444 | #define NCR_SIZE_256K 7 |
1444 | #define NCR_SIZE_512K 8 | | 1445 | #define NCR_SIZE_512K 8 |
1445 | #define NCR_SIZE_1M 9 | | 1446 | #define NCR_SIZE_1M 9 |
1446 | #define NCR_SIZE_2M 10 | | 1447 | #define NCR_SIZE_2M 10 |
1447 | #define NCR_SIZE_4M 11 | | 1448 | #define NCR_SIZE_4M 11 |
1448 | #define NCR_SIZE_8M 12 | | 1449 | #define NCR_SIZE_8M 12 |
1449 | #define NCR_SIZE_16M 13 | | 1450 | #define NCR_SIZE_16M 13 |
1450 | #define NCR_SIZE_32M 14 | | 1451 | #define NCR_SIZE_32M 14 |
1451 | #define NCR_SIZE_4G 15 | | 1452 | #define NCR_SIZE_4G 15 |