| @@ -1,14 +1,14 @@ | | | @@ -1,14 +1,14 @@ |
1 | /* $NetBSD: tprof_x86_intel.c,v 1.6 2023/04/11 02:47:01 msaitoh Exp $ */ | | 1 | /* $NetBSD: tprof_x86_intel.c,v 1.7 2023/04/11 09:53:28 msaitoh Exp $ */ |
2 | | | 2 | |
3 | /* | | 3 | /* |
4 | * Copyright (c) 2018 The NetBSD Foundation, Inc. | | 4 | * Copyright (c) 2018 The NetBSD Foundation, Inc. |
5 | * All rights reserved. | | 5 | * All rights reserved. |
6 | * | | 6 | * |
7 | * This code is derived from software contributed to The NetBSD Foundation | | 7 | * This code is derived from software contributed to The NetBSD Foundation |
8 | * by Maxime Villard. | | 8 | * by Maxime Villard. |
9 | * | | 9 | * |
10 | * Redistribution and use in source and binary forms, with or without | | 10 | * Redistribution and use in source and binary forms, with or without |
11 | * modification, are permitted provided that the following conditions | | 11 | * modification, are permitted provided that the following conditions |
12 | * are met: | | 12 | * are met: |
13 | * 1. Redistributions of source code must retain the above copyright | | 13 | * 1. Redistributions of source code must retain the above copyright |
14 | * notice, this list of conditions and the following disclaimer. | | 14 | * notice, this list of conditions and the following disclaimer. |
| @@ -46,27 +46,27 @@ | | | @@ -46,27 +46,27 @@ |
46 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | | 46 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
47 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | | 47 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
48 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE | | 48 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
49 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | | 49 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
50 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS | | 50 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
51 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) | | 51 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
52 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT | | 52 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
53 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY | | 53 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
54 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF | | 54 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
55 | * SUCH DAMAGE. | | 55 | * SUCH DAMAGE. |
56 | */ | | 56 | */ |
57 | | | 57 | |
58 | #include <sys/cdefs.h> | | 58 | #include <sys/cdefs.h> |
59 | __KERNEL_RCSID(0, "$NetBSD: tprof_x86_intel.c,v 1.6 2023/04/11 02:47:01 msaitoh Exp $"); | | 59 | __KERNEL_RCSID(0, "$NetBSD: tprof_x86_intel.c,v 1.7 2023/04/11 09:53:28 msaitoh Exp $"); |
60 | | | 60 | |
61 | #include <sys/param.h> | | 61 | #include <sys/param.h> |
62 | #include <sys/systm.h> | | 62 | #include <sys/systm.h> |
63 | #include <sys/kernel.h> | | 63 | #include <sys/kernel.h> |
64 | #include <sys/module.h> | | 64 | #include <sys/module.h> |
65 | | | 65 | |
66 | #include <sys/cpu.h> | | 66 | #include <sys/cpu.h> |
67 | #include <sys/percpu.h> | | 67 | #include <sys/percpu.h> |
68 | #include <sys/xcall.h> | | 68 | #include <sys/xcall.h> |
69 | | | 69 | |
70 | #include <dev/tprof/tprof.h> | | 70 | #include <dev/tprof/tprof.h> |
71 | | | 71 | |
72 | #include <uvm/uvm.h> /* VM_MIN_KERNEL_ADDRESS */ | | 72 | #include <uvm/uvm.h> /* VM_MIN_KERNEL_ADDRESS */ |
| @@ -93,26 +93,29 @@ static u_int counter_bitwidth; | | | @@ -93,26 +93,29 @@ static u_int counter_bitwidth; |
93 | #define PERFEVTSEL_INT __BIT(20) | | 93 | #define PERFEVTSEL_INT __BIT(20) |
94 | #define PERFEVTSEL_EN __BIT(22) | | 94 | #define PERFEVTSEL_EN __BIT(22) |
95 | #define PERFEVTSEL_INV __BIT(23) | | 95 | #define PERFEVTSEL_INV __BIT(23) |
96 | #define PERFEVTSEL_COUNTER_MASK __BITS(24, 31) | | 96 | #define PERFEVTSEL_COUNTER_MASK __BITS(24, 31) |
97 | | | 97 | |
98 | static uint32_t intel_lapic_saved[MAXCPUS]; | | 98 | static uint32_t intel_lapic_saved[MAXCPUS]; |
99 | static nmi_handler_t *intel_nmi_handle; | | 99 | static nmi_handler_t *intel_nmi_handle; |
100 | | | 100 | |
101 | static uint32_t | | 101 | static uint32_t |
102 | tprof_intel_ncounters(void) | | 102 | tprof_intel_ncounters(void) |
103 | { | | 103 | { |
104 | uint32_t descs[4]; | | 104 | uint32_t descs[4]; |
105 | | | 105 | |
| | | 106 | if (cpuid_level < 0x0a) |
| | | 107 | return 0; |
| | | 108 | |
106 | x86_cpuid(0x0a, descs); | | 109 | x86_cpuid(0x0a, descs); |
107 | | | 110 | |
108 | return __SHIFTOUT(descs[0], CPUID_PERF_NGPPC); | | 111 | return __SHIFTOUT(descs[0], CPUID_PERF_NGPPC); |
109 | } | | 112 | } |
110 | | | 113 | |
111 | static u_int | | 114 | static u_int |
112 | tprof_intel_counter_bitwidth(u_int counter) | | 115 | tprof_intel_counter_bitwidth(u_int counter) |
113 | { | | 116 | { |
114 | return counter_bitwidth; | | 117 | return counter_bitwidth; |
115 | } | | 118 | } |
116 | | | 119 | |
117 | static inline void | | 120 | static inline void |
118 | tprof_intel_counter_write(u_int counter, uint64_t val) | | 121 | tprof_intel_counter_write(u_int counter, uint64_t val) |