Tue Apr 11 13:11:01 2023 UTC ()
x86: Omit needless membar_sync in intr_disestablish_xcall.

Details in comments.


(riastradh)
diff -r1.164 -r1.165 src/sys/arch/x86/x86/intr.c
cvs diff -r1.164 -r1.165 src/sys/arch/x86/x86/intr.c (expand / switch to unified diff)

--- src/sys/arch/x86/x86/intr.c 2023/01/25 15:54:53 1.164
+++ src/sys/arch/x86/x86/intr.c 2023/04/11 13:11:01 1.165
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: intr.c,v 1.164 2023/01/25 15:54:53 riastradh Exp $ */ 1/* $NetBSD: intr.c,v 1.165 2023/04/11 13:11:01 riastradh Exp $ */
2 2
3/* 3/*
4 * Copyright (c) 2007, 2008, 2009, 2019 The NetBSD Foundation, Inc. 4 * Copyright (c) 2007, 2008, 2009, 2019 The NetBSD Foundation, Inc.
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * This code is derived from software contributed to The NetBSD Foundation 7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Andrew Doran, and by Jason R. Thorpe. 8 * by Andrew Doran, and by Jason R. Thorpe.
9 * 9 *
10 * Redistribution and use in source and binary forms, with or without 10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions 11 * modification, are permitted provided that the following conditions
12 * are met: 12 * are met:
13 * 1. Redistributions of source code must retain the above copyright 13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer. 14 * notice, this list of conditions and the following disclaimer.
@@ -123,27 +123,27 @@ @@ -123,27 +123,27 @@
123 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 123 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
124 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 124 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
125 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 125 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
126 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 126 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
127 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 127 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
128 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 128 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
129 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 129 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
130 * SUCH DAMAGE. 130 * SUCH DAMAGE.
131 * 131 *
132 * @(#)isa.c 7.2 (Berkeley) 5/13/91 132 * @(#)isa.c 7.2 (Berkeley) 5/13/91
133 */ 133 */
134 134
135#include <sys/cdefs.h> 135#include <sys/cdefs.h>
136__KERNEL_RCSID(0, "$NetBSD: intr.c,v 1.164 2023/01/25 15:54:53 riastradh Exp $"); 136__KERNEL_RCSID(0, "$NetBSD: intr.c,v 1.165 2023/04/11 13:11:01 riastradh Exp $");
137 137
138#include "opt_intrdebug.h" 138#include "opt_intrdebug.h"
139#include "opt_multiprocessor.h" 139#include "opt_multiprocessor.h"
140#include "opt_acpi.h" 140#include "opt_acpi.h"
141 141
142#include <sys/param.h> 142#include <sys/param.h>
143#include <sys/systm.h> 143#include <sys/systm.h>
144#include <sys/kernel.h> 144#include <sys/kernel.h>
145#include <sys/syslog.h> 145#include <sys/syslog.h>
146#include <sys/device.h> 146#include <sys/device.h>
147#include <sys/kmem.h> 147#include <sys/kmem.h>
148#include <sys/proc.h> 148#include <sys/proc.h>
149#include <sys/errno.h> 149#include <sys/errno.h>
@@ -1154,29 +1154,33 @@ intr_disestablish_xcall(void *arg1, void @@ -1154,29 +1154,33 @@ intr_disestablish_xcall(void *arg1, void
1154 ci = ih->ih_cpu; 1154 ci = ih->ih_cpu;
1155 1155
1156 KASSERT(ci == curcpu() || !mp_online); 1156 KASSERT(ci == curcpu() || !mp_online);
1157 1157
1158 /* Disable interrupts locally. */ 1158 /* Disable interrupts locally. */
1159 psl = x86_read_psl(); 1159 psl = x86_read_psl();
1160 x86_disable_intr(); 1160 x86_disable_intr();
1161 1161
1162 pic = ci->ci_isources[ih->ih_slot]->is_pic; 1162 pic = ci->ci_isources[ih->ih_slot]->is_pic;
1163 source = ci->ci_isources[ih->ih_slot]; 1163 source = ci->ci_isources[ih->ih_slot];
1164 idtvec = source->is_idtvec; 1164 idtvec = source->is_idtvec;
1165 1165
1166 (*pic->pic_hwmask)(pic, ih->ih_pin); 1166 (*pic->pic_hwmask)(pic, ih->ih_pin);
1167 membar_sync(); 1167
 1168 /*
 1169 * ci_pending is stable on the current CPU while interrupts are
 1170 * blocked, and we only need to synchronize with interrupt
 1171 * vectors on the same CPU, so no need for atomics or membars.
 1172 */
1168 ci->ci_ipending &= ~(1ULL << ih->ih_slot); 1173 ci->ci_ipending &= ~(1ULL << ih->ih_slot);
1169 membar_sync(); 
1170 1174
1171 /* 1175 /*
1172 * Remove the handler from the chain. 1176 * Remove the handler from the chain.
1173 */ 1177 */
1174 for (p = &source->is_handlers; (q = *p) != NULL && q != ih; 1178 for (p = &source->is_handlers; (q = *p) != NULL && q != ih;
1175 p = &q->ih_next) 1179 p = &q->ih_next)
1176 ; 1180 ;
1177 if (q == NULL) { 1181 if (q == NULL) {
1178 x86_write_psl(psl); 1182 x86_write_psl(psl);
1179 panic("%s: handler not registered", __func__); 1183 panic("%s: handler not registered", __func__);
1180 /* NOTREACHED */ 1184 /* NOTREACHED */
1181 } 1185 }
1182 1186