 @@ -1,14 +1,14 @@
-/*	$NetBSD: if_scx.c,v 1.40 2023/05/21 00:35:38 nisimura Exp $	*/
+/*	$NetBSD: if_scx.c,v 1.41 2023/06/13 00:15:52 nisimura Exp $	*/
 /*-
  * Copyright (c) 2020 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Tohru Nishimura.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
 @@ -39,53 +39,53 @@
  * to handle incoming frames, outgoing frames and packet data crypto
  * processing. uP programs are stored in an external flash memory and
  * have to be loaded by device driver.
  * NetSec uses Synopsys DesignWare Core EMAC.  DWC implementation
  * register (0x20) is known to have 0x10.36 and feature register (0x1058)
  * reports 0x11056f37.
  *  <24> alternative/enhanced desc format
  *  <18> receive IP type 2 checksum offload
  *  <16> transmit checksum offload
  *  <11> event counter (mac management counter, MMC)
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_scx.c,v 1.40 2023/05/21 00:35:38 nisimura Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_scx.c,v 1.41 2023/06/13 00:15:52 nisimura Exp $");
 #include <sys/param.h>
 #include <sys/bus.h>
 #include <sys/intr.h>
 #include <sys/device.h>
 #include <sys/callout.h>
 #include <sys/mbuf.h>
 #include <sys/errno.h>
 #include <sys/rndsource.h>
 #include <sys/kernel.h>
 #include <sys/systm.h>
 #include <net/if.h>
 #include <net/if_media.h>
 #include <net/if_dl.h>
 #include <net/if_ether.h>
 #include <dev/mii/mii.h>
 #include <dev/mii/miivar.h>
 #include <net/bpf.h>
 #include <dev/fdt/fdtvar.h>
 #include <dev/acpi/acpireg.h>
 #include <dev/acpi/acpivar.h>
 #include <dev/acpi/acpi_intr.h>
-/* SC2A11 GbE 64-bit paddr descriptor */
+/* SC2A11 GbE has 64-bit paddr descriptor */
 struct tdes {
 	uint32_t t0, t1, t2, t3;
 };
 struct rdes {
 	uint32_t r0, r1, r2, r3;
 };
 #define T0_OWN		(1U<<31)	/* desc is ready to Tx */
 #define T0_LD		(1U<<30)	/* last descriptor in array */
 #define T0_DRID		(24)		/* 29:24 desc ring id */
 #define T0_PT		(1U<<21)	/* 23:21 "pass-through" */
 #define T0_TDRID	(16)		/* 20:16 target desc ring id: GMAC=15 */
 #define T0_CC		(1U<<15)	/* ??? */
 #define T0_FS		(1U<<9)		/* first segment of frame */
 @@ -95,155 +95,159 @@ struct rdes {
 #define T0_TRS		(1U<<4)		/* 5:4 "TRS" ??? */
 /* T1 frame segment address 63:32 */
 /* T2 frame segment address 31:0 */
 /* T3 31:16 TCP segment length, 15:0 frame segment length to transmit */
 #define R0_OWN		(1U<<31)	/* desc is empty */
 #define R0_LD		(1U<<30)	/* last descriptor in array */
 #define R0_SDRID	(24)		/* 29:24 source desc ring id */
 #define R0_FR		(1U<<23)	/* found fragmented */
 #define R0_ER		(1U<<21)	/* Rx error indication */
 #define R0_ERR		(3U<<16)	/* 18:16 receive error code */
 #define R0_TDRID	(12)		/* 15:12 target desc ring id */
 #define R0_FS		(1U<<9)		/* first segment of frame */
 #define R0_LS		(1U<<8)		/* last segment of frame */
-#define R0_CSUM		(3U<<6)		/* 7:6 checksum status */
+#define R0_CSUM		(3U<<6)		/* 7:6 checksum status, 0: undone */
-#define R0_CERR		(2U<<6)		/* 0: undone, 1: found ok, 2: bad */
+#define R0_CERR		(2U<<6)		/* 2: found bad */
 #define R0_COK		(1U<<6)		/* 1: found ok */
 /* R1 frame address 63:32 */
 /* R2 frame address 31:0 */
 /* R3 31:16 received frame length, 15:0 buffer length to receive */
 /*
  * SC2A11 registers. 0x100 - 1204
  */
 #define SWRESET		0x104
 #define  SRST_RUN	(1U<<31)	/* instruct start, 0 to stop */
 #define COMINIT		0x120
 #define  INIT_DB	(1U<<2)		/* ???; self clear when done */
 #define  INIT_CLS	(1U<<1)		/* ???; self clear when done */
 #define PKTCTRL		0x140		/* pkt engine control */
-#define  MODENRM	(1U<<28)	/* change mode to normal */
+#define  MODENRM	(1U<<28)	/* set operational mode to 'normal' */
 #define  ENJUMBO	(1U<<27)	/* allow jumbo frame */
 #define  RPTCSUMERR	(1U<<3)		/* log Rx checksum error */
-#define  RPTHDCOMP	(1U<<2)		/* log HD incomplete condition */
+#define  RPTHDCOMP	(1U<<2)		/* log header incomplete condition */
-#define  RPTHDERR	(1U<<1)		/* log HD error */
+#define  RPTHDERR	(1U<<1)		/* log header error */
 #define  DROPNOMATCH	(1U<<0)		/* drop no match frames */
 #define xINTSR		0x200		/* aggregated interrupt status */
 #define  IRQ_UCODE	(1U<<20)	/* ucode load completed; W1C */
 #define  IRQ_MAC	(1U<<19)	/* ??? */
 #define  IRQ_PKT	(1U<<18)	/* ??? */
 #define  IRQ_BOOTCODE	(1U<<5)		/* ??? */
 #define  IRQ_XDONE	(1U<<4)		/* ??? mode change completed */
 #define  IRQ_RX		(1U<<1)		/* top level Rx interrupt */
 #define  IRQ_TX		(1U<<0)		/* top level Tx interrupt */
 #define xINTAEN		0x204		/* INT_A enable */
 #define xINTAE_SET	0x234		/* bit to set */
 #define xINTAE_CLR	0x238		/* bit to clr */
 #define xINTBEN		0x23c		/* INT_B enable */
 #define xINTBE_SET	0x240		/* bit to set */
 #define xINTBE_CLR	0x244		/* bit to clr */
 #define TXISR		0x400		/* transmit status; W1C */
 #define TXIEN		0x404		/* tx interrupt enable */
 #define TXIE_SET	0x428		/* bit to set */
 #define TXIE_CLR	0x42c		/* bit to clr */
 #define  TXI_NTOWNR	(1U<<17)	/* ??? desc array got empty */
-#define  TXI_TR_ERR	(1U<<16)	/* tx error */
+#define  TXI_TR_ERR	(1U<<16)	/* xmit error */
-#define  TXI_TXDONE	(1U<<15)	/* tx completed */
+#define  TXI_TXDONE	(1U<<15)	/* xmit completed */
-#define  TXI_TMREXP	(1U<<14)	/* coalesce timer expired */
+#define  TXI_TMREXP	(1U<<14)	/* coalesce guard timer expired */
 #define RXISR		0x440		/* receive status; W1C */
 #define RXIEN		0x444		/* rx interrupt enable */
 #define RXIE_SET	0x468		/* bit to set */
 #define RXIE_CLR	0x46c		/* bit to clr */
-#define  RXI_RC_ERR	(1U<<16)	/* rx error */
+#define  RXI_RC_ERR	(1U<<16)	/* recv error */
-#define  RXI_PKTCNT	(1U<<15)	/* rx counter has new value */
+#define  RXI_PKTCNT	(1U<<15)	/* recv counter has new value */
-#define  RXI_TMREXP	(1U<<14)	/* coalesce timer expired */
+#define  RXI_TMREXP	(1U<<14)	/* coalesce guard timer expired */
 /* 13 sets of special purpose desc interrupt handling register exist */
 #define TDBA_LO		0x408		/* tdes array base addr 31:0 */
 #define TDBA_HI		0x434		/* tdes array base addr 63:32 */
 #define RDBA_LO		0x448		/* rdes array base addr 31:0 */
 #define RDBA_HI		0x474		/* rdes array base addr 63:32 */
 /* 13 pairs of special purpose desc array base address register exist */
 #define TXCONF		0x430
 #define RXCONF		0x470
-#define  DESCNF_UP	(1U<<31)	/* up-and-running */
+#define  DESCNF_UP	(1U<<31)	/* 'up-and-running' */
 #define  DESCNF_CHRST	(1U<<30)	/* channel reset */
 #define  DESCNF_TMR	(1U<<4)		/* coalesce timer mode select */
 #define  DESCNF_LE	(1)		/* little endian desc format */
 #define TXSUBMIT	0x410		/* submit frame(s) to transmit */
-#define TXCLSCMAX	0x418		/* tx intr coalesce upper bound */
+#define TXCOALESC	0x418		/* tx intr coalesce upper bound */
-#define RXCLSCMAX	0x458		/* rx intr coalesce upper bound */
+#define RXCOALESC	0x458		/* rx intr coalesce upper bound */
-#define TXITIMER	0x420		/* coalesce timer usec, MSB to use */
+#define TCLSCTIME	0x420		/* tintr guard time usec, MSB to on */
-#define RXITIMER	0x460		/* coalesce timer usec, MSB to use */
+#define RCLSCTIME	0x460		/* rintr guard time usec, MSB to on */
 #define TXDONECNT	0x414		/* tx completed count, auto-zero */
-#define RXDONECNT	0x454		/* rx available count, auto-zero */
+#define RXAVAILCNT	0x454		/* rx available count, auto-zero */
 #define DMACTL_TMR	0x20c		/* engine DMA timer value */
 #define UCODE_H2M	0x210		/* host2media engine ucode port */
 #define UCODE_M2H	0x21c		/* media2host engine ucode port */
 #define CORESTAT	0x218		/* engine run state */
-#define  PKTSTOP	(1U<<2)
+#define  PKTSTOP	(1U<<2)		/* pkt engine stopped */
-#define  M2HSTOP	(1U<<1)
+#define  M2HSTOP	(1U<<1)		/* M2H engine stopped */
-#define  H2MSTOP	(1U<<0)
+#define  H2MSTOP	(1U<<0)		/* H2M engine stopped */
 #define DMACTL_H2M	0x214		/* host2media engine control */
 #define DMACTL_M2H	0x220		/* media2host engine control */
 #define  DMACTL_STOP	(1U<<0)		/* instruct stop; self-clear */
 #define  M2H_MODE_TRANS	(1U<<20)	/* initiate M2H mode change */
 #define UCODE_PKT	0x0d0		/* packet engine ucode port */
 #define CLKEN		0x100		/* clock distribution enable */
-#define  CLK_G		(1U<<5)		/* feed clk domain E */
+#define  CLK_G		(1U<<5)		/* feed clk domain G */
 #define  CLK_C		(1U<<1)		/* feed clk domain C */
 #define  CLK_D		(1U<<0)		/* feed clk domain D */
 #define  CLK_ALL	0x23		/* all above; 0x24 ??? 0x3f ??? */
 /* GMAC register indirect access. thru MACCMD/MACDATA operation */
 #define MACDATA		0x11c0		/* gmac register rd/wr data */
 #define MACCMD		0x11c4		/* gmac register operation */
 #define  CMD_IOWR	(1U<<28)	/* write op */
 #define  CMD_BUSY	(1U<<31)	/* busy bit */
 #define MACSTAT		0x1024		/* gmac status; ??? */
 #define MACINTE		0x1028		/* interrupt enable; ??? */
 #define FLOWTHR		0x11cc		/* flow control threshold */
 /* 31:16 pause threshold, 15:0 resume threshold */
-#define INTF_SEL	0x11d4		/* ??? */
+#define INTF_SEL	0x11d4		/* phy interface type */
 #define  INTF_GMII	0
 #define  INTF_RGMII	1
 #define  INTF_RMII	4
 #define DESC_INIT	0x11fc		/* write 1 for desc init, SC */
 #define DESC_SRST	0x1204		/* write 1 for desc sw reset, SC */
 #define MODE_TRANS	0x500		/* mode change completion status */
 #define  N2T_DONE	(1U<<20)	/* normal->taiki change completed */
 #define  T2N_DONE	(1U<<19)	/* taiki->normal change completed */
 #define MACADRH		0x10c		/* ??? */
 #define MACADRL		0x110		/* ??? */
 #define MCVER		0x22c		/* micro controller version */
 #define HWVER		0x230		/* hardware version */
 /*
  * GMAC registers are mostly identical to Synopsys DesignWare Core
  * Ethernet. These must be handled by indirect access.
  */
 #define GMACMCR		0x0000		/* MAC configuration */
-#define  MCR_IBN	(1U<<30)	/* ??? */
+#define  MCR_IBN	(1U<<30)	/* watch in-band-signal */
 #define  MCR_CST	(1U<<25)	/* strip CRC */
 #define  MCR_TC		(1U<<24)	/* keep RGMII PHY notified */
 #define  MCR_WD		(1U<<23)	/* allow long >2048 tx frame */
 #define  MCR_JE		(1U<<20)	/* allow ~9018 tx jumbo frame */
 #define  MCR_IFG	(7U<<17)	/* 19:17 IFG value 0~7 */
 #define  MCR_DCRS	(1U<<16)	/* ignore (G)MII HDX Tx error */
 #define  MCR_PS		(1U<<15)	/* 1: MII 10/100, 0: GMII 1000 */
 #define  MCR_FES	(1U<<14)	/* force speed 100 */
 #define  MCR_DO		(1U<<13)	/* don't receive my own HDX Tx frames */
 #define  MCR_LOOP	(1U<<12)	/* run loop back */
 #define  MCR_USEFDX	(1U<<11)	/* force full duplex */
 #define  MCR_IPCEN	(1U<<10)	/* handle checksum */
 #define  MCR_DR		(1U<<9)		/* attempt no tx retry, send once */
 #define  MCR_LUD	(1U<<8)		/* link condition report when RGMII */
-#define  MCR_ACS	(1U<<7)		/* auto pad strip CRC */
+#define  MCR_ACS	(1U<<7)		/* auto pad auto strip CRC */
 #define  MCR_DC		(1U<<4)		/* report excessive tx deferral */
 #define  MCR_TE		(1U<<3)		/* run Tx MAC engine, 0 to stop */
 #define  MCR_RE		(1U<<2)		/* run Rx MAC engine, 0 to stop */
 #define  MCR_PREA	(3U)		/* 1:0 preamble len. 0~2 */
 #define GMACAFR		0x0004		/* frame DA/SA address filter */
 #define  AFR_RA		(1U<<31)	/* accept all irrespective of filt. */
 #define  AFR_HPF	(1U<<10)	/* hash+perfect filter, or hash only */
 #define  AFR_SAF	(1U<<9)		/* source address filter */
 #define  AFR_SAIF	(1U<<8)		/* SA inverse filtering */
 #define  AFR_PCF	(2U<<6)		/* ??? */
 #define  AFR_DBF	(1U<<5)		/* reject broadcast frame */
 #define  AFR_PM		(1U<<4)		/* accept all multicast frame */
 #define  AFR_DAIF	(1U<<3)		/* DA inverse filtering */
 @@ -394,35 +398,33 @@ struct rdes {
  * 0x08 - 0b	H->MAC xfer engine program start addr 63:32.
  * 0x0c - 0f	H2M program addr 31:0 (these are absolute addr, not offset)
  * 0x10 - 13	H2M program length in 4 byte count.
  * 0x14 - 0b	M->HOST xfer engine program start addr 63:32.
  * 0x18 - 0f	M2H program addr 31:0 (absolute addr, not relative)
  * 0x1c - 13	M2H program length in 4 byte count.
  * 0x20 - 23	packet engine program addr 31:0, (absolute addr, not offset)
  * 0x24 - 27	packet program length in 4 byte count.
+ *
  * above ucode are loaded via mapped reg 0x210, 0x21c and 0x0c0.
  */
 #define  _BMR		0x00412080	/* XXX TBD */
-#define  _BMR0		0x00020181	/* XXX TBD */
+/* NetSec uses local RAM to handle GMAC desc arrays */
 /* NetSec uses local RAM to handle GMAC desc arrays and frame buffers */
 #define  _RDLA		0x18000
 #define  _TDLA		0x1c000
-#define  _MCR_FDX	0x0000280c	/* XXX TBD */
+/* lower address region is used for intermediate frame data buffers */
 #define  _MCR_HDX	0x0001a00c	/* XXX TBD */
 /*
- * all below are software constraction.
+ * all below are software construction.
  */
 #define MD_NTXDESC		128
 #define MD_NRXDESC		64
 #define MD_NTXSEGS		16
 #define MD_TXQUEUELEN		8
 #define MD_TXQUEUELEN_MASK	(MD_TXQUEUELEN - 1)
 #define MD_TXQUEUE_GC		(MD_TXQUEUELEN / 4)
 #define MD_NTXDESC_MASK	(MD_NTXDESC - 1)
 #define MD_NEXTTX(x)		(((x) + 1) & MD_NTXDESC_MASK)
 #define MD_NEXTTXS(x)		(((x) + 1) & MD_TXQUEUELEN_MASK)
 #define MD_NRXDESC_MASK	(MD_NRXDESC - 1)
 @@ -522,27 +524,27 @@ do {									\
 do {									\
 	bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap,		\
 	    SCX_CDRXOFF((x)), sizeof(struct rdes), (ops));		\
 } while (/*CONSTCOND*/0)
 #define SCX_INIT_RXDESC(sc, x)						\
 do {									\
 	struct scx_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)];		\
 	struct rdes *__rxd = &(sc)->sc_rxdescs[(x)];			\
 	struct mbuf *__m = __rxs->rxs_mbuf;				\
 	bus_addr_t __p = __rxs->rxs_dmamap->dm_segs[0].ds_addr;		\
 	bus_size_t __z = __rxs->rxs_dmamap->dm_segs[0].ds_len;		\
 	__m->m_data = __m->m_ext.ext_buf;				\
-	__rxd->r3 = htole32(__z);					\
+	__rxd->r3 = htole32(__z - 4);					\
 	__rxd->r2 = htole32(BUS_ADDR_LO32(__p));			\
 	__rxd->r1 = htole32(BUS_ADDR_HI32(__p));			\
 	__rxd->r0 &= htole32(R0_LD);					\
 	__rxd->r0 |= htole32(R0_OWN);					\
 } while (/*CONSTCOND*/0)
 /* memory mapped CSR register access */
 #define CSR_READ(sc,off) \
 	    bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (off))
 #define CSR_WRITE(sc,off,val) \
 	    bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (off), (val))
 /* flash memory access */
 @@ -552,91 +554,90 @@ do {									\
 static int scx_fdt_match(device_t, cfdata_t, void *);
 static void scx_fdt_attach(device_t, device_t, void *);
 static int scx_acpi_match(device_t, cfdata_t, void *);
 static void scx_acpi_attach(device_t, device_t, void *);
 CFATTACH_DECL_NEW(scx_fdt, sizeof(struct scx_softc),
     scx_fdt_match, scx_fdt_attach, NULL, NULL);
 CFATTACH_DECL_NEW(scx_acpi, sizeof(struct scx_softc),
     scx_acpi_match, scx_acpi_attach, NULL, NULL);
 static void scx_attach_i(struct scx_softc *);
 static void scx_reset(struct scx_softc *);
 static int scx_init(struct ifnet *);
 static void scx_stop(struct ifnet *, int);
 static int scx_init(struct ifnet *);
 static int scx_ioctl(struct ifnet *, u_long, void *);
 static void scx_set_rcvfilt(struct scx_softc *);
 static void scx_start(struct ifnet *);
 static void scx_watchdog(struct ifnet *);
 static int scx_intr(void *);
 static void txreap(struct scx_softc *);
-static void rxintr(struct scx_softc *);
+static void rxfill(struct scx_softc *);
 static int add_rxbuf(struct scx_softc *, int);
 static void rxdrain(struct scx_softc *sc);
 static void mii_statchg(struct ifnet *);
 static void scx_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 static int mii_readreg(device_t, int, int, uint16_t *);
 static int mii_writereg(device_t, int, int, uint16_t);
 static void phy_tick(void *);
 static void dump_hwfeature(struct scx_softc *);
-static void stopuengine(struct scx_softc *);
+static void resetuengine(struct scx_softc *);
 static void startuengine(struct scx_softc *);
 static void loaducode(struct scx_softc *);
 static void injectucode(struct scx_softc *, int, bus_addr_t, bus_size_t);
 static int get_mdioclk(uint32_t);
-#define WAIT_FOR_SET(sc, reg, set, fail) \
+#define WAIT_FOR_SET(sc, reg, set) \
-	wait_for_bits(sc, reg, set, ~0, fail)
+	wait_for_bits(sc, reg, set, ~0, 0)
-#define WAIT_FOR_CLR(sc, reg, clr, fail) \
+#define WAIT_FOR_CLR(sc, reg, clr) \
-	wait_for_bits(sc, reg, 0, clr, fail)
+	wait_for_bits(sc, reg, 0, clr, 0)
 static int
 wait_for_bits(struct scx_softc *sc, int reg,
     uint32_t set, uint32_t clr, uint32_t fail)
+{
 	uint32_t val;
 	int ntries;
 	for (ntries = 0; ntries < 1000; ntries++) {
 		val = CSR_READ(sc, reg);
 		if ((val & set) || !(val & clr))
 			return 0;
 		if (val & fail)
 			return 1;
 		DELAY(1);
+	}
 	return 1;
+}
 /* GMAC register indirect access */
 static int
 mac_read(struct scx_softc *sc, int reg)
+{
 	CSR_WRITE(sc, MACCMD, reg | CMD_BUSY);
-	(void)WAIT_FOR_CLR(sc, MACCMD, CMD_BUSY, 0);
+	(void)WAIT_FOR_CLR(sc, MACCMD, CMD_BUSY);
 	return CSR_READ(sc, MACDATA);
+}
 static void
 mac_write(struct scx_softc *sc, int reg, int val)
+{
 	CSR_WRITE(sc, MACDATA, val);
 	CSR_WRITE(sc, MACCMD, reg | CMD_IOWR | CMD_BUSY);
-	(void)WAIT_FOR_CLR(sc, MACCMD, CMD_BUSY, 0);
+	(void)WAIT_FOR_CLR(sc, MACCMD, CMD_BUSY);
+}
 /* dig and decode "clock-frequency" value for a given clkname */
 static int
 get_clk_freq(int phandle, const char *clkname)
+{
 	u_int index, n, cells;
 	const u_int *p;
 	int err, len, resid;
 	unsigned int freq = 0;
 	err = fdtbus_get_index(phandle, "clock-names", clkname, &index);
 	if (err == -1)
 @@ -863,27 +864,27 @@ aprint_normal("%s", device_xname(self));
 	acpi_resource_cleanup(&res);
 	return;
+}
 static void
 scx_attach_i(struct scx_softc *sc)
+{
 	struct ifnet * const ifp = &sc->sc_ethercom.ec_if;
 	struct mii_data * const mii = &sc->sc_mii;
 	struct ifmedia * const ifm = &mii->mii_media;
 	uint32_t which, dwimp, dwfea;
 	uint8_t enaddr[ETHER_ADDR_LEN];
 	bus_dma_segment_t seg;
-	paddr_t paddr;
+	paddr_t p, q;
 	uint32_t csr;
 	int i, nseg, error = 0;
 	which = CSR_READ(sc, HWVER);	/* Socionext version 5.xx */
 	dwimp = mac_read(sc, GMACIMPL);	/* DWC implementation XX.YY */
 	dwfea = mac_read(sc, HWFEA);	/* DWC feature bits */
 	aprint_naive("\n");
 	aprint_normal(": Socionext NetSec Gigabit Ethernet controller "
 	    "%x.%x\n", which >> 16, which & 0xffff);
 	aprint_normal_dev(sc->sc_dev,
 	    "DesignWare EMAC ver 0x%x (0x%x) hw feature %08x\n",
 @@ -1000,41 +1001,49 @@ aprint_normal_dev(sc->sc_dev, "descripto
 	sc->sc_flowflags = 0; /* track PAUSE flow caps */
 	if_attach(ifp);
 	if_deferred_start_init(ifp, NULL);
 	ether_ifattach(ifp, enaddr);
 	callout_init(&sc->sc_callout, 0);
 	callout_setfunc(&sc->sc_callout, phy_tick, sc);
 	rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev),
 	    RND_TYPE_NET, RND_FLAG_DEFAULT);
-	stopuengine(sc);
+	resetuengine(sc);
 	loaducode(sc);
 	/* feed NetSec descriptor array base addresses and timer value */
-	paddr = SCX_CDTXADDR(sc, 0);		/* tdes array (ring#0) */
+	p = SCX_CDTXADDR(sc, 0);		/* tdes array (ring#0) */
-	CSR_WRITE(sc, TDBA_HI, BUS_ADDR_HI32(paddr));
+	q = SCX_CDRXADDR(sc, 0);		/* rdes array (ring#1) */
-	CSR_WRITE(sc, TDBA_LO, BUS_ADDR_LO32(paddr));
+	CSR_WRITE(sc, TDBA_LO, BUS_ADDR_LO32(p));
-	paddr = SCX_CDRXADDR(sc, 0);		/* rdes array (ring#1) */
+	CSR_WRITE(sc, TDBA_HI, BUS_ADDR_HI32(p));
-	CSR_WRITE(sc, RDBA_HI, BUS_ADDR_HI32(paddr));
+	CSR_WRITE(sc, RDBA_LO, BUS_ADDR_LO32(q));
-	CSR_WRITE(sc, RDBA_LO, BUS_ADDR_LO32(paddr));
+	CSR_WRITE(sc, RDBA_HI, BUS_ADDR_HI32(q));
 	CSR_WRITE(sc, TXCONF, DESCNF_LE);	/* little endian */
 	CSR_WRITE(sc, RXCONF, DESCNF_LE);	/* little endian */
 	CSR_WRITE(sc, DMACTL_TMR, sc->sc_freq / 1000000 - 1);
-	startuengine(sc);
+	CSR_WRITE(sc, DMACTL_M2H, M2H_MODE_TRANS);
 	CSR_WRITE(sc, PKTCTRL, MODENRM);	/* change to use normal mode */
 	WAIT_FOR_SET(sc, MODE_TRANS, T2N_DONE);
 	/* do {
 		csr = CSR_READ(sc, MODE_TRANS);
 	} while ((csr & T2N_DONE) == 0); */
 	CSR_WRITE(sc, TXISR, ~0);	/* clear pending emtpry/error irq */
 	CSR_WRITE(sc, xINTAE_CLR, ~0);	/* disable tx / rx interrupts */
 	return;
   fail_5:
 	for (i = 0; i < MD_NRXDESC; i++) {
 		if (sc->sc_rxsoft[i].rxs_dmamap != NULL)
 			bus_dmamap_destroy(sc->sc_dmat,
 			    sc->sc_rxsoft[i].rxs_dmamap);
+	}
   fail_4:
 	for (i = 0; i < MD_TXQUEUELEN; i++) {
 		if (sc->sc_txsoft[i].txs_dmamap != NULL)
 			bus_dmamap_destroy(sc->sc_dmat,
 @@ -1060,37 +1069,52 @@ aprint_normal_dev(sc->sc_dev, "descripto
 static void
 scx_reset(struct scx_softc *sc)
+{
 	int loop = 0, busy;
 	mac_write(sc, GMACOMR, 0);
 	mac_write(sc, GMACBMR, BMR_RST);
 	do {
 		DELAY(1);
 		busy = mac_read(sc, GMACBMR) & BMR_RST;
 	} while (++loop < 3000 && busy);
 	mac_write(sc, GMACBMR, _BMR);
 	mac_write(sc, GMACAFR, 0);
+}
-#if 0
+static void
-	CSR_WRITE(sc, CLKEN, CLK_ALL);		/* distribute clock sources */
+scx_stop(struct ifnet *ifp, int disable)
 	CSR_WRITE(sc, SWRESET, 0);		/* reset operation */
-	CSR_WRITE(sc, SWRESET, SRST_RUN);	/* manifest run */
+	struct scx_softc *sc = ifp->if_softc;
-	CSR_WRITE(sc, COMINIT, INIT_DB | INIT_CLS);
+	uint32_t csr;
 	WAIT_FOR_CLR(sc, COMINIT, (INIT_DB | INIT_CLS), 0);
-	CSR_WRITE(sc, TXISR, ~0);
+	/* Stop the one second clock. */
 	callout_stop(&sc->sc_callout);
 	/* Down the MII. */
 	mii_down(&sc->sc_mii);
 	/* Mark the interface down and cancel the watchdog timer. */
 	ifp->if_flags &= ~IFF_RUNNING;
 	ifp->if_timer = 0;
 	CSR_WRITE(sc, RXIE_CLR, ~0);
 	CSR_WRITE(sc, TXIE_CLR, ~0);
 	CSR_WRITE(sc, xINTAE_CLR, ~0);
-#endif
+	CSR_WRITE(sc, TXISR, ~0);
 	CSR_WRITE(sc, RXISR, ~0);
 	csr = mac_read(sc, GMACOMR);
 	mac_write(sc, GMACOMR, csr &~ (OMR_SR | OMR_ST));
+}
 static int
 scx_init(struct ifnet *ifp)
+{
 	struct scx_softc *sc = ifp->if_softc;
 	const uint8_t *ea = CLLADDR(ifp->if_sadl);
 	uint32_t csr;
 	int i, error;
 	/* Cancel pending I/O. */
 	scx_stop(ifp, 0);
 @@ -1132,86 +1156,64 @@ scx_init(struct ifnet *ifp)
 	csr = (ea[3] << 24) | (ea[2] << 16) | (ea[1] << 8) |  ea[0];
 	mac_write(sc, GMACMAL0, csr);
 	csr = (ea[5] << 8) | ea[4];
 	mac_write(sc, GMACMAH0, csr);
 	/* accept multicast frame or run promisc mode */
 	scx_set_rcvfilt(sc);
 	/* set current media */
 	if ((error = ether_mediachange(ifp)) != 0)
 		goto out;
 	CSR_WRITE(sc, DESC_SRST, 01);
-	WAIT_FOR_CLR(sc, DESC_SRST, 01, 0);
+	WAIT_FOR_CLR(sc, DESC_SRST, 01);
 	CSR_WRITE(sc, DESC_INIT, 01);
-	WAIT_FOR_CLR(sc, DESC_INIT, 01, 0);
+	WAIT_FOR_CLR(sc, DESC_INIT, 01);
 	/* feed local memory descriptor array base addresses */
 	mac_write(sc, GMACRDLA, _RDLA);		/* GMAC rdes store */
 	mac_write(sc, GMACTDLA, _TDLA);		/* GMAC tdes store */
 	CSR_WRITE(sc, FLOWTHR, (48<<16) | 36);	/* pause|resume threshold */
 	mac_write(sc, GMACFCR, 256 << 16);	/* 31:16 pause value */
-	CSR_WRITE(sc, RXIE_CLR, ~0);	/* clear Rx interrupt enable */
+	CSR_WRITE(sc, INTF_SEL, sc->sc_miigmii ? INTF_GMII : INTF_RGMII);
 	CSR_WRITE(sc, TXIE_CLR, ~0);	/* clear Tx interrupt enable */
-	CSR_WRITE(sc, RXCLSCMAX, 8);	/* Rx coalesce upper bound */
+	CSR_WRITE(sc, RXCOALESC, 8);		/* Rx coalesce bound */
-	CSR_WRITE(sc, TXCLSCMAX, 8);	/* Tx coalesce upper bound */
+	CSR_WRITE(sc, TXCOALESC, 8);		/* Tx coalesce bound */
-	CSR_WRITE(sc, RXITIMER, 500);	/* Rx co. timer usec */
+	CSR_WRITE(sc, RCLSCTIME, 500|(1U<<31));	/* Rx co. guard time usec */
-	CSR_WRITE(sc, TXITIMER, 500);	/* Tx co. timer usec */
+	CSR_WRITE(sc, TCLSCTIME, 500|(1U<<31));	/* Tx co. guard time usec */
 	CSR_WRITE(sc, RXIE_SET, RXI_RC_ERR | RXI_PKTCNT | RXI_TMREXP);
 	CSR_WRITE(sc, TXIE_SET, TXI_TR_ERR | TXI_TXDONE | TXI_TMREXP);
 	CSR_WRITE(sc, xINTAE_SET, IRQ_RX | IRQ_TX);
 #if 1
 	/* clear event counters, auto-zero after every read */
-	mac_write(sc, GMACEVCTL, EVC_CR /* | EVC_ROR */);
+	mac_write(sc, GMACEVCTL, EVC_CR | EVC_ROR);
 #endif
 	/* kick to start GMAC engine */
 	csr = mac_read(sc, GMACOMR);
 	mac_write(sc, GMACOMR, csr | OMR_SR | OMR_ST);
 	ifp->if_flags |= IFF_RUNNING;
 	/* start one second timer */
 	callout_schedule(&sc->sc_callout, hz);
  out:
 	return error;
+}
 static void
 scx_stop(struct ifnet *ifp, int disable)
 	struct scx_softc *sc = ifp->if_softc;
 	/* Stop the one second clock. */
 	callout_stop(&sc->sc_callout);
 	/* Down the MII. */
 	mii_down(&sc->sc_mii);
 	/* Mark the interface down and cancel the watchdog timer. */
 	ifp->if_flags &= ~IFF_RUNNING;
 	ifp->if_timer = 0;
 	CSR_WRITE(sc, xINTAE_CLR, ~0);
 	CSR_WRITE(sc, TXISR, ~0);
 	CSR_WRITE(sc, RXISR, ~0);
 static int
 scx_ioctl(struct ifnet *ifp, u_long cmd, void *data)
+{
 	struct scx_softc *sc = ifp->if_softc;
 	struct ifreq *ifr = (struct ifreq *)data;
 	struct ifmedia *ifm = &sc->sc_mii.mii_media;
 	int s, error;
 	s = splnet();
 	switch (cmd) {
 	case SIOCSIFMEDIA:
 		/* Flow control requires full-duplex mode. */
 @@ -1325,192 +1327,187 @@ aprint_normal_dev(sc->sc_dev, "[%d] %s\n
 			mac_write(sc, GMACMAH(i), addr | 1U<<31);
 		} else {
 			/* use hash table when too many */
 			crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN);
 			crc = bit_reverse_32(~crc);
 			/* 1(31) 5(30:26) bit sampling */
 			mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f);
+		}
 		ETHER_NEXT_MULTI(step, enm);
 		i++;
+	}
 	ETHER_UNLOCK(ec);
 	if (crc)
-		csr |= AFR_MHTE;
+		csr |= AFR_MHTE; /* use mchash[] */
-	csr |= AFR_HPF; /* use hash+perfect */
+	csr |= AFR_HPF; /* use perfect match as well */
  update:
 	mac_write(sc, GMACMHTH, mchash[1]);
 	mac_write(sc, GMACMHTL, mchash[0]);
  update:
 	/* With PR or PM, MHTE/MHTL/MHTH are never consulted. really? */
 	mac_write(sc, GMACAFR, csr);
 	return;
+}
 static void
 scx_start(struct ifnet *ifp)
+{
 	struct scx_softc *sc = ifp->if_softc;
 	struct mbuf *m0;
 	struct scx_txsoft *txs;
 	bus_dmamap_t dmamap;
 	int error, nexttx, lasttx, ofree, seg;
 	uint32_t tdes0;
 	if ((ifp->if_flags & IFF_RUNNING) == 0)
 		return;
 	/* Remember the previous number of free descriptors. */
 	ofree = sc->sc_txfree;
 	/*
 	 * Loop through the send queue, setting up transmit descriptors
 	 * until we drain the queue, or use up all available transmit
 	 * descriptors.
 	 */
 	for (;;) {
 		IFQ_POLL(&ifp->if_snd, m0);
 		if (m0 == NULL)
 			break;
 		if (sc->sc_txsfree < MD_TXQUEUE_GC) {
 			txreap(sc);
 			if (sc->sc_txsfree == 0)
 				break;
+		}
 		txs = &sc->sc_txsoft[sc->sc_txsnext];
 		dmamap = txs->txs_dmamap;
 		error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0,
 		    BUS_DMA_WRITE | BUS_DMA_NOWAIT);
 		if (error) {
 			if (error == EFBIG) {
 				aprint_error_dev(sc->sc_dev,
 				    "Tx packet consumes too many "
 				    "DMA segments, dropping...\n");
 				IFQ_DEQUEUE(&ifp->if_snd, m0);
 				m_freem(m0);
 				if_statinc_ref(ifp, if_oerrors);
 				continue;
+			}
 			/* Short on resources, just stop for now. */
 			break;
+		}
 		if (dmamap->dm_nsegs > sc->sc_txfree) {
 			/*
 			 * Not enough free descriptors to transmit this
 			 * packet.  We haven't committed anything yet,
 			 * so just unload the DMA map, put the packet
 			 * back on the queue, and punt.
 			 */
 			bus_dmamap_unload(sc->sc_dmat, dmamap);
 			break;
+		}
 		IFQ_DEQUEUE(&ifp->if_snd, m0);
 		/*
 		 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET.
 		 */
 		bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize,
 		    BUS_DMASYNC_PREWRITE);
 		tdes0 = 0; /* to postpone 1st segment T0_OWN write */
 		lasttx = -1;
 		for (nexttx = sc->sc_txnext, seg = 0;
 		     seg < dmamap->dm_nsegs;
 		     seg++, nexttx = MD_NEXTTX(nexttx)) {
 			struct tdes *tdes = &sc->sc_txdescs[nexttx];
-			bus_addr_t paddr = dmamap->dm_segs[seg].ds_addr;
+			bus_addr_t p = dmamap->dm_segs[seg].ds_addr;
 			bus_size_t z = dmamap->dm_segs[seg].ds_len;
 			/*
 			 * If this is the first descriptor we're
 			 * enqueueing, don't set the OWN bit just
 			 * yet.	 That could cause a race condition.
 			 * We'll do it below.
 			 */
-			tdes->t3 = htole32(dmamap->dm_segs[seg].ds_len);
+			tdes->t3 = htole32(z);
-			tdes->t2 = htole32(BUS_ADDR_LO32(paddr));
+			tdes->t2 = htole32(BUS_ADDR_LO32(p));
-			tdes->t1 = htole32(BUS_ADDR_HI32(paddr));
+			tdes->t1 = htole32(BUS_ADDR_HI32(p));
-			tdes->t0 = htole32(tdes0 | (tdes->t0 & T0_LD) |
+			tdes->t0 &= htole32(T0_LD);
 			tdes->t0 |= htole32(tdes0 |
 					(15 << T0_TDRID) | T0_PT |
 					sc->sc_t0cotso | T0_TRS);
 			tdes0 = T0_OWN; /* 2nd and other segments */
 			/* NB; t0 DRID field contains zero */
 			lasttx = nexttx;
+		}
 		/* HW lacks of per-frame xmit done interrupt control */
 		/* Write deferred 1st segment T0_OWN at the final stage */
 		sc->sc_txdescs[lasttx].t0 |= htole32(T0_LS);
 		sc->sc_txdescs[sc->sc_txnext].t0 |= htole32(T0_FS | T0_OWN);
 		SCX_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs,
 		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 		/* submit one frame to xmit */
 		CSR_WRITE(sc, TXSUBMIT, 1);
 		txs->txs_mbuf = m0;
 		txs->txs_firstdesc = sc->sc_txnext;
 		txs->txs_lastdesc = lasttx;
 		txs->txs_ndesc = dmamap->dm_nsegs;
 		sc->sc_txfree -= txs->txs_ndesc;
 		sc->sc_txnext = nexttx;
 		sc->sc_txsfree--;
 		sc->sc_txsnext = MD_NEXTTXS(sc->sc_txsnext);
 		/*
 		 * Pass the packet to any BPF listeners.
 		 */
 		bpf_mtap(ifp, m0, BPF_D_OUT);
+	}
 	if (sc->sc_txfree != ofree) {
 		/* Set a watchdog timer in case the chip flakes out. */
 		ifp->if_timer = 5;
+	}
+}
 #define EVENT_DEBUG 1
 static void
 scx_watchdog(struct ifnet *ifp)
+{
 	struct scx_softc *sc = ifp->if_softc;
 	/*
 	 * Since we're not interrupting every packet, sweep
 	 * up before we report an error.
 	 */
 	txreap(sc);
 	if (sc->sc_txfree != MD_NTXDESC) {
 		aprint_error_dev(sc->sc_dev,
 		    "device timeout (txfree %d txsfree %d txnext %d)\n",
 		    sc->sc_txfree, sc->sc_txsfree, sc->sc_txnext);
 		if_statinc(ifp, if_oerrors);
 #if EVENT_DEBUG == 1
 aprint_error_dev(sc->sc_dev,
     "rx frames %d, octects %d, bcast %d, mcast %d\n",
     mac_read(sc, GMACEVCNT(27)),
     mac_read(sc, GMACEVCNT(28)),
     mac_read(sc, GMACEVCNT(30)),
     mac_read(sc, GMACEVCNT(31)));
 aprint_error_dev(sc->sc_dev,
     "tx frames %d, octects %d, bcast %d, mcast %d\n",
     mac_read(sc, GMACEVCNT(1)),
     mac_read(sc, GMACEVCNT(0)),
     mac_read(sc, GMACEVCNT(2)),
     mac_read(sc, GMACEVCNT(3)));
 aprint_error_dev(sc->sc_dev,
     "rx frames %d, octects %d, bcast %d, mcast %d\n",
     mac_read(sc, GMACEVCNT(27)),
     mac_read(sc, GMACEVCNT(28)),
     mac_read(sc, GMACEVCNT(30)),
     mac_read(sc, GMACEVCNT(31)));
 aprint_error_dev(sc->sc_dev,
     "current tdes addr %x, buf addr %x\n",
     mac_read(sc, 0x1048), mac_read(sc, 0x1050));
 aprint_error_dev(sc->sc_dev,
     "current rdes addr %x, buf addr %x\n",
     mac_read(sc, 0x104c), mac_read(sc, 0x1054));
 #endif
 		/* Reset the interface. */
 		scx_init(ifp);
+	}
 	scx_start(ifp);
+}
 @@ -1522,28 +1519,28 @@ scx_intr(void *arg)
 	status = CSR_READ(sc, xINTSR); /* not W1C */
 	enable = CSR_READ(sc, xINTAEN);
 	if ((status & enable) == 0)
 		return 0;
 	if (status & (IRQ_TX | IRQ_RX)) {
 		CSR_WRITE(sc, xINTAE_CLR, (IRQ_TX | IRQ_RX));
 		status = CSR_READ(sc, RXISR);
 		CSR_WRITE(sc, RXISR, status);
 		if (status & RXI_RC_ERR)
 			aprint_error_dev(sc->sc_dev, "Rx error\n");
 		if (status & (RXI_PKTCNT | RXI_TMREXP)) {
-			rxintr(sc);
+			rxfill(sc);
-			(void)CSR_READ(sc, RXDONECNT); /* clear RXI_RXDONE */
+			(void)CSR_READ(sc, RXAVAILCNT); /* clear RXI_PKTCNT */
+		}
 		status = CSR_READ(sc, TXISR);
 		CSR_WRITE(sc, TXISR, status);
 		if (status & TXI_TR_ERR)
 			aprint_error_dev(sc->sc_dev, "Tx error\n");
 		if (status & (TXI_TXDONE | TXI_TMREXP)) {
 			txreap(sc);
 			(void)CSR_READ(sc, TXDONECNT); /* clear TXI_TXDONE */
+		}
 		CSR_WRITE(sc, xINTAE_SET, (IRQ_TX | IRQ_RX));
+	}
 @@ -1576,133 +1573,128 @@ txreap(struct scx_softc *sc)
 		sc->sc_txfree += txs->txs_ndesc;
 		bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap,
 , txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE);
 		bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap);
 		m_freem(txs->txs_mbuf);
 		txs->txs_mbuf = NULL;
+	}
 	sc->sc_txsdirty = i;
 	if (sc->sc_txsfree == MD_TXQUEUELEN)
 		ifp->if_timer = 0;
+}
 static void
-rxintr(struct scx_softc *sc)
+rxfill(struct scx_softc *sc)
+{
 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
 	struct scx_rxsoft *rxs;
 	struct mbuf *m;
-	uint32_t rxstat;
+	uint32_t rxstat, rlen;
-	int i, len;
+	int i;
 	for (i = sc->sc_rxptr; /*CONSTCOND*/ 1; i = MD_NEXTRX(i)) {
 		rxs = &sc->sc_rxsoft[i];
 		SCX_CDRXSYNC(sc, i,
 		    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
 		rxstat = le32toh(sc->sc_rxdescs[i].r0);
 		if (rxstat & R0_OWN) /* desc is left empty */
 			break;
-		/* R0_FS | R0_LS must have been marked for this desc */
+		/* received frame length in R3 31:16 */
 		rlen = le32toh(sc->sc_rxdescs[i].r3) >> 16;
 		/* R0_FS | R0_LS must have been marked for this desc */
 		rxs = &sc->sc_rxsoft[i];
 		bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0,
 		    rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
-		len = sc->sc_rxdescs[i].r3 >> 16; /* 31:16 received */
+		/* dispense new storage to receive frame */
 		len -= ETHER_CRC_LEN;	/* Trim CRC off */
 		m = rxs->rxs_mbuf;
 		if (add_rxbuf(sc, i) != 0) {
-			if_statinc(ifp, if_ierrors);
+			if_statinc(ifp, if_ierrors);	/* resource shortage */
-			SCX_INIT_RXDESC(sc, i);
+			SCX_INIT_RXDESC(sc, i);		/* then reuse */
 			bus_dmamap_sync(sc->sc_dmat,
 			    rxs->rxs_dmamap, 0,
 			    rxs->rxs_dmamap->dm_mapsize,
 			    BUS_DMASYNC_PREREAD);
 			continue;
+		}
 		/* complete mbuf */
 		m_set_rcvif(m, ifp);
-		m->m_pkthdr.len = m->m_len = len;
+		m->m_pkthdr.len = m->m_len = rlen;
 		m->m_flags |= M_HASFCS;
 		if (rxstat & R0_CSUM) {
 			uint32_t csum = M_CSUM_IPv4;
 			if (rxstat & R0_CERR)
 				csum |= M_CSUM_IPv4_BAD;
 			m->m_pkthdr.csum_flags |= csum;
+		}
 		/* and pass to upper layer */
 		if_percpuq_enqueue(ifp->if_percpuq, m);
+	}
 	sc->sc_rxptr = i;
+}
 static int
 add_rxbuf(struct scx_softc *sc, int i)
+{
 	struct scx_rxsoft *rxs = &sc->sc_rxsoft[i];
 	struct mbuf *m;
 	int error;
 	MGETHDR(m, M_DONTWAIT, MT_DATA);
 	if (m == NULL)
 		return ENOBUFS;
 	MCLGET(m, M_DONTWAIT);
 	if ((m->m_flags & M_EXT) == 0) {
 		m_freem(m);
 		return ENOBUFS;
+	}
 	if (rxs->rxs_mbuf != NULL)
 		bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap);
 	rxs->rxs_mbuf = m;
 	error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap,
 	    m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT);
 	if (error) {
 		aprint_error_dev(sc->sc_dev,
 		    "can't load rx DMA map %d, error = %d\n", i, error);
 		panic("add_rxbuf");
+	}
 	bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0,
 	    rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
 	SCX_INIT_RXDESC(sc, i);
 	return 0;
+}
 static void
 rxdrain(struct scx_softc *sc)
+{
 	struct scx_rxsoft *rxs;
 	int i;
 	for (i = 0; i < MD_NRXDESC; i++) {
 		rxs = &sc->sc_rxsoft[i];
 		if (rxs->rxs_mbuf != NULL) {
 			bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap);
 			m_freem(rxs->rxs_mbuf);
 			rxs->rxs_mbuf = NULL;
+		}
+	}
+}
 #define LINK_DEBUG 0
-void
+static void
 mii_statchg(struct ifnet *ifp)
+{
 	struct scx_softc *sc = ifp->if_softc;
 	struct mii_data *mii = &sc->sc_mii;
 	const int Mbps[4] = { 10, 100, 1000, 0 };
 	uint32_t miisr, mcr, fcr;
 	int spd;
 	/* decode MIISR register value */
 	miisr = mac_read(sc, GMACMIISR);
 	spd = Mbps[(miisr & MIISR_SPD) >> 1];
 #if LINK_DEBUG == 1
 	static uint32_t oldmiisr = 0;
 @@ -1818,87 +1810,91 @@ phy_tick(void *arg)
 	struct mii_data *mii = &sc->sc_mii;
 	int s;
 	s = splnet();
 	mii_tick(mii);
 	splx(s);
 #ifdef GMAC_EVENT_COUNTERS
 	/* 80 event counters exist */
 #endif
 	callout_schedule(&sc->sc_callout, hz);
+}
 static void
-stopuengine(struct scx_softc *sc)
+resetuengine(struct scx_softc *sc)
+{
-	if (CSR_READ(sc, CORESTAT) != 0) {
+	if (CSR_READ(sc, CORESTAT) == 0) {
 		/* make sure to stop */
 		CSR_WRITE(sc, DMACTL_H2M, DMACTL_STOP);
 		CSR_WRITE(sc, DMACTL_M2H, DMACTL_STOP);
-		WAIT_FOR_CLR(sc, DMACTL_H2M, DMACTL_STOP, 0);
+		WAIT_FOR_CLR(sc, DMACTL_H2M, DMACTL_STOP);
-		WAIT_FOR_CLR(sc, DMACTL_M2H, DMACTL_STOP, 0);
+		WAIT_FOR_CLR(sc, DMACTL_M2H, DMACTL_STOP);
+	}
 	CSR_WRITE(sc, SWRESET, 0);		/* reset operation */
 	CSR_WRITE(sc, SWRESET, SRST_RUN);	/* manifest run */
 	CSR_WRITE(sc, COMINIT, INIT_DB | INIT_CLS);
-	WAIT_FOR_CLR(sc, COMINIT, (INIT_DB | INIT_CLS), 0);
+	WAIT_FOR_CLR(sc, COMINIT, (INIT_DB | INIT_CLS));
+}
-static void
+#define UCODE_DEBUG 0
 startuengine(struct scx_softc *sc)
 	int err;
 	CSR_WRITE(sc, CORESTAT, 0);
 	err = WAIT_FOR_SET(sc, xINTSR, IRQ_UCODE, 0);
 	if (err) {
 		aprint_error_dev(sc->sc_dev, "uengine start failed\n");
 	CSR_WRITE(sc, xINTSR, IRQ_UCODE);
 /*
  * 3 independent uengines exist to process host2media, media2host and
  * packet data flows.
  */
 static void
 loaducode(struct scx_softc *sc)
+{
 	uint32_t up, lo, sz;
 	uint64_t addr;
 	int err;
 	CSR_WRITE(sc, xINTSR, IRQ_UCODE);
 	up = EE_READ(sc, 0x08); /* H->M ucode addr high */
 	lo = EE_READ(sc, 0x0c); /* H->M ucode addr low */
 	sz = EE_READ(sc, 0x10); /* H->M ucode size */
 	sz *= 4;
 	addr = ((uint64_t)up << 32) | lo;
 aprint_normal_dev(sc->sc_dev, "0x%x H2M ucode %u\n", lo, sz);
 	injectucode(sc, UCODE_H2M, (bus_addr_t)addr, (bus_size_t)sz);
 #if UCODE_DEBUG == 1
 aprint_normal_dev(sc->sc_dev, "0x%x H2M ucode %u\n", lo, sz);
 #endif
 	up = EE_READ(sc, 0x14); /* M->H ucode addr high */
 	lo = EE_READ(sc, 0x18); /* M->H ucode addr low */
 	sz = EE_READ(sc, 0x1c); /* M->H ucode size */
 	sz *= 4;
 	addr = ((uint64_t)up << 32) | lo;
 	injectucode(sc, UCODE_M2H, (bus_addr_t)addr, (bus_size_t)sz);
 #if UCODE_DEBUG == 1
 aprint_normal_dev(sc->sc_dev, "0x%x M2H ucode %u\n", lo, sz);
 #endif
 	lo = EE_READ(sc, 0x20); /* PKT ucode addr */
 	sz = EE_READ(sc, 0x24); /* PKT ucode size */
 	sz *= 4;
 	injectucode(sc, UCODE_PKT, (bus_addr_t)lo, (bus_size_t)sz);
 #if UCODE_DEBUG == 1
 aprint_normal_dev(sc->sc_dev, "0x%x PKT ucode %u\n", lo, sz);
 #endif
 	CSR_WRITE(sc, CORESTAT, 0);
 	err = WAIT_FOR_SET(sc, xINTSR, IRQ_UCODE);
 	if (err) {
 		aprint_error_dev(sc->sc_dev, "uengine start failed\n");
+	}
 	CSR_WRITE(sc, xINTSR, IRQ_UCODE);
+}
 static void
 injectucode(struct scx_softc *sc, int port,
 	bus_addr_t addr, bus_size_t size)
+{
 	bus_space_handle_t bsh;
 	bus_size_t off;
 	uint32_t ucode;
 	if (bus_space_map(sc->sc_st, addr, size, 0, &bsh) != 0) {
 		aprint_error_dev(sc->sc_dev,
 		    "eeprom map failure for ucode port 0x%x\n", port);
 @@ -1922,27 +1918,27 @@ get_mdioclk(uint32_t freq)
 	if (freq < 60)
 		return GAR_MDIO_35_60MHZ;
 	if (freq < 100)
 		return GAR_MDIO_60_100MHZ;
 	if (freq < 150)
 		return GAR_MDIO_100_150MHZ;
 	if (freq < 250)
 		return GAR_MDIO_150_250MHZ;
 	return GAR_MDIO_250_300MHZ;
+}
 #define HWFEA_DEBUG 1
-void
+static void
 dump_hwfeature(struct scx_softc *sc)
+{
 #if HWFEA_DEBUG == 1
 	struct {
 		uint32_t bit;
 		const char *des;
 	} field[] = {
 		{ 27, "SA/VLAN insertion replacement enabled" },
 		{ 26, "flexible PPS enabled" },
 		{ 25, "time stamping with internal system enabled" },
 		{ 24, "alternate/enhanced descriptor enabled" },
 		{ 19, "rx FIFO >2048 enabled" },
 		{ 18, "type 2 IP checksum offload enabled" },