 @@ -1,14 +1,14 @@
-/*	$NetBSD: if_scx.c,v 1.42 2023/06/14 00:07:22 nisimura Exp $	*/
+/*	$NetBSD: if_scx.c,v 1.43 2023/06/15 07:21:45 nisimura Exp $	*/
 /*-
  * Copyright (c) 2020 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Tohru Nishimura.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
 @@ -39,27 +39,27 @@
  * to handle incoming frames, outgoing frames and packet data crypto
  * processing. uP programs are stored in an external flash memory and
  * have to be loaded by device driver.
  * NetSec uses Synopsys DesignWare Core EMAC.  DWC implementation
  * register (0x20) is known to have 0x10.36 and feature register (0x1058)
  * reports 0x11056f37.
  *  <24> alternative/enhanced desc format
  *  <18> receive IP type 2 checksum offload
  *  <16> transmit checksum offload
  *  <11> event counter (mac management counter, MMC)
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_scx.c,v 1.42 2023/06/14 00:07:22 nisimura Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_scx.c,v 1.43 2023/06/15 07:21:45 nisimura Exp $");
 #include <sys/param.h>
 #include <sys/bus.h>
 #include <sys/intr.h>
 #include <sys/device.h>
 #include <sys/callout.h>
 #include <sys/mbuf.h>
 #include <sys/errno.h>
 #include <sys/rndsource.h>
 #include <sys/kernel.h>
 #include <sys/systm.h>
 #include <net/if.h>
 @@ -110,116 +110,116 @@ struct rdes {
 #define R0_COK		(1U<<6)		/* 1: found ok */
 /* R1 frame address 63:32 */
 /* R2 frame address 31:0 */
 /* R3 31:16 received frame length, 15:0 buffer length to receive */
 /*
  * SC2A11 registers. 0x100 - 1204
  */
 #define SWRESET		0x104
 #define  SRST_RUN	(1U<<31)	/* instruct start, 0 to stop */
 #define COMINIT		0x120
 #define  INIT_DB	(1U<<2)		/* ???; self clear when done */
 #define  INIT_CLS	(1U<<1)		/* ???; self clear when done */
 #define PKTCTRL		0x140		/* pkt engine control */
 #define  MODENRM	(1U<<28)	/* set operational mode to 'normal' */
 #define  ENJUMBO	(1U<<27)	/* allow jumbo frame */
 #define  RPTCSUMERR	(1U<<3)		/* log Rx checksum error */
 #define  RPTHDCOMP	(1U<<2)		/* log header incomplete condition */
 #define  RPTHDERR	(1U<<1)		/* log header error */
 #define  DROPNOMATCH	(1U<<0)		/* drop no match frames */
 #define xINTSR		0x200		/* aggregated interrupt status */
 #define  IRQ_UCODE	(1U<<20)	/* ucode load completed; W1C */
 #define  IRQ_MAC	(1U<<19)	/* ??? */
 #define  IRQ_PKT	(1U<<18)	/* ??? */
 #define  IRQ_BOOTCODE	(1U<<5)		/* ??? */
 #define  IRQ_XDONE	(1U<<4)		/* ??? mode change completed */
 #define  IRQ_RX		(1U<<1)		/* top level Rx interrupt */
 #define  IRQ_TX		(1U<<0)		/* top level Tx interrupt */
 #define xINTAEN		0x204		/* INT_A enable */
 #define xINTAE_SET	0x234		/* bit to set */
 #define xINTAE_CLR	0x238		/* bit to clr */
 #define xINTBEN		0x23c		/* INT_B enable */
 #define xINTBE_SET	0x240		/* bit to set */
 #define xINTBE_CLR	0x244		/* bit to clr */
 #define TXISR		0x400		/* transmit status; W1C */
 #define TXIEN		0x404		/* tx interrupt enable */
 #define TXIE_SET	0x428		/* bit to set */
 #define TXIE_CLR	0x42c		/* bit to clr */
 #define  TXI_NTOWNR	(1U<<17)	/* ??? desc array got empty */
-#define  TXI_TR_ERR	(1U<<16)	/* xmit error */
+#define  TXI_TR_ERR	(1U<<16)	/* xmit error detected */
 #define  TXI_TXDONE	(1U<<15)	/* xmit completed */
 #define  TXI_TMREXP	(1U<<14)	/* coalesce guard timer expired */
 #define RXISR		0x440		/* receive status; W1C */
 #define RXIEN		0x444		/* rx interrupt enable */
 #define RXIE_SET	0x468		/* bit to set */
 #define RXIE_CLR	0x46c		/* bit to clr */
-#define  RXI_RC_ERR	(1U<<16)	/* recv error */
+#define  RXI_RC_ERR	(1U<<16)	/* recv error detected */
 #define  RXI_PKTCNT	(1U<<15)	/* recv counter has new value */
 #define  RXI_TMREXP	(1U<<14)	/* coalesce guard timer expired */
 #define TDBA_LO		0x408		/* tdes array base addr 31:0 */
 #define TDBA_HI		0x434		/* tdes array base addr 63:32 */
 #define RDBA_LO		0x448		/* rdes array base addr 31:0 */
 #define RDBA_HI		0x474		/* rdes array base addr 63:32 */
 #define TXCONF		0x430		/* tdes config */
 #define RXCONF		0x470		/* rdes config */
 #define  DESCNF_UP	(1U<<31)	/* 'up-and-running' */
 #define  DESCNF_CHRST	(1U<<30)	/* channel reset */
-#define  DESCNF_TMR	(1U<<4)		/* coalesce timer mode select */
+#define  DESCNF_TMR	(1U<<4)		/* coalesce timer unit select */
 #define  DESCNF_LE	(1)		/* little endian desc format */
 #define TXSUBMIT	0x410		/* submit frame(s) to transmit */
 #define TXCOALESC	0x418		/* tx intr coalesce upper bound */
 #define RXCOALESC	0x458		/* rx intr coalesce upper bound */
-#define TCLSCTIME	0x420		/* tintr guard time usec, MSB to on */
+#define TCLSCTIME	0x420		/* tintr guard time usec */
-#define RCLSCTIME	0x460		/* rintr guard time usec, MSB to on */
+#define RCLSCTIME	0x460		/* rintr guard time usec */
 #define TXDONECNT	0x414		/* tx completed count, auto-zero */
 #define RXAVAILCNT	0x454		/* rx available count, auto-zero */
-#define DMACTL_TMR	0x20c		/* engine DMA timer value */
+#define DMACTL_TMR	0x20c		/* DMA cycle tick value */
 #define PKTCTRL		0x140		/* pkt engine control */
 #define  MODENRM	(1U<<28)	/* set operational mode to 'normal' */
 #define  ENJUMBO	(1U<<27)	/* allow jumbo frame */
 #define  RPTCSUMERR	(1U<<3)		/* log Rx checksum error */
 #define  RPTHDCOMP	(1U<<2)		/* log header incomplete condition */
 #define  RPTHDERR	(1U<<1)		/* log header error */
 #define  DROPNOMATCH	(1U<<0)		/* drop no match frames */
 #define UCODE_PKT	0x0d0		/* packet engine ucode port */
 #define UCODE_H2M	0x210		/* host2media engine ucode port */
 #define UCODE_M2H	0x21c		/* media2host engine ucode port */
 #define CORESTAT	0x218		/* engine run state */
 #define  PKTSTOP	(1U<<2)		/* pkt engine stopped */
 #define  M2HSTOP	(1U<<1)		/* M2H engine stopped */
 #define  H2MSTOP	(1U<<0)		/* H2M engine stopped */
 #define DMACTL_H2M	0x214		/* host2media engine control */
 #define DMACTL_M2H	0x220		/* media2host engine control */
 #define  DMACTL_STOP	(1U<<0)		/* instruct stop; self-clear */
 #define  M2H_MODE_TRANS	(1U<<20)	/* initiate M2H mode change */
-#define UCODE_PKT	0x0d0		/* packet engine ucode port */
+#define MODE_TRANS	0x500		/* mode change completion status */
 #define  N2T_DONE	(1U<<20)	/* normal->taiki change completed */
 #define  T2N_DONE	(1U<<19)	/* taiki->normal change completed */
 #define CLKEN		0x100		/* clock distribution enable */
 #define  CLK_G		(1U<<5)		/* feed clk domain G */
 #define  CLK_C		(1U<<1)		/* feed clk domain C */
 #define  CLK_D		(1U<<0)		/* feed clk domain D */
 #define DESC_INIT	0x11fc		/* write 1 for desc init, SC */
 #define DESC_SRST	0x1204		/* write 1 for desc sw reset, SC */
 /* GMAC register indirect access. thru MACCMD/MACDATA operation */
 #define MACDATA		0x11c0		/* gmac register rd/wr data */
 #define MACCMD		0x11c4		/* gmac register operation */
 #define  CMD_IOWR	(1U<<28)	/* write op */
 #define  CMD_BUSY	(1U<<31)	/* busy bit */
 #define MACSTAT		0x1024		/* mac interrupt status (unused) */
 #define MACINTE		0x1028		/* mac interrupt enable (unused) */
 #define FLOWTHR		0x11cc		/* flow control threshold */
 /* 31:16 pause threshold, 15:0 resume threshold */
 #define INTF_SEL	0x11d4		/* phy interface type */
 #define  INTF_GMII	0
 #define  INTF_RGMII	1
 #define  INTF_RMII	4
 #define DESC_INIT	0x11fc		/* write 1 for desc init, SC */
 #define DESC_SRST	0x1204		/* write 1 for desc sw reset, SC */
 #define MODE_TRANS	0x500		/* mode change completion status */
 #define  N2T_DONE	(1U<<20)	/* normal->taiki change completed */
 #define  T2N_DONE	(1U<<19)	/* taiki->normal change completed */
 #define MCVER		0x22c		/* micro controller version */
 #define HWVER		0x230		/* hardware version */
 /*
  * GMAC registers are mostly identical to Synopsys DesignWare Core
  * Ethernet. These must be handled by indirect access.
  */
 #define GMACMCR		0x0000		/* MAC configuration */
 #define  MCR_IBN	(1U<<30)	/* watch in-band-signal */
 #define  MCR_CST	(1U<<25)	/* strip CRC */
 #define  MCR_TC		(1U<<24)	/* keep RGMII PHY notified */
 #define  MCR_WD		(1U<<23)	/* allow long >2048 tx frame */
 #define  MCR_JE		(1U<<20)	/* allow ~9018 tx jumbo frame */
 @@ -344,28 +344,31 @@ struct rdes {
 #define  DMAI_FBI	(1U<<13)	/* DMA bus error detected */
 #define  DMAI_ETI	(1U<<10)	/* single frame Tx completed */
 #define  DMAI_RWT	(1U<<9)		/* longer than 2048 frame received */
 #define  DMAI_RPS	(1U<<8)		/* Rx process is now stopped */
 #define  DMAI_RU	(1U<<7)		/* Rx descriptor not available */
 #define  DMAI_RI	(1U<<6)		/* frame Rx completed by !R1_DIC */
 #define  DMAI_UNF	(1U<<5)		/* Tx underflow detected */
 #define  DMAI_OVF	(1U<<4)		/* receive buffer overflow detected */
 #define  DMAI_TJT	(1U<<3)		/* longer than 2048 frame sent */
 #define  DMAI_TU	(1U<<2)		/* Tx descriptor not available */
 #define  DMAI_TPS	(1U<<1)		/* transmission is stopped */
 #define  DMAI_TI	(1U<<0)		/* frame Tx completed by T0_IC */
 #define GMACOMR		0x1018		/* DMA operation mode */
 #define  OMR_DT		(1U<<26)	/* don't drop error frames */
 #define  OMR_RSF	(1U<<25)	/* 1: Rx store&forward, 0: immed. */
 #define  OMR_DFF	(1U<<24)	/* don't flush rx frames on shortage */
 #define  OMR_TSF	(1U<<21)	/* 1: Tx store&forward, 0: immed. */
 #define  OMR_FTF	(1U<<20)	/* initiate tx FIFO reset, SC */
 #define  OMR_TTC	(14)		/* 16:14 Tx threshold */
 #define  OMR_ST		(1U<<13)	/* run Tx DMA engine, 0 to stop */
 #define  OMR_RFD	(11)		/* 12:11 Rx FIFO fill level */
 #define  OMR_EFC	(1U<<8)		/* transmit PAUSE to throttle Rx lvl. */
 #define  OMR_FEF	(1U<<7)		/* allow to receive error frames */
 #define  OMR_SR		(1U<<1)		/* run Rx DMA engine, 0 to stop */
 #define GMACEVCS	0x1020		/* missed frame or ovf detected */
 #define GMACRWDT	0x1024		/* enable rx watchdog timer interrupt */
 #define GMACAXIB	0x1028		/* AXI bus mode control */
 #define GMACAXIS	0x102c		/* AXI status report */
 /* 0x1048 current tx desc address */
 /* 0x104c current rx desc address */
 /* 0x1050 current tx buffer address */
 @@ -393,27 +396,27 @@ struct rdes {
  * 0x00 - 07	48-bit MAC station address. 4 byte wise in BE order.
  * 0x08 - 0b	H->MAC xfer engine program start addr 63:32.
  * 0x0c - 0f	H2M program addr 31:0 (these are absolute addr, not offset)
  * 0x10 - 13	H2M program length in 4 byte count.
  * 0x14 - 0b	M->HOST xfer engine program start addr 63:32.
  * 0x18 - 0f	M2H program addr 31:0 (absolute addr, not relative)
  * 0x1c - 13	M2H program length in 4 byte count.
  * 0x20 - 23	packet engine program addr 31:0, (absolute addr, not offset)
  * 0x24 - 27	packet program length in 4 byte count.
+ *
  * above ucode are loaded via mapped reg 0x210, 0x21c and 0x0c0.
  */
-#define  _BMR		0x00412080	/* XXX TBD */
+#define  _BMR		0x00412080	/* NetSec BMR value, magic spell */
 /* NetSec uses local RAM to handle GMAC desc arrays */
 #define  _RDLA		0x18000
 #define  _TDLA		0x1c000
 /* lower address region is used for intermediate frame data buffers */
 /*
  * all below are software construction.
  */
 #define MD_NTXDESC		128
 #define MD_NRXDESC		64
 #define MD_NTXSEGS		16
 #define MD_TXQUEUELEN		8
 @@ -1123,53 +1126,53 @@ scx_init(struct ifnet *ifp)
 	struct scx_softc *sc = ifp->if_softc;
 	const uint8_t *ea = CLLADDR(ifp->if_sadl);
 	uint32_t csr;
 	int i, error;
 	/* Cancel pending I/O. */
 	scx_stop(ifp, 0);
 	/* Reset the chip to a known state. */
 	scx_reset(sc);
 	/* build sane Tx */
 	memset(sc->sc_txdescs, 0, sizeof(struct tdes) * MD_NTXDESC);
-	sc->sc_txdescs[MD_NTXDESC - 1].t0 = T0_LD; /* tie off the ring */
+	sc->sc_txdescs[MD_NTXDESC - 1].t0 = htole32(T0_LD); /* tie off */
 	SCX_CDTXSYNC(sc, 0, MD_NTXDESC,
 		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 	sc->sc_txfree = MD_NTXDESC;
 	sc->sc_txnext = 0;
 	for (i = 0; i < MD_TXQUEUELEN; i++)
 		sc->sc_txsoft[i].txs_mbuf = NULL;
 	sc->sc_txsfree = MD_TXQUEUELEN;
 	sc->sc_txsnext = 0;
 	sc->sc_txsdirty = 0;
 	/* load Rx descriptors with fresh mbuf */
 	for (i = 0; i < MD_NRXDESC; i++) {
 		if (sc->sc_rxsoft[i].rxs_mbuf == NULL) {
 			if ((error = add_rxbuf(sc, i)) != 0) {
 				aprint_error_dev(sc->sc_dev,
 				    "unable to allocate or map rx "
 				    "buffer %d, error = %d\n",
 				    i, error);
 				rxdrain(sc);
 				goto out;
+			}
+		}
 		else
 			SCX_INIT_RXDESC(sc, i);
+	}
-	sc->sc_rxdescs[MD_NRXDESC - 1].r0 = R0_LD; /* tie off the ring */
+	sc->sc_rxdescs[MD_NRXDESC - 1].r0 = htole32(R0_LD); /* tie off */
 	sc->sc_rxptr = 0;
 	/* set my address in perfect match slot 0. little endian order */
 	csr = (ea[3] << 24) | (ea[2] << 16) | (ea[1] << 8) |  ea[0];
 	mac_write(sc, GMACMAL0, csr);
 	csr = (ea[5] << 8) | ea[4];
 	mac_write(sc, GMACMAH0, csr);
 	/* accept multicast frame or run promisc mode */
 	scx_set_rcvfilt(sc);
 	/* set current media */
 	if ((error = ether_mediachange(ifp)) != 0)
 @@ -1182,28 +1185,28 @@ scx_init(struct ifnet *ifp)
 	WAIT_FOR_CLR(sc, DESC_INIT, 01);
 	/* feed local memory descriptor array base addresses */
 	mac_write(sc, GMACRDLA, _RDLA);		/* GMAC rdes store */
 	mac_write(sc, GMACTDLA, _TDLA);		/* GMAC tdes store */
 	CSR_WRITE(sc, FLOWTHR, (48<<16) | 36);	/* pause|resume threshold */
 	mac_write(sc, GMACFCR, 256 << 16);	/* 31:16 pause value */
 	CSR_WRITE(sc, INTF_SEL, sc->sc_miigmii ? INTF_GMII : INTF_RGMII);
 	CSR_WRITE(sc, RXCOALESC, 8);		/* Rx coalesce bound */
 	CSR_WRITE(sc, TXCOALESC, 8);		/* Tx coalesce bound */
-	CSR_WRITE(sc, RCLSCTIME, 500|(1U<<31));	/* Rx co. guard time usec */
+	CSR_WRITE(sc, RCLSCTIME, 500);		/* Rx co. guard time usec */
-	CSR_WRITE(sc, TCLSCTIME, 500|(1U<<31));	/* Tx co. guard time usec */
+	CSR_WRITE(sc, TCLSCTIME, 500);		/* Tx co. guard time usec */
 	CSR_WRITE(sc, RXIE_SET, RXI_RC_ERR | RXI_PKTCNT | RXI_TMREXP);
 	CSR_WRITE(sc, TXIE_SET, TXI_TR_ERR | TXI_TXDONE | TXI_TMREXP);
 	CSR_WRITE(sc, xINTAE_SET, IRQ_RX | IRQ_TX);
 #if 1
 	/* clear event counters, auto-zero after every read */
 	mac_write(sc, GMACEVCTL, EVC_CR | EVC_ROR);
 #endif
 	/* kick to start GMAC engine */
 	csr = mac_read(sc, GMACOMR);
 	mac_write(sc, GMACOMR, csr | OMR_SR | OMR_ST);
 	ifp->if_flags |= IFF_RUNNING;
 @@ -1530,36 +1533,36 @@ scx_intr(void *arg)
 	status = CSR_READ(sc, xINTSR); /* not W1C */
 	enable = CSR_READ(sc, xINTAEN);
 	if ((status & enable) == 0)
 		return 0;
 	if (status & (IRQ_TX | IRQ_RX)) {
 		CSR_WRITE(sc, xINTAE_CLR, (IRQ_TX | IRQ_RX));
 		status = CSR_READ(sc, RXISR);
 		CSR_WRITE(sc, RXISR, status);
 		if (status & RXI_RC_ERR)
 			aprint_error_dev(sc->sc_dev, "Rx error\n");
 		if (status & (RXI_PKTCNT | RXI_TMREXP)) {
 			rxfill(sc);
-			(void)CSR_READ(sc, RXAVAILCNT); /* clear RXI_PKTCNT */
+			(void)CSR_READ(sc, RXAVAILCNT); /* clear IRQ_RX ? */
+		}
 		status = CSR_READ(sc, TXISR);
 		CSR_WRITE(sc, TXISR, status);
 		if (status & TXI_TR_ERR)
 			aprint_error_dev(sc->sc_dev, "Tx error\n");
 		if (status & (TXI_TXDONE | TXI_TMREXP)) {
 			txreap(sc);
-			(void)CSR_READ(sc, TXDONECNT); /* clear TXI_TXDONE */
+			(void)CSR_READ(sc, TXDONECNT); /* clear IRQ_TX ? */
+		}
 		CSR_WRITE(sc, xINTAE_SET, (IRQ_TX | IRQ_RX));
+	}
 	return 1;
+}
 static void
 txreap(struct scx_softc *sc)
+{
 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
 	struct scx_txsoft *txs;
 	uint32_t txstat;