 @@ -1,14 +1,14 @@
-/*	$NetBSD: specialreg.h,v 1.198.2.1 2023/01/23 12:52:17 martin Exp $	*/
+/*	$NetBSD: specialreg.h,v 1.198.2.2 2023/06/21 19:02:18 martin Exp $	*/
 /*
  * Copyright (c) 2014-2020 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -858,49 +858,50 @@
 /*
  * AMD Processor Capacity Parameters and Extended Features.
  * CPUID Fn8000_0008
  * %eax: Long Mode Size Identifiers
  * %ebx: Extended Feature Identifiers
  * %ecx: Size Identifiers
  * %edx: RDPRU Register Identifier Range
  */
 /* %ebx */
 #define CPUID_CAPEX_CLZERO	   __BIT(0)  /* CLZERO instruction */
 #define CPUID_CAPEX_IRPERF	   __BIT(1)  /* InstRetCntMsr */
 #define CPUID_CAPEX_XSAVEERPTR	   __BIT(2)  /* RstrFpErrPtrs by XRSTOR */
 #define CPUID_CAPEX_INVLPGB	   __BIT(3)  /* INVLPGB instruction */
 #define CPUID_CAPEX_RDPRU	   __BIT(4)  /* RDPRU instruction */
 #define CPUID_CAPEX_MBE		   __BIT(6)  /* Memory Bandwidth Enforcement */
 #define CPUID_CAPEX_MCOMMIT	   __BIT(8)  /* MCOMMIT instruction */
 #define CPUID_CAPEX_WBNOINVD	   __BIT(9)  /* WBNOINVD instruction */
 #define CPUID_CAPEX_IBPB	   __BIT(12) /* Speculation Control IBPB */
 #define CPUID_CAPEX_INT_WBINVD	   __BIT(13) /* Interruptable WB[NO]INVD */
 #define CPUID_CAPEX_IBRS	   __BIT(14) /* Speculation Control IBRS */
 #define CPUID_CAPEX_STIBP	   __BIT(15) /* Speculation Control STIBP */
 #define CPUID_CAPEX_IBRS_ALWAYSON  __BIT(16) /* IBRS always on mode */
 #define CPUID_CAPEX_STIBP_ALWAYSON __BIT(17) /* STIBP always on mode */
 #define CPUID_CAPEX_PREFER_IBRS	   __BIT(18) /* IBRS preferred */
 #define CPUID_CAPEX_IBRS_SAMEMODE  __BIT(19) /* IBRS same speculation limits */
 #define CPUID_CAPEX_EFER_LSMSLE_UN __BIT(20) /* EFER.LMSLE is unsupported */
 #define CPUID_CAPEX_AMD_PPIN	   __BIT(23) /* Protected Processor Inventory Number */
 #define CPUID_CAPEX_SSBD	   __BIT(24) /* Speculation Control SSBD */
 #define CPUID_CAPEX_VIRT_SSBD	   __BIT(25) /* Virt Spec Control SSBD */
 #define CPUID_CAPEX_SSB_NO	   __BIT(26) /* SSBD not required */
 #define CPUID_CAPEX_CPPC	   __BIT(27) /* Collaborative Processor Perf. Control */
 #define CPUID_CAPEX_PSFD	   __BIT(28) /* Predictive Store Forward Dis */
 #define CPUID_CAPEX_BTC_NO	   __BIT(29) /* Branch Type Confusion NO */
 #define CPUID_CAPEX_FLAGS	"\20"					   \
-	"\1CLZERO"	"\2IRPERF"	"\3XSAVEERPTR"			   \
+	"\1CLZERO"	"\2IRPERF"	"\3XSAVEERPTR"	"\4INVLPGB"	   \
 	"\5RDPRU"			"\7MBE"				   \
 	"\11MCOMMIT"	"\12WBNOINVD"	"\13B10"			   \
 	"\15IBPB"	"\16INT_WBINVD"	"\17IBRS"	"\20STIBP"	   \
 	"\21IBRS_ALWAYSON" "\22STIBP_ALWAYSON" "\23PREFER_IBRS"		   \
 							"\24IBRS_SAMEMODE" \
 	"\25EFER_LSMSLE_UN"				"\30PPIN"	   \
 	"\31SSBD"	"\32VIRT_SSBD"	"\33SSB_NO"	"\34CPPC"	   \
 	"\35PSFD"	"\36BTC_NO"
 /* %ecx */
 #define CPUID_CAPEX_PerfTscSize	__BITS(17,16)	/* Perf. tstamp counter size */
 #define CPUID_CAPEX_ApicIdSize	__BITS(15,12)	/* APIC ID Size */
 #define CPUID_CAPEX_NC		__BITS(7,0)	/* Number of threads - 1 */
 @@ -926,38 +927,41 @@
 #define CPUID_AMD_SVM_PFThreshold     __BIT(12) /* PAUSE filter threshold */
 #define CPUID_AMD_SVM_AVIC	      __BIT(13) /* Advanced Virt. Intr. Ctrl */
 #define CPUID_AMD_SVM_V_VMSAVE_VMLOAD __BIT(15) /* Virtual VM{SAVE/LOAD} */
 #define CPUID_AMD_SVM_vGIF	      __BIT(16) /* Virtualized GIF */
 #define CPUID_AMD_SVM_GMET	      __BIT(17) /* Guest Mode Execution Trap */
 #define CPUID_AMD_SVM_X2AVIC	      __BIT(18) /* Virt. Intr. Ctrl 4 x2APIC */
 #define CPUID_AMD_SVM_SSSCHECK	      __BIT(19)  /* Shadow Stack restrictions */
 #define CPUID_AMD_SVM_SPEC_CTRL	      __BIT(20) /* SPEC_CTRL virtualization */
 #define CPUID_AMD_SVM_ROGPT	      __BIT(21) /* Read-Only Guest PTable */
 #define CPUID_AMD_SVM_HOST_MCE_OVERRIDE __BIT(23) /* #MC intercept */
 #define CPUID_AMD_SVM_TLBICTL	      __BIT(24) /* TLB Intercept Control */
 #define CPUID_AMD_SVM_VNMI	      __BIT(25) /* NMI Virtualization */
 #define CPUID_AMD_SVM_IBSVIRT	      __BIT(26) /* IBS Virtualization */
 #define CPUID_AMD_SVM_XLVTOFFFLTCHG   __BIT(27) /* Ext LVToffset FLT changed */
 #define CPUID_AMD_SVM_VMCBADRCHKCHG   __BIT(28) /* VMCB addr check changed */
 #define CPUID_AMD_SVM_FLAGS	 "\20"					\
 	"\1" "NP"	"\2" "LbrVirt"	"\3" "SVML"	"\4" "NRIPS"	\
 	"\5" "TSCRate"	"\6" "VMCBCleanBits" 				\
 			        "\7" "FlushByASID" "\10" "DecodeAssist"	\
 	"\11" "B08"	"\12" "B09"	"\13" "PauseFilter" "\14" "B11"	\
 	"\15" "PFThreshold" "\16" "AVIC" "\17" "B14"			\
 						"\20" "V_VMSAVE_VMLOAD"	\
 	"\21" "VGIF"	"\22" "GMET"	"\23x2AVIC"	"\24SSSCHECK"	\
 	"\25" "SPEC_CTRL" "\26" "ROGPT"		"\30HOST_MCE_OVERRIDE"	\
-	"\31" "TLBICTL"	"\32VNMI"	"\33IBSVIRT"	"\34B27"	\
+	"\31" "TLBICTL"	"\32VNMI" "\33IBSVIRT" "\34ExtLvtOffsetFaultChg" \
-	"\35B28"
+	"\35VmcbAddrChkChg"
 /*
  * AMD Instruction-Based Sampling Capabilities.
  * CPUID Fn8000_001b
  */
 /* %eax */
 #define CPUID_IBS_FFV		__BIT(0)  /* Feature Flags Valid */
 #define CPUID_IBS_FETCHSUM	__BIT(1)  /* Fetch Sampling */
 #define CPUID_IBS_OPSAM		__BIT(2)  /* execution SAMpling */
 #define CPUID_IBS_RDWROPCNT	__BIT(3)  /* Read Write of Op Counter */
 #define CPUID_IBS_OPCNT		__BIT(4)  /* OP CouNTing mode */
 #define CPUID_IBS_BRNTRGT	__BIT(5)  /* Branch Target */
 #define CPUID_IBS_OPCNTEXT	__BIT(6)  /* OpCurCnt and OpMaxCnt extended */
 @@ -1040,59 +1044,65 @@
 	"\11SecureTSC"	"\12TscAuxVirt"	"\13HwEnfCacheCoh"  "\14" "64BitHost" \
 	"\15" "RSTRINJ"	"\16" "ALTINJ"	"\17" "DebugSwap" "\20PreventHostIbs" \
 	"\21VTE"      "\22VmgexitParam" "\23VirtualTomMsr" "\24IbsVirtGuest"  \
 	"\31VmsaRegProt" "\32SmtProtection"				      \
 	"\35SvsmCommPageMSR" "\36NestedVirtSnpMsr"
 /*
  * AMD Extended Features 2.
  * CPUID Fn8000_0021
  */
 /* %eax */
 #define CPUID_AMDEXT2_NONESTEDDBP __BIT(0) /* No nested data breakpoints */
 #define CPUID_AMDEXT2_FGKBNOSERIAL __BIT(1) /* {FS,GS,K}BASE WRMSR !serializ */
 #define CPUID_AMDEXT2_LFENCESERIAL __BIT(2) /* LFENCE always serializing */
 #define CPUID_AMDEXT2_SMMPGCFGLCK __BIT(3) /* SMM Paging configuration lock */
 #define CPUID_AMDEXT2_NULLSELCLRB __BIT(6) /* Null segment selector clr base */
 #define CPUID_AMDEXT2_UPADDRIGN	  __BIT(7) /* Upper Address Ignore */
 #define CPUID_AMDEXT2_AUTOIBRS	  __BIT(8) /* Automatic IBRS */
 #define CPUID_AMDEXT2_NOSMMCTL	  __BIT(9) /* SMM_CTL MSR is not supported */
 #define CPUID_AMDEXT2_FSRS	  __BIT(10) /* Fast Short Rep Stosb */
 #define CPUID_AMDEXT2_FSRC	  __BIT(11) /* Fast Short Rep Cmpsb */
 #define CPUID_AMDEXT2_PREFETCHCTL __BIT(13) /* Prefetch control MSR */
 #define CPUID_AMDEXT2_CPUIDUSRDIS __BIT(17) /* CPUID dis. for non-priv. soft */
 #define CPUID_AMDEXT2_EPSF	  __BIT(18) /* Enhanced Predective Store Fwd */
 #define CPUID_AMDEXT2_FLAGS	 "\20"					      \
-	"\1NoNestedDataBp"	"\3LfenceAlwaysSerialize" "\4SmmPgCfgLock"    \
+	"\1NoNestedDataBp" "\2FsGsKernelGsBaseNonSerializing"		      \
 				"\3LfenceAlwaysSerialize" "\4SmmPgCfgLock"    \
 			     "\7NullSelectClearsBase" "\10UpperAddressIgnore" \
-	"\11AutomaticIBRS" "\12NoSmmCtlMSR"				      \
+	"\11AutomaticIBRS" "\12NoSmmCtlMSR"	"\13FSRS"	"\14FSRC"     \
 			"\16PrefetchCtlMSR"				      \
-			"\22CpuidUserDis"
+			"\22CpuidUserDis"	"\23EPSF"
 /*
  * AMD Extended Performance Monitoring and Debug
  * CPUID Fn8000_0022
  */
 /* %eax */
 #define CPUID_AXPERF_PERFMONV2	__BIT(0)  /* Version 2 */
 #define CPUID_AXPERF_LBRSTACK	__BIT(1)  /* Last Branch Record Stack */
 #define CPUID_AXPERF_LBRPMCFREEZE __BIT(2) /* Freezing LBR and PMC */
 #define CPUID_AXPERF_FLAGS	 "\20"					      \
 	"\1PerfMonV2"	"\2LbrStack"	"\3LbrAndPmcFreeze"
 /* %ebx */
 #define CPUID_AXPERF_NCPC      __BITS(3, 0)	/* Num of Core PMC counters */
 #define CPUID_AXPERF_NLBRSTACK __BITS(9, 4)	/* Num of LBR Stack entries */
-#define CPUID_AXPERF_NNBPC     __BITS(15, 10)	/* Num of Northbridge PMC */
+#define CPUID_AXPERF_NNBPC     __BITS(15, 10)	/* Num of NorthBridge PMCs */
 #define CPUID_AXPERF_NUMCPC    __BITS(21, 16)	/* Num of UMC PMCs */
 /*
  * Centaur Extended Feature flags.
  * CPUID FnC000_0001
  */
 #define CPUID_VIA_HAS_RNG	__BIT(2)	/* Random number generator */
 #define CPUID_VIA_DO_RNG	__BIT(3)
 #define CPUID_VIA_HAS_ACE	__BIT(6)	/* AES Encryption */
 #define CPUID_VIA_DO_ACE	__BIT(7)
 #define CPUID_VIA_HAS_ACE2	__BIT(8)	/* AES+CTR instructions */
 #define CPUID_VIA_DO_ACE2	__BIT(9)
 #define CPUID_VIA_HAS_PHE	__BIT(10)	/* SHA1+SHA256 HMAC */
 #define CPUID_VIA_DO_PHE	__BIT(11)

 @@ -1,14 +1,14 @@
-/*	$NetBSD: i386.c,v 1.133.2.1 2023/01/23 12:54:14 martin Exp $	*/
+/*	$NetBSD: i386.c,v 1.133.2.2 2023/06/21 19:02:18 martin Exp $	*/
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Frank van der Linden,  and by Jason R. Thorpe.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
 @@ -47,27 +47,27 @@
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
 #ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.133.2.1 2023/01/23 12:54:14 martin Exp $");
+__RCSID("$NetBSD: i386.c,v 1.133.2.2 2023/06/21 19:02:18 martin Exp $");
 #endif /* not lint */
 #include <sys/types.h>
 #include <sys/param.h>
 #include <sys/bitops.h>
 #include <sys/sysctl.h>
 #include <sys/ioctl.h>
 #include <sys/cpuio.h>
 #include <errno.h>
 #include <string.h>
 #include <stdio.h>
 #include <stdlib.h>
 @@ -2268,38 +2268,39 @@ identifycpu(int fd, const char *cpuname)
 			    CPUID_AMD_SVM_FLAGS, descs[3]);
+		}
 		if (ci->ci_max_ext_cpuid >= 0x8000001b) {
 			x86_cpuid(0x8000001b, descs);
 			print_bits(cpuname, "IBS features",
 			    CPUID_IBS_FLAGS, descs[0]);
+		}
 		if (ci->ci_max_ext_cpuid >= 0x8000001f) {
 			x86_cpuid(0x8000001f, descs);
 			print_bits(cpuname, "Encrypted Memory features",
 			    CPUID_AMD_ENCMEM_FLAGS, descs[0]);
+		}
 		if (ci->ci_max_ext_cpuid >= 0x80000022) {
-			uint8_t ncore, nnb, nlbrs;
+			uint8_t ncore, nnb, numc, nlbrs;
 			x86_cpuid(0x80000022, descs);
 			print_bits(cpuname, "Perfmon:",
 			    CPUID_AXPERF_FLAGS, descs[0]);
 			ncore = __SHIFTOUT(descs[1], CPUID_AXPERF_NCPC);
 			nnb = __SHIFTOUT(descs[1], CPUID_AXPERF_NNBPC);
 			numc = __SHIFTOUT(descs[1], CPUID_AXPERF_NUMCPC);
 			nlbrs = __SHIFTOUT(descs[1], CPUID_AXPERF_NLBRSTACK);
 			aprint_verbose("%s: Perfmon: counters: "
-			    "Core %hhu, Northbridge %hhu\n", cpuname,
+			    "Core %hhu, Northbridge %hhu, UMC %hhu\n", cpuname,
-			    ncore, nnb);
+			    ncore, nnb, numc);
 			aprint_verbose("%s: Perfmon: LBR Stack %hhu entries\n",
 			    cpuname, nlbrs);
+		}
 	} else if (cpu_vendor == CPUVENDOR_INTEL) {
 		if (ci->ci_max_cpuid >= 0x0a) {
 			unsigned int pmcver, ncounter, veclen;
 			x86_cpuid(0x0a, descs);
 			pmcver = __SHIFTOUT(descs[0], CPUID_PERF_VERSION);
 			ncounter = __SHIFTOUT(descs[0], CPUID_PERF_NGPPC);
 			veclen = __SHIFTOUT(descs[0], CPUID_PERF_BVECLEN);
 			aprint_verbose("%s: Perfmon: Ver. %u",
 			    cpuname, pmcver);