Fri Jul 28 06:21:02 2023 UTC ()
arm/bus_dma: Fix misleading comment:

- * For a virtually-indexed write-back cache, we need
- * to do the following things:
+ * For a write-back cache, we need to do the following things:

This comment was written long ago when we supported only virtually-
indexed caches for arm. But subsequent comments are valid also for
physically-indexed cache.


(rin)
diff -r1.143 -r1.144 src/sys/arch/arm/arm32/bus_dma.c
cvs diff -r1.143 -r1.144 src/sys/arch/arm/arm32/bus_dma.c (expand / switch to unified diff)

--- src/sys/arch/arm/arm32/bus_dma.c 2023/04/03 06:42:57 1.143
+++ src/sys/arch/arm/arm32/bus_dma.c 2023/07/28 06:21:02 1.144
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: bus_dma.c,v 1.143 2023/04/03 06:42:57 skrll Exp $ */ 1/* $NetBSD: bus_dma.c,v 1.144 2023/07/28 06:21:02 rin Exp $ */
2 2
3/*- 3/*-
4 * Copyright (c) 1996, 1997, 1998, 2020 The NetBSD Foundation, Inc. 4 * Copyright (c) 1996, 1997, 1998, 2020 The NetBSD Foundation, Inc.
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * This code is derived from software contributed to The NetBSD Foundation 7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
9 * NASA Ames Research Center. 9 * NASA Ames Research Center.
10 * 10 *
11 * Redistribution and use in source and binary forms, with or without 11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions 12 * modification, are permitted provided that the following conditions
13 * are met: 13 * are met:
14 * 1. Redistributions of source code must retain the above copyright 14 * 1. Redistributions of source code must retain the above copyright
@@ -26,27 +26,27 @@ @@ -26,27 +26,27 @@
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 * POSSIBILITY OF SUCH DAMAGE. 30 * POSSIBILITY OF SUCH DAMAGE.
31 */ 31 */
32 32
33#define _ARM32_BUS_DMA_PRIVATE 33#define _ARM32_BUS_DMA_PRIVATE
34 34
35#include "opt_arm_bus_space.h" 35#include "opt_arm_bus_space.h"
36#include "opt_cputypes.h" 36#include "opt_cputypes.h"
37 37
38#include <sys/cdefs.h> 38#include <sys/cdefs.h>
39__KERNEL_RCSID(0, "$NetBSD: bus_dma.c,v 1.143 2023/04/03 06:42:57 skrll Exp $"); 39__KERNEL_RCSID(0, "$NetBSD: bus_dma.c,v 1.144 2023/07/28 06:21:02 rin Exp $");
40 40
41#include <sys/param.h> 41#include <sys/param.h>
42 42
43#include <sys/bus.h> 43#include <sys/bus.h>
44#include <sys/cpu.h> 44#include <sys/cpu.h>
45#include <sys/kmem.h> 45#include <sys/kmem.h>
46#include <sys/mbuf.h> 46#include <sys/mbuf.h>
47 47
48#include <uvm/uvm.h> 48#include <uvm/uvm.h>
49 49
50#include <arm/cpuconf.h> 50#include <arm/cpuconf.h>
51#include <arm/cpufunc.h> 51#include <arm/cpufunc.h>
52 52
@@ -1104,28 +1104,27 @@ _bus_dmamap_sync(bus_dma_tag_t t, bus_dm @@ -1104,28 +1104,27 @@ _bus_dmamap_sync(bus_dma_tag_t t, bus_dm
1104 */ 1104 */
1105 if ((ops & (BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE)) != 0 && 1105 if ((ops & (BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE)) != 0 &&
1106 (ops & (BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE)) != 0) 1106 (ops & (BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE)) != 0)
1107 panic("%s: mix PRE and POST", __func__); 1107 panic("%s: mix PRE and POST", __func__);
1108 1108
1109 KASSERTMSG(offset < map->dm_mapsize, 1109 KASSERTMSG(offset < map->dm_mapsize,
1110 "offset %" PRIxBUSADDR " mapsize %" PRIuBUSSIZE, 1110 "offset %" PRIxBUSADDR " mapsize %" PRIuBUSSIZE,
1111 offset, map->dm_mapsize); 1111 offset, map->dm_mapsize);
1112 KASSERTMSG(len > 0 && offset + len <= map->dm_mapsize, 1112 KASSERTMSG(len > 0 && offset + len <= map->dm_mapsize,
1113 "len %" PRIuBUSSIZE " offset %" PRIxBUSADDR " mapsize %" PRIuBUSSIZE, 1113 "len %" PRIuBUSSIZE " offset %" PRIxBUSADDR " mapsize %" PRIuBUSSIZE,
1114 len, offset, map->dm_mapsize); 1114 len, offset, map->dm_mapsize);
1115 1115
1116 /* 1116 /*
1117 * For a virtually-indexed write-back cache, we need 1117 * For a write-back cache, we need to do the following things:
1118 * to do the following things: 
1119 * 1118 *
1120 * PREREAD -- Invalidate the D-cache. We do this 1119 * PREREAD -- Invalidate the D-cache. We do this
1121 * here in case a write-back is required by the back-end. 1120 * here in case a write-back is required by the back-end.
1122 * 1121 *
1123 * PREWRITE -- Write-back the D-cache. Note that if 1122 * PREWRITE -- Write-back the D-cache. Note that if
1124 * we are doing a PREREAD | PREWRITE, we can collapse 1123 * we are doing a PREREAD | PREWRITE, we can collapse
1125 * the whole thing into a single Wb-Inv. 1124 * the whole thing into a single Wb-Inv.
1126 * 1125 *
1127 * POSTREAD -- Re-invalidate the D-cache in case speculative 1126 * POSTREAD -- Re-invalidate the D-cache in case speculative
1128 * memory accesses caused cachelines to become valid with now 1127 * memory accesses caused cachelines to become valid with now
1129 * invalid data. 1128 * invalid data.
1130 * 1129 *
1131 * POSTWRITE -- Nothing. 1130 * POSTWRITE -- Nothing.