Sat Jul 29 09:48:51 2023 UTC ()
Pull up the following revisions, all via patch, requested by msaitoh
in ticket #1669:

	sys/arch/x86/include/specialreg.h               1.204-1.206, 1.208

- Add Intel CPUID 0x07 %ecx bit 24 BUS_LOCK_DETECT.
- Add AMD CPUID 0x80000008 %ebx bit 30 IBPB_RET and CPUID 0x8000000a
  %edx bit 29 BusLockThreshold.
- Fix typo in comment.


(martin)
diff -r1.150.2.14 -r1.150.2.15 src/sys/arch/x86/include/specialreg.h
cvs diff -r1.150.2.14 -r1.150.2.15 src/sys/arch/x86/include/specialreg.h (expand / switch to unified diff)

--- src/sys/arch/x86/include/specialreg.h 2023/07/25 09:12:35 1.150.2.14
+++ src/sys/arch/x86/include/specialreg.h 2023/07/29 09:48:51 1.150.2.15
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: specialreg.h,v 1.150.2.14 2023/07/25 09:12:35 martin Exp $ */ 1/* $NetBSD: specialreg.h,v 1.150.2.15 2023/07/29 09:48:51 martin Exp $ */
2 2
3/* 3/*
4 * Copyright (c) 2014-2020 The NetBSD Foundation, Inc. 4 * Copyright (c) 2014-2020 The NetBSD Foundation, Inc.
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * Redistribution and use in source and binary forms, with or without 7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions 8 * modification, are permitted provided that the following conditions
9 * are met: 9 * are met:
10 * 1. Redistributions of source code must retain the above copyright 10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer. 11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright 12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the 13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution. 14 * documentation and/or other materials provided with the distribution.
@@ -456,41 +456,42 @@ @@ -456,41 +456,42 @@
456#define CPUID_SEF_AVX512_VBMI2 __BIT(6) /* AVX-512 Vector Byte Manipulation 2 */ 456#define CPUID_SEF_AVX512_VBMI2 __BIT(6) /* AVX-512 Vector Byte Manipulation 2 */
457#define CPUID_SEF_CET_SS __BIT(7) /* CET Shadow Stack */ 457#define CPUID_SEF_CET_SS __BIT(7) /* CET Shadow Stack */
458#define CPUID_SEF_GFNI __BIT(8) /* Galois Field instructions */ 458#define CPUID_SEF_GFNI __BIT(8) /* Galois Field instructions */
459#define CPUID_SEF_VAES __BIT(9) /* Vector AES instruction set */ 459#define CPUID_SEF_VAES __BIT(9) /* Vector AES instruction set */
460#define CPUID_SEF_VPCLMULQDQ __BIT(10) /* CLMUL instruction set */ 460#define CPUID_SEF_VPCLMULQDQ __BIT(10) /* CLMUL instruction set */
461#define CPUID_SEF_AVX512_VNNI __BIT(11) /* Vector Neural Network Instruction */ 461#define CPUID_SEF_AVX512_VNNI __BIT(11) /* Vector Neural Network Instruction */
462#define CPUID_SEF_AVX512_BITALG __BIT(12) /* BITALG instructions */ 462#define CPUID_SEF_AVX512_BITALG __BIT(12) /* BITALG instructions */
463#define CPUID_SEF_TME_EN __BIT(13) /* Total Memory Encryption */ 463#define CPUID_SEF_TME_EN __BIT(13) /* Total Memory Encryption */
464#define CPUID_SEF_AVX512_VPOPCNTDQ __BIT(14) /* Vector Population Count D/Q */ 464#define CPUID_SEF_AVX512_VPOPCNTDQ __BIT(14) /* Vector Population Count D/Q */
465#define CPUID_SEF_LA57 __BIT(16) /* 57bit linear addr & 5LVL paging */ 465#define CPUID_SEF_LA57 __BIT(16) /* 57bit linear addr & 5LVL paging */
466#define CPUID_SEF_MAWAU __BITS(21, 17) /* MAWAU for BND{LD,ST}X */ 466#define CPUID_SEF_MAWAU __BITS(21, 17) /* MAWAU for BND{LD,ST}X */
467#define CPUID_SEF_RDPID __BIT(22) /* RDPID and IA32_TSC_AUX */ 467#define CPUID_SEF_RDPID __BIT(22) /* RDPID and IA32_TSC_AUX */
468#define CPUID_SEF_KL __BIT(23) /* Key Locker */ 468#define CPUID_SEF_KL __BIT(23) /* Key Locker */
 469#define CPUID_SEF_BUS_LOCK_DETECT __BIT(24) /* OS bus-lock detection */
469#define CPUID_SEF_CLDEMOTE __BIT(25) /* Cache line demote */ 470#define CPUID_SEF_CLDEMOTE __BIT(25) /* Cache line demote */
470#define CPUID_SEF_MOVDIRI __BIT(27) /* MOVDIRI instruction */ 471#define CPUID_SEF_MOVDIRI __BIT(27) /* MOVDIRI instruction */
471#define CPUID_SEF_MOVDIR64B __BIT(28) /* MOVDIR64B instruction */ 472#define CPUID_SEF_MOVDIR64B __BIT(28) /* MOVDIR64B instruction */
472#define CPUID_SEF_ENQCMD __BIT(29) /* Enqueue Stores */ 473#define CPUID_SEF_ENQCMD __BIT(29) /* Enqueue Stores */
473#define CPUID_SEF_SGXLC __BIT(30) /* SGX Launch Configuration */ 474#define CPUID_SEF_SGXLC __BIT(30) /* SGX Launch Configuration */
474#define CPUID_SEF_PKS __BIT(31) /* Protection Keys for kern-mode pages */ 475#define CPUID_SEF_PKS __BIT(31) /* Protection Keys for kern-mode pages */
475 476
476#define CPUID_SEF_FLAGS1 "\177\20" \ 477#define CPUID_SEF_FLAGS1 "\177\20" \
477 "b\0PREFETCHWT1\0" "b\1AVX512_VBMI\0" "b\2UMIP\0" "b\3PKU\0" \ 478 "b\0PREFETCHWT1\0" "b\1AVX512_VBMI\0" "b\2UMIP\0" "b\3PKU\0" \
478 "b\4OSPKE\0" "b\5WAITPKG\0" "b\6AVX512_VBMI2\0" "b\7CET_SS\0" \ 479 "b\4OSPKE\0" "b\5WAITPKG\0" "b\6AVX512_VBMI2\0" "b\7CET_SS\0" \
479 "b\10GFNI\0" "b\11VAES\0" "b\12VPCLMULQDQ\0" "b\13AVX512_VNNI\0"\ 480 "b\10GFNI\0" "b\11VAES\0" "b\12VPCLMULQDQ\0" "b\13AVX512_VNNI\0"\
480 "b\14AVX512_BITALG\0" "b\15TME_EN\0" "b\16AVX512_VPOPCNTDQ\0" \ 481 "b\14AVX512_BITALG\0" "b\15TME_EN\0" "b\16AVX512_VPOPCNTDQ\0" \
481 "b\20LA57\0" \ 482 "b\20LA57\0" \
482 "f\21\5MAWAU\0" "b\26RDPID\0" "b\27KL\0" \ 483 "f\21\5MAWAU\0" "b\26RDPID\0" "b\27KL\0" \
483 "b\31CLDEMOTE\0" "b\33MOVDIRI\0" \ 484 "b\30BUS_LOCK_DETECT" "b\31CLDEMOTE\0" "b\33MOVDIRI\0" \
484 "b\34MOVDIR64B\0" "b\35ENQCMD\0" "b\36SGXLC\0" "b\37PKS\0" 485 "b\34MOVDIR64B\0" "b\35ENQCMD\0" "b\36SGXLC\0" "b\37PKS\0"
485 486
486/* %ecx = 0, %edx */ 487/* %ecx = 0, %edx */
487#define CPUID_SEF_SGX_KEYS __BIT(1) /* Attestation support for SGX */ 488#define CPUID_SEF_SGX_KEYS __BIT(1) /* Attestation support for SGX */
488#define CPUID_SEF_AVX512_4VNNIW __BIT(2) /* AVX512 4-reg Neural Network ins */ 489#define CPUID_SEF_AVX512_4VNNIW __BIT(2) /* AVX512 4-reg Neural Network ins */
489#define CPUID_SEF_AVX512_4FMAPS __BIT(3) /* AVX512 4-reg Mult Accum Single precision */ 490#define CPUID_SEF_AVX512_4FMAPS __BIT(3) /* AVX512 4-reg Mult Accum Single precision */
490#define CPUID_SEF_FSRM __BIT(4) /* Fast Short Rep Move */ 491#define CPUID_SEF_FSRM __BIT(4) /* Fast Short Rep Move */
491#define CPUID_SEF_UINTR __BIT(5) /* User Interrupts */ 492#define CPUID_SEF_UINTR __BIT(5) /* User Interrupts */
492#define CPUID_SEF_AVX512_VP2INTERSECT __BIT(8) /* AVX512 VP2INTERSECT */ 493#define CPUID_SEF_AVX512_VP2INTERSECT __BIT(8) /* AVX512 VP2INTERSECT */
493#define CPUID_SEF_SRBDS_CTRL __BIT(9) /* IA32_MCU_OPT_CTRL */ 494#define CPUID_SEF_SRBDS_CTRL __BIT(9) /* IA32_MCU_OPT_CTRL */
494#define CPUID_SEF_MD_CLEAR __BIT(10) /* VERW clears CPU buffers */ 495#define CPUID_SEF_MD_CLEAR __BIT(10) /* VERW clears CPU buffers */
495#define CPUID_SEF_RTM_ALWAYS_ABORT __BIT(11) /* XBEGIN immediately abort */ 496#define CPUID_SEF_RTM_ALWAYS_ABORT __BIT(11) /* XBEGIN immediately abort */
496#define CPUID_SEF_RTM_FORCE_ABORT __BIT(13) /* MSR_TSX_FORCE_ABORT bit 0 */ 497#define CPUID_SEF_RTM_FORCE_ABORT __BIT(13) /* MSR_TSX_FORCE_ABORT bit 0 */
@@ -879,37 +880,38 @@ @@ -879,37 +880,38 @@
879#define CPUID_CAPEX_STIBP __BIT(15) /* Speculation Control STIBP */ 880#define CPUID_CAPEX_STIBP __BIT(15) /* Speculation Control STIBP */
880#define CPUID_CAPEX_IBRS_ALWAYSON __BIT(16) /* IBRS always on mode */ 881#define CPUID_CAPEX_IBRS_ALWAYSON __BIT(16) /* IBRS always on mode */
881#define CPUID_CAPEX_STIBP_ALWAYSON __BIT(17) /* STIBP always on mode */ 882#define CPUID_CAPEX_STIBP_ALWAYSON __BIT(17) /* STIBP always on mode */
882#define CPUID_CAPEX_PREFER_IBRS __BIT(18) /* IBRS preferred */ 883#define CPUID_CAPEX_PREFER_IBRS __BIT(18) /* IBRS preferred */
883#define CPUID_CAPEX_IBRS_SAMEMODE __BIT(19) /* IBRS same speculation limits */ 884#define CPUID_CAPEX_IBRS_SAMEMODE __BIT(19) /* IBRS same speculation limits */
884#define CPUID_CAPEX_EFER_LSMSLE_UN __BIT(20) /* EFER.LMSLE is unsupported */ 885#define CPUID_CAPEX_EFER_LSMSLE_UN __BIT(20) /* EFER.LMSLE is unsupported */
885#define CPUID_CAPEX_AMD_PPIN __BIT(23) /* Protected Processor Inventory Number */ 886#define CPUID_CAPEX_AMD_PPIN __BIT(23) /* Protected Processor Inventory Number */
886#define CPUID_CAPEX_SSBD __BIT(24) /* Speculation Control SSBD */ 887#define CPUID_CAPEX_SSBD __BIT(24) /* Speculation Control SSBD */
887#define CPUID_CAPEX_VIRT_SSBD __BIT(25) /* Virt Spec Control SSBD */ 888#define CPUID_CAPEX_VIRT_SSBD __BIT(25) /* Virt Spec Control SSBD */
888#define CPUID_CAPEX_SSB_NO __BIT(26) /* SSBD not required */ 889#define CPUID_CAPEX_SSB_NO __BIT(26) /* SSBD not required */
889#define CPUID_CAPEX_CPPC __BIT(27) /* Collaborative Processor Perf. Control */ 890#define CPUID_CAPEX_CPPC __BIT(27) /* Collaborative Processor Perf. Control */
890#define CPUID_CAPEX_PSFD __BIT(28) /* Predictive Store Forward Dis */ 891#define CPUID_CAPEX_PSFD __BIT(28) /* Predictive Store Forward Dis */
891#define CPUID_CAPEX_BTC_NO __BIT(29) /* Branch Type Confusion NO */ 892#define CPUID_CAPEX_BTC_NO __BIT(29) /* Branch Type Confusion NO */
 893#define CPUID_CAPEX_IBPB_RET __BIT(30) /* Clear RET address predictor */
892 894
893#define CPUID_CAPEX_FLAGS "\20" \ 895#define CPUID_CAPEX_FLAGS "\20" \
894 "\1CLZERO" "\2IRPERF" "\3XSAVEERPTR" "\4INVLPGB" \ 896 "\1CLZERO" "\2IRPERF" "\3XSAVEERPTR" "\4INVLPGB" \
895 "\5RDPRU" "\7MBE" \ 897 "\5RDPRU" "\7MBE" \
896 "\11MCOMMIT" "\12WBNOINVD" "\13B10" \ 898 "\11MCOMMIT" "\12WBNOINVD" "\13B10" \
897 "\15IBPB" "\16INT_WBINVD" "\17IBRS" "\20STIBP" \ 899 "\15IBPB" "\16INT_WBINVD" "\17IBRS" "\20STIBP" \
898 "\21IBRS_ALWAYSON" "\22STIBP_ALWAYSON" "\23PREFER_IBRS" \ 900 "\21IBRS_ALWAYSON" "\22STIBP_ALWAYSON" "\23PREFER_IBRS" \
899 "\24IBRS_SAMEMODE" \ 901 "\24IBRS_SAMEMODE" \
900 "\25EFER_LSMSLE_UN" "\30PPIN" \ 902 "\25EFER_LSMSLE_UN" "\30PPIN" \
901 "\31SSBD" "\32VIRT_SSBD" "\33SSB_NO" "\34CPPC" \ 903 "\31SSBD" "\32VIRT_SSBD" "\33SSB_NO" "\34CPPC" \
902 "\35PSFD" "\36BTC_NO" 904 "\35PSFD" "\36BTC_NO" "\37IBPB_RET"
903 905
904/* %ecx */ 906/* %ecx */
905#define CPUID_CAPEX_PerfTscSize __BITS(17,16) /* Perf. tstamp counter size */ 907#define CPUID_CAPEX_PerfTscSize __BITS(17,16) /* Perf. tstamp counter size */
906#define CPUID_CAPEX_ApicIdSize __BITS(15,12) /* APIC ID Size */ 908#define CPUID_CAPEX_ApicIdSize __BITS(15,12) /* APIC ID Size */
907#define CPUID_CAPEX_NC __BITS(7,0) /* Number of threads - 1 */ 909#define CPUID_CAPEX_NC __BITS(7,0) /* Number of threads - 1 */
908 910
909/* 911/*
910 * AMD SVM Revision and Feature. 912 * AMD SVM Revision and Feature.
911 * CPUID Fn8000_000a 913 * CPUID Fn8000_000a
912 */ 914 */
913 915
914/* %eax: SVM revision */ 916/* %eax: SVM revision */
915#define CPUID_AMD_SVM_REV __BITS(7,0) 917#define CPUID_AMD_SVM_REV __BITS(7,0)
@@ -929,39 +931,40 @@ @@ -929,39 +931,40 @@
929#define CPUID_AMD_SVM_V_VMSAVE_VMLOAD __BIT(15) /* Virtual VM{SAVE/LOAD} */ 931#define CPUID_AMD_SVM_V_VMSAVE_VMLOAD __BIT(15) /* Virtual VM{SAVE/LOAD} */
930#define CPUID_AMD_SVM_vGIF __BIT(16) /* Virtualized GIF */ 932#define CPUID_AMD_SVM_vGIF __BIT(16) /* Virtualized GIF */
931#define CPUID_AMD_SVM_GMET __BIT(17) /* Guest Mode Execution Trap */ 933#define CPUID_AMD_SVM_GMET __BIT(17) /* Guest Mode Execution Trap */
932#define CPUID_AMD_SVM_X2AVIC __BIT(18) /* Virt. Intr. Ctrl 4 x2APIC */ 934#define CPUID_AMD_SVM_X2AVIC __BIT(18) /* Virt. Intr. Ctrl 4 x2APIC */
933#define CPUID_AMD_SVM_SSSCHECK __BIT(19) /* Shadow Stack restrictions */ 935#define CPUID_AMD_SVM_SSSCHECK __BIT(19) /* Shadow Stack restrictions */
934#define CPUID_AMD_SVM_SPEC_CTRL __BIT(20) /* SPEC_CTRL virtualization */ 936#define CPUID_AMD_SVM_SPEC_CTRL __BIT(20) /* SPEC_CTRL virtualization */
935#define CPUID_AMD_SVM_ROGPT __BIT(21) /* Read-Only Guest PTable */ 937#define CPUID_AMD_SVM_ROGPT __BIT(21) /* Read-Only Guest PTable */
936#define CPUID_AMD_SVM_HOST_MCE_OVERRIDE __BIT(23) /* #MC intercept */ 938#define CPUID_AMD_SVM_HOST_MCE_OVERRIDE __BIT(23) /* #MC intercept */
937#define CPUID_AMD_SVM_TLBICTL __BIT(24) /* TLB Intercept Control */ 939#define CPUID_AMD_SVM_TLBICTL __BIT(24) /* TLB Intercept Control */
938#define CPUID_AMD_SVM_VNMI __BIT(25) /* NMI Virtualization */ 940#define CPUID_AMD_SVM_VNMI __BIT(25) /* NMI Virtualization */
939#define CPUID_AMD_SVM_IBSVIRT __BIT(26) /* IBS Virtualization */ 941#define CPUID_AMD_SVM_IBSVIRT __BIT(26) /* IBS Virtualization */
940#define CPUID_AMD_SVM_XLVTOFFFLTCHG __BIT(27) /* Ext LVToffset FLT changed */ 942#define CPUID_AMD_SVM_XLVTOFFFLTCHG __BIT(27) /* Ext LVToffset FLT changed */
941#define CPUID_AMD_SVM_VMCBADRCHKCHG __BIT(28) /* VMCB addr check changed */ 943#define CPUID_AMD_SVM_VMCBADRCHKCHG __BIT(28) /* VMCB addr check changed */
 944#define CPUID_AMD_SVM_BUSLOCKTHRESH __BIT(29) /* Bus Lock Threshold */
942 945
943 946
944#define CPUID_AMD_SVM_FLAGS "\20" \ 947#define CPUID_AMD_SVM_FLAGS "\20" \
945 "\1" "NP" "\2" "LbrVirt" "\3" "SVML" "\4" "NRIPS" \ 948 "\1" "NP" "\2" "LbrVirt" "\3" "SVML" "\4" "NRIPS" \
946 "\5" "TSCRate" "\6" "VMCBCleanBits" \ 949 "\5" "TSCRate" "\6" "VMCBCleanBits" \
947 "\7" "FlushByASID" "\10" "DecodeAssist" \ 950 "\7" "FlushByASID" "\10" "DecodeAssist" \
948 "\11" "B08" "\12" "B09" "\13" "PauseFilter" "\14" "B11" \ 951 "\11" "B08" "\12" "B09" "\13" "PauseFilter" "\14" "B11" \
949 "\15" "PFThreshold" "\16" "AVIC" "\17" "B14" \ 952 "\15" "PFThreshold" "\16" "AVIC" "\17" "B14" \
950 "\20" "V_VMSAVE_VMLOAD" \ 953 "\20" "V_VMSAVE_VMLOAD" \
951 "\21" "VGIF" "\22" "GMET" "\23x2AVIC" "\24SSSCHECK" \ 954 "\21" "VGIF" "\22" "GMET" "\23x2AVIC" "\24SSSCHECK" \
952 "\25" "SPEC_CTRL" "\26" "ROGPT" "\30HOST_MCE_OVERRIDE" \ 955 "\25" "SPEC_CTRL" "\26" "ROGPT" "\30HOST_MCE_OVERRIDE" \
953 "\31" "TLBICTL" "\32VNMI" "\33IBSVIRT" "\34ExtLvtOffsetFaultChg" \ 956 "\31" "TLBICTL" "\32VNMI" "\33IBSVIRT" "\34ExtLvtOffsetFaultChg" \
954 "\35VmcbAddrChkChg" 957 "\35VmcbAddrChkChg" "\36BusLockThreshold"
955 958
956/* 959/*
957 * AMD Instruction-Based Sampling Capabilities. 960 * AMD Instruction-Based Sampling Capabilities.
958 * CPUID Fn8000_001b 961 * CPUID Fn8000_001b
959 */ 962 */
960/* %eax */ 963/* %eax */
961#define CPUID_IBS_FFV __BIT(0) /* Feature Flags Valid */ 964#define CPUID_IBS_FFV __BIT(0) /* Feature Flags Valid */
962#define CPUID_IBS_FETCHSUM __BIT(1) /* Fetch Sampling */ 965#define CPUID_IBS_FETCHSUM __BIT(1) /* Fetch Sampling */
963#define CPUID_IBS_OPSAM __BIT(2) /* execution SAMpling */ 966#define CPUID_IBS_OPSAM __BIT(2) /* execution SAMpling */
964#define CPUID_IBS_RDWROPCNT __BIT(3) /* Read Write of Op Counter */ 967#define CPUID_IBS_RDWROPCNT __BIT(3) /* Read Write of Op Counter */
965#define CPUID_IBS_OPCNT __BIT(4) /* OP CouNTing mode */ 968#define CPUID_IBS_OPCNT __BIT(4) /* OP CouNTing mode */
966#define CPUID_IBS_BRNTRGT __BIT(5) /* Branch Target */ 969#define CPUID_IBS_BRNTRGT __BIT(5) /* Branch Target */
967#define CPUID_IBS_OPCNTEXT __BIT(6) /* OpCurCnt and OpMaxCnt extended */ 970#define CPUID_IBS_OPCNTEXT __BIT(6) /* OpCurCnt and OpMaxCnt extended */
@@ -1055,27 +1058,27 @@ @@ -1055,27 +1058,27 @@
1055/* %eax */ 1058/* %eax */
1056#define CPUID_AMDEXT2_NONESTEDDBP __BIT(0) /* No nested data breakpoints */ 1059#define CPUID_AMDEXT2_NONESTEDDBP __BIT(0) /* No nested data breakpoints */
1057#define CPUID_AMDEXT2_FGKBNOSERIAL __BIT(1) /* {FS,GS,K}BASE WRMSR !serializ */ 1060#define CPUID_AMDEXT2_FGKBNOSERIAL __BIT(1) /* {FS,GS,K}BASE WRMSR !serializ */
1058#define CPUID_AMDEXT2_LFENCESERIAL __BIT(2) /* LFENCE always serializing */ 1061#define CPUID_AMDEXT2_LFENCESERIAL __BIT(2) /* LFENCE always serializing */
1059#define CPUID_AMDEXT2_SMMPGCFGLCK __BIT(3) /* SMM Paging configuration lock */ 1062#define CPUID_AMDEXT2_SMMPGCFGLCK __BIT(3) /* SMM Paging configuration lock */
1060#define CPUID_AMDEXT2_NULLSELCLRB __BIT(6) /* Null segment selector clr base */ 1063#define CPUID_AMDEXT2_NULLSELCLRB __BIT(6) /* Null segment selector clr base */
1061#define CPUID_AMDEXT2_UPADDRIGN __BIT(7) /* Upper Address Ignore */ 1064#define CPUID_AMDEXT2_UPADDRIGN __BIT(7) /* Upper Address Ignore */
1062#define CPUID_AMDEXT2_AUTOIBRS __BIT(8) /* Automatic IBRS */ 1065#define CPUID_AMDEXT2_AUTOIBRS __BIT(8) /* Automatic IBRS */
1063#define CPUID_AMDEXT2_NOSMMCTL __BIT(9) /* SMM_CTL MSR is not supported */ 1066#define CPUID_AMDEXT2_NOSMMCTL __BIT(9) /* SMM_CTL MSR is not supported */
1064#define CPUID_AMDEXT2_FSRS __BIT(10) /* Fast Short Rep Stosb */ 1067#define CPUID_AMDEXT2_FSRS __BIT(10) /* Fast Short Rep Stosb */
1065#define CPUID_AMDEXT2_FSRC __BIT(11) /* Fast Short Rep Cmpsb */ 1068#define CPUID_AMDEXT2_FSRC __BIT(11) /* Fast Short Rep Cmpsb */
1066#define CPUID_AMDEXT2_PREFETCHCTL __BIT(13) /* Prefetch control MSR */ 1069#define CPUID_AMDEXT2_PREFETCHCTL __BIT(13) /* Prefetch control MSR */
1067#define CPUID_AMDEXT2_CPUIDUSRDIS __BIT(17) /* CPUID dis. for non-priv. soft */ 1070#define CPUID_AMDEXT2_CPUIDUSRDIS __BIT(17) /* CPUID dis. for non-priv. soft */
1068#define CPUID_AMDEXT2_EPSF __BIT(18) /* Enhanced Predective Store Fwd */ 1071#define CPUID_AMDEXT2_EPSF __BIT(18) /* Enhanced Predictive Store Fwd */
1069 1072
1070#define CPUID_AMDEXT2_FLAGS "\20" \ 1073#define CPUID_AMDEXT2_FLAGS "\20" \
1071 "\1NoNestedDataBp" "\2FsGsKernelGsBaseNonSerializing" \ 1074 "\1NoNestedDataBp" "\2FsGsKernelGsBaseNonSerializing" \
1072 "\3LfenceAlwaysSerialize" "\4SmmPgCfgLock" \ 1075 "\3LfenceAlwaysSerialize" "\4SmmPgCfgLock" \
1073 "\7NullSelectClearsBase" "\10UpperAddressIgnore" \ 1076 "\7NullSelectClearsBase" "\10UpperAddressIgnore" \
1074 "\11AutomaticIBRS" "\12NoSmmCtlMSR" "\13FSRS" "\14FSRC" \ 1077 "\11AutomaticIBRS" "\12NoSmmCtlMSR" "\13FSRS" "\14FSRC" \
1075 "\16PrefetchCtlMSR" \ 1078 "\16PrefetchCtlMSR" \
1076 "\22CpuidUserDis" "\23EPSF" 1079 "\22CpuidUserDis" "\23EPSF"
1077 1080
1078/* 1081/*
1079 * AMD Extended Performance Monitoring and Debug 1082 * AMD Extended Performance Monitoring and Debug
1080 * CPUID Fn8000_0022 1083 * CPUID Fn8000_0022
1081 */ 1084 */