 @@ -1,14 +1,14 @@
-/*	$NetBSD: octeon_rnm.c,v 1.2.4.2 2020/05/19 17:39:04 martin Exp $	*/
+/*	$NetBSD: octeon_rnm.c,v 1.2.4.3 2023/07/30 11:41:48 martin Exp $	*/
 /*
  * Copyright (c) 2007 Internet Initiative Japan, Inc.
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -89,46 +89,47 @@
  *	more than one sample from each RO could be squeezed in there.
+ *
  *	The hardware exposes only 64 bits of each SHA-1 hash, and the
  *	Linux driver uses 32 bits of that -- which, if treated as full
  *	entropy, would mean an assessment of 3.9 bits of RO samples to
  *	get 1 bit of entropy, whereas we take 256 bits of RO samples to
  *	get one bit of entropy, so this seems reasonably conservative.
+ *
  * Reference: Cavium Networks OCTEON Plus CN50XX Hardware Reference
  * Manual, CN50XX-HM-0.99E PRELIMINARY, July 2008.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: octeon_rnm.c,v 1.2.4.2 2020/05/19 17:39:04 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: octeon_rnm.c,v 1.2.4.3 2023/07/30 11:41:48 martin Exp $");
 #include <sys/param.h>
 #include <sys/device.h>
 #include <sys/kernel.h>
 #include <sys/rndsource.h>
 #include <sys/systm.h>
 #include <mips/locore.h>
 #include <mips/cavium/include/iobusvar.h>
 #include <mips/cavium/dev/octeon_rnmreg.h>
 #include <mips/cavium/dev/octeon_corereg.h>
 #include <mips/cavium/octeonvar.h>
 #include <sys/bus.h>
 //#define	OCTEON_RNM_DEBUG
 #define	ENT_DELAY_CLOCK 8	/* cycles for each 64-bit RO sample batch */
-#define	RNG_DELAY_CLOCK 81	/* cycles for each SHA-1 output */
+#define	LFSR_DELAY_CLOCK 81	/* cycles to fill LFSR buffer */
 #define	SHA1_DELAY_CLOCK 81	/* cycles to compute SHA-1 output */
 #define	NROGROUPS	16
 #define	RNG_FIFO_WORDS	(512/sizeof(uint64_t))
 struct octeon_rnm_softc {
 	bus_space_tag_t		sc_bust;
 	bus_space_handle_t	sc_regh;
 	kmutex_t		sc_lock;
 	krndsource_t		sc_rndsrc;	/* /dev/random source */
 	unsigned		sc_rogroup;
 };
 static int octeon_rnm_match(device_t, struct cfdata *, void *);
 static void octeon_rnm_attach(device_t, device_t, void *);
 @@ -185,27 +186,27 @@ octeon_rnm_attach(device_t parent, devic
 	/* Create a mutex to serialize access to the FIFO.  */
 	mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM);
 	/*
 	 * Reset the core, enable the RNG engine without entropy, wait
 	 * 81 cycles for it to produce a single sample, and draw the
 	 * deterministic sample to test.
+	 *
 	 * XXX Verify that the output matches the SHA-1 computation
 	 * described by the data sheet, not just a known answer.
 	 */
 	octeon_rnm_reset(sc);
 	octeon_rnm_conditioned_deterministic(sc);
-	octeon_rnm_delay(RNG_DELAY_CLOCK*1);
+	octeon_rnm_delay(LFSR_DELAY_CLOCK + SHA1_DELAY_CLOCK);
 	sample = octeon_rnm_load(sc);
 	if (sample != expected)
 		aprint_error_dev(self, "self-test: read %016"PRIx64","
 		    " expected %016"PRIx64, sample, expected);
 	/*
 	 * Reset the core again to clear the FIFO, and enable the RNG
 	 * engine with entropy exposed directly.  Start from the first
 	 * group of ring oscillators; as we gather samples we will
 	 * rotate through the rest of them.
 	 */
 	octeon_rnm_reset(sc);
 	sc->sc_rogroup = 0;