Sat Sep 2 09:58:15 2023 UTC ()
Be clear about hart vs cpu. NFCI.


(skrll)
diff -r1.1 -r1.2 src/sys/arch/riscv/dev/plic.c
diff -r1.1 -r1.2 src/sys/arch/riscv/dev/plicvar.h
diff -r1.2 -r1.3 src/sys/arch/riscv/dev/plic_fdt.c
cvs diff -r1.1 -r1.2 src/sys/arch/riscv/dev/plic.c (expand / switch to unified diff)

--- src/sys/arch/riscv/dev/plic.c 2023/05/07 12:41:48 1.1
+++ src/sys/arch/riscv/dev/plic.c 2023/09/02 09:58:15 1.2
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: plic.c,v 1.1 2023/05/07 12:41:48 skrll Exp $ */ 1/* $NetBSD: plic.c,v 1.2 2023/09/02 09:58:15 skrll Exp $ */
2 2
3/*- 3/*-
4 * Copyright (c) 2022 The NetBSD Foundation, Inc. 4 * Copyright (c) 2022 The NetBSD Foundation, Inc.
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * Portions of this code is derived from software contributed to The NetBSD 7 * Portions of this code is derived from software contributed to The NetBSD
8 * Foundation by Simon Burge. 8 * Foundation by Simon Burge.
9 * 9 *
10 * Redistribution and use in source and binary forms, with or without 10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions 11 * modification, are permitted provided that the following conditions
12 * are met: 12 * are met:
13 * 1. Redistributions of source code must retain the above copyright 13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer. 14 * notice, this list of conditions and the following disclaimer.
@@ -22,174 +22,177 @@ @@ -22,174 +22,177 @@
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE. 29 * POSSIBILITY OF SUCH DAMAGE.
30 */ 30 */
31 31
32#include "opt_multiprocessor.h" 32#include "opt_multiprocessor.h"
33 33
34#include <sys/cdefs.h> 34#include <sys/cdefs.h>
35__KERNEL_RCSID(0, "$NetBSD: plic.c,v 1.1 2023/05/07 12:41:48 skrll Exp $"); 35__KERNEL_RCSID(0, "$NetBSD: plic.c,v 1.2 2023/09/02 09:58:15 skrll Exp $");
36 36
37#include <sys/param.h> 37#include <sys/param.h>
38 38
39#include <sys/bus.h> 39#include <sys/bus.h>
40#include <sys/cpu.h> 40#include <sys/cpu.h>
41#include <sys/kmem.h> 41#include <sys/kmem.h>
42 42
43#include <riscv/sysreg.h> 43#include <riscv/sysreg.h>
44#include <riscv/dev/plicreg.h> 44#include <riscv/dev/plicreg.h>
45#include <riscv/dev/plicvar.h> 45#include <riscv/dev/plicvar.h>
46 46
47#define PLIC_PRIORITY(irq) (PLIC_PRIORITY_BASE + (irq) * 4) 47#define PLIC_PRIORITY(irq) (PLIC_PRIORITY_BASE + (irq) * 4)
48 48
49#define PLIC_ENABLE(sc, c, irq) (PLIC_ENABLE_BASE + \ 49#define PLIC_ENABLE(sc, h, irq) (PLIC_ENABLE_BASE + \
50 sc->sc_context[(c)] * PLIC_ENABLE_SIZE + \ 50 sc->sc_context[(h)] * PLIC_ENABLE_SIZE + \
51 ((irq / 32) * sizeof(uint32_t))) 51 ((irq / 32) * sizeof(uint32_t)))
52 52
53#define PLIC_CONTEXT(sc, c) (PLIC_CONTEXT_BASE + \ 53#define PLIC_CONTEXT(sc, h) (PLIC_CONTEXT_BASE + \
54 sc->sc_context[(c)] * PLIC_CONTEXT_SIZE) 54 sc->sc_context[(h)] * PLIC_CONTEXT_SIZE)
55#define PLIC_CLAIM(sc, c) (PLIC_CONTEXT(sc, c) + PLIC_CLAIM_COMPLETE_OFFS) 55#define PLIC_CLAIM(sc, h) (PLIC_CONTEXT(sc, h) + PLIC_CLAIM_COMPLETE_OFFS)
56#define PLIC_COMPLETE(sc, c) PLIC_CLAIM(sc, c) /* same address */ 56#define PLIC_COMPLETE(sc, h) PLIC_CLAIM(sc, h) /* same address */
57#define PLIC_THRESHOLD(sc, c) (PLIC_CONTEXT(sc, c) + PLIC_THRESHOLD_OFFS) 57#define PLIC_THRESHOLD(sc, h) (PLIC_CONTEXT(sc, h) + PLIC_THRESHOLD_OFFS)
58 58
59#define PLIC_READ(sc, reg) \ 59#define PLIC_READ(sc, reg) \
60 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 60 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
61#define PLIC_WRITE(sc, reg, val) \ 61#define PLIC_WRITE(sc, reg, val) \
62 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 62 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
63 63
64 64
65struct plic_softc *plic_sc; 65struct plic_softc *plic_sc;
66 66
67 67
68void * 68void *
69plic_intr_establish_xname(u_int irq, int ipl, int flags, 69plic_intr_establish_xname(u_int irq, int ipl, int flags,
70 int (*func)(void *), void *arg, const char *xname) 70 int (*func)(void *), void *arg, const char *xname)
71{ 71{
72 struct plic_softc * const sc = plic_sc; 72 struct plic_softc * const sc = plic_sc;
73 struct plic_intrhand *ih; 73 struct plic_intrhand *ih;
74 74
75 /* XXX need a better CPU selection method */ 75 /*
76// u_int cidx = cpu_index(curcpu()); 76 * Choose hart 0.
77 u_int cidx = 0; 77 * XXX need a better hart selection method
 78 */
 79 u_int hartid = 0;
78 80
79 evcnt_attach_dynamic(&sc->sc_intrevs[irq], EVCNT_TYPE_INTR, NULL, 81 evcnt_attach_dynamic(&sc->sc_intrevs[irq], EVCNT_TYPE_INTR, NULL,
80 "plic", xname); 82 "plic", xname);
81 83
82 ih = &sc->sc_intr[irq]; 84 ih = &sc->sc_intr[irq];
83 KASSERTMSG(ih->ih_func == NULL, 85 KASSERTMSG(ih->ih_func == NULL,
84 "Oops, we need to chain PLIC interrupt handlers"); 86 "Oops, we need to chain PLIC interrupt handlers");
85 if (ih->ih_func != NULL) { 87 if (ih->ih_func != NULL) {
86 aprint_error_dev(sc->sc_dev, "irq slot %d already used\n", irq); 88 aprint_error_dev(sc->sc_dev, "irq slot %d already used\n", irq);
87 return NULL; 89 return NULL;
88 } 90 }
89 ih->ih_mpsafe = (flags & IST_MPSAFE) != 0; 91 ih->ih_mpsafe = (flags & IST_MPSAFE) != 0;
90 ih->ih_func = func; 92 ih->ih_func = func;
91 ih->ih_arg = arg; 93 ih->ih_arg = arg;
92 ih->ih_irq = irq; 94 ih->ih_irq = irq;
93 ih->ih_cidx = cidx; 95 ih->ih_hartid = hartid;
94 96
95 plic_set_priority(sc, irq, 1); 97 plic_set_priority(sc, irq, 1);
96 plic_enable(sc, cidx, irq); 98 plic_enable(sc, hartid, irq);
97 99
98 return ih; 100 return ih;
99} 101}
100 102
101void 103void
102plic_intr_disestablish(void *cookie) 104plic_intr_disestablish(void *cookie)
103{ 105{
104 struct plic_softc * const sc = plic_sc; 106 struct plic_softc * const sc = plic_sc;
105 struct plic_intrhand * const ih = cookie; 107 struct plic_intrhand * const ih = cookie;
106 const u_int cidx = ih->ih_cidx; 108 const u_int hartid = ih->ih_hartid;
107 const u_int irq = ih->ih_irq; 109 const u_int irq = ih->ih_irq;
108 110
109 plic_disable(sc, cidx, irq); 111 plic_disable(sc, hartid, irq);
110 plic_set_priority(sc, irq, 0); 112 plic_set_priority(sc, irq, 0);
111 113
112 memset(&sc->sc_intr[irq], 0, sizeof(*sc->sc_intr)); 114 memset(&sc->sc_intr[irq], 0, sizeof(*sc->sc_intr));
113} 115}
114 116
115int 117int
116plic_intr(void *arg) 118plic_intr(void *arg)
117{ 119{
118 struct plic_softc * const sc = arg; 120 struct plic_softc * const sc = arg;
119 const cpuid_t cpuid = cpu_number(); 121 const cpuid_t hartid = cpu_number();
120 const bus_addr_t claim_addr = PLIC_CLAIM(sc, cpuid); 122 const bus_addr_t claim_addr = PLIC_CLAIM(sc, hartid);
121 const bus_addr_t complete_addr = PLIC_COMPLETE(sc, cpuid); 123 const bus_addr_t complete_addr = PLIC_COMPLETE(sc, hartid);
122 uint32_t pending; 124 uint32_t pending;
123 int rv = 0; 125 int rv = 0;
124 126
125 while ((pending = PLIC_READ(sc, claim_addr)) > 0) { 127 while ((pending = PLIC_READ(sc, claim_addr)) > 0) {
126 struct plic_intrhand *ih = &sc->sc_intr[pending]; 128 struct plic_intrhand *ih = &sc->sc_intr[pending];
127 129
128 sc->sc_intrevs[pending].ev_count++; 130 sc->sc_intrevs[pending].ev_count++;
129 131
130 KASSERT(ih->ih_func != NULL); 132 KASSERT(ih->ih_func != NULL);
131#ifdef MULTIPROCESSOR 133#ifdef MULTIPROCESSOR
132 if (!ih->ih_mpsafe) { 134 if (!ih->ih_mpsafe) {
133 KERNEL_LOCK(1, NULL); 135 KERNEL_LOCK(1, NULL);
134 rv |= ih->ih_func(ih->ih_arg); 136 rv |= ih->ih_func(ih->ih_arg);
135 KERNEL_UNLOCK_ONE(NULL); 137 KERNEL_UNLOCK_ONE(NULL);
136 } else 138 } else
137#endif 139#endif
138 rv |= ih->ih_func(ih->ih_arg); 140 rv |= ih->ih_func(ih->ih_arg);
139 141
140 PLIC_WRITE(sc, complete_addr, pending); 142 PLIC_WRITE(sc, complete_addr, pending);
141 } 143 }
142 144
143 return rv; 145 return rv;
144} 146}
145 147
146void 148void
147plic_enable(struct plic_softc *sc, u_int cpu, u_int irq) 149plic_enable(struct plic_softc *sc, u_int hartid, u_int irq)
148{ 150{
149 KASSERT(irq < PLIC_NIRQ); 151 KASSERT(irq < PLIC_NIRQ);
150 const bus_addr_t addr = PLIC_ENABLE(sc, cpu, irq); 152 const bus_addr_t addr = PLIC_ENABLE(sc, hartid, irq);
151 const uint32_t mask = __BIT(irq % 32); 153 const uint32_t mask = __BIT(irq % 32);
152 154
153 uint32_t reg = PLIC_READ(sc, addr); 155 uint32_t reg = PLIC_READ(sc, addr);
154 reg |= mask; 156 reg |= mask;
 157
155 PLIC_WRITE(sc, addr, reg); 158 PLIC_WRITE(sc, addr, reg);
156} 159}
157 160
158void 161void
159plic_disable(struct plic_softc *sc, u_int cpu, u_int irq) 162plic_disable(struct plic_softc *sc, u_int hartid, u_int irq)
160{ 163{
161 KASSERT(irq < PLIC_NIRQ); 164 KASSERT(irq < PLIC_NIRQ);
162 const bus_addr_t addr = PLIC_ENABLE(sc, cpu, irq); 165 const bus_addr_t addr = PLIC_ENABLE(sc, hartid, irq);
163 const uint32_t mask = __BIT(irq % 32); 166 const uint32_t mask = __BIT(irq % 32);
164 167
165 uint32_t reg = PLIC_READ(sc, addr); 168 uint32_t reg = PLIC_READ(sc, addr);
166 reg &= ~mask; 169 reg &= ~mask;
167 PLIC_WRITE(sc, addr, reg); 170 PLIC_WRITE(sc, addr, reg);
168} 171}
169 172
170void 173void
171plic_set_priority(struct plic_softc *sc, u_int irq, uint32_t priority) 174plic_set_priority(struct plic_softc *sc, u_int irq, uint32_t priority)
172{ 175{
173 KASSERT(irq < PLIC_NIRQ); 176 KASSERT(irq < PLIC_NIRQ);
174 const bus_addr_t addr = PLIC_PRIORITY(irq); 177 const bus_addr_t addr = PLIC_PRIORITY(irq);
175 178
176 PLIC_WRITE(sc, addr, priority); 179 PLIC_WRITE(sc, addr, priority);
177} 180}
178 181
179void 182void
180plic_set_threshold(struct plic_softc *sc, cpuid_t cpu, uint32_t threshold) 183plic_set_threshold(struct plic_softc *sc, cpuid_t hartid, uint32_t threshold)
181{ 184{
182 const bus_addr_t addr = PLIC_THRESHOLD(sc, cpu); 185 const bus_addr_t addr = PLIC_THRESHOLD(sc, hartid);
183 186
184 PLIC_WRITE(sc, addr, threshold); 187 PLIC_WRITE(sc, addr, threshold);
185} 188}
186 189
187int 190int
188plic_attach_common(struct plic_softc *sc, bus_addr_t addr, bus_size_t size) 191plic_attach_common(struct plic_softc *sc, bus_addr_t addr, bus_size_t size)
189{ 192{
190 struct cpu_info *ci; 193 struct cpu_info *ci;
191 CPU_INFO_ITERATOR cii; 194 CPU_INFO_ITERATOR cii;
192 u_int irq; 195 u_int irq;
193 196
194 sc->sc_intr = kmem_zalloc(sizeof(*sc->sc_intr) * sc->sc_ndev, 197 sc->sc_intr = kmem_zalloc(sizeof(*sc->sc_intr) * sc->sc_ndev,
195 KM_SLEEP); 198 KM_SLEEP);
cvs diff -r1.1 -r1.2 src/sys/arch/riscv/dev/plicvar.h (expand / switch to unified diff)

--- src/sys/arch/riscv/dev/plicvar.h 2023/05/07 12:41:48 1.1
+++ src/sys/arch/riscv/dev/plicvar.h 2023/09/02 09:58:15 1.2
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: plicvar.h,v 1.1 2023/05/07 12:41:48 skrll Exp $ */ 1/* $NetBSD: plicvar.h,v 1.2 2023/09/02 09:58:15 skrll Exp $ */
2 2
3/*- 3/*-
4 * Copyright (c) 2022 The NetBSD Foundation, Inc. 4 * Copyright (c) 2022 The NetBSD Foundation, Inc.
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * Portions of this code is derived from software contributed to The NetBSD 7 * Portions of this code is derived from software contributed to The NetBSD
8 * Foundation by Simon Burge. 8 * Foundation by Simon Burge.
9 * 9 *
10 * Redistribution and use in source and binary forms, with or without 10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions 11 * modification, are permitted provided that the following conditions
12 * are met: 12 * are met:
13 * 1. Redistributions of source code must retain the above copyright 13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer. 14 * notice, this list of conditions and the following disclaimer.
@@ -27,27 +27,27 @@ @@ -27,27 +27,27 @@
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE. 29 * POSSIBILITY OF SUCH DAMAGE.
30 */ 30 */
31 31
32#ifndef _RISCV_PLICVAR_H 32#ifndef _RISCV_PLICVAR_H
33#define _RISCV_PLICVAR_H 33#define _RISCV_PLICVAR_H
34 34
35struct plic_intrhand { 35struct plic_intrhand {
36 int (*ih_func)(void *); 36 int (*ih_func)(void *);
37 void *ih_arg; 37 void *ih_arg;
38 bool ih_mpsafe; 38 bool ih_mpsafe;
39 u_int ih_irq; 39 u_int ih_irq;
40 u_int ih_cidx; 40 u_int ih_hartid;
41}; 41};
42 42
43struct plic_softc { 43struct plic_softc {
44 device_t sc_dev; 44 device_t sc_dev;
45 bus_space_tag_t sc_bst; 45 bus_space_tag_t sc_bst;
46 bus_space_handle_t sc_bsh; 46 bus_space_handle_t sc_bsh;
47 47
48 uint32_t sc_ndev; 48 uint32_t sc_ndev;
49 49
50 uint32_t sc_context[MAXCPUS]; 50 uint32_t sc_context[MAXCPUS];
51 struct plic_intrhand *sc_intr; 51 struct plic_intrhand *sc_intr;
52 struct evcnt *sc_intrevs; 52 struct evcnt *sc_intrevs;
53}; 53};
cvs diff -r1.2 -r1.3 src/sys/arch/riscv/dev/plic_fdt.c (expand / switch to unified diff)

--- src/sys/arch/riscv/dev/plic_fdt.c 2023/09/02 09:29:59 1.2
+++ src/sys/arch/riscv/dev/plic_fdt.c 2023/09/02 09:58:15 1.3
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: plic_fdt.c,v 1.2 2023/09/02 09:29:59 skrll Exp $ */ 1/* $NetBSD: plic_fdt.c,v 1.3 2023/09/02 09:58:15 skrll Exp $ */
2 2
3/*- 3/*-
4 * Copyright (c) 2022 The NetBSD Foundation, Inc. 4 * Copyright (c) 2022 The NetBSD Foundation, Inc.
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * Portions of this code is derived from software contributed to The NetBSD 7 * Portions of this code is derived from software contributed to The NetBSD
8 * Foundation by Simon Burge and Nick Hudson. 8 * Foundation by Simon Burge and Nick Hudson.
9 * 9 *
10 * Redistribution and use in source and binary forms, with or without 10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions 11 * modification, are permitted provided that the following conditions
12 * are met: 12 * are met:
13 * 1. Redistributions of source code must retain the above copyright 13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer. 14 * notice, this list of conditions and the following disclaimer.
@@ -20,27 +20,27 @@ @@ -20,27 +20,27 @@
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE. 29 * POSSIBILITY OF SUCH DAMAGE.
30 */ 30 */
31 31
32#include <sys/cdefs.h> 32#include <sys/cdefs.h>
33__KERNEL_RCSID(0, "$NetBSD: plic_fdt.c,v 1.2 2023/09/02 09:29:59 skrll Exp $"); 33__KERNEL_RCSID(0, "$NetBSD: plic_fdt.c,v 1.3 2023/09/02 09:58:15 skrll Exp $");
34 34
35#include <sys/param.h> 35#include <sys/param.h>
36 36
37#include <sys/bus.h> 37#include <sys/bus.h>
38#include <sys/cpu.h> 38#include <sys/cpu.h>
39#include <sys/device.h> 39#include <sys/device.h>
40#include <sys/intr.h> 40#include <sys/intr.h>
41 41
42#include <dev/fdt/fdtvar.h> 42#include <dev/fdt/fdtvar.h>
43 43
44#include <riscv/sysreg.h> 44#include <riscv/sysreg.h>
45#include <riscv/dev/plicreg.h> 45#include <riscv/dev/plicreg.h>
46#include <riscv/dev/plicvar.h> 46#include <riscv/dev/plicvar.h>
@@ -189,43 +189,43 @@ plic_fdt_attach(device_t parent, device_ @@ -189,43 +189,43 @@ plic_fdt_attach(device_t parent, device_
189 } else { 189 } else {
190 char intrstr[128]; 190 char intrstr[128];
191 bool ok = fdtbus_intr_str(phandle, context, 191 bool ok = fdtbus_intr_str(phandle, context,
192 intrstr, sizeof(intrstr)); 192 intrstr, sizeof(intrstr));
193 aprint_verbose_dev(self, "interrupt %s handler " 193 aprint_verbose_dev(self, "interrupt %s handler "
194 "installed\n", ok ? intrstr : "(unk)"); 194 "installed\n", ok ? intrstr : "(unk)");
195 } 195 }
196 196
197 if (intr_source == IRQ_SUPERVISOR_EXTERNAL) { 197 if (intr_source == IRQ_SUPERVISOR_EXTERNAL) {
198 /* 198 /*
199 * When finding context info, parent _must_ be a 199 * When finding context info, parent _must_ be a
200 * compatbile clint device. 200 * compatbile clint device.
201 */ 201 */
202 bus_addr_t cpuid; 202 bus_addr_t hartid;
203 int cpu_ref; 203 int cpu_ref;
204 static const struct device_compatible_entry clint_compat_data[] = { 204 static const struct device_compatible_entry clint_compat_data[] = {
205 { .compat = "riscv,cpu-intc" }, 205 { .compat = "riscv,cpu-intc" },
206 DEVICE_COMPAT_EOL 206 DEVICE_COMPAT_EOL
207 }; 207 };
208 208
209 if (of_compatible_match(xref, clint_compat_data)) { 209 if (of_compatible_match(xref, clint_compat_data)) {
210 /* get cpuid for the parent node */ 210 /* get cpuid for the parent node */
211 cpu_ref = OF_parent(xref); 211 cpu_ref = OF_parent(xref);
212 fdtbus_get_reg(cpu_ref, 0, &cpuid, NULL); 212 fdtbus_get_reg(cpu_ref, 0, &hartid, NULL);
213 213
214 KASSERT(context <= PLIC_MAX_CONTEXT); 214 KASSERT(context <= PLIC_MAX_CONTEXT);
215 sc->sc_context[cpuid] = context; 215 sc->sc_context[hartid] = context;
216 aprint_verbose_dev(self, 216 aprint_verbose_dev(self,
217 "cpu %"PRId64" context %d\n", 217 "hart %"PRId64" context %d\n",
218 cpuid, context); 218 hartid, context);
219 } else { 219 } else {
220 aprint_error_dev(self, "incompatiable CLINT " 220 aprint_error_dev(self, "incompatiable CLINT "
221 " for PLIC for context %d\n", context); 221 " for PLIC for context %d\n", context);
222 } 222 }
223 223
224 } 224 }
225 } 225 }
226 len -= (intr_cells + 1) * 4; 226 len -= (intr_cells + 1) * 4;
227 data += (intr_cells + 1); 227 data += (intr_cells + 1);
228 context++; 228 context++;
229 } 229 }
230 230
231 aprint_verbose_dev(self, ""); 231 aprint_verbose_dev(self, "");