| @@ -6233,28 +6233,28 @@ insns_between (const struct mips_cl_insn | | | @@ -6233,28 +6233,28 @@ insns_between (const struct mips_cl_insn |
| 6233 | { | | 6233 | { |
| 6234 | if (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1))) | | 6234 | if (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1))) |
| 6235 | return 1; | | 6235 | return 1; |
| 6236 | } | | 6236 | } |
| 6237 | | | 6237 | |
| 6238 | /* Check for generic coprocessor hazards. | | 6238 | /* Check for generic coprocessor hazards. |
| 6239 | | | 6239 | |
| 6240 | This case is not handled very well. There is no special | | 6240 | This case is not handled very well. There is no special |
| 6241 | knowledge of CP0 handling, and the coprocessors other than | | 6241 | knowledge of CP0 handling, and the coprocessors other than |
| 6242 | the floating point unit are not distinguished at all. */ | | 6242 | the floating point unit are not distinguished at all. */ |
| 6243 | /* Itbl support may require additional care here. FIXME! | | 6243 | /* Itbl support may require additional care here. FIXME! |
| 6244 | Need to modify this to include knowledge about | | 6244 | Need to modify this to include knowledge about |
| 6245 | user specified delays! */ | | 6245 | user specified delays! */ |
| 6246 | else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE)) | | 6246 | if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE)) |
| 6247 | || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY))) | | 6247 | || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY))) |
| 6248 | { | | 6248 | { |
| 6249 | /* Handle cases where INSN1 writes to a known general coprocessor | | 6249 | /* Handle cases where INSN1 writes to a known general coprocessor |
| 6250 | register. There must be a one instruction delay before INSN2 | | 6250 | register. There must be a one instruction delay before INSN2 |
| 6251 | if INSN2 reads that register, otherwise no delay is needed. */ | | 6251 | if INSN2 reads that register, otherwise no delay is needed. */ |
| 6252 | mask = fpr_write_mask (insn1); | | 6252 | mask = fpr_write_mask (insn1); |
| 6253 | if (mask != 0) | | 6253 | if (mask != 0) |
| 6254 | { | | 6254 | { |
| 6255 | if (!insn2 || (mask & fpr_read_mask (insn2)) != 0) | | 6255 | if (!insn2 || (mask & fpr_read_mask (insn2)) != 0) |
| 6256 | return 1; | | 6256 | return 1; |
| 6257 | } | | 6257 | } |
| 6258 | else | | 6258 | else |
| 6259 | { | | 6259 | { |
| 6260 | /* Read-after-write dependencies on the control registers | | 6260 | /* Read-after-write dependencies on the control registers |