Mon Jan 1 22:47:58 2024 UTC (139d)
Define PTE used in the pmap module int terms of the bit definitions
in mmu_{51,40}.h.


(thorpej)
diff -r1.9 -r1.10 src/sys/arch/m68k/include/pte_motorola.h
cvs diff -r1.9 -r1.10 src/sys/arch/m68k/include/pte_motorola.h (expand / switch to unified diff)

--- src/sys/arch/m68k/include/pte_motorola.h 2023/12/27 03:03:41 1.9
+++ src/sys/arch/m68k/include/pte_motorola.h 2024/01/01 22:47:58 1.10
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: pte_motorola.h,v 1.9 2023/12/27 03:03:41 thorpej Exp $ */ 1/* $NetBSD: pte_motorola.h,v 1.10 2024/01/01 22:47:58 thorpej Exp $ */
2 2
3/* 3/*
4 * Copyright (c) 1988 University of Utah. 4 * Copyright (c) 1988 University of Utah.
5 * Copyright (c) 1982, 1986, 1990, 1993 5 * Copyright (c) 1982, 1986, 1990, 1993
6 * The Regents of the University of California. All rights reserved. 6 * The Regents of the University of California. All rights reserved.
7 * 7 *
8 * This code is derived from software contributed to Berkeley by 8 * This code is derived from software contributed to Berkeley by
9 * the Systems Programming Group of the University of Utah Computer 9 * the Systems Programming Group of the University of Utah Computer
10 * Science Department. 10 * Science Department.
11 * 11 *
12 * Redistribution and use in source and binary forms, with or without 12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions 13 * modification, are permitted provided that the following conditions
14 * are met: 14 * are met:
@@ -46,75 +46,83 @@ @@ -46,75 +46,83 @@
46 46
47/* 47/*
48 * m68k motorola MMU segment/page table entries 48 * m68k motorola MMU segment/page table entries
49 */ 49 */
50 50
51typedef u_int st_entry_t; /* segment table entry */ 51typedef u_int st_entry_t; /* segment table entry */
52typedef u_int pt_entry_t; /* page table entry */ 52typedef u_int pt_entry_t; /* page table entry */
53 53
54#define PT_ENTRY_NULL NULL 54#define PT_ENTRY_NULL NULL
55#define ST_ENTRY_NULL NULL 55#define ST_ENTRY_NULL NULL
56 56
57#define PG_SHIFT PGSHIFT 57#define PG_SHIFT PGSHIFT
58 58
59#define SG_V 0x00000002 /* segment is valid */ 59/*
60#define SG_NV 0x00000000 60 * "Segment" Table Entry bits, defined in terms of the 68851 bits
61#define SG_PROT 0x00000004 /* access protection mask */ 61 * (compatible 68040 bits noted in comments).
62#define SG_RO 0x00000004 62 */
 63#define SG_V DT51_SHORT /* == UTE40_RESIDENT */
 64#define SG_NV DT51_INVALID /* == UTE40_INVALID */
 65#define SG_RO DTE51_WP /* == UTE40_W */
63#define SG_RW 0x00000000 66#define SG_RW 0x00000000
64#define SG_U 0x00000008 /* modified bit (68040) */ 67#define SG_PROT DTE51_WP
65#define SG_FRAME ((~0) << PG_SHIFT) 68#define SG_U DTE51_U /* == UTE40_U */
 69#define SG_FRAME ((~0U) << PG_SHIFT)
66#define SG_ISHIFT ((PG_SHIFT << 1) - 2) /* 24 or 22 */ 70#define SG_ISHIFT ((PG_SHIFT << 1) - 2) /* 24 or 22 */
67#define SG_IMASK ((~0) << SG_ISHIFT) 71#define SG_IMASK ((~0U) << SG_ISHIFT)
68#define SG_PSHIFT PG_SHIFT 72#define SG_PSHIFT PG_SHIFT
69#define SG_PMASK (((~0) << SG_PSHIFT) & ~SG_IMASK) 73#define SG_PMASK (((~0U) << SG_PSHIFT) & ~SG_IMASK)
70 74
71/* 68040 additions */ 75/* 68040 additions */
72#define SG4_MASK1 0xfe000000 76#define SG4_MASK1 0xfe000000U
73#define SG4_SHIFT1 25 77#define SG4_SHIFT1 25
74#define SG4_MASK2 0x01fc0000 78#define SG4_MASK2 0x01fc0000U
75#define SG4_SHIFT2 18 79#define SG4_SHIFT2 18
76#define SG4_MASK3 (((~0) << PG_SHIFT) & ~(SG4_MASK1 | SG4_MASK2)) 80#define SG4_MASK3 (((~0U) << PG_SHIFT) & ~(SG4_MASK1 | SG4_MASK2))
77#define SG4_SHIFT3 PG_SHIFT 81#define SG4_SHIFT3 PG_SHIFT
78#define SG4_ADDR1 0xfffffe00 82#define SG4_ADDR1 0xfffffe00
79#define SG4_ADDR2 ((~0) << (20 - PG_SHIFT)) 83#define SG4_ADDR2 ((~0U) << (20 - PG_SHIFT))
80#define SG4_LEV1SIZE 128 84#define SG4_LEV1SIZE 128
81#define SG4_LEV2SIZE 128 85#define SG4_LEV2SIZE 128
82#define SG4_LEV3SIZE (1 << (SG4_SHIFT2 - PG_SHIFT)) /* 64 or 32 */ 86#define SG4_LEV3SIZE (1U << (SG4_SHIFT2 - PG_SHIFT)) /* 64 or 32 */
83 87
84#define PG_V 0x00000001 88/*
85#define PG_NV 0x00000000 89 * Page Table Entry bits, defined in terms of the 68851 bits
86#define PG_PROT 0x00000004 90 * (compatible 68040 bits noted in comments).
87#define PG_U 0x00000008 91 */
88#define PG_M 0x00000010 92#define PG_V DT51_PAGE /* == PTE40_RESIDENT */
89#define PG_W 0x00000100 93#define PG_NV DT51_INVALID /* == PTE40_INVALID */
90#define PG_RO 0x00000004 94#define PG_RO PTE51_WP /* == PTE40_W */
91#define PG_RW 0x00000000 95#define PG_RW 0x00000000
92#define PG_FRAME ((~0) << PG_SHIFT) 96#define PG_PROT PG_RO
93#define PG_CI 0x00000040 97#define PG_U PTE51_U /* == PTE40_U */
94#define PG_PFNUM(x) (((x) & PG_FRAME) >> PG_SHIFT) 98#define PG_M PTE51_M /* == PTE40_M */
 99#define PG_CI PTE51_CI
 100#define PG_W __BIT(8) /* 851 unused bit XXX040 PTE40_U0 */
 101#define PG_FRAME ((~0U) << PG_SHIFT)
 102#define PG_PFNUM(x) (((uintptr_t)(x) & PG_FRAME) >> PG_SHIFT)
95 103
96/* 68040 additions */ 104/* 68040 additions */
97#define PG_CMASK 0x00000060 /* cache mode mask */ 105#define PG_CMASK PTE40_CM /* cache mode mask */
98#define PG_CWT 0x00000000 /* writethrough caching */ 106#define PG_CWT PTE40_CM_WT /* writethrough caching */
99#define PG_CCB 0x00000020 /* copyback caching */ 107#define PG_CCB PTE40_CM_CB /* copyback caching */
100#define PG_CIS 0x00000040 /* cache inhibited serialized */ 108#define PG_CIS PTE40_CM_NC_SER /* cache inhibited serialized */
101#define PG_CIN 0x00000060 /* cache inhibited nonserialized */ 109#define PG_CIN PTE40_CM_NC /* cache inhibited nonserialized */
102#define PG_SO 0x00000080 /* supervisor only */ 110#define PG_SO PTE40_S /* supervisor only */
103 111
104#define M68K_STSIZE (MAXUL2SIZE * SG4_LEV2SIZE * sizeof(st_entry_t)) 112#define M68K_STSIZE (MAXUL2SIZE * SG4_LEV2SIZE * sizeof(st_entry_t))
105 /* user process segment table size */ 113 /* user process segment table size */
106#define M68K_MAX_PTSIZE (1 << (32 - PG_SHIFT + 2)) /* max size of UPT */ 114#define M68K_MAX_PTSIZE (1U << (32 - PG_SHIFT + 2)) /* max size of UPT */
107#define M68K_MAX_KPTSIZE (M68K_MAX_PTSIZE >> 2) /* max memory to allocate to KPT */ 115#define M68K_MAX_KPTSIZE (M68K_MAX_PTSIZE >> 2) /* max memory to allocate to KPT */
108#define M68K_PTBASE 0x10000000 /* UPT map base address */ 116#define M68K_PTBASE 0x10000000 /* UPT map base address */
109#define M68K_PTMAXSIZE 0x70000000 /* UPT map maximum size */ 117#define M68K_PTMAXSIZE 0x70000000 /* UPT map maximum size */
110 118
111/* 119/*
112 * Kernel virtual address to page table entry and to physical address. 120 * Kernel virtual address to page table entry and to physical address.
113 */ 121 */
114 122
115#ifdef cesfic 123#ifdef cesfic
116#define kvtopte(va) \ 124#define kvtopte(va) \
117 (&Sysmap[((unsigned)(va)) >> PGSHIFT]) 125 (&Sysmap[((unsigned)(va)) >> PGSHIFT])
118#else 126#else
119#define kvtopte(va) \ 127#define kvtopte(va) \
120 (&Sysmap[((unsigned)(va) - VM_MIN_KERNEL_ADDRESS) >> PGSHIFT]) 128 (&Sysmap[((unsigned)(va) - VM_MIN_KERNEL_ADDRESS) >> PGSHIFT])