 @@ -1,14 +1,14 @@
-/* $NetBSD: ix_txrx.c,v 1.100.4.4 2023/10/18 11:53:22 martin Exp $ */
+/* $NetBSD: ix_txrx.c,v 1.100.4.5 2024/02/03 11:58:53 martin Exp $ */
 /******************************************************************************
   Copyright (c) 2001-2017, Intel Corporation
   All rights reserved.
   Redistribution and use in source and binary forms, with or without
   modification, are permitted provided that the following conditions are met:
 . Redistributions of source code must retain the above copyright notice,
       this list of conditions and the following disclaimer.
 . Redistributions in binary form must reproduce the above copyright
 @@ -54,57 +54,61 @@
  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: ix_txrx.c,v 1.100.4.4 2023/10/18 11:53:22 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: ix_txrx.c,v 1.100.4.5 2024/02/03 11:58:53 martin Exp $");
 #include "opt_inet.h"
 #include "opt_inet6.h"
 #include "ixgbe.h"
 #ifdef RSC
 /*
  * HW RSC control:
  *  this feature only works with
  *  IPv4, and only on 82599 and later.
  *  Also this will cause IP forwarding to
  *  fail and that can't be controlled by
  *  the stack as LRO can. For all these
  *  reasons I've deemed it best to leave
  *  this off and not bother with a tuneable
  *  interface, this would need to be compiled
  *  to enable.
  */
 static bool ixgbe_rsc_enable = FALSE;
 #endif
 #ifdef IXGBE_FDIR
 /*
  * For Flow Director: this is the
  * number of TX packets we sample
  * for the filter pool, this means
  * every 20th packet will be probed.
+ *
  * This feature can be disabled by
  * setting this to 0.
  */
 static int atr_sample_rate = 20;
 #endif
 #define IXGBE_M_ADJ(sc, rxr, mp)					\
 	if (sc->max_frame_size <= (rxr->mbuf_sz - ETHER_ALIGN))	\
 		m_adj(mp, ETHER_ALIGN)
 /************************************************************************
  *  Local Function prototypes
  ************************************************************************/
 static void          ixgbe_setup_transmit_ring(struct tx_ring *);
 static void          ixgbe_free_transmit_buffers(struct tx_ring *);
 static int           ixgbe_setup_receive_ring(struct rx_ring *);
 static void          ixgbe_free_receive_buffers(struct rx_ring *);
 static void          ixgbe_rx_checksum(u32, struct mbuf *, u32,
 @@ -112,28 +116,29 @@ static void          ixgbe_rx_checksum(u
 static void          ixgbe_refresh_mbufs(struct rx_ring *, int);
 static void          ixgbe_drain(struct ifnet *, struct tx_ring *);
 static int           ixgbe_xmit(struct tx_ring *, struct mbuf *);
 static int           ixgbe_tx_ctx_setup(struct tx_ring *,
                                         struct mbuf *, u32 *, u32 *);
 static int           ixgbe_tso_setup(struct tx_ring *,
                                      struct mbuf *, u32 *, u32 *);
 static __inline void ixgbe_rx_discard(struct rx_ring *, int);
 static __inline void ixgbe_rx_input(struct rx_ring *, struct ifnet *,
                                     struct mbuf *, u32);
 static int           ixgbe_dma_malloc(struct ixgbe_softc *, bus_size_t,
                                       struct ixgbe_dma_alloc *, int);
 static void          ixgbe_dma_free(struct ixgbe_softc *, struct ixgbe_dma_alloc *);
 #ifdef RSC
-static void	ixgbe_setup_hw_rsc(struct rx_ring *);
+static void	     ixgbe_setup_hw_rsc(struct rx_ring *);
 #endif
 /************************************************************************
  * ixgbe_legacy_start_locked - Transmit entry point
+ *
  *   Called by the stack to initiate a transmit.
  *   The driver will remain in this routine as long as there are
  *   packets to transmit and transmit resources are available.
  *   In case resources are not available, the stack is notified
  *   and the packet is requeued.
  ************************************************************************/
 int
 ixgbe_legacy_start_locked(struct ifnet *ifp, struct tx_ring *txr)
+{
 @@ -396,27 +401,27 @@ ixgbe_drain_all(struct ixgbe_softc *sc)
+}
 /************************************************************************
  * ixgbe_xmit
+ *
  *   Maps the mbufs to tx descriptors, allowing the
  *   TX engine to transmit the packets.
+ *
  *   Return 0 on success, positive on failure
  ************************************************************************/
 static int
 ixgbe_xmit(struct tx_ring *txr, struct mbuf *m_head)
+{
-	struct ixgbe_softc          *sc = txr->sc;
+	struct ixgbe_softc      *sc = txr->sc;
 	struct ixgbe_tx_buf     *txbuf;
 	union ixgbe_adv_tx_desc *txd = NULL;
 	struct ifnet	        *ifp = sc->ifp;
 	int                     i, j, error;
 	int                     first;
 	u32                     olinfo_status = 0, cmd_type_len;
 	bool                    remap = TRUE;
 	bus_dmamap_t            map;
 	/* Basic descriptor defines */
 	cmd_type_len = (IXGBE_ADVTXD_DTYP_DATA |
 	    IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT);
 @@ -477,28 +482,28 @@ retry:
 			return error;
+		}
+	}
 	/* Make certain there are enough descriptors */
 	if (txr->tx_avail < (map->dm_nsegs + 2)) {
 		txr->txr_no_space = true;
 		IXGBE_EVC_ADD(&txr->no_desc_avail, 1);
 		ixgbe_dmamap_unload(txr->txtag, txbuf->map);
 		return EAGAIN;
+	}
 	/*
-	 * Set up the appropriate offload context
+	 * Set up the appropriate offload context if requested,
-	 * this will consume the first descriptor
+	 * this may consume one TX descriptor.
 	 */
 	error = ixgbe_tx_ctx_setup(txr, m_head, &cmd_type_len, &olinfo_status);
 	if (__predict_false(error)) {
 		return (error);
+	}
 #ifdef IXGBE_FDIR
 	/* Do the flow director magic */
 	if ((sc->feat_en & IXGBE_FEATURE_FDIR) &&
 	    (txr->atr_sample) && (!sc->fdir_reinit)) {
 		++txr->atr_count;
 		if (txr->atr_count >= atr_sample_rate) {
 			ixgbe_atr(txr, m_head);
 @@ -614,28 +619,28 @@ ixgbe_allocate_transmit_buffers(struct t
 	         /*      parent */ sc->osdep.dmat,
 	         /*   alignment */ 1,
 	         /*      bounds */ 0,
 	         /*     maxsize */ IXGBE_TSO_SIZE,
 	         /*   nsegments */ sc->num_segs,
 	         /*  maxsegsize */ PAGE_SIZE,
 	         /*       flags */ 0,
 	                           &txr->txtag);
 	if (error != 0) {
 		aprint_error_dev(dev,"Unable to allocate TX DMA tag\n");
 		goto fail;
+	}
-	txr->tx_buffers = malloc(sizeof(struct ixgbe_tx_buf) *
+	txr->tx_buffers = kmem_zalloc(sizeof(struct ixgbe_tx_buf) *
-	    sc->num_tx_desc, M_DEVBUF, M_WAITOK | M_ZERO);
+	    sc->num_tx_desc, KM_SLEEP);
 	/* Create the descriptor buffer dma maps */
 	txbuf = txr->tx_buffers;
 	for (i = 0; i < sc->num_tx_desc; i++, txbuf++) {
 		error = ixgbe_dmamap_create(txr->txtag, 0, &txbuf->map);
 		if (error != 0) {
 			aprint_error_dev(dev,
 			    "Unable to create TX DMA map (%d)\n", error);
 			goto fail;
+		}
+	}
 	return 0;
 @@ -705,29 +710,31 @@ ixgbe_setup_transmit_ring(struct tx_ring
 		 * netmap_idx_n2k() handles wraparounds properly.
 		 */
 		if ((sc->feat_en & IXGBE_FEATURE_NETMAP) && slot) {
 			int si = netmap_idx_n2k(na->tx_rings[txr->me], i);
 			netmap_load_map(na, txr->txtag,
 			    txbuf->map, NMB(na, slot + si));
+		}
 #endif /* DEV_NETMAP */
 		/* Clear the EOP descriptor pointer */
 		txbuf->eop = NULL;
+	}
 #ifdef IXGBE_FDIR
 	/* Set the rate at which we sample packets */
 	if (sc->feat_en & IXGBE_FEATURE_FDIR)
 		txr->atr_sample = atr_sample_rate;
 #endif
 	/* Set number of descriptors available */
 	txr->tx_avail = sc->num_tx_desc;
 	ixgbe_dmamap_sync(txr->txdma.dma_tag, txr->txdma.dma_map,
 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 	IXGBE_TX_UNLOCK(txr);
 } /* ixgbe_setup_transmit_ring */
 /************************************************************************
  * ixgbe_setup_transmit_structures - Initialize all transmit rings.
  ************************************************************************/
 int
 @@ -744,38 +751,38 @@ ixgbe_setup_transmit_structures(struct i
 /************************************************************************
  * ixgbe_free_transmit_structures - Free all transmit rings.
  ************************************************************************/
 void
 ixgbe_free_transmit_structures(struct ixgbe_softc *sc)
+{
 	struct tx_ring *txr = sc->tx_rings;
 	for (int i = 0; i < sc->num_queues; i++, txr++) {
 		ixgbe_free_transmit_buffers(txr);
 		ixgbe_dma_free(sc, &txr->txdma);
 		IXGBE_TX_LOCK_DESTROY(txr);
+	}
-	free(sc->tx_rings, M_DEVBUF);
+	kmem_free(sc->tx_rings, sizeof(struct tx_ring) * sc->num_queues);
 } /* ixgbe_free_transmit_structures */
 /************************************************************************
  * ixgbe_free_transmit_buffers
+ *
  *   Free transmit ring related data structures.
  ************************************************************************/
 static void
 ixgbe_free_transmit_buffers(struct tx_ring *txr)
+{
-	struct ixgbe_softc      *sc = txr->sc;
+	struct ixgbe_softc  *sc = txr->sc;
 	struct ixgbe_tx_buf *tx_buffer;
 	int                 i;
 	INIT_DEBUGOUT("ixgbe_free_transmit_buffers: begin");
 	if (txr->tx_buffers == NULL)
 		return;
 	tx_buffer = txr->tx_buffers;
 	for (i = 0; i < sc->num_tx_desc; i++, tx_buffer++) {
 		if (tx_buffer->m_head != NULL) {
 			bus_dmamap_sync(txr->txtag->dt_dmat, tx_buffer->map,
 , tx_buffer->m_head->m_pkthdr.len,
 @@ -792,27 +799,28 @@ ixgbe_free_transmit_buffers(struct tx_ri
 			ixgbe_dmamap_unload(txr->txtag, tx_buffer->map);
 			ixgbe_dmamap_destroy(txr->txtag, tx_buffer->map);
 			tx_buffer->map = NULL;
+		}
+	}
 	if (txr->txr_interq != NULL) {
 		struct mbuf *m;
 		while ((m = pcq_get(txr->txr_interq)) != NULL)
 			m_freem(m);
 		pcq_destroy(txr->txr_interq);
+	}
 	if (txr->tx_buffers != NULL) {
-		free(txr->tx_buffers, M_DEVBUF);
+		kmem_free(txr->tx_buffers,
 		    sizeof(struct ixgbe_tx_buf) * sc->num_tx_desc);
 		txr->tx_buffers = NULL;
+	}
 	if (txr->txtag != NULL) {
 		ixgbe_dma_tag_destroy(txr->txtag);
 		txr->txtag = NULL;
+	}
 } /* ixgbe_free_transmit_buffers */
 /************************************************************************
  * ixgbe_tx_ctx_setup
+ *
  *   Advanced Context Descriptor setup for VLAN, CSUM or TSO
  ************************************************************************/
 @@ -844,29 +852,26 @@ ixgbe_tx_ctx_setup(struct tx_ring *txr,
 		int rv = ixgbe_tso_setup(txr, mp, cmd_type_len, olinfo_status);
 		if (rv != 0)
 			IXGBE_EVC_ADD(&sc->tso_err, 1);
 		return rv;
+	}
 	if ((mp->m_pkthdr.csum_flags & M_CSUM_OFFLOAD) == 0)
 		offload = FALSE;
 	/* Indicate the whole packet as payload when not doing TSO */
 	*olinfo_status |= mp->m_pkthdr.len << IXGBE_ADVTXD_PAYLEN_SHIFT;
 	/* Now ready a context descriptor */
 	TXD = (struct ixgbe_adv_tx_context_desc *)&txr->tx_base[ctxd];
 	/*
 	 * In advanced descriptors the vlan tag must
 	 * be placed into the context descriptor. Hence
 	 * we need to make one even if not doing offloads.
 	 */
 	if (vlan_has_tag(mp)) {
 		vtag = htole16(vlan_get_tag(mp));
 		vlan_macip_lens |= (vtag << IXGBE_ADVTXD_VLAN_SHIFT);
 	} else if (!(txr->sc->feat_en & IXGBE_FEATURE_NEEDS_CTXD) &&
 	           (offload == FALSE))
 		return (0);
 	/*
 @@ -949,26 +954,29 @@ ixgbe_tx_ctx_setup(struct tx_ring *txr,
 			offload = false;
 		break;
 	default:
 		offload = false;
 		break;
+	}
 	if (offload) /* Insert L4 checksum into data descriptors */
 		*olinfo_status |= IXGBE_TXD_POPTS_TXSM << 8;
 no_offloads:
 	type_tucmd_mlhl |= IXGBE_ADVTXD_DCMD_DEXT | IXGBE_ADVTXD_DTYP_CTXT;
 	/* Now ready a context descriptor */
 	TXD = (struct ixgbe_adv_tx_context_desc *)&txr->tx_base[ctxd];
 	/* Now copy bits into descriptor */
 	TXD->vlan_macip_lens = htole32(vlan_macip_lens);
 	TXD->type_tucmd_mlhl = htole32(type_tucmd_mlhl);
 	TXD->seqnum_seed = htole32(0);
 	TXD->mss_l4len_idx = htole32(0);
 	/* We've consumed the first desc, adjust counters */
 	if (++ctxd == txr->num_desc)
 		ctxd = 0;
 	txr->next_avail_desc = ctxd;
 	--txr->tx_avail;
 	return (0);
 @@ -1098,26 +1106,27 @@ ixgbe_tso_setup(struct tx_ring *txr, str
  *   Examine each tx_buffer in the used queue. If the hardware is done
  *   processing the packet then free associated resources. The
  *   tx_buffer is put back on the free queue.
  ************************************************************************/
 bool
 ixgbe_txeof(struct tx_ring *txr)
+{
 	struct ixgbe_softc	*sc = txr->sc;
 	struct ifnet		*ifp = sc->ifp;
 	struct ixgbe_tx_buf	*buf;
 	union ixgbe_adv_tx_desc *txd;
 	u32			work, processed = 0;
 	u32			limit = sc->tx_process_limit;
 	u16			avail;
 	KASSERT(mutex_owned(&txr->tx_mtx));
 #ifdef DEV_NETMAP
 	if ((sc->feat_en & IXGBE_FEATURE_NETMAP) &&
 	    (sc->ifp->if_capenable & IFCAP_NETMAP)) {
 		struct netmap_sc *na = NA(sc->ifp);
 		struct netmap_kring *kring = na->tx_rings[txr->me];
 		txd = txr->tx_base;
 		bus_dmamap_sync(txr->txdma.dma_tag, txr->txdma.dma_map,
 		    BUS_DMASYNC_POSTREAD);
 		/*
 		 * In netmap mode, all the work is done in the context
 @@ -1141,123 +1150,128 @@ ixgbe_txeof(struct tx_ring *txr)
+	}
 #endif /* DEV_NETMAP */
 	if (txr->tx_avail == txr->num_desc) {
 		txr->busy = 0;
 		return false;
+	}
 	/* Get work starting point */
 	work = txr->next_to_clean;
 	buf = &txr->tx_buffers[work];
 	txd = &txr->tx_base[work];
 	work -= txr->num_desc; /* The distance to ring end */
 	avail = txr->tx_avail;
 	ixgbe_dmamap_sync(txr->txdma.dma_tag, txr->txdma.dma_map,
 	    BUS_DMASYNC_POSTREAD);
 	do {
 		union ixgbe_adv_tx_desc *eop = buf->eop;
 		if (eop == NULL) /* No work */
 			break;
 		if ((le32toh(eop->wb.status) & IXGBE_TXD_STAT_DD) == 0)
 			break;	/* I/O not complete */
 		if (buf->m_head) {
 			txr->bytes += buf->m_head->m_pkthdr.len;
 			bus_dmamap_sync(txr->txtag->dt_dmat, buf->map,
 , buf->m_head->m_pkthdr.len,
 			    BUS_DMASYNC_POSTWRITE);
 			ixgbe_dmamap_unload(txr->txtag, buf->map);
 			m_freem(buf->m_head);
 			buf->m_head = NULL;
+		}
 		buf->eop = NULL;
-		txr->txr_no_space = false;
+		++avail;
 		++txr->tx_avail;
 		/* We clean the range if multi segment */
 		while (txd != eop) {
 			++txd;
 			++buf;
 			++work;
 			/* wrap the ring? */
 			if (__predict_false(!work)) {
 				work -= txr->num_desc;
 				buf = txr->tx_buffers;
 				txd = txr->tx_base;
+			}
 			if (buf->m_head) {
 				txr->bytes +=
 				    buf->m_head->m_pkthdr.len;
 				bus_dmamap_sync(txr->txtag->dt_dmat,
 				    buf->map,
 , buf->m_head->m_pkthdr.len,
 				    BUS_DMASYNC_POSTWRITE);
 				ixgbe_dmamap_unload(txr->txtag,
 				    buf->map);
 				m_freem(buf->m_head);
 				buf->m_head = NULL;
+			}
-			++txr->tx_avail;
+			++avail;
 			buf->eop = NULL;
+		}
 		++txr->packets;
 		++processed;
 		if_statinc(ifp, if_opackets);
 		/* Try the next packet */
 		++txd;
 		++buf;
 		++work;
 		/* reset with a wrap */
 		if (__predict_false(!work)) {
 			work -= txr->num_desc;
 			buf = txr->tx_buffers;
 			txd = txr->tx_base;
+		}
 		prefetch(txd);
 	} while (__predict_true(--limit));
 	ixgbe_dmamap_sync(txr->txdma.dma_tag, txr->txdma.dma_map,
 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 	work += txr->num_desc;
 	txr->next_to_clean = work;
 	if (processed) {
 		txr->tx_avail = avail;
 		txr->txr_no_space = false;
 		txr->packets += processed;
 		if_statadd(ifp, if_opackets, processed);
+	}
 	/*
 	 * Queue Hang detection, we know there's
 	 * work outstanding or the first return
 	 * would have been taken, so increment busy
 	 * if nothing managed to get cleaned, then
 	 * in local_timer it will be checked and
 	 * marked as HUNG if it exceeds a MAX attempt.
 	 */
 	if ((processed == 0) && (txr->busy != IXGBE_QUEUE_HUNG))
 		++txr->busy;
 	/*
 	 * If anything gets cleaned we reset state to 1,
 	 * note this will turn off HUNG if its set.
 	 */
 	if (processed)
 		txr->busy = 1;
 	if (txr->tx_avail == txr->num_desc)
 		txr->busy = 0;
 	return ((limit > 0) ? false : true);
 } /* ixgbe_txeof */
 #ifdef RSC
 /************************************************************************
  * ixgbe_rsc_count
+ *
  *   Used to detect a descriptor that has been merged by Hardware RSC.
  ************************************************************************/
 static inline u32
 ixgbe_rsc_count(union ixgbe_adv_rx_desc *rx)
+{
 	return (le32toh(rx->wb.lower.lo_dword.data) &
 	    IXGBE_RXDADV_RSCCNT_MASK) >> IXGBE_RXDADV_RSCCNT_SHIFT;
 } /* ixgbe_rsc_count */
 /************************************************************************
 @@ -1314,26 +1328,27 @@ ixgbe_setup_hw_rsc(struct rx_ring *rxr)
 	IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(rxr->me), rscctrl);
 	/* Enable TCP header recognition */
 	IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0),
 	    (IXGBE_READ_REG(hw, IXGBE_PSRTYPE(0)) | IXGBE_PSRTYPE_TCPHDR));
 	/* Disable RSC for ACK packets */
 	IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
 	    (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
 	rxr->hw_rsc = TRUE;
 } /* ixgbe_setup_hw_rsc */
 #endif
 /************************************************************************
  * ixgbe_refresh_mbufs
+ *
  *   Refresh mbuf buffers for RX descriptor rings
  *    - now keeps its own state so discards due to resource
  *      exhaustion are unnecessary, if an mbuf cannot be obtained
  *      it just returns, keeping its placeholder, thus it can simply
  *      be recalled to try again.
  ************************************************************************/
 static void
 ixgbe_refresh_mbufs(struct rx_ring *rxr, int limit)
+{
 @@ -1408,27 +1423,27 @@ update:
  *   rx_buffer per received packet, the maximum number of rx_buffer's
  *   that we'll need is equal to the number of receive descriptors
  *   that we've allocated.
  ************************************************************************/
 static int
 ixgbe_allocate_receive_buffers(struct rx_ring *rxr)
+{
 	struct ixgbe_softc  *sc = rxr->sc;
 	device_t            dev = sc->dev;
 	struct ixgbe_rx_buf *rxbuf;
 	int                 bsize, error;
 	bsize = sizeof(struct ixgbe_rx_buf) * rxr->num_desc;
-	rxr->rx_buffers = malloc(bsize, M_DEVBUF, M_WAITOK | M_ZERO);
+	rxr->rx_buffers = kmem_zalloc(bsize, KM_SLEEP);
 	error = ixgbe_dma_tag_create(
 	         /*      parent */ sc->osdep.dmat,
 	         /*   alignment */ 1,
 	         /*      bounds */ 0,
 	         /*     maxsize */ MJUM16BYTES,
 	         /*   nsegments */ 1,
 	         /*  maxsegsize */ MJUM16BYTES,
 	         /*       flags */ 0,
 	                           &rxr->ptag);
 	if (error != 0) {
 		aprint_error_dev(dev, "Unable to create RX DMA tag\n");
 		goto fail;
 @@ -1486,58 +1501,58 @@ ixgbe_setup_receive_ring(struct rx_ring
 	sc = rxr->sc;
 #ifdef LRO
 	ifp = sc->ifp;
 #endif /* LRO */
 	/* Clear the ring contents */
 	IXGBE_RX_LOCK(rxr);
 #ifdef DEV_NETMAP
 	if (sc->feat_en & IXGBE_FEATURE_NETMAP)
 		slot = netmap_reset(na, NR_RX, rxr->me, 0);
 #endif /* DEV_NETMAP */
-	rsize = roundup2(sc->num_rx_desc *
+	rsize = sc->num_rx_desc * sizeof(union ixgbe_adv_rx_desc);
-	    sizeof(union ixgbe_adv_rx_desc), DBA_ALIGN);
+	KASSERT((rsize % DBA_ALIGN) == 0);
 	bzero((void *)rxr->rx_base, rsize);
 	/* Cache the size */
 	rxr->mbuf_sz = sc->rx_mbuf_sz;
 	/* Free current RX buffer structs and their mbufs */
 	ixgbe_free_receive_ring(rxr);
 	/* Now replenish the mbufs */
-	for (int j = 0; j != rxr->num_desc; ++j) {
+	for (int i = 0; i < rxr->num_desc; i++) {
 		struct mbuf *mp;
-		rxbuf = &rxr->rx_buffers[j];
+		rxbuf = &rxr->rx_buffers[i];
 #ifdef DEV_NETMAP
 		/*
 		 * In netmap mode, fill the map and set the buffer
 		 * address in the NIC ring, considering the offset
 		 * between the netmap and NIC rings (see comment in
 		 * ixgbe_setup_transmit_ring() ). No need to allocate
 		 * an mbuf, so end the block with a continue;
 		 */
 		if ((sc->feat_en & IXGBE_FEATURE_NETMAP) && slot) {
-			int sj = netmap_idx_n2k(na->rx_rings[rxr->me], j);
+			int sj = netmap_idx_n2k(na->rx_rings[rxr->me], i);
 			uint64_t paddr;
 			void *addr;
 			addr = PNMB(na, slot + sj, &paddr);
 			netmap_load_map(na, rxr->ptag, rxbuf->pmap, addr);
 			/* Update descriptor and the cached value */
-			rxr->rx_base[j].read.pkt_addr = htole64(paddr);
+			rxr->rx_base[i].read.pkt_addr = htole64(paddr);
 			rxbuf->addr = htole64(paddr);
 			continue;
+		}
 #endif /* DEV_NETMAP */
 		rxbuf->flags = 0;
 		rxbuf->buf = ixgbe_getcl();
 		if (rxbuf->buf == NULL) {
 			IXGBE_EVC_ADD(&rxr->no_mbuf, 1);
 			error = ENOBUFS;
 			goto fail;
+		}
 		mp = rxbuf->buf;
 @@ -1549,55 +1564,62 @@ ixgbe_setup_receive_ring(struct rx_ring
 		if (error != 0) {
 			/*
 			 * Clear this entry for later cleanup in
 			 * ixgbe_discard() which is called via
 			 * ixgbe_free_receive_ring().
 			 */
 			m_freem(mp);
 			rxbuf->buf = NULL;
 			goto fail;
+		}
 		bus_dmamap_sync(rxr->ptag->dt_dmat, rxbuf->pmap,
 , mp->m_pkthdr.len, BUS_DMASYNC_PREREAD);
 		/* Update the descriptor and the cached value */
-		rxr->rx_base[j].read.pkt_addr =
+		rxr->rx_base[i].read.pkt_addr =
 		    htole64(rxbuf->pmap->dm_segs[0].ds_addr);
 		rxbuf->addr = htole64(rxbuf->pmap->dm_segs[0].ds_addr);
+	}
 	/* Setup our descriptor indices */
 	rxr->next_to_check = 0;
 	rxr->next_to_refresh = sc->num_rx_desc - 1; /* Fully allocated */
 #ifdef LRO
 	rxr->lro_enabled = FALSE;
 #endif
 	rxr->discard_multidesc = false;
 	IXGBE_EVC_STORE(&rxr->rx_copies, 0);
 #if 0 /* NetBSD */
 	IXGBE_EVC_STORE(&rxr->rx_bytes, 0);
 #if 1	/* Fix inconsistency */
 	IXGBE_EVC_STORE(&rxr->rx_packets, 0);
 #endif
 #endif
 	rxr->vtag_strip = FALSE;
 	ixgbe_dmamap_sync(rxr->rxdma.dma_tag, rxr->rxdma.dma_map,
 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 	/*
 	 * Now set up the LRO interface
 	 */
 #ifdef RSC
 	if (ixgbe_rsc_enable)
 		ixgbe_setup_hw_rsc(rxr);
 #endif
 #ifdef LRO
-	else if (ifp->if_capenable & IFCAP_LRO) {
+#ifdef RSC
 	else
 #endif
 	if (ifp->if_capenable & IFCAP_LRO) {
 		device_t dev = sc->dev;
 		int err = tcp_lro_init(lro);
 		if (err) {
 			device_printf(dev, "LRO Initialization failed!\n");
 			goto fail;
+		}
 		INIT_DEBUGOUT("RX Soft LRO Initialized\n");
 		rxr->lro_enabled = TRUE;
 		lro->ifp = sc->ifp;
+	}
 #endif /* LRO */
 	IXGBE_RX_UNLOCK(rxr);
 @@ -1654,54 +1676,55 @@ ixgbe_free_receive_structures(struct ixg
 	INIT_DEBUGOUT("ixgbe_free_receive_structures: begin");
 	for (int i = 0; i < sc->num_queues; i++, rxr++) {
 		ixgbe_free_receive_buffers(rxr);
 #ifdef LRO
 		/* Free LRO memory */
 		tcp_lro_free(&rxr->lro);
 #endif /* LRO */
 		/* Free the ring memory as well */
 		ixgbe_dma_free(sc, &rxr->rxdma);
 		IXGBE_RX_LOCK_DESTROY(rxr);
+	}
-	free(sc->rx_rings, M_DEVBUF);
+	kmem_free(sc->rx_rings, sizeof(struct rx_ring) * sc->num_queues);
 } /* ixgbe_free_receive_structures */
 /************************************************************************
  * ixgbe_free_receive_buffers - Free receive ring data structures
  ************************************************************************/
 static void
 ixgbe_free_receive_buffers(struct rx_ring *rxr)
+{
 	struct ixgbe_softc  *sc = rxr->sc;
 	struct ixgbe_rx_buf *rxbuf;
 	INIT_DEBUGOUT("ixgbe_free_receive_buffers: begin");
 	/* Cleanup any existing buffers */
 	if (rxr->rx_buffers != NULL) {
 		for (int i = 0; i < sc->num_rx_desc; i++) {
 			rxbuf = &rxr->rx_buffers[i];
 			ixgbe_rx_discard(rxr, i);
 			if (rxbuf->pmap != NULL) {
 				ixgbe_dmamap_destroy(rxr->ptag, rxbuf->pmap);
 				rxbuf->pmap = NULL;
+			}
+		}
 		if (rxr->rx_buffers != NULL) {
-			free(rxr->rx_buffers, M_DEVBUF);
+			kmem_free(rxr->rx_buffers,
 			    sizeof(struct ixgbe_rx_buf) * rxr->num_desc);
 			rxr->rx_buffers = NULL;
+		}
+	}
 	if (rxr->ptag != NULL) {
 		ixgbe_dma_tag_destroy(rxr->ptag);
 		rxr->ptag = NULL;
+	}
 	return;
 } /* ixgbe_free_receive_buffers */
 /************************************************************************
 @@ -1844,27 +1867,30 @@ ixgbe_rxeof(struct ix_queue *que)
 	    sizeof(union ixgbe_adv_rx_desc) * numdesc,
 	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
 	/*
 	 * The max number of loop is rx_process_limit. If discard_multidesc is
 	 * true, continue processing to not to send broken packet to the upper
 	 * layer.
 	 */
 	for (i = rxr->next_to_check;
 	     (loopcount < limit) || (discard_multidesc == true);) {
 		struct mbuf *sendmp, *mp;
 		struct mbuf *newmp;
-		u32         rsc, ptype;
+#ifdef RSC
 		u32         rsc;
 #endif
 		u32         ptype;
 		u16         len;
 		u16         vtag = 0;
 		bool        eop;
 		bool        discard = false;
 		if (wraparound) {
 			/* Sync the last half. */
 			KASSERT(syncremain != 0);
 			numdesc = syncremain;
 			wraparound = false;
 		} else if (__predict_false(loopcount >= limit)) {
 			KASSERT(discard_multidesc == true);
 			numdesc = 1;
 @@ -1879,27 +1905,29 @@ ixgbe_rxeof(struct ix_queue *que)
 		cur = &rxr->rx_base[i];
 		staterr = le32toh(cur->wb.upper.status_error);
 #ifdef RSS
 		pkt_info = le16toh(cur->wb.lower.lo_dword.hs_rss.pkt_info);
 #endif
 		if ((staterr & IXGBE_RXD_STAT_DD) == 0)
 			break;
 		loopcount++;
 		sendmp = newmp = NULL;
 		nbuf = NULL;
 #ifdef RSC
 		rsc = 0;
 #endif
 		cur->wb.upper.status_error = 0;
 		rbuf = &rxr->rx_buffers[i];
 		mp = rbuf->buf;
 		len = le16toh(cur->wb.upper.length);
 		ptype = le32toh(cur->wb.lower.lo_dword.data) &
 		    IXGBE_RXDADV_PKTTYPE_MASK;
 		eop = ((staterr & IXGBE_RXD_STAT_EOP) != 0);
 		/* Make sure bad packets are discarded */
 		if (eop && (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) != 0) {
 #if __FreeBSD_version >= 1100036
 			if (sc->feat_en & IXGBE_FEATURE_VF)
 @@ -1965,34 +1993,37 @@ ixgbe_rxeof(struct ix_queue *que)
 		 * descriptors, rather the next descriptor
 		 * is indicated in bits of the descriptor.
 		 * This also means that we might process
 		 * more than one packet at a time, something
 		 * that has never been true before, it
 		 * required eliminating global chain pointers
 		 * in favor of what we are doing here.  -jfv
 		 */
 		if (!eop) {
 			/*
 			 * Figure out the next descriptor
 			 * of this frame.
 			 */
 #ifdef RSC
 			if (rxr->hw_rsc == TRUE) {
 				rsc = ixgbe_rsc_count(cur);
 				rxr->rsc_num += (rsc - 1);
+			}
 			if (rsc) { /* Get hardware index */
 				nextp = ((staterr & IXGBE_RXDADV_NEXTP_MASK) >>
 				    IXGBE_RXDADV_NEXTP_SHIFT);
-			} else { /* Just sequential */
+			} else
 #endif
 			{ /* Just sequential */
 				nextp = i + 1;
 				if (nextp == sc->num_rx_desc)
 					nextp = 0;
+			}
 			nbuf = &rxr->rx_buffers[nextp];
 			prefetch(nbuf);
+		}
 		/*
 		 * Rather than using the fmp/lmp global pointers
 		 * we now keep the head of a packet chain in the
 		 * buffer struct and pass this along from one
 		 * descriptor to the next, until we get EOP.
 		 */
 @@ -2322,40 +2353,40 @@ ixgbe_dma_free(struct ixgbe_softc *sc, s
  *   the descriptors associated with each, called only once at attach.
  ************************************************************************/
 int
 ixgbe_allocate_queues(struct ixgbe_softc *sc)
+{
 	device_t	dev = sc->dev;
 	struct ix_queue	*que;
 	struct tx_ring	*txr;
 	struct rx_ring	*rxr;
 	int             rsize, tsize, error = IXGBE_SUCCESS;
 	int             txconf = 0, rxconf = 0;
 	/* First, allocate the top level queue structs */
-	sc->queues = (struct ix_queue *)malloc(sizeof(struct ix_queue) *
+	sc->queues = kmem_zalloc(sizeof(struct ix_queue) * sc->num_queues,
-	    sc->num_queues, M_DEVBUF, M_WAITOK | M_ZERO);
+	    KM_SLEEP);
 	/* Second, allocate the TX ring struct memory */
-	sc->tx_rings = malloc(sizeof(struct tx_ring) *
+	sc->tx_rings = kmem_zalloc(sizeof(struct tx_ring) * sc->num_queues,
-	    sc->num_queues, M_DEVBUF, M_WAITOK | M_ZERO);
+	    KM_SLEEP);
 	/* Third, allocate the RX ring */
-	sc->rx_rings = (struct rx_ring *)malloc(sizeof(struct rx_ring) *
+	sc->rx_rings = kmem_zalloc(sizeof(struct rx_ring) * sc->num_queues,
-	    sc->num_queues, M_DEVBUF, M_WAITOK | M_ZERO);
+	    KM_SLEEP);
 	/* For the ring itself */
-	tsize = roundup2(sc->num_tx_desc * sizeof(union ixgbe_adv_tx_desc),
+	tsize = sc->num_tx_desc * sizeof(union ixgbe_adv_tx_desc);
-	    DBA_ALIGN);
+	KASSERT((tsize % DBA_ALIGN) == 0);
 	/*
 	 * Now set up the TX queues, txconf is needed to handle the
 	 * possibility that things fail midcourse and we need to
 	 * undo memory gracefully
 	 */
 	for (int i = 0; i < sc->num_queues; i++, txconf++) {
 		/* Set up some basics */
 		txr = &sc->tx_rings[i];
 		txr->sc = sc;
 		txr->txr_interq = NULL;
 		/* In case SR-IOV is enabled, align the index properly */
 #ifdef PCI_IOV
 @@ -2391,28 +2422,28 @@ ixgbe_allocate_queues(struct ixgbe_softc
 			txr->txr_interq = pcq_create(IXGBE_BR_SIZE, KM_SLEEP);
 			if (txr->txr_interq == NULL) {
 				aprint_error_dev(dev,
 				    "Critical Failure setting up buf ring\n");
 				error = ENOMEM;
 				goto err_tx_desc;
+			}
+		}
+	}
 	/*
 	 * Next the RX queues...
 	 */
-	rsize = roundup2(sc->num_rx_desc * sizeof(union ixgbe_adv_rx_desc),
+	rsize = sc->num_rx_desc * sizeof(union ixgbe_adv_rx_desc);
-	    DBA_ALIGN);
+	KASSERT((rsize % DBA_ALIGN) == 0);
 	for (int i = 0; i < sc->num_queues; i++, rxconf++) {
 		rxr = &sc->rx_rings[i];
 		/* Set up some basics */
 		rxr->sc = sc;
 #ifdef PCI_IOV
 		/* In case SR-IOV is enabled, align the index properly */
 		rxr->me = ixgbe_vf_que_index(sc->iov_mode, sc->pool,
 		    i);
 #else
 		rxr->me = i;
 #endif
 		rxr->num_desc = sc->num_rx_desc;
 @@ -2450,39 +2481,39 @@ ixgbe_allocate_queues(struct ixgbe_softc
 		mutex_init(&que->dc_mtx, MUTEX_DEFAULT, IPL_NET);
 		que->disabled_count = 0;
+	}
 	return (0);
 err_rx_desc:
 	for (rxr = sc->rx_rings; rxconf > 0; rxr++, rxconf--)
 		ixgbe_dma_free(sc, &rxr->rxdma);
 err_tx_desc:
 	for (txr = sc->tx_rings; txconf > 0; txr++, txconf--)
 		ixgbe_dma_free(sc, &txr->txdma);
-	free(sc->rx_rings, M_DEVBUF);
+	kmem_free(sc->rx_rings, sizeof(struct rx_ring) * sc->num_queues);
-	free(sc->tx_rings, M_DEVBUF);
+	kmem_free(sc->tx_rings, sizeof(struct tx_ring) * sc->num_queues);
-	free(sc->queues, M_DEVBUF);
+	kmem_free(sc->queues, sizeof(struct ix_queue) * sc->num_queues);
 	return (error);
 } /* ixgbe_allocate_queues */
 /************************************************************************
  * ixgbe_free_queues
+ *
  *   Free descriptors for the transmit and receive rings, and then
  *   the memory associated with each.
  ************************************************************************/
 void
 ixgbe_free_queues(struct ixgbe_softc *sc)
+{
 	struct ix_queue *que;
 	int i;
 	ixgbe_free_transmit_structures(sc);
 	ixgbe_free_receive_structures(sc);
 	for (i = 0; i < sc->num_queues; i++) {
 		que = &sc->queues[i];
 		mutex_destroy(&que->dc_mtx);
+	}
-	free(sc->queues, M_DEVBUF);
+	kmem_free(sc->queues, sizeof(struct ix_queue) * sc->num_queues);
 } /* ixgbe_free_queues */

 @@ -1,14 +1,14 @@
-/* $NetBSD: ixv.c,v 1.183.4.5 2023/11/03 10:10:49 martin Exp $ */
+/* $NetBSD: ixv.c,v 1.183.4.6 2024/02/03 11:58:53 martin Exp $ */
 /******************************************************************************
   Copyright (c) 2001-2017, Intel Corporation
   All rights reserved.
   Redistribution and use in source and binary forms, with or without
   modification, are permitted provided that the following conditions are met:
 . Redistributions of source code must retain the above copyright notice,
       this list of conditions and the following disclaimer.
 . Redistributions in binary form must reproduce the above copyright
 @@ -25,27 +25,27 @@
   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE.
 ******************************************************************************/
 /*$FreeBSD: head/sys/dev/ixgbe/if_ixv.c 331224 2018-03-19 20:55:05Z erj $*/
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: ixv.c,v 1.183.4.5 2023/11/03 10:10:49 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: ixv.c,v 1.183.4.6 2024/02/03 11:58:53 martin Exp $");
 #ifdef _KERNEL_OPT
 #include "opt_inet.h"
 #include "opt_inet6.h"
 #include "opt_net_mpsafe.h"
 #endif
 #include "ixgbe.h"
 /************************************************************************
  * Driver version
  ************************************************************************/
 static const char ixv_driver_version[] = "2.0.1-k";
 @@ -820,27 +820,26 @@ ixv_init_locked(struct ixgbe_softc *sc)
 	/* Start watchdog */
 	callout_reset(&sc->timer, hz, ixv_local_timer, sc);
 	atomic_store_relaxed(&sc->timer_pending, 0);
 	/* OK to schedule workqueues. */
 	sc->schedule_wqs_ok = true;
 	/* Update saved flags. See ixgbe_ifflags_cb() */
 	sc->if_flags = ifp->if_flags;
 	sc->ec_capenable = sc->osdep.ec.ec_capenable;
 	/* Inform the stack we're ready */
 	ifp->if_flags |= IFF_RUNNING;
 	ifp->if_flags &= ~IFF_OACTIVE;
 	/* And now turn on interrupts */
 	ixv_enable_intr(sc);
 	return;
 } /* ixv_init_locked */
 /************************************************************************
  * ixv_enable_queue
  ************************************************************************/
 static inline void
 ixv_enable_queue(struct ixgbe_softc *sc, u32 vector)
+{
 @@ -1485,52 +1484,52 @@ ixv_stop_locked(void *arg)
+{
 	struct ifnet	*ifp;
 	struct ixgbe_softc *sc = arg;
 	struct ixgbe_hw *hw = &sc->hw;
 	ifp = sc->ifp;
 	KASSERT(mutex_owned(&sc->core_mtx));
 	INIT_DEBUGOUT("ixv_stop_locked: begin\n");
 	ixv_disable_intr(sc);
 	/* Tell the stack that the interface is no longer active */
-	ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
+	ifp->if_flags &= ~IFF_RUNNING;
 	hw->mac.ops.reset_hw(hw);
 	sc->hw.adapter_stopped = FALSE;
 	hw->mac.ops.stop_adapter(hw);
 	callout_stop(&sc->timer);
 	/* Don't schedule workqueues. */
 	sc->schedule_wqs_ok = false;
 	/* reprogram the RAR[0] in case user changed it. */
 	hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
 	return;
 } /* ixv_stop_locked */
 /************************************************************************
  * ixv_allocate_pci_resources
  ************************************************************************/
 static int
 ixv_allocate_pci_resources(struct ixgbe_softc *sc,
     const struct pci_attach_args *pa)
+{
-	pcireg_t	memtype, csr;
+	pcireg_t memtype, csr;
-	device_t	dev = sc->dev;
+	device_t dev = sc->dev;
 	bus_addr_t addr;
 	int flags;
 	memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, PCI_BAR(0));
 	switch (memtype) {
 	case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT:
 	case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT:
 		sc->osdep.mem_bus_space_tag = pa->pa_memt;
 		if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, PCI_BAR(0),
 		      memtype, &addr, &sc->osdep.mem_size, &flags) != 0)
 			goto map_err;
 		if ((flags & BUS_SPACE_MAP_PREFETCHABLE) != 0) {
 			aprint_normal_dev(dev, "clearing prefetchable bit\n");
 @@ -1739,26 +1738,27 @@ static void
 ixv_initialize_transmit_units(struct ixgbe_softc *sc)
+{
 	struct tx_ring	*txr = sc->tx_rings;
 	struct ixgbe_hw	*hw = &sc->hw;
 	int i;
 	for (i = 0; i < sc->num_queues; i++, txr++) {
 		u64 tdba = txr->txdma.dma_paddr;
 		u32 txctrl, txdctl;
 		int j = txr->me;
 		/* Set WTHRESH to 8, burst writeback */
 		txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(j));
 		txdctl &= ~IXGBE_TXDCTL_WTHRESH_MASK;
 		txdctl |= IXGBE_TX_WTHRESH << IXGBE_TXDCTL_WTHRESH_SHIFT;
 		IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(j), txdctl);
 		/* Set the HW Tx Head and Tail indices */
 		IXGBE_WRITE_REG(&sc->hw, IXGBE_VFTDH(j), 0);
 		IXGBE_WRITE_REG(&sc->hw, IXGBE_VFTDT(j), 0);
 		/* Set Tx Tail register */
 		txr->tail = IXGBE_VFTDT(j);
 		txr->txr_no_space = false;
 		/* Set Ring parameters */

 @@ -1,14 +1,14 @@
-/* $NetBSD: ixgbe.h,v 1.86.4.4 2023/10/18 11:53:22 martin Exp $ */
+/* $NetBSD: ixgbe.h,v 1.86.4.5 2024/02/03 11:58:53 martin Exp $ */
 /******************************************************************************
   SPDX-License-Identifier: BSD-3-Clause
   Copyright (c) 2001-2017, Intel Corporation
   All rights reserved.
   Redistribution and use in source and binary forms, with or without
   modification, are permitted provided that the following conditions are met:
 . Redistributions of source code must retain the above copyright notice,
       this list of conditions and the following disclaimer.
 @@ -315,27 +315,27 @@ struct ixgbe_dma_alloc {
 struct ixgbe_mc_addr {
 	u8  addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
 	u32 vmdq;
 };
 /*
  * Driver queue struct: this is the interrupt container
  *                      for the associated tx and rx ring.
  */
 struct ix_queue {
 	struct ixgbe_softc *sc;
 	u32              msix;           /* This queue's MSI-X vector */
 	u32              eitr_setting;
-	u32              me;
+	u8               me;
 	struct resource  *res;
 	int              busy;
 	struct tx_ring   *txr;
 	struct rx_ring   *rxr;
 	struct work      wq_cookie;
 	void             *que_si;
 	/* Per queue event conters */
 	struct evcnt     irqs;		/* Hardware interrupt */
 	struct evcnt     handleq;	/* software_interrupt */
 	struct evcnt     req;		/* deferred */
 	char             namebuf[32];	/* Name for sysctl */
 	char             evnamebuf[32];	/* Name for evcnt */
 @@ -347,108 +347,111 @@ struct ix_queue {
 	 *     > 0 : this queue is disabled
 	 *           the value is ixgbe_disable_queue() called count
 	 */
 	int              disabled_count;
 	bool             txrx_use_workqueue;
 };
 /*
  * The transmit ring, one per queue
  */
 struct tx_ring {
 	struct ixgbe_softc	*sc;
 	kmutex_t		tx_mtx;
-	u32			me;
+	u8			me;
 	u32			tail;
 	int			busy;
 	union ixgbe_adv_tx_desc	*tx_base;
 	struct ixgbe_tx_buf	*tx_buffers;
 	struct ixgbe_dma_alloc	txdma;
 	volatile u16		tx_avail;
 	u16			next_avail_desc;
 	u16			next_to_clean;
 	u16			num_desc;
 	ixgbe_dma_tag_t		*txtag;
 #if 0
 	char			mtx_name[16]; /* NetBSD has no mutex name */
 #endif
 	pcq_t			*txr_interq;
 	struct work		wq_cookie;
 	void			*txr_si;
 	bool			txr_no_space; /* Like IFF_OACTIVE */
 #ifdef IXGBE_FDIR
 	/* Flow Director */
 	u16			atr_sample;
 	u16			atr_count;
 #endif
 	u64			bytes;  /* Used for AIM */
 	u64			packets;
 	/* Soft Stats */
 	struct evcnt		total_packets;
 	struct evcnt		pcq_drops;
 	struct evcnt		no_desc_avail;
 	struct evcnt		tso_tx;
 	/* Per queue conters.  The adapter total is in struct adapter */
 	u64              q_efbig_tx_dma_setup;
 	u64              q_mbuf_defrag_failed;
 	u64              q_efbig2_tx_dma_setup;
 	u64              q_einval_tx_dma_setup;
 	u64              q_other_tx_dma_setup;
 	u64              q_eagain_tx_dma_setup;
 	u64              q_enomem_tx_dma_setup;
 	u64              q_tso_err;
 };
 /*
  * The Receive ring, one per rx queue
  */
 struct rx_ring {
 	struct ixgbe_softc	*sc;
 	kmutex_t		rx_mtx;
-	u32			me;
+	u8			me;
 	u32			tail;
 	union ixgbe_adv_rx_desc	*rx_base;
 	struct ixgbe_dma_alloc	rxdma;
 #ifdef LRO
 	struct lro_ctrl		lro;
 #endif /* LRO */
 	bool			lro_enabled;
 #endif /* LRO */
 #ifdef RSC
 	bool			hw_rsc;
 #endif
 	bool			vtag_strip;
 	bool			discard_multidesc;
 	u16			next_to_refresh;
 	u16			next_to_check;
 	u16			num_desc;
 	u16			mbuf_sz;
 #if 0
 	char			mtx_name[16]; /* NetBSD has no mutex name */
 #endif
 	struct ixgbe_rx_buf	*rx_buffers;
 	ixgbe_dma_tag_t		*ptag;
 	u64			bytes; /* Used for AIM calc */
 	u64			packets;
 	/* Soft stats */
 	struct evcnt		rx_copies;
 	struct evcnt		rx_packets;
 	struct evcnt		rx_bytes;
 	struct evcnt		rx_discarded;
 	struct evcnt		no_mbuf;
 #ifdef RSC
 	u64			rsc_num;
 #endif
 	/* Flow Director */
 	u64			flm;
 };
 struct ixgbe_vf {
 	u_int    pool;
 	u_int    rar_index;
 	u_int    max_frame_size;
 	uint32_t flags;
 	uint8_t  ether_addr[ETHER_ADDR_LEN];
 	uint16_t mc_hash[IXGBE_MAX_VF_MC];
 	uint16_t num_mc_hashes;
 	uint16_t default_vlan;
 	uint16_t vlan_tag;
 	uint16_t api_ver;

 @@ -1,14 +1,14 @@
-/* $NetBSD: ixgbe_type.h,v 1.55.4.5 2023/10/18 11:53:22 martin Exp $ */
+/* $NetBSD: ixgbe_type.h,v 1.55.4.6 2024/02/03 11:58:53 martin Exp $ */
 /******************************************************************************
   SPDX-License-Identifier: BSD-3-Clause
   Copyright (c) 2001-2020, Intel Corporation
   All rights reserved.
   Redistribution and use in source and binary forms, with or without
   modification, are permitted provided that the following conditions are met:
 . Redistributions of source code must retain the above copyright notice,
       this list of conditions and the following disclaimer.
 @@ -2615,26 +2615,27 @@ enum {
 #define IXGBE_RFCTL_NFS_VER_SHIFT	8
 #define IXGBE_RFCTL_NFS_VER_2		0
 #define IXGBE_RFCTL_NFS_VER_3		1
 #define IXGBE_RFCTL_NFS_VER_4		2
 #define IXGBE_RFCTL_IPV6_DIS		0x00000400
 #define IXGBE_RFCTL_IPV6_XSUM_DIS	0x00000800
 #define IXGBE_RFCTL_IPFRSP_DIS		0x00004000
 #define IXGBE_RFCTL_IPV6_EX_DIS		0x00010000
 #define IXGBE_RFCTL_NEW_IPV6_EXT_DIS	0x00020000
 /* Transmit Config masks */
 #define IXGBE_TXDCTL_ENABLE		0x02000000 /* Ena specific Tx Queue */
 #define IXGBE_TXDCTL_SWFLSH		0x04000000 /* Tx Desc. wr-bk flushing */
 #define IXGBE_TXDCTL_WTHRESH_MASK	0x007f0000
 #define IXGBE_TXDCTL_WTHRESH_SHIFT	16 /* shift to WTHRESH bits */
 /* Enable short packet padding to 64 bytes */
 #define IXGBE_TX_PAD_ENABLE		0x00000400
 #define IXGBE_JUMBO_FRAME_ENABLE	0x00000004  /* Allow jumbo frames */
 /* This allows for 16K packets + 4k for vlan */
 #define IXGBE_MAX_FRAME_SZ		0x40040000
 #define IXGBE_TDWBAL_HEAD_WB_ENABLE	0x1 /* Tx head write-back enable */
 #define IXGBE_TDWBAL_SEQNUM_WB_ENABLE	0x2 /* Tx seq# write-back enable */
 /* Receive Config masks */
 #define IXGBE_RXCTRL_RXEN		0x00000001 /* Enable Receiver */
 #define IXGBE_RXCTRL_DMBYPS		0x00000002 /* Desc Monitor Bypass */