Sun Feb 25 18:27:54 2024 UTC (111d)
s/asynchronious/asynchronous/ in comment.


(andvar)
diff -r1.89 -r1.90 src/sys/arch/x86/x86/lapic.c
cvs diff -r1.89 -r1.90 src/sys/arch/x86/x86/lapic.c (expand / switch to context diff)
--- src/sys/arch/x86/x86/lapic.c 2022/09/07 00:40:19 1.89
+++ src/sys/arch/x86/x86/lapic.c 2024/02/25 18:27:54 1.90
@@ -1,4 +1,4 @@
-/*	$NetBSD: lapic.c,v 1.89 2022/09/07 00:40:19 knakahara Exp $	*/
+/*	$NetBSD: lapic.c,v 1.90 2024/02/25 18:27:54 andvar Exp $	*/
 
 /*-
  * Copyright (c) 2000, 2008, 2020 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: lapic.c,v 1.89 2022/09/07 00:40:19 knakahara Exp $");
+__KERNEL_RCSID(0, "$NetBSD: lapic.c,v 1.90 2024/02/25 18:27:54 andvar Exp $");
 
 #include "acpica.h"
 #include "ioapic.h"
@@ -534,7 +534,7 @@
 	 *
 	 * If the current tick is almost the Initial Counter, explicitly
 	 * check for the pending interrupt bit as the interrupt delivery
-	 * could be asynchronious and compensate as well.
+	 * could be asynchronous and compensate as well.
 	 *
 	 * This can't be done without splhigh() as the calling code might
 	 * have masked the clockinterrupt already.