Mon Feb 26 20:20:01 2024 UTC (86d)
s/Transmi /Transmit / in comments.


(andvar)
diff -r1.10 -r1.11 src/sys/arch/powerpc/include/booke/etsecreg.h
diff -r1.11 -r1.12 src/sys/dev/mii/makphyreg.h
cvs diff -r1.10 -r1.11 src/sys/arch/powerpc/include/booke/etsecreg.h (expand / switch to unified diff)

--- src/sys/arch/powerpc/include/booke/etsecreg.h 2022/05/11 14:58:00 1.10
+++ src/sys/arch/powerpc/include/booke/etsecreg.h 2024/02/26 20:20:01 1.11
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: etsecreg.h,v 1.10 2022/05/11 14:58:00 andvar Exp $ */ 1/* $NetBSD: etsecreg.h,v 1.11 2024/02/26 20:20:01 andvar Exp $ */
2/*- 2/*-
3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc. 3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc.
4 * All rights reserved. 4 * All rights reserved.
5 * 5 *
6 * This code is derived from software contributed to The NetBSD Foundation 6 * This code is derived from software contributed to The NetBSD Foundation
7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects 7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects
8 * Agency and which was developed by Matt Thomas of 3am Software Foundry. 8 * Agency and which was developed by Matt Thomas of 3am Software Foundry.
9 * 9 *
10 * This material is based upon work supported by the Defense Advanced Research 10 * This material is based upon work supported by the Defense Advanced Research
11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under 11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under
12 * Contract No. N66001-09-C-2073. 12 * Contract No. N66001-09-C-2073.
13 * Approved for Public Release, Distribution Unlimited 13 * Approved for Public Release, Distribution Unlimited
14 * 14 *
@@ -164,27 +164,27 @@ struct rxfcb { @@ -164,27 +164,27 @@ struct rxfcb {
164#define ECNTRL_RPM __PPCBIT(27) /* Reduced Pin Mode */ 164#define ECNTRL_RPM __PPCBIT(27) /* Reduced Pin Mode */
165#define ECNTRL_R100M __PPCBIT(28) /* RGMII/RMII 100 Mode */ 165#define ECNTRL_R100M __PPCBIT(28) /* RGMII/RMII 100 Mode */
166#define ECNTRL_RMM __PPCBIT(29) /* Reduced Pin Mode for 10/100 */ 166#define ECNTRL_RMM __PPCBIT(29) /* Reduced Pin Mode for 10/100 */
167#define ECNTRL_SGMIIM __PPCBIT(30) /* SGMII Interface Mode */ 167#define ECNTRL_SGMIIM __PPCBIT(30) /* SGMII Interface Mode */
168#define ECNTRL_DEFAULT ECNTRL_STEN 168#define ECNTRL_DEFAULT ECNTRL_STEN
169 169
170#define PTV 0x028 /* Pause time value register */ 170#define PTV 0x028 /* Pause time value register */
171#define DMACTRL 0x02c /* DMA control register */ 171#define DMACTRL 0x02c /* DMA control register */
172#define DMACTRL_LE __PPCBIT(16) /* Little Endian Descriptor Mode */ 172#define DMACTRL_LE __PPCBIT(16) /* Little Endian Descriptor Mode */
173#define DMACTRL_TDSEN __PPCBIT(24) /* TX Data Snoop enable */ 173#define DMACTRL_TDSEN __PPCBIT(24) /* TX Data Snoop enable */
174#define DMACTRL_TBDSEN __PPCBIT(25) /* TxBD Data Snoop enable */ 174#define DMACTRL_TBDSEN __PPCBIT(25) /* TxBD Data Snoop enable */
175#define DMACTRL_GRS __PPCBIT(27) /* graceful receive stop */ 175#define DMACTRL_GRS __PPCBIT(27) /* graceful receive stop */
176#define DMACTRL_GTS __PPCBIT(28) /* graceful transmit stop */ 176#define DMACTRL_GTS __PPCBIT(28) /* graceful transmit stop */
177#define DMACTRL_TOD __PPCBIT(29) /* Transmi On Demand for TxBD ring 0 */ 177#define DMACTRL_TOD __PPCBIT(29) /* Transmit On Demand for TxBD ring 0 */
178#define DMACTRL_WWR __PPCBIT(30) /* Write With Response */ 178#define DMACTRL_WWR __PPCBIT(30) /* Write With Response */
179#define DMACTRL_WOP __PPCBIT(31) /* Wait or pool for TxBD ring 0 */ 179#define DMACTRL_WOP __PPCBIT(31) /* Wait or pool for TxBD ring 0 */
180#define DMACTRL_DEFAULT (DMACTRL_WOP|DMACTRL_WWR|DMACTRL_TDSEN|DMACTRL_TBDSEN) 180#define DMACTRL_DEFAULT (DMACTRL_WOP|DMACTRL_WWR|DMACTRL_TDSEN|DMACTRL_TBDSEN)
181 181
182#define TBIPA 0x030 /* TBI phy address register */ 182#define TBIPA 0x030 /* TBI phy address register */
183 183
184/* 0x100-0x2ff eTSEC transmit control/status registers */ 184/* 0x100-0x2ff eTSEC transmit control/status registers */
185 185
186#define TCTRL 0x100 /* Transmit control register */ 186#define TCTRL 0x100 /* Transmit control register */
187#define TCTRL_IPCSEN __PPCBIT(17) /* IP header checksum generation enable */ 187#define TCTRL_IPCSEN __PPCBIT(17) /* IP header checksum generation enable */
188#define TCTRL_TUCSEN __PPCBIT(18) /* TCP/UDP header checksum generation enable */ 188#define TCTRL_TUCSEN __PPCBIT(18) /* TCP/UDP header checksum generation enable */
189#define TCTRL_VLINS __PPCBIT(19) /* VLAN tag insertion */ 189#define TCTRL_VLINS __PPCBIT(19) /* VLAN tag insertion */
190#define TCTRL_THDF __PPCBIT(29) /* Transmit half duplex */ 190#define TCTRL_THDF __PPCBIT(29) /* Transmit half duplex */
cvs diff -r1.11 -r1.12 src/sys/dev/mii/makphyreg.h (expand / switch to unified diff)

--- src/sys/dev/mii/makphyreg.h 2020/08/03 07:25:59 1.11
+++ src/sys/dev/mii/makphyreg.h 2024/02/26 20:20:01 1.12
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: makphyreg.h,v 1.11 2020/08/03 07:25:59 msaitoh Exp $ */ 1/* $NetBSD: makphyreg.h,v 1.12 2024/02/26 20:20:01 andvar Exp $ */
2 2
3/*- 3/*-
4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 4 * Copyright (c) 2001 The NetBSD Foundation, Inc.
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * This code is derived from software contributed to The NetBSD Foundation 7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Jason R. Thorpe. 8 * by Jason R. Thorpe.
9 * 9 *
10 * Redistribution and use in source and binary forms, with or without 10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions 11 * modification, are permitted provided that the following conditions
12 * are met: 12 * are met:
13 * 1. Redistributions of source code must retain the above copyright 13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer. 14 * notice, this list of conditions and the following disclaimer.
@@ -64,27 +64,27 @@ @@ -64,27 +64,27 @@
64/* bit 10 is reserved */ 64/* bit 10 is reserved */
65#define E3016_PSCR_NLPGEN_DIS (1U << 11) /* Disable Linkpulse Generation */ 65#define E3016_PSCR_NLPGEN_DIS (1U << 11) /* Disable Linkpulse Generation */
66#define E3016_PSCR_REG8NXTPG (1U << 12) /* En. Link Partner Next Page R */ 66#define E3016_PSCR_REG8NXTPG (1U << 12) /* En. Link Partner Next Page R */
67#define E3016_PSCR_NLPCHK_DIS (1U << 13) /* Disable NLP check */ 67#define E3016_PSCR_NLPCHK_DIS (1U << 13) /* Disable NLP check */
68#define E3016_PSCR_EN_DETECT (1U << 14) /* Energy Detect */ 68#define E3016_PSCR_EN_DETECT (1U << 14) /* Energy Detect */
69/* bit 15 is reserved */ 69/* bit 15 is reserved */
70 70
71/* 88E1112 page 1 */ 71/* 88E1112 page 1 */
72#define MAKPHY_FSCR 0x10 /* Fiber specific control register */ 72#define MAKPHY_FSCR 0x10 /* Fiber specific control register */
73#define FSCR_XMITTER_DIS 0x0008 /* Transmitter Disable */ 73#define FSCR_XMITTER_DIS 0x0008 /* Transmitter Disable */
74 74
75/* 88E1112 page 2 */ 75/* 88E1112 page 2 */
76#define MAKPHY_MSCR 0x10 /* MAC specific control register */ 76#define MAKPHY_MSCR 0x10 /* MAC specific control register */
77#define MSCR_TX_FIFODEPTH 0xc000 /* Transmi FIFO Depth */ 77#define MSCR_TX_FIFODEPTH 0xc000 /* Transmit FIFO Depth */
78#define MSCR_RX_FIFODEPTH 0x3000 /* Receive FIFO Depth */ 78#define MSCR_RX_FIFODEPTH 0x3000 /* Receive FIFO Depth */
79#define MSCR_AUTOPREF_MASK 0x0c00 /* Autoselect preferred media mask */ 79#define MSCR_AUTOPREF_MASK 0x0c00 /* Autoselect preferred media mask */
80#define MSCR_AUTOPREF_NO 0x0000 /* No preference */ 80#define MSCR_AUTOPREF_NO 0x0000 /* No preference */
81#define MSCR_AUTOPREF_FIBER 0x0400 /* Preferred Fiber */ 81#define MSCR_AUTOPREF_FIBER 0x0400 /* Preferred Fiber */
82#define MSCR_AUTOPREF_COPPER 0x0800 /* Preferred Copper */ 82#define MSCR_AUTOPREF_COPPER 0x0800 /* Preferred Copper */
83#define MSCR_MODE_MASK 0x0380 /* Mode select mask */ 83#define MSCR_MODE_MASK 0x0380 /* Mode select mask */
84#define MSCR_M_100FX 0x0000 /* 100BASE-FX */ 84#define MSCR_M_100FX 0x0000 /* 100BASE-FX */
85#define MSCR_M_COOPER_GBIC 0x0080 /* Copper GBIC */ 85#define MSCR_M_COOPER_GBIC 0x0080 /* Copper GBIC */
86#define MSCR_M_AUTO_COPPER_SGMII 0x0100 /* Auto Copper/SGMII */ 86#define MSCR_M_AUTO_COPPER_SGMII 0x0100 /* Auto Copper/SGMII */
87#define MSCR_M_AUTO_COPPER_1000X 0x0180 /* Auto Copper/1000BASE-X */ 87#define MSCR_M_AUTO_COPPER_1000X 0x0180 /* Auto Copper/1000BASE-X */
88#define MSCR_M_COPPER 0x0280 /* Copper only */ 88#define MSCR_M_COPPER 0x0280 /* Copper only */
89#define MSCR_M_SGMII 0x0300 /* SGMII only */ 89#define MSCR_M_SGMII 0x0300 /* SGMII only */
90#define MSCR_M_1000X 0x0380 /* 1000BASE-X only */ 90#define MSCR_M_1000X 0x0380 /* 1000BASE-X only */