 @@ -1,1473 +1,1473 @@
-/*	$NetBSD: if_wm.c,v 1.508.4.54 2024/02/03 12:04:06 martin Exp $	*/
+/*	$NetBSD: if_wm.c,v 1.508.4.55 2024/02/29 10:46:27 martin Exp $	*/
 /*
  * Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc.
  * All rights reserved.
+ *
  * Written by Jason R. Thorpe for Wasabi Systems, Inc.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  * 3. All advertising materials mentioning features or use of this software
  *    must display the following acknowledgement:
  *	This product includes software developed for the NetBSD Project by
  *	Wasabi Systems, Inc.
  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
  *    or promote products derived from this software without specific prior
  *    written permission.
+ *
  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 /*******************************************************************************
   Copyright (c) 2001-2005, Intel Corporation
   All rights reserved.
   Redistribution and use in source and binary forms, with or without
   modification, are permitted provided that the following conditions are met:
 . Redistributions of source code must retain the above copyright notice,
       this list of conditions and the following disclaimer.
 . Redistributions in binary form must reproduce the above copyright
       notice, this list of conditions and the following disclaimer in the
       documentation and/or other materials provided with the distribution.
 . Neither the name of the Intel Corporation nor the names of its
       contributors may be used to endorse or promote products derived from
       this software without specific prior written permission.
   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE.
 *******************************************************************************/
 /*
  * Device driver for the Intel i8254x family of Gigabit Ethernet chips.
+ *
  * TODO (in order of importance):
+ *
  *	- Check XXX'ed comments
  *	- TX Multi queue improvement (refine queue selection logic)
  *	- Split header buffer for newer descriptors
  *	- EEE (Energy Efficiency Ethernet)
  *	- Virtual Function
  *	- Set LED correctly (based on contents in EEPROM)
  *	- Rework how parameters are loaded from the EEPROM.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.508.4.54 2024/02/03 12:04:06 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.508.4.55 2024/02/29 10:46:27 martin Exp $");
 #ifdef _KERNEL_OPT
 #include "opt_net_mpsafe.h"
 #include "opt_if_wm.h"
 #endif
 #include <sys/param.h>
 #include <sys/callout.h>
 #include <sys/cpu.h>
 #include <sys/device.h>
 #include <sys/errno.h>
 #include <sys/interrupt.h>
 #include <sys/ioctl.h>
 #include <sys/kernel.h>
 #include <sys/kmem.h>
 #include <sys/mbuf.h>
 #include <sys/pcq.h>
 #include <sys/queue.h>
 #include <sys/rndsource.h>
 #include <sys/socket.h>
 #include <sys/sysctl.h>
 #include <sys/syslog.h>
 #include <sys/systm.h>
 #include <sys/workqueue.h>
 #include <net/if.h>
 #include <net/if_dl.h>
 #include <net/if_media.h>
 #include <net/if_ether.h>
 #include <net/bpf.h>
 #include <net/rss_config.h>
 #include <netinet/in.h>			/* XXX for struct ip */
 #include <netinet/in_systm.h>		/* XXX for struct ip */
 #include <netinet/ip.h>			/* XXX for struct ip */
 #include <netinet/ip6.h>		/* XXX for struct ip6_hdr */
 #include <netinet/tcp.h>		/* XXX for struct tcphdr */
 #include <sys/bus.h>
 #include <sys/intr.h>
 #include <machine/endian.h>
 #include <dev/mii/mii.h>
 #include <dev/mii/miivar.h>
 #include <dev/mii/miidevs.h>
 #include <dev/mii/mii_bitbang.h>
 #include <dev/mii/ikphyreg.h>
 #include <dev/mii/igphyreg.h>
 #include <dev/mii/igphyvar.h>
 #include <dev/mii/inbmphyreg.h>
 #include <dev/mii/ihphyreg.h>
 #include <dev/mii/makphyreg.h>
 #include <dev/pci/pcireg.h>
 #include <dev/pci/pcivar.h>
 #include <dev/pci/pcidevs.h>
 #include <dev/pci/if_wmreg.h>
 #include <dev/pci/if_wmvar.h>
 #ifdef WM_DEBUG
 #define	WM_DEBUG_LINK		__BIT(0)
 #define	WM_DEBUG_TX		__BIT(1)
 #define	WM_DEBUG_RX		__BIT(2)
 #define	WM_DEBUG_GMII		__BIT(3)
 #define	WM_DEBUG_MANAGE		__BIT(4)
 #define	WM_DEBUG_NVM		__BIT(5)
 #define	WM_DEBUG_INIT		__BIT(6)
 #define	WM_DEBUG_LOCK		__BIT(7)
 #if 0
 #define WM_DEBUG_DEFAULT	WM_DEBUG_TX | WM_DEBUG_RX | WM_DEBUG_LINK | \
 	WM_DEBUG_GMII | WM_DEBUG_MANAGE | WM_DEBUG_NVM | WM_DEBUG_INIT |    \
 	WM_DEBUG_LOCK
 #endif
 #define	DPRINTF(sc, x, y)			  \
 	do {					  \
 		if ((sc)->sc_debug & (x))	  \
 			printf y;		  \
 	} while (0)
 #else
 #define	DPRINTF(sc, x, y)	__nothing
 #endif /* WM_DEBUG */
 #ifdef NET_MPSAFE
 #define WM_MPSAFE	1
 #define WM_CALLOUT_FLAGS	CALLOUT_MPSAFE
 #define WM_SOFTINT_FLAGS	SOFTINT_MPSAFE
 #define WM_WORKQUEUE_FLAGS	WQ_PERCPU | WQ_MPSAFE
 #else
 #define WM_CALLOUT_FLAGS	0
 #define WM_SOFTINT_FLAGS	0
 #define WM_WORKQUEUE_FLAGS	WQ_PERCPU
 #endif
 #define WM_WORKQUEUE_PRI PRI_SOFTNET
 /*
  * This device driver's max interrupt numbers.
  */
 #define WM_MAX_NQUEUEINTR	16
 #define WM_MAX_NINTR		(WM_MAX_NQUEUEINTR + 1)
 #ifndef WM_DISABLE_MSI
 #define	WM_DISABLE_MSI 0
 #endif
 #ifndef WM_DISABLE_MSIX
 #define	WM_DISABLE_MSIX 0
 #endif
 int wm_disable_msi = WM_DISABLE_MSI;
 int wm_disable_msix = WM_DISABLE_MSIX;
 #ifndef WM_WATCHDOG_TIMEOUT
 #define WM_WATCHDOG_TIMEOUT 5
 #endif
 static int wm_watchdog_timeout = WM_WATCHDOG_TIMEOUT;
 /*
  * Transmit descriptor list size.  Due to errata, we can only have
  * 256 hardware descriptors in the ring on < 82544, but we use 4096
  * on >= 82544. We tell the upper layers that they can queue a lot
  * of packets, and we go ahead and manage up to 64 (16 for the i82547)
  * of them at a time.
+ *
  * We allow up to 64 DMA segments per packet.  Pathological packet
  * chains containing many small mbufs have been observed in zero-copy
  * situations with jumbo frames. If a mbuf chain has more than 64 DMA segments,
  * m_defrag() is called to reduce it.
  */
 #define	WM_NTXSEGS		64
 #define	WM_IFQUEUELEN		256
 #define	WM_TXQUEUELEN_MAX	64
 #define	WM_TXQUEUELEN_MAX_82547	16
 #define	WM_TXQUEUELEN(txq)	((txq)->txq_num)
 #define	WM_TXQUEUELEN_MASK(txq)	(WM_TXQUEUELEN(txq) - 1)
 #define	WM_TXQUEUE_GC(txq)	(WM_TXQUEUELEN(txq) / 8)
 #define	WM_NTXDESC_82542	256
 #define	WM_NTXDESC_82544	4096
 #define	WM_NTXDESC(txq)		((txq)->txq_ndesc)
 #define	WM_NTXDESC_MASK(txq)	(WM_NTXDESC(txq) - 1)
 #define	WM_TXDESCS_SIZE(txq)	(WM_NTXDESC(txq) * (txq)->txq_descsize)
 #define	WM_NEXTTX(txq, x)	(((x) + 1) & WM_NTXDESC_MASK(txq))
 #define	WM_NEXTTXS(txq, x)	(((x) + 1) & WM_TXQUEUELEN_MASK(txq))
 #define	WM_MAXTXDMA		 (2 * round_page(IP_MAXPACKET)) /* for TSO */
 #define	WM_TXINTERQSIZE		256
 #ifndef WM_TX_PROCESS_LIMIT_DEFAULT
 #define	WM_TX_PROCESS_LIMIT_DEFAULT		100U
 #endif
 #ifndef WM_TX_INTR_PROCESS_LIMIT_DEFAULT
 #define	WM_TX_INTR_PROCESS_LIMIT_DEFAULT	0U
 #endif
 /*
  * Receive descriptor list size.  We have one Rx buffer for normal
  * sized packets.  Jumbo packets consume 5 Rx buffers for a full-sized
  * packet.  We allocate 256 receive descriptors, each with a 2k
  * buffer (MCLBYTES), which gives us room for 50 jumbo packets.
  */
 #define	WM_NRXDESC		256U
 #define	WM_NRXDESC_MASK		(WM_NRXDESC - 1)
 #define	WM_NEXTRX(x)		(((x) + 1) & WM_NRXDESC_MASK)
 #define	WM_PREVRX(x)		(((x) - 1) & WM_NRXDESC_MASK)
 #ifndef WM_RX_PROCESS_LIMIT_DEFAULT
 #define	WM_RX_PROCESS_LIMIT_DEFAULT		100U
 #endif
 #ifndef WM_RX_INTR_PROCESS_LIMIT_DEFAULT
 #define	WM_RX_INTR_PROCESS_LIMIT_DEFAULT	0U
 #endif
 typedef union txdescs {
 	wiseman_txdesc_t sctxu_txdescs[WM_NTXDESC_82544];
 	nq_txdesc_t	 sctxu_nq_txdescs[WM_NTXDESC_82544];
 } txdescs_t;
 typedef union rxdescs {
 	wiseman_rxdesc_t sctxu_rxdescs[WM_NRXDESC];
 	ext_rxdesc_t	 sctxu_ext_rxdescs[WM_NRXDESC]; /* 82574 only */
 	nq_rxdesc_t	 sctxu_nq_rxdescs[WM_NRXDESC]; /* 82575 and newer */
 } rxdescs_t;
 #define	WM_CDTXOFF(txq, x)	((txq)->txq_descsize * (x))
 #define	WM_CDRXOFF(rxq, x)	((rxq)->rxq_descsize * (x))
 /*
  * Software state for transmit jobs.
  */
 struct wm_txsoft {
 	struct mbuf *txs_mbuf;		/* head of our mbuf chain */
 	bus_dmamap_t txs_dmamap;	/* our DMA map */
 	int txs_firstdesc;		/* first descriptor in packet */
 	int txs_lastdesc;		/* last descriptor in packet */
 	int txs_ndesc;			/* # of descriptors used */
 };
 /*
  * Software state for receive buffers. Each descriptor gets a 2k (MCLBYTES)
  * buffer and a DMA map. For packets which fill more than one buffer, we chain
  * them together.
  */
 struct wm_rxsoft {
 	struct mbuf *rxs_mbuf;		/* head of our mbuf chain */
 	bus_dmamap_t rxs_dmamap;	/* our DMA map */
 };
 #define WM_LINKUP_TIMEOUT	50
 static uint16_t swfwphysem[] = {
 	SWFW_PHY0_SM,
 	SWFW_PHY1_SM,
 	SWFW_PHY2_SM,
 	SWFW_PHY3_SM
 };
 static const uint32_t wm_82580_rxpbs_table[] = {
 , 72, 144, 1, 2, 4, 8, 16, 35, 70, 140
 };
 struct wm_softc;
 #if defined(_LP64) && !defined(WM_DISABLE_EVENT_COUNTERS)
 #if !defined(WM_EVENT_COUNTERS)
 #define WM_EVENT_COUNTERS 1
 #endif
 #endif
 #ifdef WM_EVENT_COUNTERS
 #define WM_Q_EVCNT_DEFINE(qname, evname)				 \
 	char qname##_##evname##_evcnt_name[sizeof("qname##XX##evname")]; \
 	struct evcnt qname##_ev_##evname
 #define WM_Q_EVCNT_ATTACH(qname, evname, q, qnum, xname, evtype)	\
 	do {								\
 		snprintf((q)->qname##_##evname##_evcnt_name,		\
 		    sizeof((q)->qname##_##evname##_evcnt_name),		\
 		    "%s%02d%s", #qname, (qnum), #evname);		\
 		evcnt_attach_dynamic(&(q)->qname##_ev_##evname,		\
 		    (evtype), NULL, (xname),				\
 		    (q)->qname##_##evname##_evcnt_name);		\
 	} while (0)
 #define WM_Q_MISC_EVCNT_ATTACH(qname, evname, q, qnum, xname)		\
 	WM_Q_EVCNT_ATTACH(qname, evname, q, qnum, xname, EVCNT_TYPE_MISC)
 #define WM_Q_INTR_EVCNT_ATTACH(qname, evname, q, qnum, xname)		\
 	WM_Q_EVCNT_ATTACH(qname, evname, q, qnum, xname, EVCNT_TYPE_INTR)
 #define WM_Q_EVCNT_DETACH(qname, evname, q, qnum)	\
 	evcnt_detach(&(q)->qname##_ev_##evname)
 #endif /* WM_EVENT_COUNTERS */
 struct wm_txqueue {
 	kmutex_t *txq_lock;		/* lock for tx operations */
 	struct wm_softc *txq_sc;	/* shortcut (skip struct wm_queue) */
 	/* Software state for the transmit descriptors. */
 	int txq_num;			/* must be a power of two */
 	struct wm_txsoft txq_soft[WM_TXQUEUELEN_MAX];
 	/* TX control data structures. */
 	int txq_ndesc;			/* must be a power of two */
 	size_t txq_descsize;		/* a tx descriptor size */
 	txdescs_t *txq_descs_u;
 	bus_dmamap_t txq_desc_dmamap;	/* control data DMA map */
 	bus_dma_segment_t txq_desc_seg;	/* control data segment */
 	int txq_desc_rseg;		/* real number of control segment */
 #define	txq_desc_dma	txq_desc_dmamap->dm_segs[0].ds_addr
 #define	txq_descs	txq_descs_u->sctxu_txdescs
 #define	txq_nq_descs	txq_descs_u->sctxu_nq_txdescs
 	bus_addr_t txq_tdt_reg;		/* offset of TDT register */
 	int txq_free;			/* number of free Tx descriptors */
 	int txq_next;			/* next ready Tx descriptor */
 	int txq_sfree;			/* number of free Tx jobs */
 	int txq_snext;			/* next free Tx job */
 	int txq_sdirty;			/* dirty Tx jobs */
 	/* These 4 variables are used only on the 82547. */
 	int txq_fifo_size;		/* Tx FIFO size */
 	int txq_fifo_head;		/* current head of FIFO */
 	uint32_t txq_fifo_addr;		/* internal address of start of FIFO */
 	int txq_fifo_stall;		/* Tx FIFO is stalled */
 	/*
 	 * When ncpu > number of Tx queues, a Tx queue is shared by multiple
 	 * CPUs. This queue intermediate them without block.
 	 */
 	pcq_t *txq_interq;
 	/*
 	 * NEWQUEUE devices must use not ifp->if_flags but txq->txq_flags
 	 * to manage Tx H/W queue's busy flag.
 	 */
 	int txq_flags;			/* flags for H/W queue, see below */
 #define	WM_TXQ_NO_SPACE		0x1
 #define	WM_TXQ_LINKDOWN_DISCARD	0x2
 	bool txq_stopping;
 	bool txq_sending;
 	time_t txq_lastsent;
 	/* Checksum flags used for previous packet */
 	uint32_t	txq_last_hw_cmd;
 	uint8_t		txq_last_hw_fields;
 	uint16_t	txq_last_hw_ipcs;
 	uint16_t	txq_last_hw_tucs;
 	uint32_t txq_packets;		/* for AIM */
 	uint32_t txq_bytes;		/* for AIM */
 #ifdef WM_EVENT_COUNTERS
 	/* TX event counters */
 	WM_Q_EVCNT_DEFINE(txq, txsstall);   /* Stalled due to no txs */
 	WM_Q_EVCNT_DEFINE(txq, txdstall);   /* Stalled due to no txd */
 	WM_Q_EVCNT_DEFINE(txq, fifo_stall); /* FIFO stalls (82547) */
 	WM_Q_EVCNT_DEFINE(txq, txdw);	    /* Tx descriptor interrupts */
 	WM_Q_EVCNT_DEFINE(txq, txqe);	    /* Tx queue empty interrupts */
 					    /* XXX not used? */
 	WM_Q_EVCNT_DEFINE(txq, ipsum);	    /* IP checksums comp. */
 	WM_Q_EVCNT_DEFINE(txq, tusum);	    /* TCP/UDP cksums comp. */
 	WM_Q_EVCNT_DEFINE(txq, tusum6);	    /* TCP/UDP v6 cksums comp. */
 	WM_Q_EVCNT_DEFINE(txq, tso);	    /* TCP seg offload (IPv4) */
 	WM_Q_EVCNT_DEFINE(txq, tso6);	    /* TCP seg offload (IPv6) */
 	WM_Q_EVCNT_DEFINE(txq, tsopain);    /* Painful header manip. for TSO */
 	WM_Q_EVCNT_DEFINE(txq, pcqdrop);    /* Pkt dropped in pcq */
 	WM_Q_EVCNT_DEFINE(txq, descdrop);   /* Pkt dropped in MAC desc ring */
 					    /* other than toomanyseg */
 	WM_Q_EVCNT_DEFINE(txq, toomanyseg); /* Pkt dropped(toomany DMA segs) */
 	WM_Q_EVCNT_DEFINE(txq, defrag);	    /* m_defrag() */
 	WM_Q_EVCNT_DEFINE(txq, underrun);   /* Tx underrun */
 	WM_Q_EVCNT_DEFINE(txq, skipcontext); /* Tx skip wrong cksum context */
 	char txq_txseg_evcnt_names[WM_NTXSEGS][sizeof("txqXXtxsegXXX")];
 	struct evcnt txq_ev_txseg[WM_NTXSEGS]; /* Tx packets w/ N segments */
 #endif /* WM_EVENT_COUNTERS */
 };
 struct wm_rxqueue {
 	kmutex_t *rxq_lock;		/* lock for rx operations */
 	struct wm_softc *rxq_sc;	/* shortcut (skip struct wm_queue) */
 	/* Software state for the receive descriptors. */
 	struct wm_rxsoft rxq_soft[WM_NRXDESC];
 	/* RX control data structures. */
 	int rxq_ndesc;			/* must be a power of two */
 	size_t rxq_descsize;		/* a rx descriptor size */
 	rxdescs_t *rxq_descs_u;
 	bus_dmamap_t rxq_desc_dmamap;	/* control data DMA map */
 	bus_dma_segment_t rxq_desc_seg;	/* control data segment */
 	int rxq_desc_rseg;		/* real number of control segment */
 #define	rxq_desc_dma	rxq_desc_dmamap->dm_segs[0].ds_addr
 #define	rxq_descs	rxq_descs_u->sctxu_rxdescs
 #define	rxq_ext_descs	rxq_descs_u->sctxu_ext_rxdescs
 #define	rxq_nq_descs	rxq_descs_u->sctxu_nq_rxdescs
 	bus_addr_t rxq_rdt_reg;		/* offset of RDT register */
 	int rxq_ptr;			/* next ready Rx desc/queue ent */
 	int rxq_discard;
 	int rxq_len;
 	struct mbuf *rxq_head;
 	struct mbuf *rxq_tail;
 	struct mbuf **rxq_tailp;
 	bool rxq_stopping;
 	uint32_t rxq_packets;		/* for AIM */
 	uint32_t rxq_bytes;		/* for AIM */
 #ifdef WM_EVENT_COUNTERS
 	/* RX event counters */
 	WM_Q_EVCNT_DEFINE(rxq, intr);	/* Interrupts */
 	WM_Q_EVCNT_DEFINE(rxq, defer);	/* Rx deferred processing */
 	WM_Q_EVCNT_DEFINE(rxq, ipsum);	/* IP checksums checked */
 	WM_Q_EVCNT_DEFINE(rxq, tusum);	/* TCP/UDP cksums checked */
 	WM_Q_EVCNT_DEFINE(rxq, qdrop);	/* Rx queue drop packet */
 #endif
 };
 struct wm_queue {
 	int wmq_id;			/* index of TX/RX queues */
 	int wmq_intr_idx;		/* index of MSI-X tables */
 	uint32_t wmq_itr;		/* interrupt interval per queue. */
 	bool wmq_set_itr;
 	struct wm_txqueue wmq_txq;
 	struct wm_rxqueue wmq_rxq;
 	char sysctlname[32];		/* Name for sysctl */
 	bool wmq_txrx_use_workqueue;
 	bool wmq_wq_enqueued;
 	struct work wmq_cookie;
 	void *wmq_si;
 	krndsource_t rnd_source;	/* random source */
 };
 struct wm_phyop {
 	int (*acquire)(struct wm_softc *) __attribute__((warn_unused_result));
 	void (*release)(struct wm_softc *);
 	int (*readreg_locked)(device_t, int, int, uint16_t *);
 	int (*writereg_locked)(device_t, int, int, uint16_t);
 	int reset_delay_us;
 	bool no_errprint;
 };
 struct wm_nvmop {
 	int (*acquire)(struct wm_softc *) __attribute__((warn_unused_result));
 	void (*release)(struct wm_softc *);
 	int (*read)(struct wm_softc *, int, int, uint16_t *);
 };
 /*
  * Software state per device.
  */
 struct wm_softc {
 	device_t sc_dev;		/* generic device information */
 	bus_space_tag_t sc_st;		/* bus space tag */
 	bus_space_handle_t sc_sh;	/* bus space handle */
 	bus_size_t sc_ss;		/* bus space size */
 	bus_space_tag_t sc_iot;		/* I/O space tag */
 	bus_space_handle_t sc_ioh;	/* I/O space handle */
 	bus_size_t sc_ios;		/* I/O space size */
 	bus_space_tag_t sc_flasht;	/* flash registers space tag */
 	bus_space_handle_t sc_flashh;	/* flash registers space handle */
 	bus_size_t sc_flashs;		/* flash registers space size */
 	off_t sc_flashreg_offset;	/*
 					 * offset to flash registers from
 					 * start of BAR
 					 */
 	bus_dma_tag_t sc_dmat;		/* bus DMA tag */
 	struct ethercom sc_ethercom;	/* Ethernet common data */
 	struct mii_data sc_mii;		/* MII/media information */
 	pci_chipset_tag_t sc_pc;
 	pcitag_t sc_pcitag;
 	int sc_bus_speed;		/* PCI/PCIX bus speed */
 	int sc_pcixe_capoff;		/* PCI[Xe] capability reg offset */
 	uint16_t sc_pcidevid;		/* PCI device ID */
 	wm_chip_type sc_type;		/* MAC type */
 	int sc_rev;			/* MAC revision */
 	wm_phy_type sc_phytype;		/* PHY type */
 	uint8_t sc_sfptype;		/* SFP type */
 	uint32_t sc_mediatype;		/* Media type (Copper, Fiber, SERDES)*/
 #define	WM_MEDIATYPE_UNKNOWN		0x00
 #define	WM_MEDIATYPE_FIBER		0x01
 #define	WM_MEDIATYPE_COPPER		0x02
 #define	WM_MEDIATYPE_SERDES		0x03 /* Internal SERDES */
 	int sc_funcid;			/* unit number of the chip (0 to 3) */
 	u_int sc_flags;			/* flags; see below */
 	int sc_if_flags;		/* last if_flags */
 	int sc_flowflags;		/* 802.3x flow control flags */
 	int sc_align_tweak;
 	void *sc_ihs[WM_MAX_NINTR];	/*
 					 * interrupt cookie.
 					 * - legacy and msi use sc_ihs[0] only
 					 * - msix use sc_ihs[0] to sc_ihs[nintrs-1]
 					 */
 	pci_intr_handle_t *sc_intrs;	/*
 					 * legacy and msi use sc_intrs[0] only
 					 * msix use sc_intrs[0] to sc_ihs[nintrs-1]
 					 */
 	int sc_nintrs;			/* number of interrupts */
 	int sc_link_intr_idx;		/* index of MSI-X tables */
 	callout_t sc_tick_ch;		/* tick callout */
 	bool sc_core_stopping;
 	int sc_nvm_ver_major;
 	int sc_nvm_ver_minor;
 	int sc_nvm_ver_build;
 	int sc_nvm_addrbits;		/* NVM address bits */
 	unsigned int sc_nvm_wordsize;	/* NVM word size */
 	int sc_ich8_flash_base;
 	int sc_ich8_flash_bank_size;
 	int sc_nvm_k1_enabled;
 	int sc_nqueues;
 	struct wm_queue *sc_queue;
 	u_int sc_tx_process_limit;	/* Tx proc. repeat limit in softint */
 	u_int sc_tx_intr_process_limit;	/* Tx proc. repeat limit in H/W intr */
 	u_int sc_rx_process_limit;	/* Rx proc. repeat limit in softint */
 	u_int sc_rx_intr_process_limit;	/* Rx proc. repeat limit in H/W intr */
 	struct workqueue *sc_queue_wq;
 	bool sc_txrx_use_workqueue;
 	int sc_affinity_offset;
 #ifdef WM_EVENT_COUNTERS
 	/* Event counters. */
 	struct evcnt sc_ev_linkintr;	/* Link interrupts */
 	/* >= WM_T_82542_2_1 */
 	struct evcnt sc_ev_rx_xon;	/* Rx PAUSE(0) frames */
 	struct evcnt sc_ev_tx_xon;	/* Tx PAUSE(0) frames */
 	struct evcnt sc_ev_rx_xoff;	/* Rx PAUSE(!0) frames */
 	struct evcnt sc_ev_tx_xoff;	/* Tx PAUSE(!0) frames */
 	struct evcnt sc_ev_rx_macctl;	/* Rx Unsupported */
 	struct evcnt sc_ev_crcerrs;	/* CRC Error */
 	struct evcnt sc_ev_algnerrc;	/* Alignment Error */
 	struct evcnt sc_ev_symerrc;	/* Symbol Error */
 	struct evcnt sc_ev_rxerrc;	/* Receive Error */
 	struct evcnt sc_ev_mpc;		/* Missed Packets */
 	struct evcnt sc_ev_scc;		/* Single Collision */
 	struct evcnt sc_ev_ecol;	/* Excessive Collision */
 	struct evcnt sc_ev_mcc;		/* Multiple Collision */
 	struct evcnt sc_ev_latecol;	/* Late Collision */
 	struct evcnt sc_ev_colc;	/* Collision */
 	struct evcnt sc_ev_cbtmpc;	/* Circuit Breaker Tx Mng. Packet */
 	struct evcnt sc_ev_dc;		/* Defer */
 	struct evcnt sc_ev_tncrs;	/* Tx-No CRS */
 	struct evcnt sc_ev_sec;		/* Sequence Error */
 	/* Old */
 	struct evcnt sc_ev_cexterr;	/* Carrier Extension Error */
 	/* New */
 	struct evcnt sc_ev_htdpmc;	/* Host Tx Discarded Pkts by MAC */
 	struct evcnt sc_ev_rlec;	/* Receive Length Error */
 	struct evcnt sc_ev_cbrdpc;	/* Circuit Breaker Rx Dropped Packet */
 	struct evcnt sc_ev_prc64;	/* Packets Rx (64 bytes) */
 	struct evcnt sc_ev_prc127;	/* Packets Rx (65-127 bytes) */
 	struct evcnt sc_ev_prc255;	/* Packets Rx (128-255 bytes) */
 	struct evcnt sc_ev_prc511;	/* Packets Rx (256-511 bytes) */
 	struct evcnt sc_ev_prc1023;	/* Packets Rx (512-1023 bytes) */
 	struct evcnt sc_ev_prc1522;	/* Packets Rx (1024-1522 bytes) */
 	struct evcnt sc_ev_gprc;	/* Good Packets Rx */
 	struct evcnt sc_ev_bprc;	/* Broadcast Packets Rx */
 	struct evcnt sc_ev_mprc;	/* Multicast Packets Rx */
 	struct evcnt sc_ev_gptc;	/* Good Packets Tx */
 	struct evcnt sc_ev_gorc;	/* Good Octets Rx */
 	struct evcnt sc_ev_gotc;	/* Good Octets Tx */
 	struct evcnt sc_ev_rnbc;	/* Rx No Buffers */
 	struct evcnt sc_ev_ruc;		/* Rx Undersize */
 	struct evcnt sc_ev_rfc;		/* Rx Fragment */
 	struct evcnt sc_ev_roc;		/* Rx Oversize */
 	struct evcnt sc_ev_rjc;		/* Rx Jabber */
 	struct evcnt sc_ev_mgtprc;	/* Management Packets RX */
 	struct evcnt sc_ev_mgtpdc;	/* Management Packets Dropped */
 	struct evcnt sc_ev_mgtptc;	/* Management Packets TX */
 	struct evcnt sc_ev_tor;		/* Total Octets Rx */
 	struct evcnt sc_ev_tot;		/* Total Octets Tx */
 	struct evcnt sc_ev_tpr;		/* Total Packets Rx */
 	struct evcnt sc_ev_tpt;		/* Total Packets Tx */
 	struct evcnt sc_ev_ptc64;	/* Packets Tx (64 bytes) */
 	struct evcnt sc_ev_ptc127;	/* Packets Tx (65-127 bytes) */
 	struct evcnt sc_ev_ptc255;	/* Packets Tx (128-255 bytes) */
 	struct evcnt sc_ev_ptc511;	/* Packets Tx (256-511 bytes) */
 	struct evcnt sc_ev_ptc1023;	/* Packets Tx (512-1023 bytes) */
 	struct evcnt sc_ev_ptc1522;	/* Packets Tx (1024-1522 Bytes) */
 	struct evcnt sc_ev_mptc;	/* Multicast Packets Tx */
 	struct evcnt sc_ev_bptc;	/* Broadcast Packets Tx */
 	struct evcnt sc_ev_tsctc;	/* TCP Segmentation Context Tx */
 	/* Old */
 	struct evcnt sc_ev_tsctfc;	/* TCP Segmentation Context Tx Fail */
 	/* New */
 	struct evcnt sc_ev_cbrmpc;	/* Circuit Breaker Rx Mng. Packet */
 	struct evcnt sc_ev_iac;		/* Interrupt Assertion */
 	/* Old */
 	struct evcnt sc_ev_icrxptc;	/* Intr. Cause Rx Pkt Timer Expire */
 	struct evcnt sc_ev_icrxatc;	/* Intr. Cause Rx Abs Timer Expire */
 	struct evcnt sc_ev_ictxptc;	/* Intr. Cause Tx Pkt Timer Expire */
 	struct evcnt sc_ev_ictxatc;	/* Intr. Cause Tx Abs Timer Expire */
 	struct evcnt sc_ev_ictxqec;	/* Intr. Cause Tx Queue Empty */
 	struct evcnt sc_ev_ictxqmtc;	/* Intr. Cause Tx Queue Min Thresh */
 	/*
 	 * sc_ev_rxdmtc is shared with both "Intr. cause" and
 	 * non "Intr. cause" register.
 	 */
 	struct evcnt sc_ev_rxdmtc;	/* (Intr. Cause) Rx Desc Min Thresh */
 	struct evcnt sc_ev_icrxoc;	/* Intr. Cause Receiver Overrun */
 	/* New */
 	struct evcnt sc_ev_rpthc;	/* Rx Packets To Host */
 	struct evcnt sc_ev_debug1;	/* Debug Counter 1 */
 	struct evcnt sc_ev_debug2;	/* Debug Counter 2 */
 	struct evcnt sc_ev_debug3;	/* Debug Counter 3 */
 	struct evcnt sc_ev_hgptc;	/* Host Good Packets TX */
 	struct evcnt sc_ev_debug4;	/* Debug Counter 4 */
 	struct evcnt sc_ev_htcbdpc;	/* Host Tx Circuit Breaker Drp. Pkts */
 	struct evcnt sc_ev_hgorc;	/* Host Good Octets Rx */
 	struct evcnt sc_ev_hgotc;	/* Host Good Octets Tx */
 	struct evcnt sc_ev_lenerrs;	/* Length Error */
 	struct evcnt sc_ev_tlpic;	/* EEE Tx LPI */
 	struct evcnt sc_ev_rlpic;	/* EEE Rx LPI */
 	struct evcnt sc_ev_b2ogprc;	/* BMC2OS pkts received by host */
 	struct evcnt sc_ev_o2bspc;	/* OS2BMC pkts transmitted by host */
 	struct evcnt sc_ev_b2ospc;	/* BMC2OS pkts sent by BMC */
 	struct evcnt sc_ev_o2bgptc;	/* OS2BMC pkts received by BMC */
 	struct evcnt sc_ev_scvpc;	/* SerDes/SGMII Code Violation Pkt. */
 	struct evcnt sc_ev_hrmpc;	/* Header Redirection Missed Packet */
 #endif /* WM_EVENT_COUNTERS */
 	struct sysctllog *sc_sysctllog;
 	/* This variable are used only on the 82547. */
 	callout_t sc_txfifo_ch;		/* Tx FIFO stall work-around timer */
 	uint32_t sc_ctrl;		/* prototype CTRL register */
 #if 0
 	uint32_t sc_ctrl_ext;		/* prototype CTRL_EXT register */
 #endif
 	uint32_t sc_icr;		/* prototype interrupt bits */
 	uint32_t sc_itr_init;		/* prototype intr throttling reg */
 	uint32_t sc_tctl;		/* prototype TCTL register */
 	uint32_t sc_rctl;		/* prototype RCTL register */
 	uint32_t sc_txcw;		/* prototype TXCW register */
 	uint32_t sc_tipg;		/* prototype TIPG register */
 	uint32_t sc_fcrtl;		/* prototype FCRTL register */
 	uint32_t sc_pba;		/* prototype PBA register */
 	int sc_tbi_linkup;		/* TBI link status */
 	int sc_tbi_serdes_anegticks;	/* autonegotiation ticks */
 	int sc_tbi_serdes_ticks;	/* tbi ticks */
 	struct timeval sc_linkup_delay_time; /* delay LINK_STATE_UP */
 	int sc_mchash_type;		/* multicast filter offset */
 	struct if_percpuq *sc_ipq;	/* softint-based input queues */
 	kmutex_t *sc_core_lock;		/* lock for softc operations */
 	kmutex_t *sc_ich_phymtx;	/*
 					 * 82574/82583/ICH/PCH specific PHY
 					 * mutex. For 82574/82583, the mutex
 					 * is used for both PHY and NVM.
 					 */
 	kmutex_t *sc_ich_nvmmtx;	/* ICH/PCH specific NVM mutex */
 	struct wm_phyop phy;
 	struct wm_nvmop nvm;
 #ifdef WM_DEBUG
 	uint32_t sc_debug;
 #endif
 };
 #define WM_CORE_LOCK(_sc)						\
 	if ((_sc)->sc_core_lock) mutex_enter((_sc)->sc_core_lock)
 #define WM_CORE_UNLOCK(_sc)						\
 	if ((_sc)->sc_core_lock) mutex_exit((_sc)->sc_core_lock)
 #define WM_CORE_LOCKED(_sc)						\
 	(!(_sc)->sc_core_lock || mutex_owned((_sc)->sc_core_lock))
 #define	WM_RXCHAIN_RESET(rxq)						\
 do {									\
 	(rxq)->rxq_tailp = &(rxq)->rxq_head;				\
 	*(rxq)->rxq_tailp = NULL;					\
 	(rxq)->rxq_len = 0;						\
 } while (/*CONSTCOND*/0)
 #define	WM_RXCHAIN_LINK(rxq, m)						\
 do {									\
 	*(rxq)->rxq_tailp = (rxq)->rxq_tail = (m);			\
 	(rxq)->rxq_tailp = &(m)->m_next;				\
 } while (/*CONSTCOND*/0)
 #ifdef WM_EVENT_COUNTERS
 #define	WM_EVCNT_INCR(ev)	(ev)->ev_count++
 #define	WM_EVCNT_STORE(ev, val)	(ev)->ev_count = (val)
 #define	WM_EVCNT_ADD(ev, val)	(ev)->ev_count += (val)
 #define WM_Q_EVCNT_INCR(qname, evname)			\
 	WM_EVCNT_INCR(&(qname)->qname##_ev_##evname)
 #define WM_Q_EVCNT_STORE(qname, evname, val)		\
 	WM_EVCNT_STORE(&(qname)->qname##_ev_##evname, (val))
 #define WM_Q_EVCNT_ADD(qname, evname, val)		\
 	WM_EVCNT_ADD(&(qname)->qname##_ev_##evname, (val))
 #else /* !WM_EVENT_COUNTERS */
 #define	WM_EVCNT_INCR(ev)	__nothing
 #define	WM_EVCNT_STORE(ev, val)	__nothing
 #define	WM_EVCNT_ADD(ev, val)	__nothing
 #define WM_Q_EVCNT_INCR(qname, evname)		__nothing
 #define WM_Q_EVCNT_STORE(qname, evname, val)	__nothing
 #define WM_Q_EVCNT_ADD(qname, evname, val)	__nothing
 #endif /* !WM_EVENT_COUNTERS */
 #define	CSR_READ(sc, reg)						\
 	bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
 #define	CSR_WRITE(sc, reg, val)						\
 	bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
 #define	CSR_WRITE_FLUSH(sc)						\
 	(void)CSR_READ((sc), WMREG_STATUS)
 #define ICH8_FLASH_READ32(sc, reg)					\
 	bus_space_read_4((sc)->sc_flasht, (sc)->sc_flashh,		\
 	    (reg) + sc->sc_flashreg_offset)
 #define ICH8_FLASH_WRITE32(sc, reg, data)				\
 	bus_space_write_4((sc)->sc_flasht, (sc)->sc_flashh,		\
 	    (reg) + sc->sc_flashreg_offset, (data))
 #define ICH8_FLASH_READ16(sc, reg)					\
 	bus_space_read_2((sc)->sc_flasht, (sc)->sc_flashh,		\
 	    (reg) + sc->sc_flashreg_offset)
 #define ICH8_FLASH_WRITE16(sc, reg, data)				\
 	bus_space_write_2((sc)->sc_flasht, (sc)->sc_flashh,		\
 	    (reg) + sc->sc_flashreg_offset, (data))
 #define	WM_CDTXADDR(txq, x)	((txq)->txq_desc_dma + WM_CDTXOFF((txq), (x)))
 #define	WM_CDRXADDR(rxq, x)	((rxq)->rxq_desc_dma + WM_CDRXOFF((rxq), (x)))
 #define	WM_CDTXADDR_LO(txq, x)	(WM_CDTXADDR((txq), (x)) & 0xffffffffU)
 #define	WM_CDTXADDR_HI(txq, x)						\
 	(sizeof(bus_addr_t) == 8 ?					\
 	 (uint64_t)WM_CDTXADDR((txq), (x)) >> 32 : 0)
 #define	WM_CDRXADDR_LO(rxq, x)	(WM_CDRXADDR((rxq), (x)) & 0xffffffffU)
 #define	WM_CDRXADDR_HI(rxq, x)						\
 	(sizeof(bus_addr_t) == 8 ?					\
 	 (uint64_t)WM_CDRXADDR((rxq), (x)) >> 32 : 0)
 /*
  * Register read/write functions.
  * Other than CSR_{READ|WRITE}().
  */
 #if 0
 static inline uint32_t wm_io_read(struct wm_softc *, int);
 #endif
 static inline void wm_io_write(struct wm_softc *, int, uint32_t);
 static inline void wm_82575_write_8bit_ctlr_reg(struct wm_softc *, uint32_t,
     uint32_t, uint32_t);
 static inline void wm_set_dma_addr(volatile wiseman_addr_t *, bus_addr_t);
 /*
  * Descriptor sync/init functions.
  */
 static inline void wm_cdtxsync(struct wm_txqueue *, int, int, int);
 static inline void wm_cdrxsync(struct wm_rxqueue *, int, int);
 static inline void wm_init_rxdesc(struct wm_rxqueue *, int);
 /*
  * Device driver interface functions and commonly used functions.
  * match, attach, detach, init, start, stop, ioctl, watchdog and so on.
  */
 static const struct wm_product *wm_lookup(const struct pci_attach_args *);
 static int	wm_match(device_t, cfdata_t, void *);
 static void	wm_attach(device_t, device_t, void *);
 static int	wm_detach(device_t, int);
 static bool	wm_suspend(device_t, const pmf_qual_t *);
 static bool	wm_resume(device_t, const pmf_qual_t *);
 static void	wm_watchdog(struct ifnet *);
 static void	wm_watchdog_txq(struct ifnet *, struct wm_txqueue *,
     uint16_t *);
 static void	wm_watchdog_txq_locked(struct ifnet *, struct wm_txqueue *,
     uint16_t *);
 static void	wm_tick(void *);
 static int	wm_ifflags_cb(struct ethercom *);
 static int	wm_ioctl(struct ifnet *, u_long, void *);
 /* MAC address related */
 static uint16_t	wm_check_alt_mac_addr(struct wm_softc *);
 static int	wm_read_mac_addr(struct wm_softc *, uint8_t *);
 static void	wm_set_ral(struct wm_softc *, const uint8_t *, int);
 static uint32_t	wm_mchash(struct wm_softc *, const uint8_t *);
 static int	wm_rar_count(struct wm_softc *);
 static void	wm_set_filter(struct wm_softc *);
 /* Reset and init related */
 static void	wm_set_vlan(struct wm_softc *);
 static void	wm_set_pcie_completion_timeout(struct wm_softc *);
 static void	wm_get_auto_rd_done(struct wm_softc *);
 static void	wm_lan_init_done(struct wm_softc *);
 static void	wm_get_cfg_done(struct wm_softc *);
 static void	wm_phy_post_reset(struct wm_softc *);
 static int	wm_write_smbus_addr(struct wm_softc *);
 static void	wm_init_lcd_from_nvm(struct wm_softc *);
 static int	wm_oem_bits_config_ich8lan(struct wm_softc *, bool);
 static void	wm_initialize_hardware_bits(struct wm_softc *);
 static uint32_t	wm_rxpbs_adjust_82580(uint32_t);
 static int	wm_reset_phy(struct wm_softc *);
 static void	wm_flush_desc_rings(struct wm_softc *);
 static void	wm_reset(struct wm_softc *);
 static int	wm_add_rxbuf(struct wm_rxqueue *, int);
 static void	wm_rxdrain(struct wm_rxqueue *);
 static void	wm_init_rss(struct wm_softc *);
 static void	wm_adjust_qnum(struct wm_softc *, int);
 static inline bool	wm_is_using_msix(struct wm_softc *);
 static inline bool	wm_is_using_multiqueue(struct wm_softc *);
 static int	wm_softint_establish_queue(struct wm_softc *, int, int);
 static int	wm_setup_legacy(struct wm_softc *);
 static int	wm_setup_msix(struct wm_softc *);
 static int	wm_init(struct ifnet *);
 static int	wm_init_locked(struct ifnet *);
 static void	wm_init_sysctls(struct wm_softc *);
 static void	wm_update_stats(struct wm_softc *);
 static void	wm_clear_evcnt(struct wm_softc *);
 static void	wm_unset_stopping_flags(struct wm_softc *);
 static void	wm_set_stopping_flags(struct wm_softc *);
 static void	wm_stop(struct ifnet *, int);
 static void	wm_stop_locked(struct ifnet *, int);
 static void	wm_dump_mbuf_chain(struct wm_softc *, struct mbuf *);
 static void	wm_82547_txfifo_stall(void *);
 static int	wm_82547_txfifo_bugchk(struct wm_softc *, struct mbuf *);
 static void	wm_itrs_writereg(struct wm_softc *, struct wm_queue *);
 /* DMA related */
 static int	wm_alloc_tx_descs(struct wm_softc *, struct wm_txqueue *);
 static void	wm_free_tx_descs(struct wm_softc *, struct wm_txqueue *);
 static void	wm_init_tx_descs(struct wm_softc *, struct wm_txqueue *);
 static void	wm_init_tx_regs(struct wm_softc *, struct wm_queue *,
     struct wm_txqueue *);
 static int	wm_alloc_rx_descs(struct wm_softc *, struct wm_rxqueue *);
 static void	wm_free_rx_descs(struct wm_softc *, struct wm_rxqueue *);
 static void	wm_init_rx_regs(struct wm_softc *, struct wm_queue *,
     struct wm_rxqueue *);
 static int	wm_alloc_tx_buffer(struct wm_softc *, struct wm_txqueue *);
 static void	wm_free_tx_buffer(struct wm_softc *, struct wm_txqueue *);
 static void	wm_init_tx_buffer(struct wm_softc *, struct wm_txqueue *);
 static int	wm_alloc_rx_buffer(struct wm_softc *, struct wm_rxqueue *);
 static void	wm_free_rx_buffer(struct wm_softc *, struct wm_rxqueue *);
 static int	wm_init_rx_buffer(struct wm_softc *, struct wm_rxqueue *);
 static void	wm_init_tx_queue(struct wm_softc *, struct wm_queue *,
     struct wm_txqueue *);
 static int	wm_init_rx_queue(struct wm_softc *, struct wm_queue *,
     struct wm_rxqueue *);
 static int	wm_alloc_txrx_queues(struct wm_softc *);
 static void	wm_free_txrx_queues(struct wm_softc *);
 static int	wm_init_txrx_queues(struct wm_softc *);
 /* Start */
 static void	wm_tx_offload(struct wm_softc *, struct wm_txqueue *,
     struct wm_txsoft *, uint32_t *, uint8_t *);
 static inline int	wm_select_txqueue(struct ifnet *, struct mbuf *);
 static void	wm_start(struct ifnet *);
 static void	wm_start_locked(struct ifnet *);
 static int	wm_transmit(struct ifnet *, struct mbuf *);
 static void	wm_transmit_locked(struct ifnet *, struct wm_txqueue *);
 static void	wm_send_common_locked(struct ifnet *, struct wm_txqueue *,
     bool);
 static void	wm_nq_tx_offload(struct wm_softc *, struct wm_txqueue *,
     struct wm_txsoft *, uint32_t *, uint32_t *, bool *);
 static void	wm_nq_start(struct ifnet *);
 static void	wm_nq_start_locked(struct ifnet *);
 static int	wm_nq_transmit(struct ifnet *, struct mbuf *);
 static void	wm_nq_transmit_locked(struct ifnet *, struct wm_txqueue *);
 static void	wm_nq_send_common_locked(struct ifnet *, struct wm_txqueue *,
     bool);
 static void	wm_deferred_start_locked(struct wm_txqueue *);
 static void	wm_handle_queue(void *);
 static void	wm_handle_queue_work(struct work *, void *);
 /* Interrupt */
 static bool	wm_txeof(struct wm_txqueue *, u_int);
 static bool	wm_rxeof(struct wm_rxqueue *, u_int);
 static void	wm_linkintr_gmii(struct wm_softc *, uint32_t);
 static void	wm_linkintr_tbi(struct wm_softc *, uint32_t);
 static void	wm_linkintr_serdes(struct wm_softc *, uint32_t);
 static void	wm_linkintr(struct wm_softc *, uint32_t);
 static int	wm_intr_legacy(void *);
 static inline void	wm_txrxintr_disable(struct wm_queue *);
 static inline void	wm_txrxintr_enable(struct wm_queue *);
 static void	wm_itrs_calculate(struct wm_softc *, struct wm_queue *);
 static int	wm_txrxintr_msix(void *);
 static int	wm_linkintr_msix(void *);
 /*
  * Media related.
  * GMII, SGMII, TBI, SERDES and SFP.
  */
 /* Common */
 static void	wm_tbi_serdes_set_linkled(struct wm_softc *);
 /* GMII related */
 static void	wm_gmii_reset(struct wm_softc *);
 static void	wm_gmii_setup_phytype(struct wm_softc *, uint32_t, uint16_t);
 static int	wm_get_phy_id_82575(struct wm_softc *);
 static void	wm_gmii_mediainit(struct wm_softc *, pci_product_id_t);
 static int	wm_gmii_mediachange(struct ifnet *);
 static void	wm_gmii_mediastatus(struct ifnet *, struct ifmediareq *);
 static void	wm_i82543_mii_sendbits(struct wm_softc *, uint32_t, int);
 static uint32_t	wm_i82543_mii_recvbits(struct wm_softc *);
 static int	wm_gmii_i82543_readreg(device_t, int, int);
 static void	wm_gmii_i82543_writereg(device_t, int, int, int);
 static int	wm_gmii_mdic_readreg(device_t, int, int);
 static void	wm_gmii_mdic_writereg(device_t, int, int, int);
 static int	wm_gmii_i82544_readreg(device_t, int, int);
 static int	wm_gmii_i82544_readreg_locked(device_t, int, int, uint16_t *);
 static void	wm_gmii_i82544_writereg(device_t, int, int, int);
 static int	wm_gmii_i82544_writereg_locked(device_t, int, int, uint16_t);
 static int	wm_gmii_i80003_readreg(device_t, int, int);
 static void	wm_gmii_i80003_writereg(device_t, int, int, int);
 static int	wm_gmii_bm_readreg(device_t, int, int);
 static void	wm_gmii_bm_writereg(device_t, int, int, int);
 static int	wm_enable_phy_wakeup_reg_access_bm(device_t, uint16_t *);
 static int	wm_disable_phy_wakeup_reg_access_bm(device_t, uint16_t *);
 static int	wm_access_phy_wakeup_reg_bm(device_t, int, int16_t *, int,
 	bool);
 static int	wm_gmii_hv_readreg(device_t, int, int);
 static int	wm_gmii_hv_readreg_locked(device_t, int, int, uint16_t *);
 static void	wm_gmii_hv_writereg(device_t, int, int, int);
 static int	wm_gmii_hv_writereg_locked(device_t, int, int, uint16_t);
 static int	wm_gmii_82580_readreg(device_t, int, int);
 static void	wm_gmii_82580_writereg(device_t, int, int, int);
 static int	wm_gmii_gs40g_readreg(device_t, int, int);
 static void	wm_gmii_gs40g_writereg(device_t, int, int, int);
 static void	wm_gmii_statchg(struct ifnet *);
 /*
  * kumeran related (80003, ICH* and PCH*).
  * These functions are not for accessing MII registers but for accessing
  * kumeran specific registers.
  */
 static int	wm_kmrn_readreg(struct wm_softc *, int, uint16_t *);
 static int	wm_kmrn_readreg_locked(struct wm_softc *, int, uint16_t *);
 static int	wm_kmrn_writereg(struct wm_softc *, int, uint16_t);
 static int	wm_kmrn_writereg_locked(struct wm_softc *, int, uint16_t);
 /* SGMII */
 static bool	wm_sgmii_uses_mdio(struct wm_softc *);
 static void	wm_sgmii_sfp_preconfig(struct wm_softc *);
 static int	wm_sgmii_readreg(device_t, int, int);
 static void	wm_sgmii_writereg(device_t, int, int, int);
 /* TBI related */
 static bool	wm_tbi_havesignal(struct wm_softc *, uint32_t);
 static void	wm_tbi_mediainit(struct wm_softc *);
 static int	wm_tbi_mediachange(struct ifnet *);
 static void	wm_tbi_mediastatus(struct ifnet *, struct ifmediareq *);
 static int	wm_check_for_link(struct wm_softc *);
 static void	wm_tbi_tick(struct wm_softc *);
 /* SERDES related */
 static void	wm_serdes_power_up_link_82575(struct wm_softc *);
 static int	wm_serdes_mediachange(struct ifnet *);
 static void	wm_serdes_mediastatus(struct ifnet *, struct ifmediareq *);
 static void	wm_serdes_tick(struct wm_softc *);
 /* SFP related */
 static int	wm_sfp_read_data_byte(struct wm_softc *, uint16_t, uint8_t *);
 static uint32_t	wm_sfp_get_media_type(struct wm_softc *);
 /*
  * NVM related.
  * Microwire, SPI (w/wo EERD) and Flash.
  */
 /* Misc functions */
 static void	wm_eeprom_sendbits(struct wm_softc *, uint32_t, int);
 static void	wm_eeprom_recvbits(struct wm_softc *, uint32_t *, int);
 static int	wm_nvm_set_addrbits_size_eecd(struct wm_softc *);
 /* Microwire */
 static int	wm_nvm_read_uwire(struct wm_softc *, int, int, uint16_t *);
 /* SPI */
 static int	wm_nvm_ready_spi(struct wm_softc *);
 static int	wm_nvm_read_spi(struct wm_softc *, int, int, uint16_t *);
 /* Using with EERD */
 static int	wm_poll_eerd_eewr_done(struct wm_softc *, int);
 static int	wm_nvm_read_eerd(struct wm_softc *, int, int, uint16_t *);
 /* Flash */
 static int	wm_nvm_valid_bank_detect_ich8lan(struct wm_softc *,
     unsigned int *);
 static int32_t	wm_ich8_cycle_init(struct wm_softc *);
 static int32_t	wm_ich8_flash_cycle(struct wm_softc *, uint32_t);
 static int32_t	wm_read_ich8_data(struct wm_softc *, uint32_t, uint32_t,
     uint32_t *);
 static int32_t	wm_read_ich8_byte(struct wm_softc *, uint32_t, uint8_t *);
 static int32_t	wm_read_ich8_word(struct wm_softc *, uint32_t, uint16_t *);
 static int32_t	wm_read_ich8_dword(struct wm_softc *, uint32_t, uint32_t *);
 static int	wm_nvm_read_ich8(struct wm_softc *, int, int, uint16_t *);
 static int	wm_nvm_read_spt(struct wm_softc *, int, int, uint16_t *);
 /* iNVM */
 static int	wm_nvm_read_word_invm(struct wm_softc *, uint16_t, uint16_t *);
 static int	wm_nvm_read_invm(struct wm_softc *, int, int, uint16_t *);
 /* Lock, detecting NVM type, validate checksum and read */
 static int	wm_nvm_is_onboard_eeprom(struct wm_softc *);
 static int	wm_nvm_flash_presence_i210(struct wm_softc *);
 static int	wm_nvm_validate_checksum(struct wm_softc *);
 static void	wm_nvm_version_invm(struct wm_softc *);
 static void	wm_nvm_version(struct wm_softc *);
 static int	wm_nvm_read(struct wm_softc *, int, int, uint16_t *);
 /*
  * Hardware semaphores.
  * Very complexed...
  */
 static int	wm_get_null(struct wm_softc *);
 static void	wm_put_null(struct wm_softc *);
 static int	wm_get_eecd(struct wm_softc *);
 static void	wm_put_eecd(struct wm_softc *);
 static int	wm_get_swsm_semaphore(struct wm_softc *); /* 8257[123] */
 static void	wm_put_swsm_semaphore(struct wm_softc *);
 static int	wm_get_swfw_semaphore(struct wm_softc *, uint16_t);
 static void	wm_put_swfw_semaphore(struct wm_softc *, uint16_t);
 static int	wm_get_nvm_80003(struct wm_softc *);
 static void	wm_put_nvm_80003(struct wm_softc *);
 static int	wm_get_nvm_82571(struct wm_softc *);
 static void	wm_put_nvm_82571(struct wm_softc *);
 static int	wm_get_phy_82575(struct wm_softc *);
 static void	wm_put_phy_82575(struct wm_softc *);
 static int	wm_get_swfwhw_semaphore(struct wm_softc *); /* For 574/583 */
 static void	wm_put_swfwhw_semaphore(struct wm_softc *);
 static int	wm_get_swflag_ich8lan(struct wm_softc *);	/* For PHY */
 static void	wm_put_swflag_ich8lan(struct wm_softc *);
 static int	wm_get_nvm_ich8lan(struct wm_softc *);
 static void	wm_put_nvm_ich8lan(struct wm_softc *);
 static int	wm_get_hw_semaphore_82573(struct wm_softc *);
 static void	wm_put_hw_semaphore_82573(struct wm_softc *);
 /*
  * Management mode and power management related subroutines.
  * BMC, AMT, suspend/resume and EEE.
  */
 #if 0
 static int	wm_check_mng_mode(struct wm_softc *);
 static int	wm_check_mng_mode_ich8lan(struct wm_softc *);
 static int	wm_check_mng_mode_82574(struct wm_softc *);
 static int	wm_check_mng_mode_generic(struct wm_softc *);
 #endif
 static int	wm_enable_mng_pass_thru(struct wm_softc *);
 static bool	wm_phy_resetisblocked(struct wm_softc *);
 static void	wm_get_hw_control(struct wm_softc *);
 static void	wm_release_hw_control(struct wm_softc *);
 static void	wm_gate_hw_phy_config_ich8lan(struct wm_softc *, bool);
 static int	wm_init_phy_workarounds_pchlan(struct wm_softc *);
 static void	wm_init_manageability(struct wm_softc *);
 static void	wm_release_manageability(struct wm_softc *);
 static void	wm_get_wakeup(struct wm_softc *);
 static int	wm_ulp_disable(struct wm_softc *);
 static int	wm_enable_phy_wakeup(struct wm_softc *);
 static void	wm_igp3_phy_powerdown_workaround_ich8lan(struct wm_softc *);
 static void	wm_suspend_workarounds_ich8lan(struct wm_softc *);
 static int	wm_resume_workarounds_pchlan(struct wm_softc *);
 static void	wm_enable_wakeup(struct wm_softc *);
 static void	wm_disable_aspm(struct wm_softc *);
 /* LPLU (Low Power Link Up) */
 static void	wm_lplu_d0_disable(struct wm_softc *);
 /* EEE */
 static void	wm_set_eee_i350(struct wm_softc *);
 /*
  * Workarounds (mainly PHY related).
  * Basically, PHY's workarounds are in the PHY drivers.
  */
 static void	wm_kmrn_lock_loss_workaround_ich8lan(struct wm_softc *);
 static void	wm_gig_downshift_workaround_ich8lan(struct wm_softc *);
 static void	wm_hv_phy_workarounds_ich8lan(struct wm_softc *);
 static void	wm_copy_rx_addrs_to_phy_ich8lan(struct wm_softc *);
 static void	wm_lv_phy_workarounds_ich8lan(struct wm_softc *);
 static int	wm_k1_workaround_lpt_lp(struct wm_softc *, bool);
 static int	wm_k1_gig_workaround_hv(struct wm_softc *, int);
 static int	wm_k1_workaround_lv(struct wm_softc *);
 static int	wm_link_stall_workaround_hv(struct wm_softc *);
 static void	wm_set_mdio_slow_mode_hv(struct wm_softc *);
 static void	wm_set_mdio_slow_mode_hv_locked(struct wm_softc *);
 static void	wm_configure_k1_ich8lan(struct wm_softc *, int);
 static void	wm_reset_init_script_82575(struct wm_softc *);
 static void	wm_reset_mdicnfg_82580(struct wm_softc *);
 static bool	wm_phy_is_accessible_pchlan(struct wm_softc *);
 static void	wm_toggle_lanphypc_pch_lpt(struct wm_softc *);
 static int	wm_platform_pm_pch_lpt(struct wm_softc *, bool);
 static void	wm_pll_workaround_i210(struct wm_softc *);
 static void	wm_legacy_irq_quirk_spt(struct wm_softc *);
 static bool	wm_phy_need_linkdown_discard(struct wm_softc *);
 static void	wm_set_linkdown_discard(struct wm_softc *);
 static void	wm_clear_linkdown_discard(struct wm_softc *);
 static int	wm_sysctl_tdh_handler(SYSCTLFN_PROTO);
 static int	wm_sysctl_tdt_handler(SYSCTLFN_PROTO);
 #ifdef WM_DEBUG
 static int	wm_sysctl_debug(SYSCTLFN_PROTO);
 #endif
 CFATTACH_DECL3_NEW(wm, sizeof(struct wm_softc),
     wm_match, wm_attach, wm_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN);
 /*
  * Devices supported by this driver.
  */
 static const struct wm_product {
 	pci_vendor_id_t		wmp_vendor;
 	pci_product_id_t	wmp_product;
 	const char		*wmp_name;
 	wm_chip_type		wmp_type;
 	uint32_t		wmp_flags;
 #define	WMP_F_UNKNOWN		WM_MEDIATYPE_UNKNOWN
 #define	WMP_F_FIBER		WM_MEDIATYPE_FIBER
 #define	WMP_F_COPPER		WM_MEDIATYPE_COPPER
 #define	WMP_F_SERDES		WM_MEDIATYPE_SERDES
 #define WMP_MEDIATYPE(x)	((x) & 0x03)
 } wm_products[] = {
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82542,
 	  "Intel i82542 1000BASE-X Ethernet",
 	  WM_T_82542_2_1,	WMP_F_FIBER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82543GC_FIBER,
 	  "Intel i82543GC 1000BASE-X Ethernet",
 	  WM_T_82543,		WMP_F_FIBER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82543GC_COPPER,
 	  "Intel i82543GC 1000BASE-T Ethernet",
 	  WM_T_82543,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82544EI_COPPER,
 	  "Intel i82544EI 1000BASE-T Ethernet",
 	  WM_T_82544,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82544EI_FIBER,
 	  "Intel i82544EI 1000BASE-X Ethernet",
 	  WM_T_82544,		WMP_F_FIBER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82544GC_COPPER,
 	  "Intel i82544GC 1000BASE-T Ethernet",
 	  WM_T_82544,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82544GC_LOM,
 	  "Intel i82544GC (LOM) 1000BASE-T Ethernet",
 	  WM_T_82544,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82540EM,
 	  "Intel i82540EM 1000BASE-T Ethernet",
 	  WM_T_82540,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82540EM_LOM,
 	  "Intel i82540EM (LOM) 1000BASE-T Ethernet",
 	  WM_T_82540,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82540EP_LOM,
 	  "Intel i82540EP 1000BASE-T Ethernet",
 	  WM_T_82540,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82540EP,
 	  "Intel i82540EP 1000BASE-T Ethernet",
 	  WM_T_82540,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82540EP_LP,
 	  "Intel i82540EP 1000BASE-T Ethernet",
 	  WM_T_82540,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82545EM_COPPER,
 	  "Intel i82545EM 1000BASE-T Ethernet",
 	  WM_T_82545,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82545GM_COPPER,
 	  "Intel i82545GM 1000BASE-T Ethernet",
 	  WM_T_82545_3,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82545GM_FIBER,
 	  "Intel i82545GM 1000BASE-X Ethernet",
 	  WM_T_82545_3,		WMP_F_FIBER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82545GM_SERDES,
 	  "Intel i82545GM Gigabit Ethernet (SERDES)",
 	  WM_T_82545_3,		WMP_F_SERDES },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546EB_COPPER,
 	  "Intel i82546EB 1000BASE-T Ethernet",
 	  WM_T_82546,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546EB_QUAD,
 	  "Intel i82546EB 1000BASE-T Ethernet",
 	  WM_T_82546,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82545EM_FIBER,
 	  "Intel i82545EM 1000BASE-X Ethernet",
 	  WM_T_82545,		WMP_F_FIBER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546EB_FIBER,
 	  "Intel i82546EB 1000BASE-X Ethernet",
 	  WM_T_82546,		WMP_F_FIBER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546GB_COPPER,
 	  "Intel i82546GB 1000BASE-T Ethernet",
 	  WM_T_82546_3,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546GB_FIBER,
 	  "Intel i82546GB 1000BASE-X Ethernet",
 	  WM_T_82546_3,		WMP_F_FIBER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546GB_SERDES,
 	  "Intel i82546GB Gigabit Ethernet (SERDES)",
 	  WM_T_82546_3,		WMP_F_SERDES },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546GB_QUAD_COPPER,
 	  "i82546GB quad-port Gigabit Ethernet",
 	  WM_T_82546_3,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546GB_QUAD_COPPER_KSP3,
 	  "i82546GB quad-port Gigabit Ethernet (KSP3)",
 	  WM_T_82546_3,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546GB_PCIE,
 	  "Intel PRO/1000MT (82546GB)",
 	  WM_T_82546_3,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541EI,
 	  "Intel i82541EI 1000BASE-T Ethernet",
 	  WM_T_82541,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541ER_LOM,
 	  "Intel i82541ER (LOM) 1000BASE-T Ethernet",
 	  WM_T_82541,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541EI_MOBILE,
 	  "Intel i82541EI Mobile 1000BASE-T Ethernet",
 	  WM_T_82541,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541ER,
 	  "Intel i82541ER 1000BASE-T Ethernet",
 	  WM_T_82541_2,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541GI,
 	  "Intel i82541GI 1000BASE-T Ethernet",
 	  WM_T_82541_2,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541GI_MOBILE,
 	  "Intel i82541GI Mobile 1000BASE-T Ethernet",
 	  WM_T_82541_2,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541PI,
 	  "Intel i82541PI 1000BASE-T Ethernet",
 	  WM_T_82541_2,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82547EI,
 	  "Intel i82547EI 1000BASE-T Ethernet",
 	  WM_T_82547,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82547EI_MOBILE,
 	  "Intel i82547EI Mobile 1000BASE-T Ethernet",
 	  WM_T_82547,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82547GI,
 	  "Intel i82547GI 1000BASE-T Ethernet",
 	  WM_T_82547_2,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82571EB_COPPER,
 	  "Intel PRO/1000 PT (82571EB)",
 	  WM_T_82571,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82571EB_FIBER,
 	  "Intel PRO/1000 PF (82571EB)",
 	  WM_T_82571,		WMP_F_FIBER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82571EB_SERDES,
 	  "Intel PRO/1000 PB (82571EB)",
 	  WM_T_82571,		WMP_F_SERDES },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82571EB_QUAD_COPPER,
 	  "Intel PRO/1000 QT (82571EB)",
 	  WM_T_82571,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82571GB_QUAD_COPPER,
 	  "Intel PRO/1000 PT Quad Port Server Adapter",
 	  WM_T_82571,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82571PT_QUAD_COPPER,
 	  "Intel Gigabit PT Quad Port Server ExpressModule",
 	  WM_T_82571,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82571EB_DUAL_SERDES,
 	  "Intel 82571EB Dual Gigabit Ethernet (SERDES)",
 	  WM_T_82571,		WMP_F_SERDES },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82571EB_QUAD_SERDES,
 	  "Intel 82571EB Quad Gigabit Ethernet (SERDES)",
 	  WM_T_82571,		WMP_F_SERDES },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82571EB_QUAD_FIBER,
 	  "Intel 82571EB Quad 1000baseX Ethernet",
 	  WM_T_82571,		WMP_F_FIBER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82572EI_COPPER,
 	  "Intel i82572EI 1000baseT Ethernet",
 	  WM_T_82572,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82572EI_FIBER,
 	  "Intel i82572EI 1000baseX Ethernet",
 	  WM_T_82572,		WMP_F_FIBER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82572EI_SERDES,
 	  "Intel i82572EI Gigabit Ethernet (SERDES)",
 	  WM_T_82572,		WMP_F_SERDES },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82572EI,
 	  "Intel i82572EI 1000baseT Ethernet",
 	  WM_T_82572,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82573E,
 	  "Intel i82573E",
 	  WM_T_82573,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82573E_IAMT,
 	  "Intel i82573E IAMT",
 	  WM_T_82573,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82573L,
 	  "Intel i82573L Gigabit Ethernet",
 	  WM_T_82573,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82574L,
 	  "Intel i82574L",
 	  WM_T_82574,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82574LA,
 	  "Intel i82574L",
 	  WM_T_82574,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82583V,
 	  "Intel i82583V",
 	  WM_T_82583,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_80K3LAN_CPR_DPT,
 	  "i80003 dual 1000baseT Ethernet",
 	  WM_T_80003,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_80K3LAN_FIB_DPT,
 	  "i80003 dual 1000baseX Ethernet",
 	  WM_T_80003,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_80K3LAN_SDS_DPT,
 	  "Intel i80003ES2 dual Gigabit Ethernet (SERDES)",
 	  WM_T_80003,		WMP_F_SERDES },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_80K3LAN_CPR_SPT,
 	  "Intel i80003 1000baseT Ethernet",
 	  WM_T_80003,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_80K3LAN_SDS_SPT,
 	  "Intel i80003 Gigabit Ethernet (SERDES)",
 	  WM_T_80003,		WMP_F_SERDES },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801H_M_AMT,
 	  "Intel i82801H (M_AMT) LAN Controller",
 	  WM_T_ICH8,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801H_AMT,
 	  "Intel i82801H (AMT) LAN Controller",
 	  WM_T_ICH8,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801H_LAN,
 	  "Intel i82801H LAN Controller",
 	  WM_T_ICH8,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801H_IFE_LAN,
 	  "Intel i82801H (IFE) 10/100 LAN Controller",
 	  WM_T_ICH8,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801H_M_LAN,
 	  "Intel i82801H (M) LAN Controller",
 	  WM_T_ICH8,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801H_IFE_GT,
 	  "Intel i82801H IFE (GT) 10/100 LAN Controller",
 	  WM_T_ICH8,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801H_IFE_G,
 	  "Intel i82801H IFE (G) 10/100 LAN Controller",
 	  WM_T_ICH8,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801H_82567V_3,
 	  "82567V-3 LAN Controller",
 	  WM_T_ICH8,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_IGP_AMT,
 	  "82801I (AMT) LAN Controller",
 	  WM_T_ICH9,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_IFE,
 	  "82801I 10/100 LAN Controller",
 	  WM_T_ICH9,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_IFE_G,
 	  "82801I (G) 10/100 LAN Controller",
 	  WM_T_ICH9,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_IFE_GT,
 	  "82801I (GT) 10/100 LAN Controller",
 	  WM_T_ICH9,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_IGP_C,
 	  "82801I (C) LAN Controller",
 	  WM_T_ICH9,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_IGP_M,
 	  "82801I mobile LAN Controller",
 	  WM_T_ICH9,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_IGP_M_V,
 	  "82801I mobile (V) LAN Controller",
 	  WM_T_ICH9,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_IGP_M_AMT,
 	  "82801I mobile (AMT) LAN Controller",
 	  WM_T_ICH9,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_BM,
 	  "82567LM-4 LAN Controller",
 	  WM_T_ICH9,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801J_R_BM_LM,
 	  "82567LM-2 LAN Controller",
 	  WM_T_ICH10,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801J_R_BM_LF,
 	  "82567LF-2 LAN Controller",
 	  WM_T_ICH10,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801J_D_BM_LM,
 	  "82567LM-3 LAN Controller",
 	  WM_T_ICH10,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801J_D_BM_LF,
 @@ -1697,1998 +1697,2002 @@ static const struct wm_product {
 	  "I219 LM (7) Ethernet Connection",
 	  WM_T_PCH_CNP,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_LM8,
 	  "I219 LM (8) Ethernet Connection",
 	  WM_T_PCH_CNP,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_LM9,
 	  "I219 LM (9) Ethernet Connection",
 	  WM_T_PCH_CNP,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_LM10,
 	  "I219 LM (10) Ethernet Connection",
 	  WM_T_PCH_CNP,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_LM11,
 	  "I219 LM (11) Ethernet Connection",
 	  WM_T_PCH_CNP,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_LM12,
 	  "I219 LM (12) Ethernet Connection",
 	  WM_T_PCH_SPT,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_LM13,
 	  "I219 LM (13) Ethernet Connection",
 	  WM_T_PCH_TGP,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_LM14,
 	  "I219 LM (14) Ethernet Connection",
 	  WM_T_PCH_TGP,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_LM15,
 	  "I219 LM (15) Ethernet Connection",
 	  WM_T_PCH_TGP,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_LM16,
 	  "I219 LM (16) Ethernet Connection",
 	  WM_T_PCH_TGP,		WMP_F_COPPER }, /* ADP */
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_LM17,
 	  "I219 LM (17) Ethernet Connection",
 	  WM_T_PCH_TGP,		WMP_F_COPPER }, /* ADP */
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_LM18,
 	  "I219 LM (18) Ethernet Connection",
 	  WM_T_PCH_TGP,		WMP_F_COPPER }, /* MTP */
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_LM19,
 	  "I219 LM (19) Ethernet Connection",
 	  WM_T_PCH_TGP,		WMP_F_COPPER }, /* MTP */
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_LM20,
 	  "I219 LM (20) Ethernet Connection",
 	  WM_T_PCH_TGP,		WMP_F_COPPER }, /* MTP */
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_LM21,
 	  "I219 LM (21) Ethernet Connection",
 	  WM_T_PCH_TGP,		WMP_F_COPPER }, /* MTP */
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_LM22,
 	  "I219 LM (22) Ethernet Connection",
 	  WM_T_PCH_TGP,		WMP_F_COPPER }, /* ADP(RPL) */
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_LM23,
 	  "I219 LM (23) Ethernet Connection",
 	  WM_T_PCH_TGP,		WMP_F_COPPER }, /* ADP(RPL) */
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_V,
 	  "I219 V Ethernet Connection",
 	  WM_T_PCH_SPT,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_V2,
 	  "I219 V (2) Ethernet Connection",
 	  WM_T_PCH_SPT,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_V4,
 	  "I219 V (4) Ethernet Connection",
 	  WM_T_PCH_SPT,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_V5,
 	  "I219 V (5) Ethernet Connection",
 	  WM_T_PCH_SPT,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_V6,
 	  "I219 V (6) Ethernet Connection",
 	  WM_T_PCH_CNP,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_V7,
 	  "I219 V (7) Ethernet Connection",
 	  WM_T_PCH_CNP,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_V8,
 	  "I219 V (8) Ethernet Connection",
 	  WM_T_PCH_CNP,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_V9,
 	  "I219 V (9) Ethernet Connection",
 	  WM_T_PCH_CNP,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_V10,
 	  "I219 V (10) Ethernet Connection",
 	  WM_T_PCH_CNP,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_V11,
 	  "I219 V (11) Ethernet Connection",
 	  WM_T_PCH_CNP,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_V12,
 	  "I219 V (12) Ethernet Connection",
 	  WM_T_PCH_SPT,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_V13,
 	  "I219 V (13) Ethernet Connection",
 	  WM_T_PCH_TGP,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_V14,
 	  "I219 V (14) Ethernet Connection",
 	  WM_T_PCH_TGP,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_V15,
 	  "I219 V (15) Ethernet Connection",
 	  WM_T_PCH_TGP,		WMP_F_COPPER },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_V16,
 	  "I219 V (16) Ethernet Connection",
 	  WM_T_PCH_TGP,		WMP_F_COPPER }, /* ADP */
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_V17,
 	  "I219 V (17) Ethernet Connection",
 	  WM_T_PCH_TGP,		WMP_F_COPPER }, /* ADP */
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_V18,
 	  "I219 V (18) Ethernet Connection",
 	  WM_T_PCH_TGP,		WMP_F_COPPER }, /* MTP */
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_V19,
 	  "I219 V (19) Ethernet Connection",
 	  WM_T_PCH_TGP,		WMP_F_COPPER }, /* MTP */
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_V20,
 	  "I219 V (20) Ethernet Connection",
 	  WM_T_PCH_TGP,		WMP_F_COPPER }, /* MTP */
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_V21,
 	  "I219 V (21) Ethernet Connection",
 	  WM_T_PCH_TGP,		WMP_F_COPPER }, /* MTP */
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_V22,
 	  "I219 V (22) Ethernet Connection",
 	  WM_T_PCH_TGP,		WMP_F_COPPER }, /* ADP(RPL) */
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_V23,
 	  "I219 V (23) Ethernet Connection",
 	  WM_T_PCH_TGP,		WMP_F_COPPER }, /* ADP(RPL) */
 	{ 0,			0,
 	  NULL,
 ,			0 },
 };
 /*
  * Register read/write functions.
  * Other than CSR_{READ|WRITE}().
  */
 #if 0 /* Not currently used */
 static inline uint32_t
 wm_io_read(struct wm_softc *sc, int reg)
+{
 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg);
 	return (bus_space_read_4(sc->sc_iot, sc->sc_ioh, 4));
+}
 #endif
 static inline void
 wm_io_write(struct wm_softc *sc, int reg, uint32_t val)
+{
 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg);
 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, 4, val);
+}
 static inline void
 wm_82575_write_8bit_ctlr_reg(struct wm_softc *sc, uint32_t reg, uint32_t off,
     uint32_t data)
+{
 	uint32_t regval;
 	int i;
 	regval = (data & SCTL_CTL_DATA_MASK) | (off << SCTL_CTL_ADDR_SHIFT);
 	CSR_WRITE(sc, reg, regval);
 	for (i = 0; i < SCTL_CTL_POLL_TIMEOUT; i++) {
 		delay(5);
 		if (CSR_READ(sc, reg) & SCTL_CTL_READY)
 			break;
+	}
 	if (i == SCTL_CTL_POLL_TIMEOUT) {
 		aprint_error("%s: WARNING:"
 		    " i82575 reg 0x%08x setup did not indicate ready\n",
 		    device_xname(sc->sc_dev), reg);
+	}
+}
 static inline void
 wm_set_dma_addr(volatile wiseman_addr_t *wa, bus_addr_t v)
+{
 	wa->wa_low = htole32(v & 0xffffffffU);
 	if (sizeof(bus_addr_t) == 8)
 		wa->wa_high = htole32((uint64_t) v >> 32);
 	else
 		wa->wa_high = 0;
+}
 /*
  * Descriptor sync/init functions.
  */
 static inline void
 wm_cdtxsync(struct wm_txqueue *txq, int start, int num, int ops)
+{
 	struct wm_softc *sc = txq->txq_sc;
 	/* If it will wrap around, sync to the end of the ring. */
 	if ((start + num) > WM_NTXDESC(txq)) {
 		bus_dmamap_sync(sc->sc_dmat, txq->txq_desc_dmamap,
 		    WM_CDTXOFF(txq, start), txq->txq_descsize *
 		    (WM_NTXDESC(txq) - start), ops);
 		num -= (WM_NTXDESC(txq) - start);
 		start = 0;
+	}
 	/* Now sync whatever is left. */
 	bus_dmamap_sync(sc->sc_dmat, txq->txq_desc_dmamap,
 	    WM_CDTXOFF(txq, start), txq->txq_descsize * num, ops);
+}
 static inline void
 wm_cdrxsync(struct wm_rxqueue *rxq, int start, int ops)
+{
 	struct wm_softc *sc = rxq->rxq_sc;
 	bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_dmamap,
 	    WM_CDRXOFF(rxq, start), rxq->rxq_descsize, ops);
+}
 static inline void
 wm_init_rxdesc(struct wm_rxqueue *rxq, int start)
+{
 	struct wm_softc *sc = rxq->rxq_sc;
 	struct wm_rxsoft *rxs = &rxq->rxq_soft[start];
 	struct mbuf *m = rxs->rxs_mbuf;
 	/*
 	 * Note: We scoot the packet forward 2 bytes in the buffer
 	 * so that the payload after the Ethernet header is aligned
 	 * to a 4-byte boundary.
 	 * XXX BRAINDAMAGE ALERT!
 	 * The stupid chip uses the same size for every buffer, which
 	 * is set in the Receive Control register.  We are using the 2K
 	 * size option, but what we REALLY want is (2K - 2)!  For this
 	 * reason, we can't "scoot" packets longer than the standard
 	 * Ethernet MTU.  On strict-alignment platforms, if the total
 	 * size exceeds (2K - 2) we set align_tweak to 0 and let
 	 * the upper layer copy the headers.
 	 */
 	m->m_data = m->m_ext.ext_buf + sc->sc_align_tweak;
 	if (sc->sc_type == WM_T_82574) {
 		ext_rxdesc_t *rxd = &rxq->rxq_ext_descs[start];
 		rxd->erx_data.erxd_addr =
 		    htole64(rxs->rxs_dmamap->dm_segs[0].ds_addr + sc->sc_align_tweak);
 		rxd->erx_data.erxd_dd = 0;
 	} else if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) {
 		nq_rxdesc_t *rxd = &rxq->rxq_nq_descs[start];
 		rxd->nqrx_data.nrxd_paddr =
 		    htole64(rxs->rxs_dmamap->dm_segs[0].ds_addr + sc->sc_align_tweak);
 		/* Currently, split header is not supported. */
 		rxd->nqrx_data.nrxd_haddr = 0;
 	} else {
 		wiseman_rxdesc_t *rxd = &rxq->rxq_descs[start];
 		wm_set_dma_addr(&rxd->wrx_addr,
 		    rxs->rxs_dmamap->dm_segs[0].ds_addr + sc->sc_align_tweak);
 		rxd->wrx_len = 0;
 		rxd->wrx_cksum = 0;
 		rxd->wrx_status = 0;
 		rxd->wrx_errors = 0;
 		rxd->wrx_special = 0;
+	}
 	wm_cdrxsync(rxq, start, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 	CSR_WRITE(sc, rxq->rxq_rdt_reg, start);
+}
 /*
  * Device driver interface functions and commonly used functions.
  * match, attach, detach, init, start, stop, ioctl, watchdog and so on.
  */
 /* Lookup supported device table */
 static const struct wm_product *
 wm_lookup(const struct pci_attach_args *pa)
+{
 	const struct wm_product *wmp;
 	for (wmp = wm_products; wmp->wmp_name != NULL; wmp++) {
 		if (PCI_VENDOR(pa->pa_id) == wmp->wmp_vendor &&
 		    PCI_PRODUCT(pa->pa_id) == wmp->wmp_product)
 			return wmp;
+	}
 	return NULL;
+}
 /* The match function (ca_match) */
 static int
 wm_match(device_t parent, cfdata_t cf, void *aux)
+{
 	struct pci_attach_args *pa = aux;
 	if (wm_lookup(pa) != NULL)
 		return 1;
 	return 0;
+}
 /* The attach function (ca_attach) */
 static void
 wm_attach(device_t parent, device_t self, void *aux)
+{
 	struct wm_softc *sc = device_private(self);
 	struct pci_attach_args *pa = aux;
 	prop_dictionary_t dict;
 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
 	pci_chipset_tag_t pc = pa->pa_pc;
 	int counts[PCI_INTR_TYPE_SIZE];
 	pci_intr_type_t max_type;
 	const char *eetype, *xname;
 	bus_space_tag_t memt;
 	bus_space_handle_t memh;
 	bus_size_t memsize;
 	int memh_valid;
 	int i, error;
 	const struct wm_product *wmp;
 	prop_data_t ea;
 	prop_number_t pn;
 	uint8_t enaddr[ETHER_ADDR_LEN];
 	char buf[256];
 	char wqname[MAXCOMLEN];
 	uint16_t cfg1, cfg2, swdpin, nvmword;
 	pcireg_t preg, memtype;
 	uint16_t eeprom_data, apme_mask;
 	bool force_clear_smbi;
 	uint32_t link_mode;
 	uint32_t reg;
 #if defined(WM_DEBUG) && defined(WM_DEBUG_DEFAULT)
 	sc->sc_debug = WM_DEBUG_DEFAULT;
 #endif
 	sc->sc_dev = self;
 	callout_init(&sc->sc_tick_ch, WM_CALLOUT_FLAGS);
 	sc->sc_core_stopping = false;
 	wmp = wm_lookup(pa);
 #ifdef DIAGNOSTIC
 	if (wmp == NULL) {
 		printf("\n");
 		panic("wm_attach: impossible");
+	}
 #endif
 	sc->sc_mediatype = WMP_MEDIATYPE(wmp->wmp_flags);
 	sc->sc_pc = pa->pa_pc;
 	sc->sc_pcitag = pa->pa_tag;
 	if (pci_dma64_available(pa)) {
 		aprint_verbose(", 64-bit DMA");
 		sc->sc_dmat = pa->pa_dmat64;
 	} else {
 		aprint_verbose(", 32-bit DMA");
 		sc->sc_dmat = pa->pa_dmat;
+	}
 	sc->sc_pcidevid = PCI_PRODUCT(pa->pa_id);
 	sc->sc_rev = PCI_REVISION(pci_conf_read(pc, pa->pa_tag,PCI_CLASS_REG));
 	pci_aprint_devinfo_fancy(pa, "Ethernet controller", wmp->wmp_name, 1);
 	sc->sc_type = wmp->wmp_type;
 	/* Set default function pointers */
 	sc->phy.acquire = sc->nvm.acquire = wm_get_null;
 	sc->phy.release = sc->nvm.release = wm_put_null;
 	sc->phy.reset_delay_us = (sc->sc_type >= WM_T_82571) ? 100 : 10000;
 	if (sc->sc_type < WM_T_82543) {
 		if (sc->sc_rev < 2) {
 			aprint_error_dev(sc->sc_dev,
 			    "i82542 must be at least rev. 2\n");
 			return;
+		}
 		if (sc->sc_rev < 3)
 			sc->sc_type = WM_T_82542_2_0;
+	}
 	/*
 	 * Disable MSI for Errata:
 	 * "Message Signaled Interrupt Feature May Corrupt Write Transactions"
+	 *
 	 *  82544: Errata 25
 	 *  82540: Errata  6 (easy to reproduce device timeout)
 	 *  82545: Errata  4 (easy to reproduce device timeout)
 	 *  82546: Errata 26 (easy to reproduce device timeout)
 	 *  82541: Errata  7 (easy to reproduce device timeout)
+	 *
 	 * "Byte Enables 2 and 3 are not set on MSI writes"
+	 *
 	 *  82571 & 82572: Errata 63
 	 */
 	if ((sc->sc_type <= WM_T_82541_2) || (sc->sc_type == WM_T_82571)
 	    || (sc->sc_type == WM_T_82572))
 		pa->pa_flags &= ~PCI_FLAGS_MSI_OKAY;
 	if ((sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576)
 	    || (sc->sc_type == WM_T_82580)
 	    || (sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354)
 	    || (sc->sc_type == WM_T_I210) || (sc->sc_type == WM_T_I211))
 		sc->sc_flags |= WM_F_NEWQUEUE;
 	/* Set device properties (mactype) */
 	dict = device_properties(sc->sc_dev);
 	prop_dictionary_set_uint32(dict, "mactype", sc->sc_type);
 	/*
 	 * Map the device.  All devices support memory-mapped acccess,
 	 * and it is really required for normal operation.
 	 */
 	memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, WM_PCI_MMBA);
 	switch (memtype) {
 	case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT:
 	case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT:
 		memh_valid = (pci_mapreg_map(pa, WM_PCI_MMBA,
 			memtype, 0, &memt, &memh, NULL, &memsize) == 0);
 		break;
 	default:
 		memh_valid = 0;
 		break;
+	}
 	if (memh_valid) {
 		sc->sc_st = memt;
 		sc->sc_sh = memh;
 		sc->sc_ss = memsize;
 	} else {
 		aprint_error_dev(sc->sc_dev,
 		    "unable to map device registers\n");
 		return;
+	}
 	/*
 	 * In addition, i82544 and later support I/O mapped indirect
 	 * register access.  It is not desirable (nor supported in
 	 * this driver) to use it for normal operation, though it is
 	 * required to work around bugs in some chip versions.
 	 */
 	switch (sc->sc_type) {
 	case WM_T_82544:
 	case WM_T_82541:
 	case WM_T_82541_2:
 	case WM_T_82547:
 	case WM_T_82547_2:
 		/* First we have to find the I/O BAR. */
 		for (i = PCI_MAPREG_START; i < PCI_MAPREG_END; i += 4) {
 			memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, i);
 			if (memtype == PCI_MAPREG_TYPE_IO)
 				break;
 			if (PCI_MAPREG_MEM_TYPE(memtype) ==
 			    PCI_MAPREG_MEM_TYPE_64BIT)
 				i += 4;	/* skip high bits, too */
+		}
 		if (i < PCI_MAPREG_END) {
 			/*
 			 * We found PCI_MAPREG_TYPE_IO. Note that 82580
 			 * (and newer?) chip has no PCI_MAPREG_TYPE_IO.
 			 * It's no problem because newer chips has no this
 			 * bug.
+			 *
 			 * The i8254x doesn't apparently respond when the
 			 * I/O BAR is 0, which looks somewhat like it's not
 			 * been configured.
 			 */
 			preg = pci_conf_read(pc, pa->pa_tag, i);
 			if (PCI_MAPREG_MEM_ADDR(preg) == 0) {
 				aprint_error_dev(sc->sc_dev,
 				    "WARNING: I/O BAR at zero.\n");
 			} else if (pci_mapreg_map(pa, i, PCI_MAPREG_TYPE_IO,
 , &sc->sc_iot, &sc->sc_ioh, NULL, &sc->sc_ios)
 			    == 0) {
 				sc->sc_flags |= WM_F_IOH_VALID;
 			} else
 				aprint_error_dev(sc->sc_dev,
 				    "WARNING: unable to map I/O space\n");
+		}
 		break;
 	default:
 		break;
+	}
 	/* Enable bus mastering.  Disable MWI on the i82542 2.0. */
 	preg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
 	preg |= PCI_COMMAND_MASTER_ENABLE;
 	if (sc->sc_type < WM_T_82542_2_1)
 		preg &= ~PCI_COMMAND_INVALIDATE_ENABLE;
 	pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, preg);
 	/* Power up chip */
 	if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, NULL))
 	    && error != EOPNOTSUPP) {
 		aprint_error_dev(sc->sc_dev, "cannot activate %d\n", error);
 		return;
+	}
 	wm_adjust_qnum(sc, pci_msix_count(pa->pa_pc, pa->pa_tag));
 	/*
 	 *  Don't use MSI-X if we can use only one queue to save interrupt
 	 * resource.
 	 */
 	if (sc->sc_nqueues > 1) {
 		max_type = PCI_INTR_TYPE_MSIX;
 		/*
 		 *  82583 has a MSI-X capability in the PCI configuration space
 		 * but it doesn't support it. At least the document doesn't
 		 * say anything about MSI-X.
 		 */
 		counts[PCI_INTR_TYPE_MSIX]
 		    = (sc->sc_type == WM_T_82583) ? 0 : sc->sc_nqueues + 1;
 	} else {
 		max_type = PCI_INTR_TYPE_MSI;
 		counts[PCI_INTR_TYPE_MSIX] = 0;
+	}
 	/* Allocation settings */
 	counts[PCI_INTR_TYPE_MSI] = 1;
 	counts[PCI_INTR_TYPE_INTX] = 1;
 	/* overridden by disable flags */
 	if (wm_disable_msi != 0) {
 		counts[PCI_INTR_TYPE_MSI] = 0;
 		if (wm_disable_msix != 0) {
 			max_type = PCI_INTR_TYPE_INTX;
 			counts[PCI_INTR_TYPE_MSIX] = 0;
+		}
 	} else if (wm_disable_msix != 0) {
 		max_type = PCI_INTR_TYPE_MSI;
 		counts[PCI_INTR_TYPE_MSIX] = 0;
+	}
 alloc_retry:
 	if (pci_intr_alloc(pa, &sc->sc_intrs, counts, max_type) != 0) {
 		aprint_error_dev(sc->sc_dev, "failed to allocate interrupt\n");
 		return;
+	}
 	if (pci_intr_type(pc, sc->sc_intrs[0]) == PCI_INTR_TYPE_MSIX) {
 		error = wm_setup_msix(sc);
 		if (error) {
 			pci_intr_release(pc, sc->sc_intrs,
 			    counts[PCI_INTR_TYPE_MSIX]);
 			/* Setup for MSI: Disable MSI-X */
 			max_type = PCI_INTR_TYPE_MSI;
 			counts[PCI_INTR_TYPE_MSI] = 1;
 			counts[PCI_INTR_TYPE_INTX] = 1;
 			goto alloc_retry;
+		}
 	} else if (pci_intr_type(pc, sc->sc_intrs[0]) == PCI_INTR_TYPE_MSI) {
 		wm_adjust_qnum(sc, 0);	/* Must not use multiqueue */
 		error = wm_setup_legacy(sc);
 		if (error) {
 			pci_intr_release(sc->sc_pc, sc->sc_intrs,
 			    counts[PCI_INTR_TYPE_MSI]);
 			/* The next try is for INTx: Disable MSI */
 			max_type = PCI_INTR_TYPE_INTX;
 			counts[PCI_INTR_TYPE_INTX] = 1;
 			goto alloc_retry;
+		}
 	} else {
 		wm_adjust_qnum(sc, 0);	/* Must not use multiqueue */
 		error = wm_setup_legacy(sc);
 		if (error) {
 			pci_intr_release(sc->sc_pc, sc->sc_intrs,
 			    counts[PCI_INTR_TYPE_INTX]);
 			return;
+		}
+	}
 	snprintf(wqname, sizeof(wqname), "%sTxRx", device_xname(sc->sc_dev));
 	error = workqueue_create(&sc->sc_queue_wq, wqname,
 	    wm_handle_queue_work, sc, WM_WORKQUEUE_PRI, IPL_NET,
 	    WM_WORKQUEUE_FLAGS);
 	if (error) {
 		aprint_error_dev(sc->sc_dev,
 		    "unable to create workqueue\n");
 		goto out;
+	}
 	/*
 	 * Check the function ID (unit number of the chip).
 	 */
 	if ((sc->sc_type == WM_T_82546) || (sc->sc_type == WM_T_82546_3)
 	    || (sc->sc_type == WM_T_82571) || (sc->sc_type == WM_T_80003)
 	    || (sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576)
 	    || (sc->sc_type == WM_T_82580)
 	    || (sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354))
 		sc->sc_funcid = (CSR_READ(sc, WMREG_STATUS)
 		    >> STATUS_FUNCID_SHIFT) & STATUS_FUNCID_MASK;
 	else
 		sc->sc_funcid = 0;
 	/*
 	 * Determine a few things about the bus we're connected to.
 	 */
 	if (sc->sc_type < WM_T_82543) {
 		/* We don't really know the bus characteristics here. */
 		sc->sc_bus_speed = 33;
 	} else if (sc->sc_type == WM_T_82547 || sc->sc_type == WM_T_82547_2) {
 		/*
 		 * CSA (Communication Streaming Architecture) is about as fast
 		 * a 32-bit 66MHz PCI Bus.
 		 */
 		sc->sc_flags |= WM_F_CSA;
 		sc->sc_bus_speed = 66;
 		aprint_verbose_dev(sc->sc_dev,
 		    "Communication Streaming Architecture\n");
 		if (sc->sc_type == WM_T_82547) {
 			callout_init(&sc->sc_txfifo_ch, WM_CALLOUT_FLAGS);
 			callout_setfunc(&sc->sc_txfifo_ch,
 			    wm_82547_txfifo_stall, sc);
 			aprint_verbose_dev(sc->sc_dev,
 			    "using 82547 Tx FIFO stall work-around\n");
+		}
 	} else if (sc->sc_type >= WM_T_82571) {
 		sc->sc_flags |= WM_F_PCIE;
 		if ((sc->sc_type != WM_T_ICH8) && (sc->sc_type != WM_T_ICH9)
 		    && (sc->sc_type != WM_T_ICH10)
 		    && (sc->sc_type != WM_T_PCH)
 		    && (sc->sc_type != WM_T_PCH2)
 		    && (sc->sc_type != WM_T_PCH_LPT)
 		    && (sc->sc_type != WM_T_PCH_SPT)
 		    && (sc->sc_type != WM_T_PCH_CNP)
 		    && (sc->sc_type != WM_T_PCH_TGP)) {
 			/* ICH* and PCH* have no PCIe capability registers */
 			if (pci_get_capability(pa->pa_pc, pa->pa_tag,
 				PCI_CAP_PCIEXPRESS, &sc->sc_pcixe_capoff,
 				NULL) == 0)
 				aprint_error_dev(sc->sc_dev,
 				    "unable to find PCIe capability\n");
+		}
 		aprint_verbose_dev(sc->sc_dev, "PCI-Express bus\n");
 	} else {
 		reg = CSR_READ(sc, WMREG_STATUS);
 		if (reg & STATUS_BUS64)
 			sc->sc_flags |= WM_F_BUS64;
 		if ((reg & STATUS_PCIX_MODE) != 0) {
 			pcireg_t pcix_cmd, pcix_sts, bytecnt, maxb;
 			sc->sc_flags |= WM_F_PCIX;
 			if (pci_get_capability(pa->pa_pc, pa->pa_tag,
 				PCI_CAP_PCIX, &sc->sc_pcixe_capoff, NULL) == 0)
 				aprint_error_dev(sc->sc_dev,
 				    "unable to find PCIX capability\n");
 			else if (sc->sc_type != WM_T_82545_3 &&
 			    sc->sc_type != WM_T_82546_3) {
 				/*
 				 * Work around a problem caused by the BIOS
 				 * setting the max memory read byte count
 				 * incorrectly.
 				 */
 				pcix_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag,
 				    sc->sc_pcixe_capoff + PCIX_CMD);
 				pcix_sts = pci_conf_read(pa->pa_pc, pa->pa_tag,
 				    sc->sc_pcixe_capoff + PCIX_STATUS);
 				bytecnt = (pcix_cmd & PCIX_CMD_BYTECNT_MASK) >>
 				    PCIX_CMD_BYTECNT_SHIFT;
 				maxb = (pcix_sts & PCIX_STATUS_MAXB_MASK) >>
 				    PCIX_STATUS_MAXB_SHIFT;
 				if (bytecnt > maxb) {
 					aprint_verbose_dev(sc->sc_dev,
 					    "resetting PCI-X MMRBC: %d -> %d\n",
 << bytecnt, 512 << maxb);
 					pcix_cmd = (pcix_cmd &
 					    ~PCIX_CMD_BYTECNT_MASK) |
 					    (maxb << PCIX_CMD_BYTECNT_SHIFT);
 					pci_conf_write(pa->pa_pc, pa->pa_tag,
 					    sc->sc_pcixe_capoff + PCIX_CMD,
 					    pcix_cmd);
+				}
+			}
+		}
 		/*
 		 * The quad port adapter is special; it has a PCIX-PCIX
 		 * bridge on the board, and can run the secondary bus at
 		 * a higher speed.
 		 */
 		if (wmp->wmp_product == PCI_PRODUCT_INTEL_82546EB_QUAD) {
 			sc->sc_bus_speed = (sc->sc_flags & WM_F_PCIX) ? 120
 								      : 66;
 		} else if (sc->sc_flags & WM_F_PCIX) {
 			switch (reg & STATUS_PCIXSPD_MASK) {
 			case STATUS_PCIXSPD_50_66:
 				sc->sc_bus_speed = 66;
 				break;
 			case STATUS_PCIXSPD_66_100:
 				sc->sc_bus_speed = 100;
 				break;
 			case STATUS_PCIXSPD_100_133:
 				sc->sc_bus_speed = 133;
 				break;
 			default:
 				aprint_error_dev(sc->sc_dev,
 				    "unknown PCIXSPD %d; assuming 66MHz\n",
 				    reg & STATUS_PCIXSPD_MASK);
 				sc->sc_bus_speed = 66;
 				break;
+			}
 		} else
 			sc->sc_bus_speed = (reg & STATUS_PCI66) ? 66 : 33;
 		aprint_verbose_dev(sc->sc_dev, "%d-bit %dMHz %s bus\n",
 		    (sc->sc_flags & WM_F_BUS64) ? 64 : 32, sc->sc_bus_speed,
 		    (sc->sc_flags & WM_F_PCIX) ? "PCIX" : "PCI");
+	}
 	/* clear interesting stat counters */
 	CSR_READ(sc, WMREG_COLC);
 	CSR_READ(sc, WMREG_RXERRC);
 	if ((sc->sc_type == WM_T_82574) || (sc->sc_type == WM_T_82583)
 	    || (sc->sc_type >= WM_T_ICH8))
 		sc->sc_ich_phymtx = mutex_obj_alloc(MUTEX_DEFAULT, IPL_NET);
 	if (sc->sc_type >= WM_T_ICH8)
 		sc->sc_ich_nvmmtx = mutex_obj_alloc(MUTEX_DEFAULT, IPL_NET);
 	/* Set PHY, NVM mutex related stuff */
 	switch (sc->sc_type) {
 	case WM_T_82542_2_0:
 	case WM_T_82542_2_1:
 	case WM_T_82543:
 	case WM_T_82544:
 		/* Microwire */
 		sc->nvm.read = wm_nvm_read_uwire;
 		sc->sc_nvm_wordsize = 64;
 		sc->sc_nvm_addrbits = 6;
 		break;
 	case WM_T_82540:
 	case WM_T_82545:
 	case WM_T_82545_3:
 	case WM_T_82546:
 	case WM_T_82546_3:
 		/* Microwire */
 		sc->nvm.read = wm_nvm_read_uwire;
 		reg = CSR_READ(sc, WMREG_EECD);
 		if (reg & EECD_EE_SIZE) {
 			sc->sc_nvm_wordsize = 256;
 			sc->sc_nvm_addrbits = 8;
 		} else {
 			sc->sc_nvm_wordsize = 64;
 			sc->sc_nvm_addrbits = 6;
+		}
 		sc->sc_flags |= WM_F_LOCK_EECD;
 		sc->nvm.acquire = wm_get_eecd;
 		sc->nvm.release = wm_put_eecd;
 		break;
 	case WM_T_82541:
 	case WM_T_82541_2:
 	case WM_T_82547:
 	case WM_T_82547_2:
 		reg = CSR_READ(sc, WMREG_EECD);
 		/*
 		 * wm_nvm_set_addrbits_size_eecd() accesses SPI in it only
 		 * on 8254[17], so set flags and functios before calling it.
 		 */
 		sc->sc_flags |= WM_F_LOCK_EECD;
 		sc->nvm.acquire = wm_get_eecd;
 		sc->nvm.release = wm_put_eecd;
 		if (reg & EECD_EE_TYPE) {
 			/* SPI */
 			sc->nvm.read = wm_nvm_read_spi;
 			sc->sc_flags |= WM_F_EEPROM_SPI;
 			wm_nvm_set_addrbits_size_eecd(sc);
 		} else {
 			/* Microwire */
 			sc->nvm.read = wm_nvm_read_uwire;
 			if ((reg & EECD_EE_ABITS) != 0) {
 				sc->sc_nvm_wordsize = 256;
 				sc->sc_nvm_addrbits = 8;
 			} else {
 				sc->sc_nvm_wordsize = 64;
 				sc->sc_nvm_addrbits = 6;
+			}
+		}
 		break;
 	case WM_T_82571:
 	case WM_T_82572:
 		/* SPI */
 		sc->nvm.read = wm_nvm_read_eerd;
 		/* Not use WM_F_LOCK_EECD because we use EERD */
 		sc->sc_flags |= WM_F_EEPROM_SPI;
 		wm_nvm_set_addrbits_size_eecd(sc);
 		sc->phy.acquire = wm_get_swsm_semaphore;
 		sc->phy.release = wm_put_swsm_semaphore;
 		sc->nvm.acquire = wm_get_nvm_82571;
 		sc->nvm.release = wm_put_nvm_82571;
 		break;
 	case WM_T_82573:
 	case WM_T_82574:
 	case WM_T_82583:
 		sc->nvm.read = wm_nvm_read_eerd;
 		/* Not use WM_F_LOCK_EECD because we use EERD */
 		if (sc->sc_type == WM_T_82573) {
 			sc->phy.acquire = wm_get_swsm_semaphore;
 			sc->phy.release = wm_put_swsm_semaphore;
 			sc->nvm.acquire = wm_get_nvm_82571;
 			sc->nvm.release = wm_put_nvm_82571;
 		} else {
 			/* Both PHY and NVM use the same semaphore. */
 			sc->phy.acquire = sc->nvm.acquire
 			    = wm_get_swfwhw_semaphore;
 			sc->phy.release = sc->nvm.release
 			    = wm_put_swfwhw_semaphore;
+		}
 		if (wm_nvm_is_onboard_eeprom(sc) == 0) {
 			sc->sc_flags |= WM_F_EEPROM_FLASH;
 			sc->sc_nvm_wordsize = 2048;
 		} else {
 			/* SPI */
 			sc->sc_flags |= WM_F_EEPROM_SPI;
 			wm_nvm_set_addrbits_size_eecd(sc);
+		}
 		break;
 	case WM_T_82575:
 	case WM_T_82576:
 	case WM_T_82580:
 	case WM_T_I350:
 	case WM_T_I354:
 	case WM_T_80003:
 		/* SPI */
 		sc->sc_flags |= WM_F_EEPROM_SPI;
 		wm_nvm_set_addrbits_size_eecd(sc);
 		if ((sc->sc_type == WM_T_80003)
 		    || (sc->sc_nvm_wordsize < (1 << 15))) {
 			sc->nvm.read = wm_nvm_read_eerd;
 			/* Don't use WM_F_LOCK_EECD because we use EERD */
 		} else {
 			sc->nvm.read = wm_nvm_read_spi;
 			sc->sc_flags |= WM_F_LOCK_EECD;
+		}
 		sc->phy.acquire = wm_get_phy_82575;
 		sc->phy.release = wm_put_phy_82575;
 		sc->nvm.acquire = wm_get_nvm_80003;
 		sc->nvm.release = wm_put_nvm_80003;
 		break;
 	case WM_T_ICH8:
 	case WM_T_ICH9:
 	case WM_T_ICH10:
 	case WM_T_PCH:
 	case WM_T_PCH2:
 	case WM_T_PCH_LPT:
 		sc->nvm.read = wm_nvm_read_ich8;
 		/* FLASH */
 		sc->sc_flags |= WM_F_EEPROM_FLASH;
 		sc->sc_nvm_wordsize = 2048;
 		memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag,WM_ICH8_FLASH);
 		if (pci_mapreg_map(pa, WM_ICH8_FLASH, memtype, 0,
 		    &sc->sc_flasht, &sc->sc_flashh, NULL, &sc->sc_flashs)) {
 			aprint_error_dev(sc->sc_dev,
 			    "can't map FLASH registers\n");
 			goto out;
+		}
 		reg = ICH8_FLASH_READ32(sc, ICH_FLASH_GFPREG);
 		sc->sc_ich8_flash_base = (reg & ICH_GFPREG_BASE_MASK) *
 		    ICH_FLASH_SECTOR_SIZE;
 		sc->sc_ich8_flash_bank_size =
 		    ((reg >> 16) & ICH_GFPREG_BASE_MASK) + 1;
 		sc->sc_ich8_flash_bank_size -= (reg & ICH_GFPREG_BASE_MASK);
 		sc->sc_ich8_flash_bank_size *= ICH_FLASH_SECTOR_SIZE;
 		sc->sc_ich8_flash_bank_size /= 2 * sizeof(uint16_t);
 		sc->sc_flashreg_offset = 0;
 		sc->phy.acquire = wm_get_swflag_ich8lan;
 		sc->phy.release = wm_put_swflag_ich8lan;
 		sc->nvm.acquire = wm_get_nvm_ich8lan;
 		sc->nvm.release = wm_put_nvm_ich8lan;
 		break;
 	case WM_T_PCH_SPT:
 	case WM_T_PCH_CNP:
 	case WM_T_PCH_TGP:
 		sc->nvm.read = wm_nvm_read_spt;
 		/* SPT has no GFPREG; flash registers mapped through BAR0 */
 		sc->sc_flags |= WM_F_EEPROM_FLASH;
 		sc->sc_flasht = sc->sc_st;
 		sc->sc_flashh = sc->sc_sh;
 		sc->sc_ich8_flash_base = 0;
 		sc->sc_nvm_wordsize =
 		    (((CSR_READ(sc, WMREG_STRAP) >> 1) & 0x1F) + 1)
 		    * NVM_SIZE_MULTIPLIER;
 		/* It is size in bytes, we want words */
 		sc->sc_nvm_wordsize /= 2;
 		/* Assume 2 banks */
 		sc->sc_ich8_flash_bank_size = sc->sc_nvm_wordsize / 2;
 		sc->sc_flashreg_offset = WM_PCH_SPT_FLASHOFFSET;
 		sc->phy.acquire = wm_get_swflag_ich8lan;
 		sc->phy.release = wm_put_swflag_ich8lan;
 		sc->nvm.acquire = wm_get_nvm_ich8lan;
 		sc->nvm.release = wm_put_nvm_ich8lan;
 		break;
 	case WM_T_I210:
 	case WM_T_I211:
 		/* Allow a single clear of the SW semaphore on I210 and newer*/
 		sc->sc_flags |= WM_F_WA_I210_CLSEM;
 		if (wm_nvm_flash_presence_i210(sc)) {
 			sc->nvm.read = wm_nvm_read_eerd;
 			/* Don't use WM_F_LOCK_EECD because we use EERD */
 			sc->sc_flags |= WM_F_EEPROM_FLASH_HW;
 			wm_nvm_set_addrbits_size_eecd(sc);
 		} else {
 			sc->nvm.read = wm_nvm_read_invm;
 			sc->sc_flags |= WM_F_EEPROM_INVM;
 			sc->sc_nvm_wordsize = INVM_SIZE;
+		}
 		sc->phy.acquire = wm_get_phy_82575;
 		sc->phy.release = wm_put_phy_82575;
 		sc->nvm.acquire = wm_get_nvm_80003;
 		sc->nvm.release = wm_put_nvm_80003;
 		break;
 	default:
 		break;
+	}
 	/* Ensure the SMBI bit is clear before first NVM or PHY access */
 	switch (sc->sc_type) {
 	case WM_T_82571:
 	case WM_T_82572:
 		reg = CSR_READ(sc, WMREG_SWSM2);
 		if ((reg & SWSM2_LOCK) == 0) {
 			CSR_WRITE(sc, WMREG_SWSM2, reg | SWSM2_LOCK);
 			force_clear_smbi = true;
 		} else
 			force_clear_smbi = false;
 		break;
 	case WM_T_82573:
 	case WM_T_82574:
 	case WM_T_82583:
 		force_clear_smbi = true;
 		break;
 	default:
 		force_clear_smbi = false;
 		break;
+	}
 	if (force_clear_smbi) {
 		reg = CSR_READ(sc, WMREG_SWSM);
 		if ((reg & SWSM_SMBI) != 0)
 			aprint_error_dev(sc->sc_dev,
 			    "Please update the Bootagent\n");
 		CSR_WRITE(sc, WMREG_SWSM, reg & ~SWSM_SMBI);
+	}
 	/*
 	 * Defer printing the EEPROM type until after verifying the checksum
 	 * This allows the EEPROM type to be printed correctly in the case
 	 * that no EEPROM is attached.
 	 */
 	/*
 	 * Validate the EEPROM checksum. If the checksum fails, flag
 	 * this for later, so we can fail future reads from the EEPROM.
 	 */
 	if (wm_nvm_validate_checksum(sc)) {
 		/*
 		 * Read twice again because some PCI-e parts fail the
 		 * first check due to the link being in sleep state.
 		 */
 		if (wm_nvm_validate_checksum(sc))
 			sc->sc_flags |= WM_F_EEPROM_INVALID;
+	}
 	if (sc->sc_flags & WM_F_EEPROM_INVALID)
 		aprint_verbose_dev(sc->sc_dev, "No EEPROM");
 	else {
 		aprint_verbose_dev(sc->sc_dev, "%u words ",
 		    sc->sc_nvm_wordsize);
 		if (sc->sc_flags & WM_F_EEPROM_INVM)
 			aprint_verbose("iNVM");
 		else if (sc->sc_flags & WM_F_EEPROM_FLASH_HW)
 			aprint_verbose("FLASH(HW)");
 		else if (sc->sc_flags & WM_F_EEPROM_FLASH)
 			aprint_verbose("FLASH");
 		else {
 			if (sc->sc_flags & WM_F_EEPROM_SPI)
 				eetype = "SPI";
 			else
 				eetype = "MicroWire";
 			aprint_verbose("(%d address bits) %s EEPROM",
 			    sc->sc_nvm_addrbits, eetype);
+		}
+	}
 	wm_nvm_version(sc);
 	aprint_verbose("\n");
 	/*
 	 * XXX The first call of wm_gmii_setup_phytype. The result might be
 	 * incorrect.
 	 */
 	wm_gmii_setup_phytype(sc, 0, 0);
 	/* Check for WM_F_WOL on some chips before wm_reset() */
 	switch (sc->sc_type) {
 	case WM_T_ICH8:
 	case WM_T_ICH9:
 	case WM_T_ICH10:
 	case WM_T_PCH:
 	case WM_T_PCH2:
 	case WM_T_PCH_LPT:
 	case WM_T_PCH_SPT:
 	case WM_T_PCH_CNP:
 	case WM_T_PCH_TGP:
 		apme_mask = WUC_APME;
 		eeprom_data = CSR_READ(sc, WMREG_WUC);
 		if ((eeprom_data & apme_mask) != 0)
 			sc->sc_flags |= WM_F_WOL;
 		break;
 	default:
 		break;
+	}
 	/* Reset the chip to a known state. */
 	wm_reset(sc);
 	/* sc->sc_pba is set in wm_reset(). */
 	aprint_verbose_dev(sc->sc_dev, "RX packet buffer size: %uKB\n",
 	    sc->sc_pba);
 	/*
 	 * Check for I21[01] PLL workaround.
+	 *
 	 * Three cases:
 	 * a) Chip is I211.
 	 * b) Chip is I210 and it uses INVM (not FLASH).
 	 * c) Chip is I210 (and it uses FLASH) and the NVM image version < 3.25
 	 */
 	if (sc->sc_type == WM_T_I211)
 		sc->sc_flags |= WM_F_PLL_WA_I210;
 	if (sc->sc_type == WM_T_I210) {
 		if (!wm_nvm_flash_presence_i210(sc))
 			sc->sc_flags |= WM_F_PLL_WA_I210;
 		else if ((sc->sc_nvm_ver_major < 3)
 		    || ((sc->sc_nvm_ver_major == 3)
 			&& (sc->sc_nvm_ver_minor < 25))) {
 			aprint_verbose_dev(sc->sc_dev,
 			    "ROM image version %d.%d is older than 3.25\n",
 			    sc->sc_nvm_ver_major, sc->sc_nvm_ver_minor);
 			sc->sc_flags |= WM_F_PLL_WA_I210;
+		}
+	}
 	if ((sc->sc_flags & WM_F_PLL_WA_I210) != 0)
 		wm_pll_workaround_i210(sc);
 	wm_get_wakeup(sc);
 	/* Non-AMT based hardware can now take control from firmware */
 	if ((sc->sc_flags & WM_F_HAS_AMT) == 0)
 		wm_get_hw_control(sc);
 	/*
 	 * Read the Ethernet address from the EEPROM, if not first found
 	 * in device properties.
 	 */
 	ea = prop_dictionary_get(dict, "mac-address");
 	if (ea != NULL) {
 		KASSERT(prop_object_type(ea) == PROP_TYPE_DATA);
 		KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN);
 		memcpy(enaddr, prop_data_data_nocopy(ea), ETHER_ADDR_LEN);
 	} else {
 		if (wm_read_mac_addr(sc, enaddr) != 0) {
 			aprint_error_dev(sc->sc_dev,
 			    "unable to read Ethernet address\n");
 			goto out;
+		}
+	}
 	aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n",
 	    ether_sprintf(enaddr));
 	/*
 	 * Read the config info from the EEPROM, and set up various
 	 * bits in the control registers based on their contents.
 	 */
 	pn = prop_dictionary_get(dict, "i82543-cfg1");
 	if (pn != NULL) {
 		KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER);
 		cfg1 = (uint16_t) prop_number_integer_value(pn);
 	} else {
 		if (wm_nvm_read(sc, NVM_OFF_CFG1, 1, &cfg1)) {
 			aprint_error_dev(sc->sc_dev, "unable to read CFG1\n");
 			goto out;
+		}
+	}
 	pn = prop_dictionary_get(dict, "i82543-cfg2");
 	if (pn != NULL) {
 		KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER);
 		cfg2 = (uint16_t) prop_number_integer_value(pn);
 	} else {
 		if (wm_nvm_read(sc, NVM_OFF_CFG2, 1, &cfg2)) {
 			aprint_error_dev(sc->sc_dev, "unable to read CFG2\n");
 			goto out;
+		}
+	}
 	/* check for WM_F_WOL */
 	switch (sc->sc_type) {
 	case WM_T_82542_2_0:
 	case WM_T_82542_2_1:
 	case WM_T_82543:
 		/* dummy? */
 		eeprom_data = 0;
 		apme_mask = NVM_CFG3_APME;
 		break;
 	case WM_T_82544:
 		apme_mask = NVM_CFG2_82544_APM_EN;
 		eeprom_data = cfg2;
 		break;
 	case WM_T_82546:
 	case WM_T_82546_3:
 	case WM_T_82571:
 	case WM_T_82572:
 	case WM_T_82573:
 	case WM_T_82574:
 	case WM_T_82583:
 	case WM_T_80003:
 	case WM_T_82575:
 	case WM_T_82576:
 		apme_mask = NVM_CFG3_APME;
 		wm_nvm_read(sc, (sc->sc_funcid == 1) ? NVM_OFF_CFG3_PORTB
 		    : NVM_OFF_CFG3_PORTA, 1, &eeprom_data);
 		break;
 	case WM_T_82580:
 	case WM_T_I350:
 	case WM_T_I354:
 	case WM_T_I210:
 	case WM_T_I211:
 		apme_mask = NVM_CFG3_APME;
 		wm_nvm_read(sc,
 		    NVM_OFF_LAN_FUNC_82580(sc->sc_funcid) + NVM_OFF_CFG3_PORTA,
 , &eeprom_data);
 		break;
 	case WM_T_ICH8:
 	case WM_T_ICH9:
 	case WM_T_ICH10:
 	case WM_T_PCH:
 	case WM_T_PCH2:
 	case WM_T_PCH_LPT:
 	case WM_T_PCH_SPT:
 	case WM_T_PCH_CNP:
 	case WM_T_PCH_TGP:
 		/* Already checked before wm_reset () */
 		apme_mask = eeprom_data = 0;
 		break;
 	default: /* XXX 82540 */
 		apme_mask = NVM_CFG3_APME;
 		wm_nvm_read(sc, NVM_OFF_CFG3_PORTA, 1, &eeprom_data);
 		break;
+	}
 	/* Check for WM_F_WOL flag after the setting of the EEPROM stuff */
 	if ((eeprom_data & apme_mask) != 0)
 		sc->sc_flags |= WM_F_WOL;
 	/*
 	 * We have the eeprom settings, now apply the special cases
 	 * where the eeprom may be wrong or the board won't support
 	 * wake on lan on a particular port
 	 */
 	switch (sc->sc_pcidevid) {
 	case PCI_PRODUCT_INTEL_82546GB_PCIE:
 		sc->sc_flags &= ~WM_F_WOL;
 		break;
 	case PCI_PRODUCT_INTEL_82546EB_FIBER:
 	case PCI_PRODUCT_INTEL_82546GB_FIBER:
 		/* Wake events only supported on port A for dual fiber
 		 * regardless of eeprom setting */
 		if (sc->sc_funcid == 1)
 			sc->sc_flags &= ~WM_F_WOL;
 		break;
 	case PCI_PRODUCT_INTEL_82546GB_QUAD_COPPER_KSP3:
 		/* If quad port adapter, disable WoL on all but port A */
 		if (sc->sc_funcid != 0)
 			sc->sc_flags &= ~WM_F_WOL;
 		break;
 	case PCI_PRODUCT_INTEL_82571EB_FIBER:
 		/* Wake events only supported on port A for dual fiber
 		 * regardless of eeprom setting */
 		if (sc->sc_funcid == 1)
 			sc->sc_flags &= ~WM_F_WOL;
 		break;
 	case PCI_PRODUCT_INTEL_82571EB_QUAD_COPPER:
 	case PCI_PRODUCT_INTEL_82571EB_QUAD_FIBER:
 	case PCI_PRODUCT_INTEL_82571GB_QUAD_COPPER:
 		/* If quad port adapter, disable WoL on all but port A */
 		if (sc->sc_funcid != 0)
 			sc->sc_flags &= ~WM_F_WOL;
 		break;
+	}
 	if (sc->sc_type >= WM_T_82575) {
 		if (wm_nvm_read(sc, NVM_OFF_COMPAT, 1, &nvmword) == 0) {
 			aprint_debug_dev(sc->sc_dev, "COMPAT = %hx\n",
 			    nvmword);
 			if ((sc->sc_type == WM_T_82575) ||
 			    (sc->sc_type == WM_T_82576)) {
 				/* Check NVM for autonegotiation */
 				if ((nvmword & NVM_COMPAT_SERDES_FORCE_MODE)
 				    != 0)
 					sc->sc_flags |= WM_F_PCS_DIS_AUTONEGO;
+			}
 			if ((sc->sc_type == WM_T_82575) ||
 			    (sc->sc_type == WM_T_I350)) {
 				if (nvmword & NVM_COMPAT_MAS_EN(sc->sc_funcid))
 					sc->sc_flags |= WM_F_MAS;
+			}
+		}
+	}
 	/*
 	 * XXX need special handling for some multiple port cards
 	 * to disable a paticular port.
 	 */
 	if (sc->sc_type >= WM_T_82544) {
 		pn = prop_dictionary_get(dict, "i82543-swdpin");
 		if (pn != NULL) {
 			KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER);
 			swdpin = (uint16_t) prop_number_integer_value(pn);
 		} else {
 			if (wm_nvm_read(sc, NVM_OFF_SWDPIN, 1, &swdpin)) {
 				aprint_error_dev(sc->sc_dev,
 				    "unable to read SWDPIN\n");
 				goto out;
+			}
+		}
+	}
 	if (cfg1 & NVM_CFG1_ILOS)
 		sc->sc_ctrl |= CTRL_ILOS;
 	/*
 	 * XXX
 	 * This code isn't correct because pin 2 and 3 are located
 	 * in different position on newer chips. Check all datasheet.
+	 *
 	 * Until resolve this problem, check if a chip < 82580
 	 */
 	if (sc->sc_type <= WM_T_82580) {
 		if (sc->sc_type >= WM_T_82544) {
 			sc->sc_ctrl |=
 			    ((swdpin >> NVM_SWDPIN_SWDPIO_SHIFT) & 0xf) <<
 			    CTRL_SWDPIO_SHIFT;
 			sc->sc_ctrl |=
 			    ((swdpin >> NVM_SWDPIN_SWDPIN_SHIFT) & 0xf) <<
 			    CTRL_SWDPINS_SHIFT;
 		} else {
 			sc->sc_ctrl |=
 			    ((cfg1 >> NVM_CFG1_SWDPIO_SHIFT) & 0xf) <<
 			    CTRL_SWDPIO_SHIFT;
+		}
+	}
 	if ((sc->sc_type >= WM_T_82580) && (sc->sc_type <= WM_T_I211)) {
 		wm_nvm_read(sc,
 		    NVM_OFF_LAN_FUNC_82580(sc->sc_funcid) + NVM_OFF_CFG3_PORTA,
 , &nvmword);
 		if (nvmword & NVM_CFG3_ILOS)
 			sc->sc_ctrl |= CTRL_ILOS;
+	}
 #if 0
 	if (sc->sc_type >= WM_T_82544) {
 		if (cfg1 & NVM_CFG1_IPS0)
 			sc->sc_ctrl_ext |= CTRL_EXT_IPS;
 		if (cfg1 & NVM_CFG1_IPS1)
 			sc->sc_ctrl_ext |= CTRL_EXT_IPS1;
 		sc->sc_ctrl_ext |=
 		    ((swdpin >> (NVM_SWDPIN_SWDPIO_SHIFT + 4)) & 0xd) <<
 		    CTRL_EXT_SWDPIO_SHIFT;
 		sc->sc_ctrl_ext |=
 		    ((swdpin >> (NVM_SWDPIN_SWDPIN_SHIFT + 4)) & 0xd) <<
 		    CTRL_EXT_SWDPINS_SHIFT;
 	} else {
 		sc->sc_ctrl_ext |=
 		    ((cfg2 >> NVM_CFG2_SWDPIO_SHIFT) & 0xf) <<
 		    CTRL_EXT_SWDPIO_SHIFT;
+	}
 #endif
 	CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
 #if 0
 	CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext);
 #endif
 	if (sc->sc_type == WM_T_PCH) {
 		uint16_t val;
 		/* Save the NVM K1 bit setting */
 		wm_nvm_read(sc, NVM_OFF_K1_CONFIG, 1, &val);
 		if ((val & NVM_K1_CONFIG_ENABLE) != 0)
 			sc->sc_nvm_k1_enabled = 1;
 		else
 			sc->sc_nvm_k1_enabled = 0;
+	}
 	/* Determine if we're GMII, TBI, SERDES or SGMII mode */
 	if (sc->sc_type == WM_T_ICH8 || sc->sc_type == WM_T_ICH9
 	    || sc->sc_type == WM_T_ICH10 || sc->sc_type == WM_T_PCH
 	    || sc->sc_type == WM_T_PCH2 || sc->sc_type == WM_T_PCH_LPT
 	    || sc->sc_type == WM_T_PCH_SPT || sc->sc_type == WM_T_PCH_CNP
 	    || sc->sc_type == WM_T_PCH_TGP
 	    || sc->sc_type == WM_T_82573
 	    || sc->sc_type == WM_T_82574 || sc->sc_type == WM_T_82583) {
 		/* Copper only */
 	} else if ((sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576)
 	    || (sc->sc_type ==WM_T_82580) || (sc->sc_type ==WM_T_I350)
 	    || (sc->sc_type ==WM_T_I354) || (sc->sc_type ==WM_T_I210)
 	    || (sc->sc_type ==WM_T_I211)) {
 		reg = CSR_READ(sc, WMREG_CTRL_EXT);
 		link_mode = reg & CTRL_EXT_LINK_MODE_MASK;
 		switch (link_mode) {
 		case CTRL_EXT_LINK_MODE_1000KX:
 			aprint_normal_dev(sc->sc_dev, "1000KX\n");
 			sc->sc_mediatype = WM_MEDIATYPE_SERDES;
 			break;
 		case CTRL_EXT_LINK_MODE_SGMII:
 			if (wm_sgmii_uses_mdio(sc)) {
 				aprint_normal_dev(sc->sc_dev,
 				    "SGMII(MDIO)\n");
 				sc->sc_flags |= WM_F_SGMII;
 				sc->sc_mediatype = WM_MEDIATYPE_COPPER;
 				break;
+			}
 			aprint_verbose_dev(sc->sc_dev, "SGMII(I2C)\n");
 			/*FALLTHROUGH*/
 		case CTRL_EXT_LINK_MODE_PCIE_SERDES:
 			sc->sc_mediatype = wm_sfp_get_media_type(sc);
 			if (sc->sc_mediatype == WM_MEDIATYPE_UNKNOWN) {
 				if (link_mode
 				    == CTRL_EXT_LINK_MODE_SGMII) {
 					sc->sc_mediatype = WM_MEDIATYPE_COPPER;
 					sc->sc_flags |= WM_F_SGMII;
 					aprint_verbose_dev(sc->sc_dev,
 					    "SGMII\n");
 				} else {
 					sc->sc_mediatype = WM_MEDIATYPE_SERDES;
 					aprint_verbose_dev(sc->sc_dev,
 					    "SERDES\n");
+				}
 				break;
+			}
 			if (sc->sc_mediatype == WM_MEDIATYPE_SERDES)
 				aprint_normal_dev(sc->sc_dev, "SERDES(SFP)\n");
 			else if (sc->sc_mediatype == WM_MEDIATYPE_COPPER) {
 				aprint_normal_dev(sc->sc_dev, "SGMII(SFP)\n");
 				sc->sc_flags |= WM_F_SGMII;
+			}
 			/* Do not change link mode for 100BaseFX */
 			if (sc->sc_sfptype == SFF_SFP_ETH_FLAGS_100FX)
 				break;
 			/* Change current link mode setting */
 			reg &= ~CTRL_EXT_LINK_MODE_MASK;
 			if (sc->sc_mediatype == WM_MEDIATYPE_COPPER)
 				reg |= CTRL_EXT_LINK_MODE_SGMII;
 			else
 				reg |= CTRL_EXT_LINK_MODE_PCIE_SERDES;
 			CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
 			break;
 		case CTRL_EXT_LINK_MODE_GMII:
 		default:
 			aprint_normal_dev(sc->sc_dev, "Copper\n");
 			sc->sc_mediatype = WM_MEDIATYPE_COPPER;
 			break;
+		}
 		reg &= ~CTRL_EXT_I2C_ENA;
 		if ((sc->sc_flags & WM_F_SGMII) != 0)
 			reg |= CTRL_EXT_I2C_ENA;
 		else
 			reg &= ~CTRL_EXT_I2C_ENA;
 		CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
 		if ((sc->sc_flags & WM_F_SGMII) != 0) {
 			if (!wm_sgmii_uses_mdio(sc))
 				wm_gmii_setup_phytype(sc, 0, 0);
 			wm_reset_mdicnfg_82580(sc);
+		}
 	} else if (sc->sc_type < WM_T_82543 ||
 	    (CSR_READ(sc, WMREG_STATUS) & STATUS_TBIMODE) != 0) {
 		if (sc->sc_mediatype == WM_MEDIATYPE_COPPER) {
 			aprint_error_dev(sc->sc_dev,
 			    "WARNING: TBIMODE set on 1000BASE-T product!\n");
 			sc->sc_mediatype = WM_MEDIATYPE_FIBER;
+		}
 	} else {
 		if (sc->sc_mediatype == WM_MEDIATYPE_FIBER) {
 			aprint_error_dev(sc->sc_dev,
 			    "WARNING: TBIMODE clear on 1000BASE-X product!\n");
 			sc->sc_mediatype = WM_MEDIATYPE_COPPER;
+		}
+	}
 	/*
 	 * The I350 has a bug where it always strips the CRC whether
 	 * asked to or not. So ask for stripped CRC here and cope in rxeof
 	 */
 	if ((sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354)
 	    || (sc->sc_type == WM_T_I210) || (sc->sc_type == WM_T_I211))
 		sc->sc_flags |= WM_F_CRC_STRIP;
 	/*
 	 * Workaround for some chips to delay sending LINK_STATE_UP.
 	 * Some systems can't send packet soon after linkup. See also
 	 * wm_linkintr_gmii(), wm_tick() and wm_gmii_mediastatus().
 	 */
 	switch (sc->sc_type) {
 	case WM_T_I350:
 	case WM_T_I354:
 	case WM_T_I210:
 	case WM_T_I211:
 		if (sc->sc_mediatype == WM_MEDIATYPE_COPPER)
 			sc->sc_flags |= WM_F_DELAY_LINKUP;
 		break;
 	default:
 		break;
+	}
 	/* Set device properties (macflags) */
 	prop_dictionary_set_uint32(dict, "macflags", sc->sc_flags);
 	if (sc->sc_flags != 0) {
 		snprintb(buf, sizeof(buf), WM_FLAGS, sc->sc_flags);
 		aprint_verbose_dev(sc->sc_dev, "%s\n", buf);
+	}
 	/* Initialize the media structures accordingly. */
 	if (sc->sc_mediatype == WM_MEDIATYPE_COPPER)
 		wm_gmii_mediainit(sc, wmp->wmp_product);
 	else
 		wm_tbi_mediainit(sc); /* All others */
 	ifp = &sc->sc_ethercom.ec_if;
 	xname = device_xname(sc->sc_dev);
 	strlcpy(ifp->if_xname, xname, IFNAMSIZ);
 	ifp->if_softc = sc;
 	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 #ifdef WM_MPSAFE
 	ifp->if_extflags = IFEF_MPSAFE;
 #endif
 	ifp->if_ioctl = wm_ioctl;
 	if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) {
 		ifp->if_start = wm_nq_start;
 		/*
 		 * When the number of CPUs is one and the controller can use
 		 * MSI-X, wm(4) use MSI-X but *does not* use multiqueue.
 		 * That is, wm(4) use two interrupts, one is used for Tx/Rx
 		 * and the other is used for link status changing.
 		 * In this situation, wm_nq_transmit() is disadvantageous
 		 * because of wm_select_txqueue() and pcq(9) overhead.
 		 */
 		if (wm_is_using_multiqueue(sc))
 			ifp->if_transmit = wm_nq_transmit;
 	} else {
 		ifp->if_start = wm_start;
 		/*
 		 * wm_transmit() has the same disadvantages as wm_nq_transmit()
 		 * described above.
 		 */
 		if (wm_is_using_multiqueue(sc))
 			ifp->if_transmit = wm_transmit;
+	}
 	/* wm(4) doest not use ifp->if_watchdog, use wm_tick as watchdog. */
 	ifp->if_init = wm_init;
 	ifp->if_stop = wm_stop;
 	IFQ_SET_MAXLEN(&ifp->if_snd, max(WM_IFQUEUELEN, IFQ_MAXLEN));
 	IFQ_SET_READY(&ifp->if_snd);
 	/* Check for jumbo frame */
 	switch (sc->sc_type) {
 	case WM_T_82573:
 		/* XXX limited to 9234 if ASPM is disabled */
 		wm_nvm_read(sc, NVM_OFF_INIT_3GIO_3, 1, &nvmword);
 		if ((nvmword & NVM_3GIO_3_ASPM_MASK) != 0)
 			sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU;
 		break;
 	case WM_T_82571:
 	case WM_T_82572:
 	case WM_T_82574:
 	case WM_T_82583:
 	case WM_T_82575:
 	case WM_T_82576:
 	case WM_T_82580:
 	case WM_T_I350:
 	case WM_T_I354:
 	case WM_T_I210:
 	case WM_T_I211:
 	case WM_T_80003:
 	case WM_T_ICH9:
 	case WM_T_ICH10:
 	case WM_T_PCH2:	/* PCH2 supports 9K frame size */
 	case WM_T_PCH_LPT:
 	case WM_T_PCH_SPT:
 	case WM_T_PCH_CNP:
 	case WM_T_PCH_TGP:
 		/* XXX limited to 9234 */
 		sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU;
 		break;
 	case WM_T_PCH:
 		/* XXX limited to 4096 */
 		sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU;
 		break;
 	case WM_T_82542_2_0:
 	case WM_T_82542_2_1:
 	case WM_T_ICH8:
 		/* No support for jumbo frame */
 		break;
 	default:
 		/* ETHER_MAX_LEN_JUMBO */
 		sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU;
 		break;
+	}
 	/* If we're a i82543 or greater, we can support VLANs. */
 	if (sc->sc_type >= WM_T_82543)
 		sc->sc_ethercom.ec_capabilities |=
 		    ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING;
 	/*
 	 * We can perform TCPv4 and UDPv4 checksums in-bound.  Only
 	 * on i82543 and later.
 	 */
 	if (sc->sc_type >= WM_T_82543) {
 		ifp->if_capabilities |=
 		    IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx |
 		    IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx |
 		    IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx |
 		    IFCAP_CSUM_TCPv6_Tx |
 		    IFCAP_CSUM_UDPv6_Tx;
+	}
 	/*
 	 * XXXyamt: i'm not sure which chips support RXCSUM_IPV6OFL.
+	 *
 	 *	82541GI (8086:1076) ... no
 	 *	82572EI (8086:10b9) ... yes
 	 */
 	if (sc->sc_type >= WM_T_82571) {
 		ifp->if_capabilities |=
 		    IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx;
+	}
 	/*
 	 * If we're a i82544 or greater (except i82547), we can do
 	 * TCP segmentation offload.
 	 */
 	if (sc->sc_type >= WM_T_82544 && sc->sc_type != WM_T_82547)
 		ifp->if_capabilities |= IFCAP_TSOv4;
 	if (sc->sc_type >= WM_T_82571)
 		ifp->if_capabilities |= IFCAP_TSOv6;
 	sc->sc_tx_process_limit = WM_TX_PROCESS_LIMIT_DEFAULT;
 	sc->sc_tx_intr_process_limit = WM_TX_INTR_PROCESS_LIMIT_DEFAULT;
 	sc->sc_rx_process_limit = WM_RX_PROCESS_LIMIT_DEFAULT;
 	sc->sc_rx_intr_process_limit = WM_RX_INTR_PROCESS_LIMIT_DEFAULT;
 #ifdef WM_MPSAFE
 	sc->sc_core_lock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_NET);
 #else
 	sc->sc_core_lock = NULL;
 #endif
 	/* Attach the interface. */
 	error = if_initialize(ifp);
 	if (error != 0) {
 		aprint_error_dev(sc->sc_dev, "if_initialize failed(%d)\n",
 		    error);
 		return; /* Error */
+	}
 	sc->sc_ipq = if_percpuq_create(&sc->sc_ethercom.ec_if);
 	ether_ifattach(ifp, enaddr);
 	ether_set_ifflags_cb(&sc->sc_ethercom, wm_ifflags_cb);
 	if_register(ifp);
 #ifdef WM_EVENT_COUNTERS
 	/* Attach event counters. */
 	evcnt_attach_dynamic(&sc->sc_ev_linkintr, EVCNT_TYPE_INTR,
 	    NULL, xname, "linkintr");
 	evcnt_attach_dynamic(&sc->sc_ev_crcerrs, EVCNT_TYPE_MISC,
 	    NULL, xname, "CRC Error");
 	evcnt_attach_dynamic(&sc->sc_ev_symerrc, EVCNT_TYPE_MISC,
 	    NULL, xname, "Symbol Error");
 	evcnt_attach_dynamic(&sc->sc_ev_mpc, EVCNT_TYPE_MISC,
 	    NULL, xname, "Missed Packets");
 	evcnt_attach_dynamic(&sc->sc_ev_colc, EVCNT_TYPE_MISC,
 	    NULL, xname, "Collision");
 	evcnt_attach_dynamic(&sc->sc_ev_sec, EVCNT_TYPE_MISC,
 	    NULL, xname, "Sequence Error");
 	evcnt_attach_dynamic(&sc->sc_ev_rlec, EVCNT_TYPE_MISC,
 	    NULL, xname, "Receive Length Error");
 	if (sc->sc_type >= WM_T_82543) {
 		evcnt_attach_dynamic(&sc->sc_ev_algnerrc, EVCNT_TYPE_MISC,
 		    NULL, xname, "Alignment Error");
 		evcnt_attach_dynamic(&sc->sc_ev_rxerrc, EVCNT_TYPE_MISC,
 		    NULL, xname, "Receive Error");
 		/* XXX Does 82575 have HTDPMC? */
 		if ((sc->sc_type < WM_T_82575) || WM_IS_ICHPCH(sc))
 			evcnt_attach_dynamic(&sc->sc_ev_cexterr,
 			    EVCNT_TYPE_MISC, NULL, xname,
 			    "Carrier Extension Error");
 		else
 			evcnt_attach_dynamic(&sc->sc_ev_htdpmc,
 			    EVCNT_TYPE_MISC, NULL, xname,
 			    "Host Transmit Discarded Packets by MAC");
 		evcnt_attach_dynamic(&sc->sc_ev_tncrs, EVCNT_TYPE_MISC,
 		    NULL, xname, "Tx with No CRS");
 		evcnt_attach_dynamic(&sc->sc_ev_tsctc, EVCNT_TYPE_MISC,
 		    NULL, xname, "TCP Segmentation Context Tx");
 		if ((sc->sc_type < WM_T_82575) || WM_IS_ICHPCH(sc))
 			evcnt_attach_dynamic(&sc->sc_ev_tsctfc,
 			    EVCNT_TYPE_MISC, NULL, xname,
 			    "TCP Segmentation Context Tx Fail");
 		else {
 			/* XXX Is the circuit breaker only for 82576? */
 			evcnt_attach_dynamic(&sc->sc_ev_cbrdpc,
 			    EVCNT_TYPE_MISC, NULL, xname,
 			    "Circuit Breaker Rx Dropped Packet");
 			evcnt_attach_dynamic(&sc->sc_ev_cbrmpc,
 			    EVCNT_TYPE_MISC, NULL, xname,
 			    "Circuit Breaker Rx Manageability Packet");
+		}
+	}
 	if (sc->sc_type >= WM_T_82542_2_1) {
 		evcnt_attach_dynamic(&sc->sc_ev_tx_xoff, EVCNT_TYPE_MISC,
 		    NULL, xname, "XOFF Transmitted");
 		evcnt_attach_dynamic(&sc->sc_ev_tx_xon, EVCNT_TYPE_MISC,
 		    NULL, xname, "XON Transmitted");
 		evcnt_attach_dynamic(&sc->sc_ev_rx_xoff, EVCNT_TYPE_MISC,
 		    NULL, xname, "XOFF Received");
 		evcnt_attach_dynamic(&sc->sc_ev_rx_xon, EVCNT_TYPE_MISC,
 		    NULL, xname, "XON Received");
 		evcnt_attach_dynamic(&sc->sc_ev_rx_macctl, EVCNT_TYPE_MISC,
 		    NULL, xname, "FC Received Unsupported");
+	}
 	evcnt_attach_dynamic(&sc->sc_ev_scc, EVCNT_TYPE_MISC,
 	    NULL, xname, "Single Collision");
 	evcnt_attach_dynamic(&sc->sc_ev_ecol, EVCNT_TYPE_MISC,
 	    NULL, xname, "Excessive Collisions");
 	evcnt_attach_dynamic(&sc->sc_ev_mcc, EVCNT_TYPE_MISC,
 	    NULL, xname, "Multiple Collision");
 	evcnt_attach_dynamic(&sc->sc_ev_latecol, EVCNT_TYPE_MISC,
 	    NULL, xname, "Late Collisions");
 	if ((sc->sc_type >= WM_T_I350) && !WM_IS_ICHPCH(sc))
 		evcnt_attach_dynamic(&sc->sc_ev_cbtmpc, EVCNT_TYPE_MISC,
 		    NULL, xname, "Circuit Breaker Tx Manageability Packet");
 	evcnt_attach_dynamic(&sc->sc_ev_dc, EVCNT_TYPE_MISC,
 	    NULL, xname, "Defer");
 	evcnt_attach_dynamic(&sc->sc_ev_prc64, EVCNT_TYPE_MISC,
 	    NULL, xname, "Packets Rx (64 bytes)");
 	evcnt_attach_dynamic(&sc->sc_ev_prc127, EVCNT_TYPE_MISC,
 	    NULL, xname, "Packets Rx (65-127 bytes)");
 	evcnt_attach_dynamic(&sc->sc_ev_prc255, EVCNT_TYPE_MISC,
 	    NULL, xname, "Packets Rx (128-255 bytes)");
 	evcnt_attach_dynamic(&sc->sc_ev_prc511, EVCNT_TYPE_MISC,
 	    NULL, xname, "Packets Rx (256-511 bytes)");
 	evcnt_attach_dynamic(&sc->sc_ev_prc1023, EVCNT_TYPE_MISC,
 	    NULL, xname, "Packets Rx (512-1023 bytes)");
 	evcnt_attach_dynamic(&sc->sc_ev_prc1522, EVCNT_TYPE_MISC,
 	    NULL, xname, "Packets Rx (1024-1522 bytes)");
 	evcnt_attach_dynamic(&sc->sc_ev_gprc, EVCNT_TYPE_MISC,
 	    NULL, xname, "Good Packets Rx");
 	evcnt_attach_dynamic(&sc->sc_ev_bprc, EVCNT_TYPE_MISC,
 	    NULL, xname, "Broadcast Packets Rx");
 	evcnt_attach_dynamic(&sc->sc_ev_mprc, EVCNT_TYPE_MISC,
 	    NULL, xname, "Multicast Packets Rx");
 	evcnt_attach_dynamic(&sc->sc_ev_gptc, EVCNT_TYPE_MISC,
 	    NULL, xname, "Good Packets Tx");
 	evcnt_attach_dynamic(&sc->sc_ev_gorc, EVCNT_TYPE_MISC,
 	    NULL, xname, "Good Octets Rx");
 	evcnt_attach_dynamic(&sc->sc_ev_gotc, EVCNT_TYPE_MISC,
 	    NULL, xname, "Good Octets Tx");
 	evcnt_attach_dynamic(&sc->sc_ev_rnbc, EVCNT_TYPE_MISC,
 	    NULL, xname, "Rx No Buffers");
 	evcnt_attach_dynamic(&sc->sc_ev_ruc, EVCNT_TYPE_MISC,
 	    NULL, xname, "Rx Undersize (valid CRC)");
 	evcnt_attach_dynamic(&sc->sc_ev_rfc, EVCNT_TYPE_MISC,
 	    NULL, xname, "Rx Fragment (bad CRC)");
 	evcnt_attach_dynamic(&sc->sc_ev_roc, EVCNT_TYPE_MISC,
 	    NULL, xname, "Rx Oversize (valid CRC)");
 	evcnt_attach_dynamic(&sc->sc_ev_rjc, EVCNT_TYPE_MISC,
 	    NULL, xname, "Rx Jabber (bad CRC)");
 	if (sc->sc_type >= WM_T_82540) {
 		evcnt_attach_dynamic(&sc->sc_ev_mgtprc, EVCNT_TYPE_MISC,
 		    NULL, xname, "Management Packets RX");
 		evcnt_attach_dynamic(&sc->sc_ev_mgtpdc, EVCNT_TYPE_MISC,
 		    NULL, xname, "Management Packets Dropped");
 		evcnt_attach_dynamic(&sc->sc_ev_mgtptc, EVCNT_TYPE_MISC,
 		    NULL, xname, "Management Packets TX");
+	}
 	evcnt_attach_dynamic(&sc->sc_ev_tor, EVCNT_TYPE_MISC,
 	    NULL, xname, "Total Octets Rx");
 	evcnt_attach_dynamic(&sc->sc_ev_tot, EVCNT_TYPE_MISC,
 	    NULL, xname, "Total Octets Tx");
 	evcnt_attach_dynamic(&sc->sc_ev_tpr, EVCNT_TYPE_MISC,
 	    NULL, xname, "Total Packets Rx");
 	evcnt_attach_dynamic(&sc->sc_ev_tpt, EVCNT_TYPE_MISC,
 	    NULL, xname, "Total Packets Tx");
 	evcnt_attach_dynamic(&sc->sc_ev_ptc64, EVCNT_TYPE_MISC,
 	    NULL, xname, "Packets Tx (64 bytes)");
 	evcnt_attach_dynamic(&sc->sc_ev_ptc127, EVCNT_TYPE_MISC,
 	    NULL, xname, "Packets Tx (65-127 bytes)");
 	evcnt_attach_dynamic(&sc->sc_ev_ptc255, EVCNT_TYPE_MISC,
 	    NULL, xname, "Packets Tx (128-255 bytes)");
 	evcnt_attach_dynamic(&sc->sc_ev_ptc511, EVCNT_TYPE_MISC,
 	    NULL, xname, "Packets Tx (256-511 bytes)");
 	evcnt_attach_dynamic(&sc->sc_ev_ptc1023, EVCNT_TYPE_MISC,
 	    NULL, xname, "Packets Tx (512-1023 bytes)");
 	evcnt_attach_dynamic(&sc->sc_ev_ptc1522, EVCNT_TYPE_MISC,
 	    NULL, xname, "Packets Tx (1024-1522 Bytes)");
 	evcnt_attach_dynamic(&sc->sc_ev_mptc, EVCNT_TYPE_MISC,
 	    NULL, xname, "Multicast Packets Tx");
 	evcnt_attach_dynamic(&sc->sc_ev_bptc, EVCNT_TYPE_MISC,
 	    NULL, xname, "Broadcast Packets Tx");
 	if (sc->sc_type >= WM_T_82571) /* PCIe, 80003 and ICH/PCHs */
 		evcnt_attach_dynamic(&sc->sc_ev_iac, EVCNT_TYPE_MISC,
 		    NULL, xname, "Interrupt Assertion");
 	if (sc->sc_type < WM_T_82575) {
 		evcnt_attach_dynamic(&sc->sc_ev_icrxptc, EVCNT_TYPE_MISC,
 		    NULL, xname, "Intr. Cause Rx Pkt Timer Expire");
 		evcnt_attach_dynamic(&sc->sc_ev_icrxatc, EVCNT_TYPE_MISC,
 		    NULL, xname, "Intr. Cause Rx Abs Timer Expire");
 		evcnt_attach_dynamic(&sc->sc_ev_ictxptc, EVCNT_TYPE_MISC,
 		    NULL, xname, "Intr. Cause Tx Pkt Timer Expire");
 		evcnt_attach_dynamic(&sc->sc_ev_ictxatc, EVCNT_TYPE_MISC,
 		    NULL, xname, "Intr. Cause Tx Abs Timer Expire");
 		evcnt_attach_dynamic(&sc->sc_ev_ictxqec, EVCNT_TYPE_MISC,
 		    NULL, xname, "Intr. Cause Tx Queue Empty");
 		evcnt_attach_dynamic(&sc->sc_ev_ictxqmtc, EVCNT_TYPE_MISC,
 		    NULL, xname, "Intr. Cause Tx Queue Min Thresh");
 		evcnt_attach_dynamic(&sc->sc_ev_rxdmtc, EVCNT_TYPE_MISC,
 		    NULL, xname, "Intr. Cause Rx Desc Min Thresh");
 		/* XXX 82575 document says it has ICRXOC. Is that right? */
 		evcnt_attach_dynamic(&sc->sc_ev_icrxoc, EVCNT_TYPE_MISC,
 		    NULL, xname, "Interrupt Cause Receiver Overrun");
 	} else if (!WM_IS_ICHPCH(sc)) {
 		/*
 		 * For 82575 and newer.
+		 *
 		 * On 80003, ICHs and PCHs, it seems all of the following
 		 * registers are zero.
 		 */
 		evcnt_attach_dynamic(&sc->sc_ev_rpthc, EVCNT_TYPE_MISC,
 		    NULL, xname, "Rx Packets To Host");
 		evcnt_attach_dynamic(&sc->sc_ev_debug1, EVCNT_TYPE_MISC,
 		    NULL, xname, "Debug Counter 1");
 		evcnt_attach_dynamic(&sc->sc_ev_debug2, EVCNT_TYPE_MISC,
 		    NULL, xname, "Debug Counter 2");
 		evcnt_attach_dynamic(&sc->sc_ev_debug3, EVCNT_TYPE_MISC,
 		    NULL, xname, "Debug Counter 3");
 		/*
 		 * 82575 datasheet says 0x4118 is for TXQEC(Tx Queue Empty).
 		 * I think it's wrong. The real count I observed is the same
 		 * as GPTC(Good Packets Tx) and TPT(Total Packets Tx).
 		 * It's HGPTC(Host Good Packets Tx) which is described in
 		 * 82576's datasheet.
 		 */
 		evcnt_attach_dynamic(&sc->sc_ev_hgptc, EVCNT_TYPE_MISC,
 		    NULL, xname, "Host Good Packets TX");
 		evcnt_attach_dynamic(&sc->sc_ev_debug4, EVCNT_TYPE_MISC,
 		    NULL, xname, "Debug Counter 4");
 		evcnt_attach_dynamic(&sc->sc_ev_rxdmtc, EVCNT_TYPE_MISC,
 		    NULL, xname, "Rx Desc Min Thresh");
 		/* XXX Is the circuit breaker only for 82576? */
 		evcnt_attach_dynamic(&sc->sc_ev_htcbdpc, EVCNT_TYPE_MISC,
 		    NULL, xname, "Host Tx Circuit Breaker Dropped Packets");
 		evcnt_attach_dynamic(&sc->sc_ev_hgorc, EVCNT_TYPE_MISC,
 		    NULL, xname, "Host Good Octets Rx");
 		evcnt_attach_dynamic(&sc->sc_ev_hgotc, EVCNT_TYPE_MISC,
 		    NULL, xname, "Host Good Octets Tx");
 		evcnt_attach_dynamic(&sc->sc_ev_lenerrs, EVCNT_TYPE_MISC,
 		    NULL, xname, "Length Errors (length/type <= 1500)");
 		evcnt_attach_dynamic(&sc->sc_ev_scvpc, EVCNT_TYPE_MISC,
 		    NULL, xname, "SerDes/SGMII Code Violation Packet");
 		evcnt_attach_dynamic(&sc->sc_ev_hrmpc, EVCNT_TYPE_MISC,
 		    NULL, xname, "Header Redirection Missed Packet");
+	}
 	if ((sc->sc_type >= WM_T_I350) && !WM_IS_ICHPCH(sc)) {
 		evcnt_attach_dynamic(&sc->sc_ev_tlpic, EVCNT_TYPE_MISC,
 		    NULL, xname, "EEE Tx LPI");
 		evcnt_attach_dynamic(&sc->sc_ev_rlpic, EVCNT_TYPE_MISC,
 		    NULL, xname, "EEE Rx LPI");
 		evcnt_attach_dynamic(&sc->sc_ev_b2ogprc, EVCNT_TYPE_MISC,
 		    NULL, xname, "BMC2OS Packets received by host");
 		evcnt_attach_dynamic(&sc->sc_ev_o2bspc, EVCNT_TYPE_MISC,
 		    NULL, xname, "OS2BMC Packets transmitted by host");
 		evcnt_attach_dynamic(&sc->sc_ev_b2ospc, EVCNT_TYPE_MISC,
 		    NULL, xname, "BMC2OS Packets sent by BMC");
 		evcnt_attach_dynamic(&sc->sc_ev_o2bgptc, EVCNT_TYPE_MISC,
 		    NULL, xname, "OS2BMC Packets received by BMC");
+	}
 #endif /* WM_EVENT_COUNTERS */
 	sc->sc_txrx_use_workqueue = false;
 	if (wm_phy_need_linkdown_discard(sc)) {
 		DPRINTF(sc, WM_DEBUG_LINK,
 		    ("%s: %s: Set linkdown discard flag\n",
 			device_xname(sc->sc_dev), __func__));
 		wm_set_linkdown_discard(sc);
+	}
 	wm_init_sysctls(sc);
 	if (pmf_device_register(self, wm_suspend, wm_resume))
 		pmf_class_network_register(self, ifp);
 	else
 		aprint_error_dev(self, "couldn't establish power handler\n");
 	sc->sc_flags |= WM_F_ATTACHED;
 out:
 	return;
+}
 /* The detach function (ca_detach) */
 static int
 wm_detach(device_t self, int flags __unused)
+{
 	struct wm_softc *sc = device_private(self);
 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
 	int i;
 	if ((sc->sc_flags & WM_F_ATTACHED) == 0)
 		return 0;
 	/* Stop the interface. Callouts are stopped in it. */
 	wm_stop(ifp, 1);
 	pmf_device_deregister(self);
 	sysctl_teardown(&sc->sc_sysctllog);
 #ifdef WM_EVENT_COUNTERS
 	evcnt_detach(&sc->sc_ev_linkintr);
 	evcnt_detach(&sc->sc_ev_crcerrs);
 	evcnt_detach(&sc->sc_ev_symerrc);
 	evcnt_detach(&sc->sc_ev_mpc);
 	evcnt_detach(&sc->sc_ev_colc);
 	evcnt_detach(&sc->sc_ev_sec);
 	evcnt_detach(&sc->sc_ev_rlec);
 	if (sc->sc_type >= WM_T_82543) {
 		evcnt_detach(&sc->sc_ev_algnerrc);
 		evcnt_detach(&sc->sc_ev_rxerrc);
 		if ((sc->sc_type < WM_T_82575) || WM_IS_ICHPCH(sc))
 			evcnt_detach(&sc->sc_ev_cexterr);
 		else
 			evcnt_detach(&sc->sc_ev_htdpmc);
 		evcnt_detach(&sc->sc_ev_tncrs);
 		evcnt_detach(&sc->sc_ev_tsctc);
 		if ((sc->sc_type < WM_T_82575) || WM_IS_ICHPCH(sc))
 			evcnt_detach(&sc->sc_ev_tsctfc);
 		else {
 			evcnt_detach(&sc->sc_ev_cbrdpc);
 			evcnt_detach(&sc->sc_ev_cbrmpc);
+		}
+	}
 	if (sc->sc_type >= WM_T_82542_2_1) {
 		evcnt_detach(&sc->sc_ev_tx_xoff);
 		evcnt_detach(&sc->sc_ev_tx_xon);
 		evcnt_detach(&sc->sc_ev_rx_xoff);
 		evcnt_detach(&sc->sc_ev_rx_xon);
 		evcnt_detach(&sc->sc_ev_rx_macctl);
+	}
 	evcnt_detach(&sc->sc_ev_scc);
 	evcnt_detach(&sc->sc_ev_ecol);
 	evcnt_detach(&sc->sc_ev_mcc);
 	evcnt_detach(&sc->sc_ev_latecol);
 	if ((sc->sc_type >= WM_T_I350) && !WM_IS_ICHPCH(sc))
 		evcnt_detach(&sc->sc_ev_cbtmpc);
 	evcnt_detach(&sc->sc_ev_dc);
 	evcnt_detach(&sc->sc_ev_prc64);
 	evcnt_detach(&sc->sc_ev_prc127);
 	evcnt_detach(&sc->sc_ev_prc255);
 	evcnt_detach(&sc->sc_ev_prc511);
 	evcnt_detach(&sc->sc_ev_prc1023);
 	evcnt_detach(&sc->sc_ev_prc1522);
 	evcnt_detach(&sc->sc_ev_gprc);
 	evcnt_detach(&sc->sc_ev_bprc);
 	evcnt_detach(&sc->sc_ev_mprc);
 	evcnt_detach(&sc->sc_ev_gptc);
 	evcnt_detach(&sc->sc_ev_gorc);
 	evcnt_detach(&sc->sc_ev_gotc);
 	evcnt_detach(&sc->sc_ev_rnbc);
 	evcnt_detach(&sc->sc_ev_ruc);
 	evcnt_detach(&sc->sc_ev_rfc);
 	evcnt_detach(&sc->sc_ev_roc);
 	evcnt_detach(&sc->sc_ev_rjc);
 	if (sc->sc_type >= WM_T_82540) {
 		evcnt_detach(&sc->sc_ev_mgtprc);
 		evcnt_detach(&sc->sc_ev_mgtpdc);
 		evcnt_detach(&sc->sc_ev_mgtptc);
+	}
 	evcnt_detach(&sc->sc_ev_tor);
 	evcnt_detach(&sc->sc_ev_tot);
 	evcnt_detach(&sc->sc_ev_tpr);
 	evcnt_detach(&sc->sc_ev_tpt);
 	evcnt_detach(&sc->sc_ev_ptc64);
 	evcnt_detach(&sc->sc_ev_ptc127);
 	evcnt_detach(&sc->sc_ev_ptc255);
 	evcnt_detach(&sc->sc_ev_ptc511);
 	evcnt_detach(&sc->sc_ev_ptc1023);
 	evcnt_detach(&sc->sc_ev_ptc1522);
 	evcnt_detach(&sc->sc_ev_mptc);
 	evcnt_detach(&sc->sc_ev_bptc);
 	if (sc->sc_type >= WM_T_82571)
 		evcnt_detach(&sc->sc_ev_iac);
 	if (sc->sc_type < WM_T_82575) {
 		evcnt_detach(&sc->sc_ev_icrxptc);
 		evcnt_detach(&sc->sc_ev_icrxatc);
 		evcnt_detach(&sc->sc_ev_ictxptc);
 		evcnt_detach(&sc->sc_ev_ictxatc);
 		evcnt_detach(&sc->sc_ev_ictxqec);
 		evcnt_detach(&sc->sc_ev_ictxqmtc);
 		evcnt_detach(&sc->sc_ev_rxdmtc);
 		evcnt_detach(&sc->sc_ev_icrxoc);
 	} else if (!WM_IS_ICHPCH(sc)) {
 		evcnt_detach(&sc->sc_ev_rpthc);
 		evcnt_detach(&sc->sc_ev_debug1);
 		evcnt_detach(&sc->sc_ev_debug2);
 		evcnt_detach(&sc->sc_ev_debug3);
 		evcnt_detach(&sc->sc_ev_hgptc);
 		evcnt_detach(&sc->sc_ev_debug4);
 		evcnt_detach(&sc->sc_ev_rxdmtc);
 		evcnt_detach(&sc->sc_ev_htcbdpc);
 		evcnt_detach(&sc->sc_ev_hgorc);
 		evcnt_detach(&sc->sc_ev_hgotc);
 		evcnt_detach(&sc->sc_ev_lenerrs);
 		evcnt_detach(&sc->sc_ev_scvpc);
 		evcnt_detach(&sc->sc_ev_hrmpc);
+	}
 	if ((sc->sc_type >= WM_T_I350) && !WM_IS_ICHPCH(sc)) {
 		evcnt_detach(&sc->sc_ev_tlpic);
 		evcnt_detach(&sc->sc_ev_rlpic);
 		evcnt_detach(&sc->sc_ev_b2ogprc);
 		evcnt_detach(&sc->sc_ev_o2bspc);
 		evcnt_detach(&sc->sc_ev_b2ospc);
 		evcnt_detach(&sc->sc_ev_o2bgptc);
+	}
 #endif /* WM_EVENT_COUNTERS */
 	/* Tell the firmware about the release */
 	WM_CORE_LOCK(sc);
 	wm_release_manageability(sc);
 	wm_release_hw_control(sc);
 	wm_enable_wakeup(sc);
 	WM_CORE_UNLOCK(sc);
 	mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY);
 	/* Delete all remaining media. */
 	ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY);
 	ether_ifdetach(ifp);
 	if_detach(ifp);
 	if_percpuq_destroy(sc->sc_ipq);
 	/* Unload RX dmamaps and free mbufs */
 	for (i = 0; i < sc->sc_nqueues; i++) {
 		struct wm_rxqueue *rxq = &sc->sc_queue[i].wmq_rxq;
 		mutex_enter(rxq->rxq_lock);
 		wm_rxdrain(rxq);
 		mutex_exit(rxq->rxq_lock);
+	}
 	/* Must unlock here */
 	/* Disestablish the interrupt handler */
 	for (i = 0; i < sc->sc_nintrs; i++) {
 		if (sc->sc_ihs[i] != NULL) {
 			pci_intr_disestablish(sc->sc_pc, sc->sc_ihs[i]);
 			sc->sc_ihs[i] = NULL;
+		}
+	}
 	pci_intr_release(sc->sc_pc, sc->sc_intrs, sc->sc_nintrs);
 	/* wm_stop() ensured that the workqueue is stopped. */
 	workqueue_destroy(sc->sc_queue_wq);
 	for (i = 0; i < sc->sc_nqueues; i++)
 		softint_disestablish(sc->sc_queue[i].wmq_si);
 	wm_free_txrx_queues(sc);
 	/* Unmap the registers */
 	if (sc->sc_ss) {
 		bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_ss);
 		sc->sc_ss = 0;
+	}
 	if (sc->sc_ios) {
 		bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ios);
 		sc->sc_ios = 0;
+	}
 	if (sc->sc_flashs) {
 		bus_space_unmap(sc->sc_flasht, sc->sc_flashh, sc->sc_flashs);
 		sc->sc_flashs = 0;
+	}
 	if (sc->sc_core_lock)
 		mutex_obj_free(sc->sc_core_lock);
 @@ -5530,3789 +5534,3821 @@ wm_reset(struct wm_softc *sc)
 		CSR_WRITE_FLUSH(sc);
 		delay(5000);
+	}
 	switch (sc->sc_type) {
 	case WM_T_82544: /* XXX check whether WM_F_IOH_VALID is set */
 	case WM_T_82541:
 	case WM_T_82541_2:
 	case WM_T_82547:
 	case WM_T_82547_2:
 		/*
 		 * On some chipsets, a reset through a memory-mapped write
 		 * cycle can cause the chip to reset before completing the
 		 * write cycle. This causes major headache that can be avoided
 		 * by issuing the reset via indirect register writes through
 		 * I/O space.
+		 *
 		 * So, if we successfully mapped the I/O BAR at attach time,
 		 * use that. Otherwise, try our luck with a memory-mapped
 		 * reset.
 		 */
 		if (sc->sc_flags & WM_F_IOH_VALID)
 			wm_io_write(sc, WMREG_CTRL, CTRL_RST);
 		else
 			CSR_WRITE(sc, WMREG_CTRL, CTRL_RST);
 		break;
 	case WM_T_82545_3:
 	case WM_T_82546_3:
 		/* Use the shadow control register on these chips. */
 		CSR_WRITE(sc, WMREG_CTRL_SHADOW, CTRL_RST);
 		break;
 	case WM_T_80003:
 		reg = CSR_READ(sc, WMREG_CTRL) | CTRL_RST;
 		if (sc->phy.acquire(sc) != 0)
 			break;
 		CSR_WRITE(sc, WMREG_CTRL, reg);
 		sc->phy.release(sc);
 		break;
 	case WM_T_ICH8:
 	case WM_T_ICH9:
 	case WM_T_ICH10:
 	case WM_T_PCH:
 	case WM_T_PCH2:
 	case WM_T_PCH_LPT:
 	case WM_T_PCH_SPT:
 	case WM_T_PCH_CNP:
 	case WM_T_PCH_TGP:
 		reg = CSR_READ(sc, WMREG_CTRL) | CTRL_RST;
 		if (wm_phy_resetisblocked(sc) == false) {
 			/*
 			 * Gate automatic PHY configuration by hardware on
 			 * non-managed 82579
 			 */
 			if ((sc->sc_type == WM_T_PCH2)
 			    && ((CSR_READ(sc, WMREG_FWSM) & FWSM_FW_VALID)
 				== 0))
 				wm_gate_hw_phy_config_ich8lan(sc, true);
 			reg |= CTRL_PHY_RESET;
 			phy_reset = 1;
 		} else
 			device_printf(sc->sc_dev, "XXX reset is blocked!!!\n");
 		if (sc->phy.acquire(sc) != 0)
 			break;
 		CSR_WRITE(sc, WMREG_CTRL, reg);
 		/* Don't insert a completion barrier when reset */
 		delay(20*1000);
 		/*
 		 * The EXTCNFCTR_MDIO_SW_OWNERSHIP bit is cleared by the reset,
 		 * so don't use sc->phy.release(sc). Release sc_ich_phymtx
 		 * only. See also wm_get_swflag_ich8lan().
 		 */
 		mutex_exit(sc->sc_ich_phymtx);
 		break;
 	case WM_T_82580:
 	case WM_T_I350:
 	case WM_T_I354:
 	case WM_T_I210:
 	case WM_T_I211:
 		CSR_WRITE(sc, WMREG_CTRL, CSR_READ(sc, WMREG_CTRL) | CTRL_RST);
 		if (sc->sc_pcidevid != PCI_PRODUCT_INTEL_DH89XXCC_SGMII)
 			CSR_WRITE_FLUSH(sc);
 		delay(5000);
 		break;
 	case WM_T_82542_2_0:
 	case WM_T_82542_2_1:
 	case WM_T_82543:
 	case WM_T_82540:
 	case WM_T_82545:
 	case WM_T_82546:
 	case WM_T_82571:
 	case WM_T_82572:
 	case WM_T_82573:
 	case WM_T_82574:
 	case WM_T_82575:
 	case WM_T_82576:
 	case WM_T_82583:
 	default:
 		/* Everything else can safely use the documented method. */
 		CSR_WRITE(sc, WMREG_CTRL, CSR_READ(sc, WMREG_CTRL) | CTRL_RST);
 		break;
+	}
 	/* Must release the MDIO ownership after MAC reset */
 	switch (sc->sc_type) {
 	case WM_T_82573:
 	case WM_T_82574:
 	case WM_T_82583:
 		if (error == 0)
 			wm_put_hw_semaphore_82573(sc);
 		break;
 	default:
 		break;
+	}
 	/* Set Phy Config Counter to 50msec */
 	if (sc->sc_type == WM_T_PCH2) {
 		reg = CSR_READ(sc, WMREG_FEXTNVM3);
 		reg &= ~FEXTNVM3_PHY_CFG_COUNTER_MASK;
 		reg |= FEXTNVM3_PHY_CFG_COUNTER_50MS;
 		CSR_WRITE(sc, WMREG_FEXTNVM3, reg);
+	}
 	if (phy_reset != 0)
 		wm_get_cfg_done(sc);
 	/* Reload EEPROM */
 	switch (sc->sc_type) {
 	case WM_T_82542_2_0:
 	case WM_T_82542_2_1:
 	case WM_T_82543:
 	case WM_T_82544:
 		delay(10);
 		reg = CSR_READ(sc, WMREG_CTRL_EXT) | CTRL_EXT_EE_RST;
 		CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
 		CSR_WRITE_FLUSH(sc);
 		delay(2000);
 		break;
 	case WM_T_82540:
 	case WM_T_82545:
 	case WM_T_82545_3:
 	case WM_T_82546:
 	case WM_T_82546_3:
 		delay(5*1000);
 		/* XXX Disable HW ARPs on ASF enabled adapters */
 		break;
 	case WM_T_82541:
 	case WM_T_82541_2:
 	case WM_T_82547:
 	case WM_T_82547_2:
 		delay(20000);
 		/* XXX Disable HW ARPs on ASF enabled adapters */
 		break;
 	case WM_T_82571:
 	case WM_T_82572:
 	case WM_T_82573:
 	case WM_T_82574:
 	case WM_T_82583:
 		if (sc->sc_flags & WM_F_EEPROM_FLASH) {
 			delay(10);
 			reg = CSR_READ(sc, WMREG_CTRL_EXT) | CTRL_EXT_EE_RST;
 			CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
 			CSR_WRITE_FLUSH(sc);
+		}
 		/* check EECD_EE_AUTORD */
 		wm_get_auto_rd_done(sc);
 		/*
 		 * Phy configuration from NVM just starts after EECD_AUTO_RD
 		 * is set.
 		 */
 		if ((sc->sc_type == WM_T_82573) || (sc->sc_type == WM_T_82574)
 		    || (sc->sc_type == WM_T_82583))
 			delay(25*1000);
 		break;
 	case WM_T_82575:
 	case WM_T_82576:
 	case WM_T_82580:
 	case WM_T_I350:
 	case WM_T_I354:
 	case WM_T_I210:
 	case WM_T_I211:
 	case WM_T_80003:
 		/* check EECD_EE_AUTORD */
 		wm_get_auto_rd_done(sc);
 		break;
 	case WM_T_ICH8:
 	case WM_T_ICH9:
 	case WM_T_ICH10:
 	case WM_T_PCH:
 	case WM_T_PCH2:
 	case WM_T_PCH_LPT:
 	case WM_T_PCH_SPT:
 	case WM_T_PCH_CNP:
 	case WM_T_PCH_TGP:
 		break;
 	default:
 		panic("%s: unknown type\n", __func__);
+	}
 	/* Check whether EEPROM is present or not */
 	switch (sc->sc_type) {
 	case WM_T_82575:
 	case WM_T_82576:
 	case WM_T_82580:
 	case WM_T_I350:
 	case WM_T_I354:
 	case WM_T_ICH8:
 	case WM_T_ICH9:
 		if ((CSR_READ(sc, WMREG_EECD) & EECD_EE_PRES) == 0) {
 			/* Not found */
 			sc->sc_flags |= WM_F_EEPROM_INVALID;
 			if (sc->sc_type == WM_T_82575)
 				wm_reset_init_script_82575(sc);
+		}
 		break;
 	default:
 		break;
+	}
 	if (phy_reset != 0)
 		wm_phy_post_reset(sc);
 	if ((sc->sc_type == WM_T_82580)
 	    || (sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354)) {
 		/* Clear global device reset status bit */
 		CSR_WRITE(sc, WMREG_STATUS, STATUS_DEV_RST_SET);
+	}
 	/* Clear any pending interrupt events. */
 	CSR_WRITE(sc, WMREG_IMC, 0xffffffffU);
 	reg = CSR_READ(sc, WMREG_ICR);
 	if (wm_is_using_msix(sc)) {
 		if (sc->sc_type != WM_T_82574) {
 			CSR_WRITE(sc, WMREG_EIMC, 0xffffffffU);
 			CSR_WRITE(sc, WMREG_EIAC, 0);
 		} else
 			CSR_WRITE(sc, WMREG_EIAC_82574, 0);
+	}
 	if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
 	    || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH)
 	    || (sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT)
 	    || (sc->sc_type == WM_T_PCH_SPT) || (sc->sc_type == WM_T_PCH_CNP)
 	    || (sc->sc_type == WM_T_PCH_TGP)) {
 		reg = CSR_READ(sc, WMREG_KABGTXD);
 		reg |= KABGTXD_BGSQLBIAS;
 		CSR_WRITE(sc, WMREG_KABGTXD, reg);
+	}
 	/* Reload sc_ctrl */
 	sc->sc_ctrl = CSR_READ(sc, WMREG_CTRL);
 	if (sc->sc_type == WM_T_I354) {
 #if 0
 		/* I354 uses an external PHY */
 		wm_set_eee_i354(sc);
 #endif
 	} else if ((sc->sc_type >= WM_T_I350) && (sc->sc_type <= WM_T_I211))
 		wm_set_eee_i350(sc);
 	/*
 	 * For PCH, this write will make sure that any noise will be detected
 	 * as a CRC error and be dropped rather than show up as a bad packet
 	 * to the DMA engine
 	 */
 	if (sc->sc_type == WM_T_PCH)
 		CSR_WRITE(sc, WMREG_CRC_OFFSET, 0x65656565);
 	if (sc->sc_type >= WM_T_82544)
 		CSR_WRITE(sc, WMREG_WUC, 0);
 	if (sc->sc_type < WM_T_82575)
 		wm_disable_aspm(sc); /* Workaround for some chips */
 	wm_reset_mdicnfg_82580(sc);
 	if ((sc->sc_flags & WM_F_PLL_WA_I210) != 0)
 		wm_pll_workaround_i210(sc);
 	if (sc->sc_type == WM_T_80003) {
 		/* Default to TRUE to enable the MDIC W/A */
 		sc->sc_flags |= WM_F_80003_MDIC_WA;
 		rv = wm_kmrn_readreg(sc,
 		    KUMCTRLSTA_OFFSET >> KUMCTRLSTA_OFFSET_SHIFT, &kmreg);
 		if (rv == 0) {
 			if ((kmreg & KUMCTRLSTA_OPMODE_MASK)
 			    == KUMCTRLSTA_OPMODE_INBAND_MDIO)
 				sc->sc_flags &= ~WM_F_80003_MDIC_WA;
 			else
 				sc->sc_flags |= WM_F_80003_MDIC_WA;
+		}
+	}
+}
 /*
  * wm_add_rxbuf:
+ *
  *	Add a receive buffer to the indiciated descriptor.
  */
 static int
 wm_add_rxbuf(struct wm_rxqueue *rxq, int idx)
+{
 	struct wm_softc *sc = rxq->rxq_sc;
 	struct wm_rxsoft *rxs = &rxq->rxq_soft[idx];
 	struct mbuf *m;
 	int error;
 	KASSERT(mutex_owned(rxq->rxq_lock));
 	MGETHDR(m, M_DONTWAIT, MT_DATA);
 	if (m == NULL)
 		return ENOBUFS;
 	MCLGET(m, M_DONTWAIT);
 	if ((m->m_flags & M_EXT) == 0) {
 		m_freem(m);
 		return ENOBUFS;
+	}
 	if (rxs->rxs_mbuf != NULL)
 		bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap);
 	rxs->rxs_mbuf = m;
 	m->m_len = m->m_pkthdr.len = m->m_ext.ext_size;
 	error = bus_dmamap_load_mbuf(sc->sc_dmat, rxs->rxs_dmamap, m,
 	    BUS_DMA_READ | BUS_DMA_NOWAIT);
 	if (error) {
 		/* XXX XXX XXX */
 		aprint_error_dev(sc->sc_dev,
 		    "unable to load rx DMA map %d, error = %d\n", idx, error);
 		panic("wm_add_rxbuf");
+	}
 	bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0,
 	    rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
 	if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) {
 		if ((sc->sc_rctl & RCTL_EN) != 0)
 			wm_init_rxdesc(rxq, idx);
 	} else
 		wm_init_rxdesc(rxq, idx);
 	return 0;
+}
 /*
  * wm_rxdrain:
+ *
  *	Drain the receive queue.
  */
 static void
 wm_rxdrain(struct wm_rxqueue *rxq)
+{
 	struct wm_softc *sc = rxq->rxq_sc;
 	struct wm_rxsoft *rxs;
 	int i;
 	KASSERT(mutex_owned(rxq->rxq_lock));
 	for (i = 0; i < WM_NRXDESC; i++) {
 		rxs = &rxq->rxq_soft[i];
 		if (rxs->rxs_mbuf != NULL) {
 			bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap);
 			m_freem(rxs->rxs_mbuf);
 			rxs->rxs_mbuf = NULL;
+		}
+	}
+}
 /*
  * Setup registers for RSS.
+ *
  * XXX not yet VMDq support
  */
 static void
 wm_init_rss(struct wm_softc *sc)
+{
 	uint32_t mrqc, reta_reg, rss_key[RSSRK_NUM_REGS];
 	int i;
 	CTASSERT(sizeof(rss_key) == RSS_KEYSIZE);
 	for (i = 0; i < RETA_NUM_ENTRIES; i++) {
 		unsigned int qid, reta_ent;
 		qid  = i % sc->sc_nqueues;
 		switch (sc->sc_type) {
 		case WM_T_82574:
 			reta_ent = __SHIFTIN(qid,
 			    RETA_ENT_QINDEX_MASK_82574);
 			break;
 		case WM_T_82575:
 			reta_ent = __SHIFTIN(qid,
 			    RETA_ENT_QINDEX1_MASK_82575);
 			break;
 		default:
 			reta_ent = __SHIFTIN(qid, RETA_ENT_QINDEX_MASK);
 			break;
+		}
 		reta_reg = CSR_READ(sc, WMREG_RETA_Q(i));
 		reta_reg &= ~RETA_ENTRY_MASK_Q(i);
 		reta_reg |= __SHIFTIN(reta_ent, RETA_ENTRY_MASK_Q(i));
 		CSR_WRITE(sc, WMREG_RETA_Q(i), reta_reg);
+	}
 	rss_getkey((uint8_t *)rss_key);
 	for (i = 0; i < RSSRK_NUM_REGS; i++)
 		CSR_WRITE(sc, WMREG_RSSRK(i), rss_key[i]);
 	if (sc->sc_type == WM_T_82574)
 		mrqc = MRQC_ENABLE_RSS_MQ_82574;
 	else
 		mrqc = MRQC_ENABLE_RSS_MQ;
 	/*
 	 * MRQC_RSS_FIELD_IPV6_EX is not set because of an errata.
 	 * See IPV6EXDIS bit in wm_initialize_hardware_bits().
 	 */
 	mrqc |= (MRQC_RSS_FIELD_IPV4 | MRQC_RSS_FIELD_IPV4_TCP);
 	mrqc |= (MRQC_RSS_FIELD_IPV6 | MRQC_RSS_FIELD_IPV6_TCP);
 #if 0
 	mrqc |= (MRQC_RSS_FIELD_IPV4_UDP | MRQC_RSS_FIELD_IPV6_UDP);
 	mrqc |= MRQC_RSS_FIELD_IPV6_UDP_EX;
 #endif
 	mrqc |= MRQC_RSS_FIELD_IPV6_TCP_EX;
 	CSR_WRITE(sc, WMREG_MRQC, mrqc);
+}
 /*
  * Adjust TX and RX queue numbers which the system actulally uses.
+ *
  * The numbers are affected by below parameters.
  *     - The nubmer of hardware queues
  *     - The number of MSI-X vectors (= "nvectors" argument)
  *     - ncpu
  */
 static void
 wm_adjust_qnum(struct wm_softc *sc, int nvectors)
+{
 	int hw_ntxqueues, hw_nrxqueues, hw_nqueues;
 	if (nvectors < 2) {
 		sc->sc_nqueues = 1;
 		return;
+	}
 	switch (sc->sc_type) {
 	case WM_T_82572:
 		hw_ntxqueues = 2;
 		hw_nrxqueues = 2;
 		break;
 	case WM_T_82574:
 		hw_ntxqueues = 2;
 		hw_nrxqueues = 2;
 		break;
 	case WM_T_82575:
 		hw_ntxqueues = 4;
 		hw_nrxqueues = 4;
 		break;
 	case WM_T_82576:
 		hw_ntxqueues = 16;
 		hw_nrxqueues = 16;
 		break;
 	case WM_T_82580:
 	case WM_T_I350:
 	case WM_T_I354:
 		hw_ntxqueues = 8;
 		hw_nrxqueues = 8;
 		break;
 	case WM_T_I210:
 		hw_ntxqueues = 4;
 		hw_nrxqueues = 4;
 		break;
 	case WM_T_I211:
 		hw_ntxqueues = 2;
 		hw_nrxqueues = 2;
 		break;
 		/*
 		 * The below Ethernet controllers do not support MSI-X;
 		 * this driver doesn't let them use multiqueue.
 		 *     - WM_T_80003
 		 *     - WM_T_ICH8
 		 *     - WM_T_ICH9
 		 *     - WM_T_ICH10
 		 *     - WM_T_PCH
 		 *     - WM_T_PCH2
 		 *     - WM_T_PCH_LPT
 		 */
 	default:
 		hw_ntxqueues = 1;
 		hw_nrxqueues = 1;
 		break;
+	}
 	hw_nqueues = min(hw_ntxqueues, hw_nrxqueues);
 	/*
 	 * As queues more than MSI-X vectors cannot improve scaling, we limit
 	 * the number of queues used actually.
 	 */
 	if (nvectors < hw_nqueues + 1)
 		sc->sc_nqueues = nvectors - 1;
 	else
 		sc->sc_nqueues = hw_nqueues;
 	/*
 	 * As queues more than CPUs cannot improve scaling, we limit
 	 * the number of queues used actually.
 	 */
 	if (ncpu < sc->sc_nqueues)
 		sc->sc_nqueues = ncpu;
+}
 static inline bool
 wm_is_using_msix(struct wm_softc *sc)
+{
 	return (sc->sc_nintrs > 1);
+}
 static inline bool
 wm_is_using_multiqueue(struct wm_softc *sc)
+{
 	return (sc->sc_nqueues > 1);
+}
 static int
 wm_softint_establish_queue(struct wm_softc *sc, int qidx, int intr_idx)
+{
 	struct wm_queue *wmq = &sc->sc_queue[qidx];
 	wmq->wmq_id = qidx;
 	wmq->wmq_intr_idx = intr_idx;
 	wmq->wmq_si = softint_establish(SOFTINT_NET | WM_SOFTINT_FLAGS,
 	    wm_handle_queue, wmq);
 	if (wmq->wmq_si != NULL)
 		return 0;
 	aprint_error_dev(sc->sc_dev, "unable to establish queue[%d] handler\n",
 	    wmq->wmq_id);
 	pci_intr_disestablish(sc->sc_pc, sc->sc_ihs[wmq->wmq_intr_idx]);
 	sc->sc_ihs[wmq->wmq_intr_idx] = NULL;
 	return ENOMEM;
+}
 /*
  * Both single interrupt MSI and INTx can use this function.
  */
 static int
 wm_setup_legacy(struct wm_softc *sc)
+{
 	pci_chipset_tag_t pc = sc->sc_pc;
 	const char *intrstr = NULL;
 	char intrbuf[PCI_INTRSTR_LEN];
 	int error;
 	error = wm_alloc_txrx_queues(sc);
 	if (error) {
 		aprint_error_dev(sc->sc_dev, "cannot allocate queues %d\n",
 		    error);
 		return ENOMEM;
+	}
 	intrstr = pci_intr_string(pc, sc->sc_intrs[0], intrbuf,
 	    sizeof(intrbuf));
 #ifdef WM_MPSAFE
 	pci_intr_setattr(pc, &sc->sc_intrs[0], PCI_INTR_MPSAFE, true);
 #endif
 	sc->sc_ihs[0] = pci_intr_establish_xname(pc, sc->sc_intrs[0],
 	    IPL_NET, wm_intr_legacy, sc, device_xname(sc->sc_dev));
 	if (sc->sc_ihs[0] == NULL) {
 		aprint_error_dev(sc->sc_dev,"unable to establish %s\n",
 		    (pci_intr_type(pc, sc->sc_intrs[0])
 			== PCI_INTR_TYPE_MSI) ? "MSI" : "INTx");
 		return ENOMEM;
+	}
 	aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr);
 	sc->sc_nintrs = 1;
 	return wm_softint_establish_queue(sc, 0, 0);
+}
 static int
 wm_setup_msix(struct wm_softc *sc)
+{
 	void *vih;
 	kcpuset_t *affinity;
 	int qidx, error, intr_idx, txrx_established;
 	pci_chipset_tag_t pc = sc->sc_pc;
 	const char *intrstr = NULL;
 	char intrbuf[PCI_INTRSTR_LEN];
 	char intr_xname[INTRDEVNAMEBUF];
 	if (sc->sc_nqueues < ncpu) {
 		/*
 		 * To avoid other devices' interrupts, the affinity of Tx/Rx
 		 * interrupts start from CPU#1.
 		 */
 		sc->sc_affinity_offset = 1;
 	} else {
 		/*
 		 * In this case, this device use all CPUs. So, we unify
 		 * affinitied cpu_index to msix vector number for readability.
 		 */
 		sc->sc_affinity_offset = 0;
+	}
 	error = wm_alloc_txrx_queues(sc);
 	if (error) {
 		aprint_error_dev(sc->sc_dev, "cannot allocate queues %d\n",
 		    error);
 		return ENOMEM;
+	}
 	kcpuset_create(&affinity, false);
 	intr_idx = 0;
 	/*
 	 * TX and RX
 	 */
 	txrx_established = 0;
 	for (qidx = 0; qidx < sc->sc_nqueues; qidx++) {
 		struct wm_queue *wmq = &sc->sc_queue[qidx];
 		int affinity_to = (sc->sc_affinity_offset + intr_idx) % ncpu;
 		intrstr = pci_intr_string(pc, sc->sc_intrs[intr_idx], intrbuf,
 		    sizeof(intrbuf));
 #ifdef WM_MPSAFE
 		pci_intr_setattr(pc, &sc->sc_intrs[intr_idx],
 		    PCI_INTR_MPSAFE, true);
 #endif
 		memset(intr_xname, 0, sizeof(intr_xname));
 		snprintf(intr_xname, sizeof(intr_xname), "%sTXRX%d",
 		    device_xname(sc->sc_dev), qidx);
 		vih = pci_intr_establish_xname(pc, sc->sc_intrs[intr_idx],
 		    IPL_NET, wm_txrxintr_msix, wmq, intr_xname);
 		if (vih == NULL) {
 			aprint_error_dev(sc->sc_dev,
 			    "unable to establish MSI-X(for TX and RX)%s%s\n",
 			    intrstr ? " at " : "",
 			    intrstr ? intrstr : "");
 			goto fail;
+		}
 		kcpuset_zero(affinity);
 		/* Round-robin affinity */
 		kcpuset_set(affinity, affinity_to);
 		error = interrupt_distribute(vih, affinity, NULL);
 		if (error == 0) {
 			aprint_normal_dev(sc->sc_dev,
 			    "for TX and RX interrupting at %s affinity to %u\n",
 			    intrstr, affinity_to);
 		} else {
 			aprint_normal_dev(sc->sc_dev,
 			    "for TX and RX interrupting at %s\n", intrstr);
+		}
 		sc->sc_ihs[intr_idx] = vih;
 		if (wm_softint_establish_queue(sc, qidx, intr_idx) != 0)
 			goto fail;
 		txrx_established++;
 		intr_idx++;
+	}
 	/* LINK */
 	intrstr = pci_intr_string(pc, sc->sc_intrs[intr_idx], intrbuf,
 	    sizeof(intrbuf));
 #ifdef WM_MPSAFE
 	pci_intr_setattr(pc, &sc->sc_intrs[intr_idx], PCI_INTR_MPSAFE, true);
 #endif
 	memset(intr_xname, 0, sizeof(intr_xname));
 	snprintf(intr_xname, sizeof(intr_xname), "%sLINK",
 	    device_xname(sc->sc_dev));
 	vih = pci_intr_establish_xname(pc, sc->sc_intrs[intr_idx],
 	    IPL_NET, wm_linkintr_msix, sc, intr_xname);
 	if (vih == NULL) {
 		aprint_error_dev(sc->sc_dev,
 		    "unable to establish MSI-X(for LINK)%s%s\n",
 		    intrstr ? " at " : "",
 		    intrstr ? intrstr : "");
 		goto fail;
+	}
 	/* Keep default affinity to LINK interrupt */
 	aprint_normal_dev(sc->sc_dev,
 	    "for LINK interrupting at %s\n", intrstr);
 	sc->sc_ihs[intr_idx] = vih;
 	sc->sc_link_intr_idx = intr_idx;
 	sc->sc_nintrs = sc->sc_nqueues + 1;
 	kcpuset_destroy(affinity);
 	return 0;
 fail:
 	for (qidx = 0; qidx < txrx_established; qidx++) {
 		struct wm_queue *wmq = &sc->sc_queue[qidx];
 		pci_intr_disestablish(sc->sc_pc,sc->sc_ihs[wmq->wmq_intr_idx]);
 		sc->sc_ihs[wmq->wmq_intr_idx] = NULL;
+	}
 	kcpuset_destroy(affinity);
 	return ENOMEM;
+}
 static void
 wm_unset_stopping_flags(struct wm_softc *sc)
+{
 	int i;
 	KASSERT(WM_CORE_LOCKED(sc));
 	/* Must unset stopping flags in ascending order. */
 	for (i = 0; i < sc->sc_nqueues; i++) {
 		struct wm_txqueue *txq = &sc->sc_queue[i].wmq_txq;
 		struct wm_rxqueue *rxq = &sc->sc_queue[i].wmq_rxq;
 		mutex_enter(txq->txq_lock);
 		txq->txq_stopping = false;
 		mutex_exit(txq->txq_lock);
 		mutex_enter(rxq->rxq_lock);
 		rxq->rxq_stopping = false;
 		mutex_exit(rxq->rxq_lock);
+	}
 	sc->sc_core_stopping = false;
+}
 static void
 wm_set_stopping_flags(struct wm_softc *sc)
+{
 	int i;
 	KASSERT(WM_CORE_LOCKED(sc));
 	sc->sc_core_stopping = true;
 	/* Must set stopping flags in ascending order. */
 	for (i = 0; i < sc->sc_nqueues; i++) {
 		struct wm_rxqueue *rxq = &sc->sc_queue[i].wmq_rxq;
 		struct wm_txqueue *txq = &sc->sc_queue[i].wmq_txq;
 		mutex_enter(rxq->rxq_lock);
 		rxq->rxq_stopping = true;
 		mutex_exit(rxq->rxq_lock);
 		mutex_enter(txq->txq_lock);
 		txq->txq_stopping = true;
 		mutex_exit(txq->txq_lock);
+	}
+}
 /*
  * Write interrupt interval value to ITR or EITR
  */
 static void
 wm_itrs_writereg(struct wm_softc *sc, struct wm_queue *wmq)
+{
 	if (!wmq->wmq_set_itr)
 		return;
 	if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) {
 		uint32_t eitr = __SHIFTIN(wmq->wmq_itr, EITR_ITR_INT_MASK);
 		/*
 		 * 82575 doesn't have CNT_INGR field.
 		 * So, overwrite counter field by software.
 		 */
 		if (sc->sc_type == WM_T_82575)
 			eitr |= __SHIFTIN(wmq->wmq_itr,
 			    EITR_COUNTER_MASK_82575);
 		else
 			eitr |= EITR_CNT_INGR;
 		CSR_WRITE(sc, WMREG_EITR(wmq->wmq_intr_idx), eitr);
 	} else if (sc->sc_type == WM_T_82574 && wm_is_using_msix(sc)) {
 		/*
 		 * 82574 has both ITR and EITR. SET EITR when we use
 		 * the multi queue function with MSI-X.
 		 */
 		CSR_WRITE(sc, WMREG_EITR_82574(wmq->wmq_intr_idx),
 		    wmq->wmq_itr & EITR_ITR_INT_MASK_82574);
 	} else {
 		KASSERT(wmq->wmq_id == 0);
 		CSR_WRITE(sc, WMREG_ITR, wmq->wmq_itr);
+	}
 	wmq->wmq_set_itr = false;
+}
 /*
  * TODO
  * Below dynamic calculation of itr is almost the same as Linux igb,
  * however it does not fit to wm(4). So, we will have been disable AIM
  * until we will find appropriate calculation of itr.
  */
 /*
  * Calculate interrupt interval value to be going to write register in
  * wm_itrs_writereg(). This function does not write ITR/EITR register.
  */
 static void
 wm_itrs_calculate(struct wm_softc *sc, struct wm_queue *wmq)
+{
 #ifdef NOTYET
 	struct wm_rxqueue *rxq = &wmq->wmq_rxq;
 	struct wm_txqueue *txq = &wmq->wmq_txq;
 	uint32_t avg_size = 0;
 	uint32_t new_itr;
 	if (rxq->rxq_packets)
 		avg_size =  rxq->rxq_bytes / rxq->rxq_packets;
 	if (txq->txq_packets)
 		avg_size = max(avg_size, txq->txq_bytes / txq->txq_packets);
 	if (avg_size == 0) {
 		new_itr = 450; /* restore default value */
 		goto out;
+	}
 	/* Add 24 bytes to size to account for CRC, preamble, and gap */
 	avg_size += 24;
 	/* Don't starve jumbo frames */
 	avg_size = min(avg_size, 3000);
 	/* Give a little boost to mid-size frames */
 	if ((avg_size > 300) && (avg_size < 1200))
 		new_itr = avg_size / 3;
 	else
 		new_itr = avg_size / 2;
 out:
 	/*
 	 * The usage of 82574 and 82575 EITR is different from otther NEWQUEUE
 	 * controllers. See sc->sc_itr_init setting in wm_init_locked().
 	 */
 	if ((sc->sc_flags & WM_F_NEWQUEUE) == 0 || sc->sc_type != WM_T_82575)
 		new_itr *= 4;
 	if (new_itr != wmq->wmq_itr) {
 		wmq->wmq_itr = new_itr;
 		wmq->wmq_set_itr = true;
 	} else
 		wmq->wmq_set_itr = false;
 	rxq->rxq_packets = 0;
 	rxq->rxq_bytes = 0;
 	txq->txq_packets = 0;
 	txq->txq_bytes = 0;
 #endif
+}
 static void
 wm_init_sysctls(struct wm_softc *sc)
+{
 	struct sysctllog **log;
 	const struct sysctlnode *rnode, *qnode, *cnode;
 	int i, rv;
 	const char *dvname;
 	log = &sc->sc_sysctllog;
 	dvname = device_xname(sc->sc_dev);
 	rv = sysctl_createv(log, 0, NULL, &rnode,
 , CTLTYPE_NODE, dvname,
 	    SYSCTL_DESCR("wm information and settings"),
 	    NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL);
 	if (rv != 0)
 		goto err;
 	rv = sysctl_createv(log, 0, &rnode, &cnode, CTLFLAG_READWRITE,
 	    CTLTYPE_BOOL, "txrx_workqueue",
 	    SYSCTL_DESCR("Use workqueue for packet processing"),
 	    NULL, 0, &sc->sc_txrx_use_workqueue, 0, CTL_CREATE, CTL_EOL);
 	if (rv != 0)
 		goto teardown;
 	for (i = 0; i < sc->sc_nqueues; i++) {
 		struct wm_queue *wmq = &sc->sc_queue[i];
 		struct wm_txqueue *txq = &wmq->wmq_txq;
 		struct wm_rxqueue *rxq = &wmq->wmq_rxq;
 		snprintf(sc->sc_queue[i].sysctlname,
 		    sizeof(sc->sc_queue[i].sysctlname), "q%d", i);
 		if (sysctl_createv(log, 0, &rnode, &qnode,
 , CTLTYPE_NODE,
 		    sc->sc_queue[i].sysctlname, SYSCTL_DESCR("Queue Name"),
 		    NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL) != 0)
 			break;
 		if (sysctl_createv(log, 0, &qnode, &cnode,
 		    CTLFLAG_READONLY, CTLTYPE_INT,
 		    "txq_free", SYSCTL_DESCR("TX queue free"),
 		    NULL, 0, &txq->txq_free,
 , CTL_CREATE, CTL_EOL) != 0)
 			break;
 		if (sysctl_createv(log, 0, &qnode, &cnode,
 		    CTLFLAG_READONLY, CTLTYPE_INT,
 		    "txd_head", SYSCTL_DESCR("TX descriptor head"),
 		    wm_sysctl_tdh_handler, 0, (void *)txq,
 , CTL_CREATE, CTL_EOL) != 0)
 			break;
 		if (sysctl_createv(log, 0, &qnode, &cnode,
 		    CTLFLAG_READONLY, CTLTYPE_INT,
 		    "txd_tail", SYSCTL_DESCR("TX descriptor tail"),
 		    wm_sysctl_tdt_handler, 0, (void *)txq,
 , CTL_CREATE, CTL_EOL) != 0)
 			break;
 		if (sysctl_createv(log, 0, &qnode, &cnode,
 		    CTLFLAG_READONLY, CTLTYPE_INT,
 		    "txq_next", SYSCTL_DESCR("TX queue next"),
 		    NULL, 0, &txq->txq_next,
 , CTL_CREATE, CTL_EOL) != 0)
 			break;
 		if (sysctl_createv(log, 0, &qnode, &cnode,
 		    CTLFLAG_READONLY, CTLTYPE_INT,
 		    "txq_sfree", SYSCTL_DESCR("TX queue sfree"),
 		    NULL, 0, &txq->txq_sfree,
 , CTL_CREATE, CTL_EOL) != 0)
 			break;
 		if (sysctl_createv(log, 0, &qnode, &cnode,
 		    CTLFLAG_READONLY, CTLTYPE_INT,
 		    "txq_snext", SYSCTL_DESCR("TX queue snext"),
 		    NULL, 0, &txq->txq_snext,
 , CTL_CREATE, CTL_EOL) != 0)
 			break;
 		if (sysctl_createv(log, 0, &qnode, &cnode,
 		    CTLFLAG_READONLY, CTLTYPE_INT,
 		    "txq_sdirty", SYSCTL_DESCR("TX queue sdirty"),
 		    NULL, 0, &txq->txq_sdirty,
 , CTL_CREATE, CTL_EOL) != 0)
 			break;
 		if (sysctl_createv(log, 0, &qnode, &cnode,
 		    CTLFLAG_READONLY, CTLTYPE_INT,
 		    "txq_flags", SYSCTL_DESCR("TX queue flags"),
 		    NULL, 0, &txq->txq_flags,
 , CTL_CREATE, CTL_EOL) != 0)
 			break;
 		if (sysctl_createv(log, 0, &qnode, &cnode,
 		    CTLFLAG_READONLY, CTLTYPE_BOOL,
 		    "txq_stopping", SYSCTL_DESCR("TX queue stopping"),
 		    NULL, 0, &txq->txq_stopping,
 , CTL_CREATE, CTL_EOL) != 0)
 			break;
 		if (sysctl_createv(log, 0, &qnode, &cnode,
 		    CTLFLAG_READONLY, CTLTYPE_BOOL,
 		    "txq_sending", SYSCTL_DESCR("TX queue sending"),
 		    NULL, 0, &txq->txq_sending,
 , CTL_CREATE, CTL_EOL) != 0)
 			break;
 		if (sysctl_createv(log, 0, &qnode, &cnode,
 		    CTLFLAG_READONLY, CTLTYPE_INT,
 		    "rxq_ptr", SYSCTL_DESCR("RX queue pointer"),
 		    NULL, 0, &rxq->rxq_ptr,
 , CTL_CREATE, CTL_EOL) != 0)
 			break;
+	}
 #ifdef WM_DEBUG
 	rv = sysctl_createv(log, 0, &rnode, &cnode, CTLFLAG_READWRITE,
 	    CTLTYPE_INT, "debug_flags",
 	    SYSCTL_DESCR(
 		    "Debug flags:\n"	\
 		    "\t0x01 LINK\n"	\
 		    "\t0x02 TX\n"	\
 		    "\t0x04 RX\n"	\
 		    "\t0x08 GMII\n"	\
 		    "\t0x10 MANAGE\n"	\
 		    "\t0x20 NVM\n"	\
 		    "\t0x40 INIT\n"	\
 		    "\t0x80 LOCK"),
 	    wm_sysctl_debug, 0, (void *)sc, 0, CTL_CREATE, CTL_EOL);
 	if (rv != 0)
 		goto teardown;
 #endif
 	return;
 teardown:
 	sysctl_teardown(log);
 err:
 	sc->sc_sysctllog = NULL;
 	device_printf(sc->sc_dev, "%s: sysctl_createv failed, rv = %d\n",
 	    __func__, rv);
+}
 static void
 wm_update_stats(struct wm_softc *sc)
+{
 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
 	uint64_t crcerrs, algnerrc, symerrc, mpc, colc,  sec, rlec, rxerrc,
 	    cexterr;
 	uint64_t total_qdrop = 0;
 	crcerrs = CSR_READ(sc, WMREG_CRCERRS);
 	symerrc = CSR_READ(sc, WMREG_SYMERRC);
 	mpc = CSR_READ(sc, WMREG_MPC);
 	colc = CSR_READ(sc, WMREG_COLC);
 	sec = CSR_READ(sc, WMREG_SEC);
 	rlec = CSR_READ(sc, WMREG_RLEC);
 	WM_EVCNT_ADD(&sc->sc_ev_crcerrs, crcerrs);
 	WM_EVCNT_ADD(&sc->sc_ev_symerrc, symerrc);
 	WM_EVCNT_ADD(&sc->sc_ev_mpc, mpc);
 	WM_EVCNT_ADD(&sc->sc_ev_colc, colc);
 	WM_EVCNT_ADD(&sc->sc_ev_sec, sec);
 	WM_EVCNT_ADD(&sc->sc_ev_rlec, rlec);
 	if (sc->sc_type >= WM_T_82543) {
 		algnerrc = CSR_READ(sc, WMREG_ALGNERRC);
 		rxerrc = CSR_READ(sc, WMREG_RXERRC);
 		WM_EVCNT_ADD(&sc->sc_ev_algnerrc, algnerrc);
 		WM_EVCNT_ADD(&sc->sc_ev_rxerrc, rxerrc);
 		if ((sc->sc_type < WM_T_82575) || WM_IS_ICHPCH(sc)) {
 			cexterr = CSR_READ(sc, WMREG_CEXTERR);
 			WM_EVCNT_ADD(&sc->sc_ev_cexterr, cexterr);
 		} else {
 			cexterr = 0;
 			/* Excessive collision + Link down */
 			WM_EVCNT_ADD(&sc->sc_ev_htdpmc,
 			    CSR_READ(sc, WMREG_HTDPMC));
+		}
 		WM_EVCNT_ADD(&sc->sc_ev_tncrs, CSR_READ(sc, WMREG_TNCRS));
 		WM_EVCNT_ADD(&sc->sc_ev_tsctc, CSR_READ(sc, WMREG_TSCTC));
 		if ((sc->sc_type < WM_T_82575) || WM_IS_ICHPCH(sc))
 			WM_EVCNT_ADD(&sc->sc_ev_tsctfc,
 			    CSR_READ(sc, WMREG_TSCTFC));
 		else {
 			WM_EVCNT_ADD(&sc->sc_ev_cbrdpc,
 			    CSR_READ(sc, WMREG_CBRDPC));
 			WM_EVCNT_ADD(&sc->sc_ev_cbrmpc,
 			    CSR_READ(sc, WMREG_CBRMPC));
+		}
 	} else
 		algnerrc = rxerrc = cexterr = 0;
 	if (sc->sc_type >= WM_T_82542_2_1) {
 		WM_EVCNT_ADD(&sc->sc_ev_rx_xon, CSR_READ(sc, WMREG_XONRXC));
 		WM_EVCNT_ADD(&sc->sc_ev_tx_xon, CSR_READ(sc, WMREG_XONTXC));
 		WM_EVCNT_ADD(&sc->sc_ev_rx_xoff, CSR_READ(sc, WMREG_XOFFRXC));
 		WM_EVCNT_ADD(&sc->sc_ev_tx_xoff, CSR_READ(sc, WMREG_XOFFTXC));
 		WM_EVCNT_ADD(&sc->sc_ev_rx_macctl, CSR_READ(sc, WMREG_FCRUC));
+	}
 	WM_EVCNT_ADD(&sc->sc_ev_scc, CSR_READ(sc, WMREG_SCC));
 	WM_EVCNT_ADD(&sc->sc_ev_ecol, CSR_READ(sc, WMREG_ECOL));
 	WM_EVCNT_ADD(&sc->sc_ev_mcc, CSR_READ(sc, WMREG_MCC));
 	WM_EVCNT_ADD(&sc->sc_ev_latecol, CSR_READ(sc, WMREG_LATECOL));
 	if ((sc->sc_type >= WM_T_I350) && !WM_IS_ICHPCH(sc)) {
 		WM_EVCNT_ADD(&sc->sc_ev_cbtmpc, CSR_READ(sc, WMREG_CBTMPC));
+	}
 	WM_EVCNT_ADD(&sc->sc_ev_dc, CSR_READ(sc, WMREG_DC));
 	WM_EVCNT_ADD(&sc->sc_ev_prc64, CSR_READ(sc, WMREG_PRC64));
 	WM_EVCNT_ADD(&sc->sc_ev_prc127, CSR_READ(sc, WMREG_PRC127));
 	WM_EVCNT_ADD(&sc->sc_ev_prc255, CSR_READ(sc, WMREG_PRC255));
 	WM_EVCNT_ADD(&sc->sc_ev_prc511, CSR_READ(sc, WMREG_PRC511));
 	WM_EVCNT_ADD(&sc->sc_ev_prc1023, CSR_READ(sc, WMREG_PRC1023));
 	WM_EVCNT_ADD(&sc->sc_ev_prc1522, CSR_READ(sc, WMREG_PRC1522));
 	WM_EVCNT_ADD(&sc->sc_ev_gprc, CSR_READ(sc, WMREG_GPRC));
 	WM_EVCNT_ADD(&sc->sc_ev_bprc, CSR_READ(sc, WMREG_BPRC));
 	WM_EVCNT_ADD(&sc->sc_ev_mprc, CSR_READ(sc, WMREG_MPRC));
 	WM_EVCNT_ADD(&sc->sc_ev_gptc, CSR_READ(sc, WMREG_GPTC));
 	WM_EVCNT_ADD(&sc->sc_ev_gorc,
 	    CSR_READ(sc, WMREG_GORCL) +
 	    ((uint64_t)CSR_READ(sc, WMREG_GORCH) << 32));
 	WM_EVCNT_ADD(&sc->sc_ev_gotc,
 	    CSR_READ(sc, WMREG_GOTCL) +
 	    ((uint64_t)CSR_READ(sc, WMREG_GOTCH) << 32));
 	WM_EVCNT_ADD(&sc->sc_ev_rnbc, CSR_READ(sc, WMREG_RNBC));
 	WM_EVCNT_ADD(&sc->sc_ev_ruc, CSR_READ(sc, WMREG_RUC));
 	WM_EVCNT_ADD(&sc->sc_ev_rfc, CSR_READ(sc, WMREG_RFC));
 	WM_EVCNT_ADD(&sc->sc_ev_roc, CSR_READ(sc, WMREG_ROC));
 	WM_EVCNT_ADD(&sc->sc_ev_rjc, CSR_READ(sc, WMREG_RJC));
 	if (sc->sc_type >= WM_T_82540) {
 		WM_EVCNT_ADD(&sc->sc_ev_mgtprc, CSR_READ(sc, WMREG_MGTPRC));
 		WM_EVCNT_ADD(&sc->sc_ev_mgtpdc, CSR_READ(sc, WMREG_MGTPDC));
 		WM_EVCNT_ADD(&sc->sc_ev_mgtptc, CSR_READ(sc, WMREG_MGTPTC));
+	}
 	/*
 	 * The TOR(L) register includes:
 	 *  - Error
 	 *  - Flow control
 	 *  - Broadcast rejected (This note is described in 82574 and newer
 	 *    datasheets. What does "broadcast rejected" mean?)
 	 */
 	WM_EVCNT_ADD(&sc->sc_ev_tor,
 	    CSR_READ(sc, WMREG_TORL) +
 	    ((uint64_t)CSR_READ(sc, WMREG_TORH) << 32));
 	WM_EVCNT_ADD(&sc->sc_ev_tot,
 	    CSR_READ(sc, WMREG_TOTL) +
 	    ((uint64_t)CSR_READ(sc, WMREG_TOTH) << 32));
 	WM_EVCNT_ADD(&sc->sc_ev_tpr, CSR_READ(sc, WMREG_TPR));
 	WM_EVCNT_ADD(&sc->sc_ev_tpt, CSR_READ(sc, WMREG_TPT));
 	WM_EVCNT_ADD(&sc->sc_ev_ptc64, CSR_READ(sc, WMREG_PTC64));
 	WM_EVCNT_ADD(&sc->sc_ev_ptc127, CSR_READ(sc, WMREG_PTC127));
 	WM_EVCNT_ADD(&sc->sc_ev_ptc255, CSR_READ(sc, WMREG_PTC255));
 	WM_EVCNT_ADD(&sc->sc_ev_ptc511, CSR_READ(sc, WMREG_PTC511));
 	WM_EVCNT_ADD(&sc->sc_ev_ptc1023, CSR_READ(sc, WMREG_PTC1023));
 	WM_EVCNT_ADD(&sc->sc_ev_ptc1522, CSR_READ(sc, WMREG_PTC1522));
 	WM_EVCNT_ADD(&sc->sc_ev_mptc, CSR_READ(sc, WMREG_MPTC));
 	WM_EVCNT_ADD(&sc->sc_ev_bptc, CSR_READ(sc, WMREG_BPTC));
 	if (sc->sc_type >= WM_T_82571)
 		WM_EVCNT_ADD(&sc->sc_ev_iac, CSR_READ(sc, WMREG_IAC));
 	if (sc->sc_type < WM_T_82575) {
 		WM_EVCNT_ADD(&sc->sc_ev_icrxptc, CSR_READ(sc, WMREG_ICRXPTC));
 		WM_EVCNT_ADD(&sc->sc_ev_icrxatc, CSR_READ(sc, WMREG_ICRXATC));
 		WM_EVCNT_ADD(&sc->sc_ev_ictxptc, CSR_READ(sc, WMREG_ICTXPTC));
 		WM_EVCNT_ADD(&sc->sc_ev_ictxatc, CSR_READ(sc, WMREG_ICTXATC));
 		WM_EVCNT_ADD(&sc->sc_ev_ictxqec, CSR_READ(sc, WMREG_ICTXQEC));
 		WM_EVCNT_ADD(&sc->sc_ev_ictxqmtc,
 		    CSR_READ(sc, WMREG_ICTXQMTC));
 		WM_EVCNT_ADD(&sc->sc_ev_rxdmtc,
 		    CSR_READ(sc, WMREG_ICRXDMTC));
 		WM_EVCNT_ADD(&sc->sc_ev_icrxoc, CSR_READ(sc, WMREG_ICRXOC));
 	} else if (!WM_IS_ICHPCH(sc)) {
 		WM_EVCNT_ADD(&sc->sc_ev_rpthc, CSR_READ(sc, WMREG_RPTHC));
 		WM_EVCNT_ADD(&sc->sc_ev_debug1, CSR_READ(sc, WMREG_DEBUG1));
 		WM_EVCNT_ADD(&sc->sc_ev_debug2, CSR_READ(sc, WMREG_DEBUG2));
 		WM_EVCNT_ADD(&sc->sc_ev_debug3, CSR_READ(sc, WMREG_DEBUG3));
 		WM_EVCNT_ADD(&sc->sc_ev_hgptc,  CSR_READ(sc, WMREG_HGPTC));
 		WM_EVCNT_ADD(&sc->sc_ev_debug4, CSR_READ(sc, WMREG_DEBUG4));
 		WM_EVCNT_ADD(&sc->sc_ev_rxdmtc, CSR_READ(sc, WMREG_RXDMTC));
 		WM_EVCNT_ADD(&sc->sc_ev_htcbdpc, CSR_READ(sc, WMREG_HTCBDPC));
 		WM_EVCNT_ADD(&sc->sc_ev_hgorc,
 		    CSR_READ(sc, WMREG_HGORCL) +
 		    ((uint64_t)CSR_READ(sc, WMREG_HGORCH) << 32));
 		WM_EVCNT_ADD(&sc->sc_ev_hgotc,
 		    CSR_READ(sc, WMREG_HGOTCL) +
 		    ((uint64_t)CSR_READ(sc, WMREG_HGOTCH) << 32));
 		WM_EVCNT_ADD(&sc->sc_ev_lenerrs, CSR_READ(sc, WMREG_LENERRS));
 		WM_EVCNT_ADD(&sc->sc_ev_scvpc, CSR_READ(sc, WMREG_SCVPC));
 		WM_EVCNT_ADD(&sc->sc_ev_hrmpc, CSR_READ(sc, WMREG_HRMPC));
 #ifdef WM_EVENT_COUNTERS
 		for (int i = 0; i < sc->sc_nqueues; i++) {
 			struct wm_rxqueue *rxq = &sc->sc_queue[i].wmq_rxq;
 			uint32_t rqdpc;
 			rqdpc = CSR_READ(sc, WMREG_RQDPC(i));
 			/*
 			 * On I210 and newer device, the RQDPC register is not
 			 * cleard on read.
 			 */
 			if ((rqdpc != 0) && (sc->sc_type >= WM_T_I210))
 				CSR_WRITE(sc, WMREG_RQDPC(i), 0);
 			WM_Q_EVCNT_ADD(rxq, qdrop, rqdpc);
 			total_qdrop += rqdpc;
+		}
 #endif
+	}
 	if ((sc->sc_type >= WM_T_I350) && !WM_IS_ICHPCH(sc)) {
 		WM_EVCNT_ADD(&sc->sc_ev_tlpic, CSR_READ(sc, WMREG_TLPIC));
 		WM_EVCNT_ADD(&sc->sc_ev_rlpic, CSR_READ(sc, WMREG_RLPIC));
 		if ((CSR_READ(sc, WMREG_MANC) & MANC_EN_BMC2OS) != 0) {
 			WM_EVCNT_ADD(&sc->sc_ev_b2ogprc,
 			    CSR_READ(sc, WMREG_B2OGPRC));
 			WM_EVCNT_ADD(&sc->sc_ev_o2bspc,
 			    CSR_READ(sc, WMREG_O2BSPC));
 			WM_EVCNT_ADD(&sc->sc_ev_b2ospc,
 			    CSR_READ(sc, WMREG_B2OSPC));
 			WM_EVCNT_ADD(&sc->sc_ev_o2bgptc,
 			    CSR_READ(sc, WMREG_O2BGPTC));
+		}
+	}
 	ifp->if_collisions += colc;
 	ifp->if_ierrors +=
 	    crcerrs + algnerrc + symerrc + rxerrc + sec + cexterr + rlec;
 	/*
 	 * WMREG_RNBC is incremented when there are no available buffers in
 	 * host memory. It does not mean the number of dropped packets, because
 	 * an Ethernet controller can receive packets in such case if there is
 	 * space in the phy's FIFO.
+	 *
 	 * If you want to know the nubmer of WMREG_RMBC, you should use such as
 	 * own EVCNT instead of if_iqdrops.
 	 */
-	ifp->if_iqdrops += mpc;
+	ifp->if_iqdrops += mpc + total_qdrop;
+}
 void
 wm_clear_evcnt(struct wm_softc *sc)
+{
 #ifdef WM_EVENT_COUNTERS
 	int i;
 	/* RX queues */
 	for (i = 0; i < sc->sc_nqueues; i++) {
 		struct wm_rxqueue *rxq = &sc->sc_queue[i].wmq_rxq;
 		WM_Q_EVCNT_STORE(rxq, intr, 0);
 		WM_Q_EVCNT_STORE(rxq, defer, 0);
 		WM_Q_EVCNT_STORE(rxq, ipsum, 0);
 		WM_Q_EVCNT_STORE(rxq, tusum, 0);
 		if ((sc->sc_type >= WM_T_82575) && !WM_IS_ICHPCH(sc))
 			WM_Q_EVCNT_STORE(rxq, qdrop, 0);
+	}
 	/* TX queues */
 	for (i = 0; i < sc->sc_nqueues; i++) {
 		struct wm_txqueue *txq = &sc->sc_queue[i].wmq_txq;
 		int j;
 		WM_Q_EVCNT_STORE(txq, txsstall, 0);
 		WM_Q_EVCNT_STORE(txq, txdstall, 0);
 		WM_Q_EVCNT_STORE(txq, fifo_stall, 0);
 		WM_Q_EVCNT_STORE(txq, txdw, 0);
 		WM_Q_EVCNT_STORE(txq, txqe, 0);
 		WM_Q_EVCNT_STORE(txq, ipsum, 0);
 		WM_Q_EVCNT_STORE(txq, tusum, 0);
 		WM_Q_EVCNT_STORE(txq, tusum6, 0);
 		WM_Q_EVCNT_STORE(txq, tso, 0);
 		WM_Q_EVCNT_STORE(txq, tso6, 0);
 		WM_Q_EVCNT_STORE(txq, tsopain, 0);
 		for (j = 0; j < WM_NTXSEGS; j++)
 			WM_EVCNT_STORE(&txq->txq_ev_txseg[j], 0);
 		WM_Q_EVCNT_STORE(txq, pcqdrop, 0);
 		WM_Q_EVCNT_STORE(txq, descdrop, 0);
 		WM_Q_EVCNT_STORE(txq, toomanyseg, 0);
 		WM_Q_EVCNT_STORE(txq, defrag, 0);
 		if (sc->sc_type <= WM_T_82544)
 			WM_Q_EVCNT_STORE(txq, underrun, 0);
 		WM_Q_EVCNT_STORE(txq, skipcontext, 0);
+	}
 	/* Miscs */
 	WM_EVCNT_STORE(&sc->sc_ev_linkintr, 0);
 	WM_EVCNT_STORE(&sc->sc_ev_crcerrs, 0);
 	WM_EVCNT_STORE(&sc->sc_ev_symerrc, 0);
 	WM_EVCNT_STORE(&sc->sc_ev_mpc, 0);
 	WM_EVCNT_STORE(&sc->sc_ev_colc, 0);
 	WM_EVCNT_STORE(&sc->sc_ev_sec, 0);
 	WM_EVCNT_STORE(&sc->sc_ev_rlec, 0);
 	if (sc->sc_type >= WM_T_82543) {
 		WM_EVCNT_STORE(&sc->sc_ev_algnerrc, 0);
 		WM_EVCNT_STORE(&sc->sc_ev_rxerrc, 0);
 		if ((sc->sc_type < WM_T_82575) || WM_IS_ICHPCH(sc))
 			WM_EVCNT_STORE(&sc->sc_ev_cexterr, 0);
 		else
 			WM_EVCNT_STORE(&sc->sc_ev_htdpmc, 0);
 		WM_EVCNT_STORE(&sc->sc_ev_tncrs, 0);
 		WM_EVCNT_STORE(&sc->sc_ev_tsctc, 0);
 		if ((sc->sc_type < WM_T_82575) || WM_IS_ICHPCH(sc))
 			WM_EVCNT_STORE(&sc->sc_ev_tsctfc, 0);
 		else {
 			WM_EVCNT_STORE(&sc->sc_ev_cbrdpc, 0);
 			WM_EVCNT_STORE(&sc->sc_ev_cbrmpc, 0);
+		}
+	}
 	if (sc->sc_type >= WM_T_82542_2_1) {
 		WM_EVCNT_STORE(&sc->sc_ev_tx_xoff, 0);
 		WM_EVCNT_STORE(&sc->sc_ev_tx_xon, 0);
 		WM_EVCNT_STORE(&sc->sc_ev_rx_xoff, 0);
 		WM_EVCNT_STORE(&sc->sc_ev_rx_xon, 0);
 		WM_EVCNT_STORE(&sc->sc_ev_rx_macctl, 0);
+	}
 	WM_EVCNT_STORE(&sc->sc_ev_scc, 0);
 	WM_EVCNT_STORE(&sc->sc_ev_ecol, 0);
 	WM_EVCNT_STORE(&sc->sc_ev_mcc, 0);
 	WM_EVCNT_STORE(&sc->sc_ev_latecol, 0);
 	if ((sc->sc_type >= WM_T_I350) && !WM_IS_ICHPCH(sc))
 		WM_EVCNT_STORE(&sc->sc_ev_cbtmpc, 0);
 	WM_EVCNT_STORE(&sc->sc_ev_dc, 0);
 	WM_EVCNT_STORE(&sc->sc_ev_prc64, 0);
 	WM_EVCNT_STORE(&sc->sc_ev_prc127, 0);
 	WM_EVCNT_STORE(&sc->sc_ev_prc255, 0);
 	WM_EVCNT_STORE(&sc->sc_ev_prc511, 0);
 	WM_EVCNT_STORE(&sc->sc_ev_prc1023, 0);
 	WM_EVCNT_STORE(&sc->sc_ev_prc1522, 0);
 	WM_EVCNT_STORE(&sc->sc_ev_gprc, 0);
 	WM_EVCNT_STORE(&sc->sc_ev_bprc, 0);
 	WM_EVCNT_STORE(&sc->sc_ev_mprc, 0);
 	WM_EVCNT_STORE(&sc->sc_ev_gptc, 0);
 	WM_EVCNT_STORE(&sc->sc_ev_gorc, 0);
 	WM_EVCNT_STORE(&sc->sc_ev_gotc, 0);
 	WM_EVCNT_STORE(&sc->sc_ev_rnbc, 0);
 	WM_EVCNT_STORE(&sc->sc_ev_ruc, 0);
 	WM_EVCNT_STORE(&sc->sc_ev_rfc, 0);
 	WM_EVCNT_STORE(&sc->sc_ev_roc, 0);
 	WM_EVCNT_STORE(&sc->sc_ev_rjc, 0);
 	if (sc->sc_type >= WM_T_82540) {
 		WM_EVCNT_STORE(&sc->sc_ev_mgtprc, 0);
 		WM_EVCNT_STORE(&sc->sc_ev_mgtpdc, 0);
 		WM_EVCNT_STORE(&sc->sc_ev_mgtptc, 0);
+	}
 	WM_EVCNT_STORE(&sc->sc_ev_tor, 0);
 	WM_EVCNT_STORE(&sc->sc_ev_tot, 0);
 	WM_EVCNT_STORE(&sc->sc_ev_tpr, 0);
 	WM_EVCNT_STORE(&sc->sc_ev_tpt, 0);
 	WM_EVCNT_STORE(&sc->sc_ev_ptc64, 0);
 	WM_EVCNT_STORE(&sc->sc_ev_ptc127, 0);
 	WM_EVCNT_STORE(&sc->sc_ev_ptc255, 0);
 	WM_EVCNT_STORE(&sc->sc_ev_ptc511, 0);
 	WM_EVCNT_STORE(&sc->sc_ev_ptc1023, 0);
 	WM_EVCNT_STORE(&sc->sc_ev_ptc1522, 0);
 	WM_EVCNT_STORE(&sc->sc_ev_mptc, 0);
 	WM_EVCNT_STORE(&sc->sc_ev_bptc, 0);
 	if (sc->sc_type >= WM_T_82571)
 		WM_EVCNT_STORE(&sc->sc_ev_iac, 0);
 	if (sc->sc_type < WM_T_82575) {
 		WM_EVCNT_STORE(&sc->sc_ev_icrxptc, 0);
 		WM_EVCNT_STORE(&sc->sc_ev_icrxatc, 0);
 		WM_EVCNT_STORE(&sc->sc_ev_ictxptc, 0);
 		WM_EVCNT_STORE(&sc->sc_ev_ictxatc, 0);
 		WM_EVCNT_STORE(&sc->sc_ev_ictxqec, 0);
 		WM_EVCNT_STORE(&sc->sc_ev_ictxqmtc, 0);
 		WM_EVCNT_STORE(&sc->sc_ev_rxdmtc, 0);
 		WM_EVCNT_STORE(&sc->sc_ev_icrxoc, 0);
 	} else if (!WM_IS_ICHPCH(sc)) {
 		WM_EVCNT_STORE(&sc->sc_ev_rpthc, 0);
 		WM_EVCNT_STORE(&sc->sc_ev_debug1, 0);
 		WM_EVCNT_STORE(&sc->sc_ev_debug2, 0);
 		WM_EVCNT_STORE(&sc->sc_ev_debug3, 0);
 		WM_EVCNT_STORE(&sc->sc_ev_hgptc, 0);
 		WM_EVCNT_STORE(&sc->sc_ev_debug4, 0);
 		WM_EVCNT_STORE(&sc->sc_ev_rxdmtc, 0);
 		WM_EVCNT_STORE(&sc->sc_ev_htcbdpc, 0);
 		WM_EVCNT_STORE(&sc->sc_ev_hgorc, 0);
 		WM_EVCNT_STORE(&sc->sc_ev_hgotc, 0);
 		WM_EVCNT_STORE(&sc->sc_ev_lenerrs, 0);
 		WM_EVCNT_STORE(&sc->sc_ev_scvpc, 0);
 		WM_EVCNT_STORE(&sc->sc_ev_hrmpc, 0);
+	}
 	if ((sc->sc_type >= WM_T_I350) && !WM_IS_ICHPCH(sc)) {
 		WM_EVCNT_STORE(&sc->sc_ev_tlpic, 0);
 		WM_EVCNT_STORE(&sc->sc_ev_rlpic, 0);
 		WM_EVCNT_STORE(&sc->sc_ev_b2ogprc, 0);
 		WM_EVCNT_STORE(&sc->sc_ev_o2bspc, 0);
 		WM_EVCNT_STORE(&sc->sc_ev_b2ospc, 0);
 		WM_EVCNT_STORE(&sc->sc_ev_o2bgptc, 0);
+	}
 #endif
+}
 /*
  * wm_init:		[ifnet interface function]
+ *
  *	Initialize the interface.
  */
 static int
 wm_init(struct ifnet *ifp)
+{
 	struct wm_softc *sc = ifp->if_softc;
 	int ret;
 	WM_CORE_LOCK(sc);
 	ret = wm_init_locked(ifp);
 	WM_CORE_UNLOCK(sc);
 	return ret;
+}
 static int
 wm_init_locked(struct ifnet *ifp)
+{
 	struct wm_softc *sc = ifp->if_softc;
 	int i, j, trynum, error = 0;
 	uint32_t reg, sfp_mask = 0;
 	DPRINTF(sc, WM_DEBUG_INIT, ("%s: %s called\n",
 		device_xname(sc->sc_dev), __func__));
 	KASSERT(WM_CORE_LOCKED(sc));
 	/*
 	 * *_HDR_ALIGNED_P is constant 1 if __NO_STRICT_ALIGMENT is set.
 	 * There is a small but measurable benefit to avoiding the adjusment
 	 * of the descriptor so that the headers are aligned, for normal mtu,
 	 * on such platforms.  One possibility is that the DMA itself is
 	 * slightly more efficient if the front of the entire packet (instead
 	 * of the front of the headers) is aligned.
+	 *
 	 * Note we must always set align_tweak to 0 if we are using
 	 * jumbo frames.
 	 */
 #ifdef __NO_STRICT_ALIGNMENT
 	sc->sc_align_tweak = 0;
 #else
 	if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN) > (MCLBYTES - 2))
 		sc->sc_align_tweak = 0;
 	else
 		sc->sc_align_tweak = 2;
 #endif /* __NO_STRICT_ALIGNMENT */
 	/* Cancel any pending I/O. */
 	wm_stop_locked(ifp, 0);
 	/* Update statistics before reset */
 	ifp->if_collisions += CSR_READ(sc, WMREG_COLC);
 	ifp->if_ierrors += CSR_READ(sc, WMREG_RXERRC);
 	/* >= PCH_SPT hardware workaround before reset. */
 	if (sc->sc_type >= WM_T_PCH_SPT)
 		wm_flush_desc_rings(sc);
 	/* Reset the chip to a known state. */
 	wm_reset(sc);
 	/*
 	 * AMT based hardware can now take control from firmware
 	 * Do this after reset.
 	 */
 	if ((sc->sc_flags & WM_F_HAS_AMT) != 0)
 		wm_get_hw_control(sc);
 	if ((sc->sc_type >= WM_T_PCH_SPT) &&
 	    pci_intr_type(sc->sc_pc, sc->sc_intrs[0]) == PCI_INTR_TYPE_INTX)
 		wm_legacy_irq_quirk_spt(sc);
 	/* Init hardware bits */
 	wm_initialize_hardware_bits(sc);
 	/* Reset the PHY. */
 	if (sc->sc_flags & WM_F_HAS_MII)
 		wm_gmii_reset(sc);
 	if (sc->sc_type >= WM_T_ICH8) {
 		reg = CSR_READ(sc, WMREG_GCR);
 		/*
 		 * ICH8 No-snoop bits are opposite polarity. Set to snoop by
 		 * default after reset.
 		 */
 		if (sc->sc_type == WM_T_ICH8)
 			reg |= GCR_NO_SNOOP_ALL;
 		else
 			reg &= ~GCR_NO_SNOOP_ALL;
 		CSR_WRITE(sc, WMREG_GCR, reg);
+	}
 	/* Ungate DMA clock to avoid packet loss */
 	if (sc->sc_type >= WM_T_PCH_TGP) {
 		reg = CSR_READ(sc, WMREG_FFLT_DBG);
 		reg |= (1 << 12);
 		CSR_WRITE(sc, WMREG_FFLT_DBG, reg);
+	}
 	if ((sc->sc_type >= WM_T_ICH8)
 	    || (sc->sc_pcidevid == PCI_PRODUCT_INTEL_82546GB_QUAD_COPPER)
 	    || (sc->sc_pcidevid == PCI_PRODUCT_INTEL_82546GB_QUAD_COPPER_KSP3)) {
 		reg = CSR_READ(sc, WMREG_CTRL_EXT);
 		reg |= CTRL_EXT_RO_DIS;
 		CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
+	}
 	/* Calculate (E)ITR value */
 	if ((sc->sc_flags & WM_F_NEWQUEUE) != 0 && sc->sc_type != WM_T_82575) {
 		/*
 		 * For NEWQUEUE's EITR (except for 82575).
 		 * 82575's EITR should be set same throttling value as other
 		 * old controllers' ITR because the interrupt/sec calculation
 		 * is the same, that is, 1,000,000,000 / (N * 256).
+		 *
 		 * 82574's EITR should be set same throttling value as ITR.
+		 *
 		 * For N interrupts/sec, set this value to:
 		 * 1,000,000 / N in contrast to ITR throttling value.
 		 */
 		sc->sc_itr_init = 450;
 	} else if (sc->sc_type >= WM_T_82543) {
 		/*
 		 * Set up the interrupt throttling register (units of 256ns)
 		 * Note that a footnote in Intel's documentation says this
 		 * ticker runs at 1/4 the rate when the chip is in 100Mbit
 		 * or 10Mbit mode.  Empirically, it appears to be the case
 		 * that that is also true for the 1024ns units of the other
 		 * interrupt-related timer registers -- so, really, we ought
 		 * to divide this value by 4 when the link speed is low.
+		 *
 		 * XXX implement this division at link speed change!
 		 */
 		/*
 		 * For N interrupts/sec, set this value to:
 		 * 1,000,000,000 / (N * 256).  Note that we set the
 		 * absolute and packet timer values to this value
 		 * divided by 4 to get "simple timer" behavior.
 		 */
 		sc->sc_itr_init = 1500;		/* 2604 ints/sec */
+	}
 	error = wm_init_txrx_queues(sc);
 	if (error)
 		goto out;
 	if (((sc->sc_flags & WM_F_SGMII) == 0) &&
 	    (sc->sc_mediatype == WM_MEDIATYPE_SERDES) &&
 	    (sc->sc_type >= WM_T_82575))
 		wm_serdes_power_up_link_82575(sc);
 	/* Clear out the VLAN table -- we don't use it (yet). */
 	CSR_WRITE(sc, WMREG_VET, 0);
 	if ((sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354))
 		trynum = 10; /* Due to hw errata */
 	else
 		trynum = 1;
 	for (i = 0; i < WM_VLAN_TABSIZE; i++)
 		for (j = 0; j < trynum; j++)
 			CSR_WRITE(sc, WMREG_VFTA + (i << 2), 0);
 	/*
 	 * Set up flow-control parameters.
+	 *
 	 * XXX Values could probably stand some tuning.
 	 */
 	if ((sc->sc_type != WM_T_ICH8) && (sc->sc_type != WM_T_ICH9)
 	    && (sc->sc_type != WM_T_ICH10) && (sc->sc_type != WM_T_PCH)
 	    && (sc->sc_type != WM_T_PCH2) && (sc->sc_type != WM_T_PCH_LPT)
 	    && (sc->sc_type != WM_T_PCH_SPT) && (sc->sc_type != WM_T_PCH_CNP)
 	    && (sc->sc_type != WM_T_PCH_TGP)) {
 		CSR_WRITE(sc, WMREG_FCAL, FCAL_CONST);
 		CSR_WRITE(sc, WMREG_FCAH, FCAH_CONST);
 		CSR_WRITE(sc, WMREG_FCT, ETHERTYPE_FLOWCONTROL);
+	}
 	sc->sc_fcrtl = FCRTL_DFLT;
 	if (sc->sc_type < WM_T_82543) {
 		CSR_WRITE(sc, WMREG_OLD_FCRTH, FCRTH_DFLT);
 		CSR_WRITE(sc, WMREG_OLD_FCRTL, sc->sc_fcrtl);
 	} else {
 		CSR_WRITE(sc, WMREG_FCRTH, FCRTH_DFLT);
 		CSR_WRITE(sc, WMREG_FCRTL, sc->sc_fcrtl);
+	}
 	if (sc->sc_type == WM_T_80003)
 		CSR_WRITE(sc, WMREG_FCTTV, 0xffff);
 	else
 		CSR_WRITE(sc, WMREG_FCTTV, FCTTV_DFLT);
 	/* Writes the control register. */
 	wm_set_vlan(sc);
 	if (sc->sc_flags & WM_F_HAS_MII) {
 		uint16_t kmreg;
 		switch (sc->sc_type) {
 		case WM_T_80003:
 		case WM_T_ICH8:
 		case WM_T_ICH9:
 		case WM_T_ICH10:
 		case WM_T_PCH:
 		case WM_T_PCH2:
 		case WM_T_PCH_LPT:
 		case WM_T_PCH_SPT:
 		case WM_T_PCH_CNP:
 		case WM_T_PCH_TGP:
 			/*
 			 * Set the mac to wait the maximum time between each
 			 * iteration and increase the max iterations when
 			 * polling the phy; this fixes erroneous timeouts at
 			 * 10Mbps.
 			 */
 			wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_TIMEOUTS,
 xFFFF);
 			wm_kmrn_readreg(sc, KUMCTRLSTA_OFFSET_INB_PARAM,
 			    &kmreg);
 			kmreg |= 0x3F;
 			wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_INB_PARAM,
 			    kmreg);
 			break;
 		default:
 			break;
+		}
 		if (sc->sc_type == WM_T_80003) {
 			reg = CSR_READ(sc, WMREG_CTRL_EXT);
 			reg &= ~CTRL_EXT_LINK_MODE_MASK;
 			CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
 			/* Bypass RX and TX FIFOs */
 			wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_FIFO_CTRL,
 			    KUMCTRLSTA_FIFO_CTRL_RX_BYPASS
 			    | KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
 			wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_INB_CTRL,
 			    KUMCTRLSTA_INB_CTRL_DIS_PADDING |
 			    KUMCTRLSTA_INB_CTRL_LINK_TMOUT_DFLT);
+		}
+	}
 #if 0
 	CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext);
 #endif
 	/* Set up checksum offload parameters. */
 	reg = CSR_READ(sc, WMREG_RXCSUM);
 	reg &= ~(RXCSUM_IPOFL | RXCSUM_IPV6OFL | RXCSUM_TUOFL);
 	if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx)
 		reg |= RXCSUM_IPOFL;
 	if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx))
 		reg |= RXCSUM_IPOFL | RXCSUM_TUOFL;
 	if (ifp->if_capenable & (IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx))
 		reg |= RXCSUM_IPV6OFL | RXCSUM_TUOFL;
 	CSR_WRITE(sc, WMREG_RXCSUM, reg);
 	/* Set registers about MSI-X */
 	if (wm_is_using_msix(sc)) {
 		uint32_t ivar, qintr_idx;
 		struct wm_queue *wmq;
 		unsigned int qid;
 		if (sc->sc_type == WM_T_82575) {
 			/* Interrupt control */
 			reg = CSR_READ(sc, WMREG_CTRL_EXT);
 			reg |= CTRL_EXT_PBA | CTRL_EXT_EIAME | CTRL_EXT_NSICR;
 			CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
 			/* TX and RX */
 			for (i = 0; i < sc->sc_nqueues; i++) {
 				wmq = &sc->sc_queue[i];
 				CSR_WRITE(sc, WMREG_MSIXBM(wmq->wmq_intr_idx),
 				    EITR_TX_QUEUE(wmq->wmq_id)
 				    | EITR_RX_QUEUE(wmq->wmq_id));
+			}
 			/* Link status */
 			CSR_WRITE(sc, WMREG_MSIXBM(sc->sc_link_intr_idx),
 			    EITR_OTHER);
 		} else if (sc->sc_type == WM_T_82574) {
 			/* Interrupt control */
 			reg = CSR_READ(sc, WMREG_CTRL_EXT);
 			reg |= CTRL_EXT_PBA | CTRL_EXT_EIAME;
 			CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
 			/*
 			 * Work around issue with spurious interrupts
 			 * in MSI-X mode.
 			 * At wm_initialize_hardware_bits(), sc_nintrs has not
 			 * initialized yet. So re-initialize WMREG_RFCTL here.
 			 */
 			reg = CSR_READ(sc, WMREG_RFCTL);
 			reg |= WMREG_RFCTL_ACKDIS;
 			CSR_WRITE(sc, WMREG_RFCTL, reg);
 			ivar = 0;
 			/* TX and RX */
 			for (i = 0; i < sc->sc_nqueues; i++) {
 				wmq = &sc->sc_queue[i];
 				qid = wmq->wmq_id;
 				qintr_idx = wmq->wmq_intr_idx;
 				ivar |= __SHIFTIN((IVAR_VALID_82574|qintr_idx),
 				    IVAR_TX_MASK_Q_82574(qid));
 				ivar |= __SHIFTIN((IVAR_VALID_82574|qintr_idx),
 				    IVAR_RX_MASK_Q_82574(qid));
+			}
 			/* Link status */
 			ivar |= __SHIFTIN((IVAR_VALID_82574
 				| sc->sc_link_intr_idx), IVAR_OTHER_MASK);
 			CSR_WRITE(sc, WMREG_IVAR, ivar | IVAR_INT_ON_ALL_WB);
 		} else {
 			/* Interrupt control */
 			CSR_WRITE(sc, WMREG_GPIE, GPIE_NSICR | GPIE_MULTI_MSIX
 			    | GPIE_EIAME | GPIE_PBA);
 			switch (sc->sc_type) {
 			case WM_T_82580:
 			case WM_T_I350:
 			case WM_T_I354:
 			case WM_T_I210:
 			case WM_T_I211:
 				/* TX and RX */
 				for (i = 0; i < sc->sc_nqueues; i++) {
 					wmq = &sc->sc_queue[i];
 					qid = wmq->wmq_id;
 					qintr_idx = wmq->wmq_intr_idx;
 					ivar = CSR_READ(sc, WMREG_IVAR_Q(qid));
 					ivar &= ~IVAR_TX_MASK_Q(qid);
 					ivar |= __SHIFTIN((qintr_idx
 						| IVAR_VALID),
 					    IVAR_TX_MASK_Q(qid));
 					ivar &= ~IVAR_RX_MASK_Q(qid);
 					ivar |= __SHIFTIN((qintr_idx
 						| IVAR_VALID),
 					    IVAR_RX_MASK_Q(qid));
 					CSR_WRITE(sc, WMREG_IVAR_Q(qid), ivar);
+				}
 				break;
 			case WM_T_82576:
 				/* TX and RX */
 				for (i = 0; i < sc->sc_nqueues; i++) {
 					wmq = &sc->sc_queue[i];
 					qid = wmq->wmq_id;
 					qintr_idx = wmq->wmq_intr_idx;
 					ivar = CSR_READ(sc,
 					    WMREG_IVAR_Q_82576(qid));
 					ivar &= ~IVAR_TX_MASK_Q_82576(qid);
 					ivar |= __SHIFTIN((qintr_idx
 						| IVAR_VALID),
 					    IVAR_TX_MASK_Q_82576(qid));
 					ivar &= ~IVAR_RX_MASK_Q_82576(qid);
 					ivar |= __SHIFTIN((qintr_idx
 						| IVAR_VALID),
 					    IVAR_RX_MASK_Q_82576(qid));
 					CSR_WRITE(sc, WMREG_IVAR_Q_82576(qid),
 					    ivar);
+				}
 				break;
 			default:
 				break;
+			}
 			/* Link status */
 			ivar = __SHIFTIN((sc->sc_link_intr_idx | IVAR_VALID),
 			    IVAR_MISC_OTHER);
 			CSR_WRITE(sc, WMREG_IVAR_MISC, ivar);
+		}
 		if (wm_is_using_multiqueue(sc)) {
 			wm_init_rss(sc);
 			/*
 			** NOTE: Receive Full-Packet Checksum Offload
 			** is mutually exclusive with Multiqueue. However
 			** this is not the same as TCP/IP checksums which
 			** still work.
 			*/
 			reg = CSR_READ(sc, WMREG_RXCSUM);
 			reg |= RXCSUM_PCSD;
 			CSR_WRITE(sc, WMREG_RXCSUM, reg);
+		}
+	}
 	/* Set up the interrupt registers. */
 	CSR_WRITE(sc, WMREG_IMC, 0xffffffffU);
 	/* Enable SFP module insertion interrupt if it's required */
 	if ((sc->sc_flags & WM_F_SFP) != 0) {
 		sc->sc_ctrl |= CTRL_EXTLINK_EN;
 		CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
 		sfp_mask = ICR_GPI(0);
+	}
 	if (wm_is_using_msix(sc)) {
 		uint32_t mask;
 		struct wm_queue *wmq;
 		switch (sc->sc_type) {
 		case WM_T_82574:
 			mask = 0;
 			for (i = 0; i < sc->sc_nqueues; i++) {
 				wmq = &sc->sc_queue[i];
 				mask |= ICR_TXQ(wmq->wmq_id);
 				mask |= ICR_RXQ(wmq->wmq_id);
+			}
 			mask |= ICR_OTHER;
 			CSR_WRITE(sc, WMREG_EIAC_82574, mask);
 			CSR_WRITE(sc, WMREG_IMS, mask | ICR_LSC);
 			break;
 		default:
 			if (sc->sc_type == WM_T_82575) {
 				mask = 0;
 				for (i = 0; i < sc->sc_nqueues; i++) {
 					wmq = &sc->sc_queue[i];
 					mask |= EITR_TX_QUEUE(wmq->wmq_id);
 					mask |= EITR_RX_QUEUE(wmq->wmq_id);
+				}
 				mask |= EITR_OTHER;
 			} else {
 				mask = 0;
 				for (i = 0; i < sc->sc_nqueues; i++) {
 					wmq = &sc->sc_queue[i];
 					mask |= 1 << wmq->wmq_intr_idx;
+				}
 				mask |= 1 << sc->sc_link_intr_idx;
+			}
 			CSR_WRITE(sc, WMREG_EIAC, mask);
 			CSR_WRITE(sc, WMREG_EIAM, mask);
 			CSR_WRITE(sc, WMREG_EIMS, mask);
 			/* For other interrupts */
 			CSR_WRITE(sc, WMREG_IMS, ICR_LSC | sfp_mask);
 			break;
+		}
 	} else {
 		sc->sc_icr = ICR_TXDW | ICR_LSC | ICR_RXSEQ | ICR_RXDMT0 |
 		    ICR_RXO | ICR_RXT0 | sfp_mask;
 		CSR_WRITE(sc, WMREG_IMS, sc->sc_icr);
+	}
 	/* Set up the inter-packet gap. */
 	CSR_WRITE(sc, WMREG_TIPG, sc->sc_tipg);
 	if (sc->sc_type >= WM_T_82543) {
 		for (int qidx = 0; qidx < sc->sc_nqueues; qidx++) {
 			struct wm_queue *wmq = &sc->sc_queue[qidx];
 			wm_itrs_writereg(sc, wmq);
+		}
 		/*
 		 * Link interrupts occur much less than TX
 		 * interrupts and RX interrupts. So, we don't
 		 * tune EINTR(WM_MSIX_LINKINTR_IDX) value like
 		 * FreeBSD's if_igb.
 		 */
+	}
 	/* Set the VLAN EtherType. */
 	CSR_WRITE(sc, WMREG_VET, ETHERTYPE_VLAN);
 	/*
 	 * Set up the transmit control register; we start out with
 	 * a collision distance suitable for FDX, but update it when
 	 * we resolve the media type.
 	 */
 	sc->sc_tctl = TCTL_EN | TCTL_PSP | TCTL_RTLC
 	    | TCTL_CT(TX_COLLISION_THRESHOLD)
 	    | TCTL_COLD(TX_COLLISION_DISTANCE_FDX);
 	if (sc->sc_type >= WM_T_82571)
 		sc->sc_tctl |= TCTL_MULR;
 	CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl);
 	if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) {
 		/* Write TDT after TCTL.EN is set. See the document. */
 		CSR_WRITE(sc, WMREG_TDT(0), 0);
+	}
 	if (sc->sc_type == WM_T_80003) {
 		reg = CSR_READ(sc, WMREG_TCTL_EXT);
 		reg &= ~TCTL_EXT_GCEX_MASK;
 		reg |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
 		CSR_WRITE(sc, WMREG_TCTL_EXT, reg);
+	}
 	/* Set the media. */
 	if ((error = mii_ifmedia_change(&sc->sc_mii)) != 0)
 		goto out;
 	/* Configure for OS presence */
 	wm_init_manageability(sc);
 	/*
 	 * Set up the receive control register; we actually program the
 	 * register when we set the receive filter. Use multicast address
 	 * offset type 0.
+	 *
 	 * Only the i82544 has the ability to strip the incoming CRC, so we
 	 * don't enable that feature.
 	 */
 	sc->sc_mchash_type = 0;
 	sc->sc_rctl = RCTL_EN | RCTL_LBM_NONE | RCTL_RDMTS_1_2 | RCTL_DPF
 	    | __SHIFTIN(sc->sc_mchash_type, RCTL_MO);
 	/* 82574 use one buffer extended Rx descriptor. */
 	if (sc->sc_type == WM_T_82574)
 		sc->sc_rctl |= RCTL_DTYP_ONEBUF;
 	if ((sc->sc_flags & WM_F_CRC_STRIP) != 0)
 		sc->sc_rctl |= RCTL_SECRC;
 	if (((sc->sc_ethercom.ec_capabilities & ETHERCAP_JUMBO_MTU) != 0)
 	    && (ifp->if_mtu > ETHERMTU)) {
 		sc->sc_rctl |= RCTL_LPE;
 		if ((sc->sc_flags & WM_F_NEWQUEUE) != 0)
 			CSR_WRITE(sc, WMREG_RLPML, ETHER_MAX_LEN_JUMBO);
+	}
 	if (MCLBYTES == 2048)
 		sc->sc_rctl |= RCTL_2k;
 	else {
 		if (sc->sc_type >= WM_T_82543) {
 			switch (MCLBYTES) {
 			case 4096:
 				sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_4k;
 				break;
 			case 8192:
 				sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_8k;
 				break;
 			case 16384:
 				sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_16k;
 				break;
 			default:
 				panic("wm_init: MCLBYTES %d unsupported",
 				    MCLBYTES);
 				break;
+			}
 		} else
 			panic("wm_init: i82542 requires MCLBYTES = 2048");
+	}
 	/* Enable ECC */
 	switch (sc->sc_type) {
 	case WM_T_82571:
 		reg = CSR_READ(sc, WMREG_PBA_ECC);
 		reg |= PBA_ECC_CORR_EN;
 		CSR_WRITE(sc, WMREG_PBA_ECC, reg);
 		break;
 	case WM_T_PCH_LPT:
 	case WM_T_PCH_SPT:
 	case WM_T_PCH_CNP:
 	case WM_T_PCH_TGP:
 		reg = CSR_READ(sc, WMREG_PBECCSTS);
 		reg |= PBECCSTS_UNCORR_ECC_ENABLE;
 		CSR_WRITE(sc, WMREG_PBECCSTS, reg);
 		sc->sc_ctrl |= CTRL_MEHE;
 		CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
 		break;
 	default:
 		break;
+	}
 	/*
 	 * Set the receive filter.
+	 *
 	 * For 82575 and 82576, the RX descriptors must be initialized after
 	 * the setting of RCTL.EN in wm_set_filter()
 	 */
 	wm_set_filter(sc);
 	/* On 575 and later set RDT only if RX enabled */
 	if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) {
 		int qidx;
 		for (qidx = 0; qidx < sc->sc_nqueues; qidx++) {
 			struct wm_rxqueue *rxq = &sc->sc_queue[qidx].wmq_rxq;
 			for (i = 0; i < WM_NRXDESC; i++) {
 				mutex_enter(rxq->rxq_lock);
 				wm_init_rxdesc(rxq, i);
 				mutex_exit(rxq->rxq_lock);
+			}
+		}
+	}
 	wm_unset_stopping_flags(sc);
 	/* Start the one second link check clock. */
 	callout_reset(&sc->sc_tick_ch, hz, wm_tick, sc);
 	/* ...all done! */
 	ifp->if_flags |= IFF_RUNNING;
 	ifp->if_flags &= ~IFF_OACTIVE;
 out:
 	sc->sc_if_flags = ifp->if_flags;
 	if (error)
 		log(LOG_ERR, "%s: interface not running\n",
 		    device_xname(sc->sc_dev));
 	return error;
+}
 /*
  * wm_stop:		[ifnet interface function]
+ *
  *	Stop transmission on the interface.
  */
 static void
 wm_stop(struct ifnet *ifp, int disable)
+{
 	struct wm_softc *sc = ifp->if_softc;
 	WM_CORE_LOCK(sc);
 	wm_stop_locked(ifp, disable);
 	WM_CORE_UNLOCK(sc);
 	/*
 	 * After wm_set_stopping_flags(), it is guaranteed that
 	 * wm_handle_queue_work() does not call workqueue_enqueue().
 	 * However, workqueue_wait() cannot call in wm_stop_locked()
 	 * because it can sleep...
 	 * so, call workqueue_wait() here.
 	 */
 	for (int i = 0; i < sc->sc_nqueues; i++)
 		workqueue_wait(sc->sc_queue_wq, &sc->sc_queue[i].wmq_cookie);
+}
 static void
 wm_stop_locked(struct ifnet *ifp, int disable)
+{
 	struct wm_softc *sc = ifp->if_softc;
 	struct wm_txsoft *txs;
 	int i, qidx;
 	DPRINTF(sc, WM_DEBUG_INIT, ("%s: %s called\n",
 		device_xname(sc->sc_dev), __func__));
 	KASSERT(WM_CORE_LOCKED(sc));
 	wm_set_stopping_flags(sc);
 	/* Stop the one second clock. */
 	callout_stop(&sc->sc_tick_ch);
 	/* Stop the 82547 Tx FIFO stall check timer. */
 	if (sc->sc_type == WM_T_82547)
 		callout_stop(&sc->sc_txfifo_ch);
 	if (sc->sc_flags & WM_F_HAS_MII) {
 		/* Down the MII. */
 		mii_down(&sc->sc_mii);
 	} else {
 #if 0
 		/* Should we clear PHY's status properly? */
 		wm_reset(sc);
 #endif
+	}
 	/* Stop the transmit and receive processes. */
 	CSR_WRITE(sc, WMREG_TCTL, 0);
 	CSR_WRITE(sc, WMREG_RCTL, 0);
 	sc->sc_rctl &= ~RCTL_EN;
 	/*
 	 * Clear the interrupt mask to ensure the device cannot assert its
 	 * interrupt line.
 	 * Clear sc->sc_icr to ensure wm_intr_legacy() makes no attempt to
 	 * service any currently pending or shared interrupt.
 	 */
 	CSR_WRITE(sc, WMREG_IMC, 0xffffffffU);
 	sc->sc_icr = 0;
 	if (wm_is_using_msix(sc)) {
 		if (sc->sc_type != WM_T_82574) {
 			CSR_WRITE(sc, WMREG_EIMC, 0xffffffffU);
 			CSR_WRITE(sc, WMREG_EIAC, 0);
 		} else
 			CSR_WRITE(sc, WMREG_EIAC_82574, 0);
+	}
 	/* Release any queued transmit buffers. */
 	for (qidx = 0; qidx < sc->sc_nqueues; qidx++) {
 		struct wm_queue *wmq = &sc->sc_queue[qidx];
 		struct wm_txqueue *txq = &wmq->wmq_txq;
 		struct mbuf *m;
 		mutex_enter(txq->txq_lock);
 		txq->txq_sending = false; /* Ensure watchdog disabled */
 		for (i = 0; i < WM_TXQUEUELEN(txq); i++) {
 			txs = &txq->txq_soft[i];
 			if (txs->txs_mbuf != NULL) {
 				bus_dmamap_unload(sc->sc_dmat,txs->txs_dmamap);
 				m_freem(txs->txs_mbuf);
 				txs->txs_mbuf = NULL;
+			}
+		}
 		/* Drain txq_interq */
 		while ((m = pcq_get(txq->txq_interq)) != NULL)
 			m_freem(m);
 		mutex_exit(txq->txq_lock);
+	}
 	/* Mark the interface as down and cancel the watchdog timer. */
 	ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
 	if (disable) {
 		for (i = 0; i < sc->sc_nqueues; i++) {
 			struct wm_rxqueue *rxq = &sc->sc_queue[i].wmq_rxq;
 			mutex_enter(rxq->rxq_lock);
 			wm_rxdrain(rxq);
 			mutex_exit(rxq->rxq_lock);
+		}
+	}
 #if 0 /* notyet */
 	if (sc->sc_type >= WM_T_82544)
 		CSR_WRITE(sc, WMREG_WUC, 0);
 #endif
+}
 static void
 wm_dump_mbuf_chain(struct wm_softc *sc, struct mbuf *m0)
+{
 	struct mbuf *m;
 	int i;
 	log(LOG_DEBUG, "%s: mbuf chain:\n", device_xname(sc->sc_dev));
 	for (m = m0, i = 0; m != NULL; m = m->m_next, i++)
 		log(LOG_DEBUG, "%s:\tm_data = %p, m_len = %d, "
 		    "m_flags = 0x%08x\n", device_xname(sc->sc_dev),
 		    m->m_data, m->m_len, m->m_flags);
 	log(LOG_DEBUG, "%s:\t%d mbuf%s in chain\n", device_xname(sc->sc_dev),
 	    i, i == 1 ? "" : "s");
+}
 /*
  * wm_82547_txfifo_stall:
+ *
  *	Callout used to wait for the 82547 Tx FIFO to drain,
  *	reset the FIFO pointers, and restart packet transmission.
  */
 static void
 wm_82547_txfifo_stall(void *arg)
+{
 	struct wm_softc *sc = arg;
 	struct wm_txqueue *txq = &sc->sc_queue[0].wmq_txq;
 	mutex_enter(txq->txq_lock);
 	if (txq->txq_stopping)
 		goto out;
 	if (txq->txq_fifo_stall) {
 		if (CSR_READ(sc, WMREG_TDT(0)) == CSR_READ(sc, WMREG_TDH(0)) &&
 		    CSR_READ(sc, WMREG_TDFT) == CSR_READ(sc, WMREG_TDFH) &&
 		    CSR_READ(sc, WMREG_TDFTS) == CSR_READ(sc, WMREG_TDFHS)) {
 			/*
 			 * Packets have drained.  Stop transmitter, reset
 			 * FIFO pointers, restart transmitter, and kick
 			 * the packet queue.
 			 */
 			uint32_t tctl = CSR_READ(sc, WMREG_TCTL);
 			CSR_WRITE(sc, WMREG_TCTL, tctl & ~TCTL_EN);
 			CSR_WRITE(sc, WMREG_TDFT, txq->txq_fifo_addr);
 			CSR_WRITE(sc, WMREG_TDFH, txq->txq_fifo_addr);
 			CSR_WRITE(sc, WMREG_TDFTS, txq->txq_fifo_addr);
 			CSR_WRITE(sc, WMREG_TDFHS, txq->txq_fifo_addr);
 			CSR_WRITE(sc, WMREG_TCTL, tctl);
 			CSR_WRITE_FLUSH(sc);
 			txq->txq_fifo_head = 0;
 			txq->txq_fifo_stall = 0;
 			wm_start_locked(&sc->sc_ethercom.ec_if);
 		} else {
 			/*
 			 * Still waiting for packets to drain; try again in
 			 * another tick.
 			 */
 			callout_schedule(&sc->sc_txfifo_ch, 1);
+		}
+	}
 out:
 	mutex_exit(txq->txq_lock);
+}
 /*
  * wm_82547_txfifo_bugchk:
+ *
  *	Check for bug condition in the 82547 Tx FIFO.  We need to
  *	prevent enqueueing a packet that would wrap around the end
  *	if the Tx FIFO ring buffer, otherwise the chip will croak.
+ *
  *	We do this by checking the amount of space before the end
  *	of the Tx FIFO buffer. If the packet will not fit, we "stall"
  *	the Tx FIFO, wait for all remaining packets to drain, reset
  *	the internal FIFO pointers to the beginning, and restart
  *	transmission on the interface.
  */
 #define	WM_FIFO_HDR		0x10
 #define	WM_82547_PAD_LEN	0x3e0
 static int
 wm_82547_txfifo_bugchk(struct wm_softc *sc, struct mbuf *m0)
+{
 	struct wm_txqueue *txq = &sc->sc_queue[0].wmq_txq;
 	int space = txq->txq_fifo_size - txq->txq_fifo_head;
 	int len = roundup(m0->m_pkthdr.len + WM_FIFO_HDR, WM_FIFO_HDR);
 	/* Just return if already stalled. */
 	if (txq->txq_fifo_stall)
 		return 1;
 	if (sc->sc_mii.mii_media_active & IFM_FDX) {
 		/* Stall only occurs in half-duplex mode. */
 		goto send_packet;
+	}
 	if (len >= WM_82547_PAD_LEN + space) {
 		txq->txq_fifo_stall = 1;
 		callout_schedule(&sc->sc_txfifo_ch, 1);
 		return 1;
+	}
 send_packet:
 	txq->txq_fifo_head += len;
 	if (txq->txq_fifo_head >= txq->txq_fifo_size)
 		txq->txq_fifo_head -= txq->txq_fifo_size;
 	return 0;
+}
 static int
 wm_alloc_tx_descs(struct wm_softc *sc, struct wm_txqueue *txq)
+{
 	int error;
 	/*
 	 * Allocate the control data structures, and create and load the
 	 * DMA map for it.
+	 *
 	 * NOTE: All Tx descriptors must be in the same 4G segment of
 	 * memory.  So must Rx descriptors.  We simplify by allocating
 	 * both sets within the same 4G segment.
 	 */
 	if (sc->sc_type < WM_T_82544)
 		WM_NTXDESC(txq) = WM_NTXDESC_82542;
 	else
 		WM_NTXDESC(txq) = WM_NTXDESC_82544;
 	if ((sc->sc_flags & WM_F_NEWQUEUE) != 0)
 		txq->txq_descsize = sizeof(nq_txdesc_t);
 	else
 		txq->txq_descsize = sizeof(wiseman_txdesc_t);
 	if ((error = bus_dmamem_alloc(sc->sc_dmat, WM_TXDESCS_SIZE(txq),
 		    PAGE_SIZE, (bus_size_t) 0x100000000ULL, &txq->txq_desc_seg,
 , &txq->txq_desc_rseg, 0)) != 0) {
 		aprint_error_dev(sc->sc_dev,
 		    "unable to allocate TX control data, error = %d\n",
 		    error);
 		goto fail_0;
+	}
 	if ((error = bus_dmamem_map(sc->sc_dmat, &txq->txq_desc_seg,
 		    txq->txq_desc_rseg, WM_TXDESCS_SIZE(txq),
 		    (void **)&txq->txq_descs_u, BUS_DMA_COHERENT)) != 0) {
 		aprint_error_dev(sc->sc_dev,
 		    "unable to map TX control data, error = %d\n", error);
 		goto fail_1;
+	}
 	if ((error = bus_dmamap_create(sc->sc_dmat, WM_TXDESCS_SIZE(txq), 1,
 		    WM_TXDESCS_SIZE(txq), 0, 0, &txq->txq_desc_dmamap)) != 0) {
 		aprint_error_dev(sc->sc_dev,
 		    "unable to create TX control data DMA map, error = %d\n",
 		    error);
 		goto fail_2;
+	}
 	if ((error = bus_dmamap_load(sc->sc_dmat, txq->txq_desc_dmamap,
 		    txq->txq_descs_u, WM_TXDESCS_SIZE(txq), NULL, 0)) != 0) {
 		aprint_error_dev(sc->sc_dev,
 		    "unable to load TX control data DMA map, error = %d\n",
 		    error);
 		goto fail_3;
+	}
 	return 0;
 fail_3:
 	bus_dmamap_destroy(sc->sc_dmat, txq->txq_desc_dmamap);
 fail_2:
 	bus_dmamem_unmap(sc->sc_dmat, (void *)txq->txq_descs_u,
 	    WM_TXDESCS_SIZE(txq));
 fail_1:
 	bus_dmamem_free(sc->sc_dmat, &txq->txq_desc_seg, txq->txq_desc_rseg);
 fail_0:
 	return error;
+}
 static void
 wm_free_tx_descs(struct wm_softc *sc, struct wm_txqueue *txq)
+{
 	bus_dmamap_unload(sc->sc_dmat, txq->txq_desc_dmamap);
 	bus_dmamap_destroy(sc->sc_dmat, txq->txq_desc_dmamap);
 	bus_dmamem_unmap(sc->sc_dmat, (void *)txq->txq_descs_u,
 	    WM_TXDESCS_SIZE(txq));
 	bus_dmamem_free(sc->sc_dmat, &txq->txq_desc_seg, txq->txq_desc_rseg);
+}
 static int
 wm_alloc_rx_descs(struct wm_softc *sc, struct wm_rxqueue *rxq)
+{
 	int error;
 	size_t rxq_descs_size;
 	/*
 	 * Allocate the control data structures, and create and load the
 	 * DMA map for it.
+	 *
 	 * NOTE: All Tx descriptors must be in the same 4G segment of
 	 * memory.  So must Rx descriptors.  We simplify by allocating
 	 * both sets within the same 4G segment.
 	 */
 	rxq->rxq_ndesc = WM_NRXDESC;
 	if (sc->sc_type == WM_T_82574)
 		rxq->rxq_descsize = sizeof(ext_rxdesc_t);
 	else if ((sc->sc_flags & WM_F_NEWQUEUE) != 0)
 		rxq->rxq_descsize = sizeof(nq_rxdesc_t);
 	else
 		rxq->rxq_descsize = sizeof(wiseman_rxdesc_t);
 	rxq_descs_size = rxq->rxq_descsize * rxq->rxq_ndesc;
 	if ((error = bus_dmamem_alloc(sc->sc_dmat, rxq_descs_size,
 		    PAGE_SIZE, (bus_size_t) 0x100000000ULL, &rxq->rxq_desc_seg,
 , &rxq->rxq_desc_rseg, 0)) != 0) {
 		aprint_error_dev(sc->sc_dev,
 		    "unable to allocate RX control data, error = %d\n",
 		    error);
 		goto fail_0;
+	}
 	if ((error = bus_dmamem_map(sc->sc_dmat, &rxq->rxq_desc_seg,
 		    rxq->rxq_desc_rseg, rxq_descs_size,
 		    (void **)&rxq->rxq_descs_u, BUS_DMA_COHERENT)) != 0) {
 		aprint_error_dev(sc->sc_dev,
 		    "unable to map RX control data, error = %d\n", error);
 		goto fail_1;
+	}
 	if ((error = bus_dmamap_create(sc->sc_dmat, rxq_descs_size, 1,
 		    rxq_descs_size, 0, 0, &rxq->rxq_desc_dmamap)) != 0) {
 		aprint_error_dev(sc->sc_dev,
 		    "unable to create RX control data DMA map, error = %d\n",
 		    error);
 		goto fail_2;
+	}
 	if ((error = bus_dmamap_load(sc->sc_dmat, rxq->rxq_desc_dmamap,
 		    rxq->rxq_descs_u, rxq_descs_size, NULL, 0)) != 0) {
 		aprint_error_dev(sc->sc_dev,
 		    "unable to load RX control data DMA map, error = %d\n",
 		    error);
 		goto fail_3;
+	}
 	return 0;
  fail_3:
 	bus_dmamap_destroy(sc->sc_dmat, rxq->rxq_desc_dmamap);
  fail_2:
 	bus_dmamem_unmap(sc->sc_dmat, (void *)rxq->rxq_descs_u,
 	    rxq_descs_size);
  fail_1:
 	bus_dmamem_free(sc->sc_dmat, &rxq->rxq_desc_seg, rxq->rxq_desc_rseg);
  fail_0:
 	return error;
+}
 static void
 wm_free_rx_descs(struct wm_softc *sc, struct wm_rxqueue *rxq)
+{
 	bus_dmamap_unload(sc->sc_dmat, rxq->rxq_desc_dmamap);
 	bus_dmamap_destroy(sc->sc_dmat, rxq->rxq_desc_dmamap);
 	bus_dmamem_unmap(sc->sc_dmat, (void *)rxq->rxq_descs_u,
 	    rxq->rxq_descsize * rxq->rxq_ndesc);
 	bus_dmamem_free(sc->sc_dmat, &rxq->rxq_desc_seg, rxq->rxq_desc_rseg);
+}
 static int
 wm_alloc_tx_buffer(struct wm_softc *sc, struct wm_txqueue *txq)
+{
 	int i, error;
 	/* Create the transmit buffer DMA maps. */
 	WM_TXQUEUELEN(txq) =
 	    (sc->sc_type == WM_T_82547 || sc->sc_type == WM_T_82547_2) ?
 	    WM_TXQUEUELEN_MAX_82547 : WM_TXQUEUELEN_MAX;
 	for (i = 0; i < WM_TXQUEUELEN(txq); i++) {
 		if ((error = bus_dmamap_create(sc->sc_dmat, WM_MAXTXDMA,
 			    WM_NTXSEGS, WTX_MAX_LEN, 0, 0,
 			    &txq->txq_soft[i].txs_dmamap)) != 0) {
 			aprint_error_dev(sc->sc_dev,
 			    "unable to create Tx DMA map %d, error = %d\n",
 			    i, error);
 			goto fail;
+		}
+	}
 	return 0;
 fail:
 	for (i = 0; i < WM_TXQUEUELEN(txq); i++) {
 		if (txq->txq_soft[i].txs_dmamap != NULL)
 			bus_dmamap_destroy(sc->sc_dmat,
 			    txq->txq_soft[i].txs_dmamap);
+	}
 	return error;
+}
 static void
 wm_free_tx_buffer(struct wm_softc *sc, struct wm_txqueue *txq)
+{
 	int i;
 	for (i = 0; i < WM_TXQUEUELEN(txq); i++) {
 		if (txq->txq_soft[i].txs_dmamap != NULL)
 			bus_dmamap_destroy(sc->sc_dmat,
 			    txq->txq_soft[i].txs_dmamap);
+	}
+}
 static int
 wm_alloc_rx_buffer(struct wm_softc *sc, struct wm_rxqueue *rxq)
+{
 	int i, error;
 	/* Create the receive buffer DMA maps. */
 	for (i = 0; i < rxq->rxq_ndesc; i++) {
 		if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1,
 			    MCLBYTES, 0, 0,
 			    &rxq->rxq_soft[i].rxs_dmamap)) != 0) {
 			aprint_error_dev(sc->sc_dev,
 			    "unable to create Rx DMA map %d error = %d\n",
 			    i, error);
 			goto fail;
+		}
 		rxq->rxq_soft[i].rxs_mbuf = NULL;
+	}
 	return 0;
  fail:
 	for (i = 0; i < rxq->rxq_ndesc; i++) {
 		if (rxq->rxq_soft[i].rxs_dmamap != NULL)
 			bus_dmamap_destroy(sc->sc_dmat,
 			    rxq->rxq_soft[i].rxs_dmamap);
+	}
 	return error;
+}
 static void
 wm_free_rx_buffer(struct wm_softc *sc, struct wm_rxqueue *rxq)
+{
 	int i;
 	for (i = 0; i < rxq->rxq_ndesc; i++) {
 		if (rxq->rxq_soft[i].rxs_dmamap != NULL)
 			bus_dmamap_destroy(sc->sc_dmat,
 			    rxq->rxq_soft[i].rxs_dmamap);
+	}
+}
 /*
  * wm_alloc_quques:
  *	Allocate {tx,rx}descs and {tx,rx} buffers
  */
 static int
 wm_alloc_txrx_queues(struct wm_softc *sc)
+{
 	int i, error, tx_done, rx_done;
 	sc->sc_queue = kmem_zalloc(sizeof(struct wm_queue) * sc->sc_nqueues,
 	    KM_SLEEP);
 	if (sc->sc_queue == NULL) {
 		aprint_error_dev(sc->sc_dev,"unable to allocate wm_queue\n");
 		error = ENOMEM;
 		goto fail_0;
+	}
 	/* For transmission */
 	error = 0;
 	tx_done = 0;
 	for (i = 0; i < sc->sc_nqueues; i++) {
 #ifdef WM_EVENT_COUNTERS
 		int j;
 		const char *xname;
 #endif
 		struct wm_txqueue *txq = &sc->sc_queue[i].wmq_txq;
 		txq->txq_sc = sc;
 		txq->txq_lock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_NET);
 		error = wm_alloc_tx_descs(sc, txq);
 		if (error)
 			break;
 		error = wm_alloc_tx_buffer(sc, txq);
 		if (error) {
 			wm_free_tx_descs(sc, txq);
 			break;
+		}
 		txq->txq_interq = pcq_create(WM_TXINTERQSIZE, KM_SLEEP);
 		if (txq->txq_interq == NULL) {
 			wm_free_tx_descs(sc, txq);
 			wm_free_tx_buffer(sc, txq);
 			error = ENOMEM;
 			break;
+		}
 #ifdef WM_EVENT_COUNTERS
 		xname = device_xname(sc->sc_dev);
 		WM_Q_MISC_EVCNT_ATTACH(txq, txsstall, txq, i, xname);
 		WM_Q_MISC_EVCNT_ATTACH(txq, txdstall, txq, i, xname);
 		WM_Q_MISC_EVCNT_ATTACH(txq, fifo_stall, txq, i, xname);
 		WM_Q_INTR_EVCNT_ATTACH(txq, txdw, txq, i, xname);
 		WM_Q_INTR_EVCNT_ATTACH(txq, txqe, txq, i, xname);
 		WM_Q_MISC_EVCNT_ATTACH(txq, ipsum, txq, i, xname);
 		WM_Q_MISC_EVCNT_ATTACH(txq, tusum, txq, i, xname);
 		WM_Q_MISC_EVCNT_ATTACH(txq, tusum6, txq, i, xname);
 		WM_Q_MISC_EVCNT_ATTACH(txq, tso, txq, i, xname);
 		WM_Q_MISC_EVCNT_ATTACH(txq, tso6, txq, i, xname);
 		WM_Q_MISC_EVCNT_ATTACH(txq, tsopain, txq, i, xname);
 		for (j = 0; j < WM_NTXSEGS; j++) {
 			snprintf(txq->txq_txseg_evcnt_names[j],
 			    sizeof(txq->txq_txseg_evcnt_names[j]),
 			    "txq%02dtxseg%d", i, j);
 			evcnt_attach_dynamic(&txq->txq_ev_txseg[j],
 			    EVCNT_TYPE_MISC,
 			    NULL, xname, txq->txq_txseg_evcnt_names[j]);
+		}
 		WM_Q_MISC_EVCNT_ATTACH(txq, pcqdrop, txq, i, xname);
 		WM_Q_MISC_EVCNT_ATTACH(txq, descdrop, txq, i, xname);
 		WM_Q_MISC_EVCNT_ATTACH(txq, toomanyseg, txq, i, xname);
 		WM_Q_MISC_EVCNT_ATTACH(txq, defrag, txq, i, xname);
 		/* Only for 82544 (and earlier?) */
 		if (sc->sc_type <= WM_T_82544)
 			WM_Q_MISC_EVCNT_ATTACH(txq, underrun, txq, i, xname);
 		WM_Q_MISC_EVCNT_ATTACH(txq, skipcontext, txq, i, xname);
 #endif /* WM_EVENT_COUNTERS */
 		tx_done++;
+	}
 	if (error)
 		goto fail_1;
 	/* For receive */
 	error = 0;
 	rx_done = 0;
 	for (i = 0; i < sc->sc_nqueues; i++) {
 #ifdef WM_EVENT_COUNTERS
 		const char *xname;
 #endif
 		struct wm_rxqueue *rxq = &sc->sc_queue[i].wmq_rxq;
 		rxq->rxq_sc = sc;
 		rxq->rxq_lock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_NET);
 		error = wm_alloc_rx_descs(sc, rxq);
 		if (error)
 			break;
 		error = wm_alloc_rx_buffer(sc, rxq);
 		if (error) {
 			wm_free_rx_descs(sc, rxq);
 			break;
+		}
 #ifdef WM_EVENT_COUNTERS
 		xname = device_xname(sc->sc_dev);
 		WM_Q_INTR_EVCNT_ATTACH(rxq, intr, rxq, i, xname);
 		WM_Q_INTR_EVCNT_ATTACH(rxq, defer, rxq, i, xname);
 		WM_Q_MISC_EVCNT_ATTACH(rxq, ipsum, rxq, i, xname);
 		WM_Q_MISC_EVCNT_ATTACH(rxq, tusum, rxq, i, xname);
 		if ((sc->sc_type >= WM_T_82575) && !WM_IS_ICHPCH(sc))
 			WM_Q_MISC_EVCNT_ATTACH(rxq, qdrop, rxq, i, xname);
 #endif /* WM_EVENT_COUNTERS */
 		rx_done++;
+	}
 	if (error)
 		goto fail_2;
 	for (i = 0; i < sc->sc_nqueues; i++) {
 		char rndname[16];
 		snprintf(rndname, sizeof(rndname), "%sTXRX%d",
 		    device_xname(sc->sc_dev), i);
 		rnd_attach_source(&sc->sc_queue[i].rnd_source, rndname,
 		    RND_TYPE_NET, RND_FLAG_DEFAULT);
+	}
 	return 0;
 fail_2:
 	for (i = 0; i < rx_done; i++) {
 		struct wm_rxqueue *rxq = &sc->sc_queue[i].wmq_rxq;
 		wm_free_rx_buffer(sc, rxq);
 		wm_free_rx_descs(sc, rxq);
 		if (rxq->rxq_lock)
 			mutex_obj_free(rxq->rxq_lock);
+	}
 fail_1:
 	for (i = 0; i < tx_done; i++) {
 		struct wm_txqueue *txq = &sc->sc_queue[i].wmq_txq;
 		pcq_destroy(txq->txq_interq);
 		wm_free_tx_buffer(sc, txq);
 		wm_free_tx_descs(sc, txq);
 		if (txq->txq_lock)
 			mutex_obj_free(txq->txq_lock);
+	}
 	kmem_free(sc->sc_queue,
 	    sizeof(struct wm_queue) * sc->sc_nqueues);
 fail_0:
 	return error;
+}
 /*
  * wm_free_quques:
  *	Free {tx,rx}descs and {tx,rx} buffers
  */
 static void
 wm_free_txrx_queues(struct wm_softc *sc)
+{
 	int i;
 	for (i = 0; i < sc->sc_nqueues; i++)
 		rnd_detach_source(&sc->sc_queue[i].rnd_source);
 	for (i = 0; i < sc->sc_nqueues; i++) {
 		struct wm_rxqueue *rxq = &sc->sc_queue[i].wmq_rxq;
 #ifdef WM_EVENT_COUNTERS
 		WM_Q_EVCNT_DETACH(rxq, intr, rxq, i);
 		WM_Q_EVCNT_DETACH(rxq, defer, rxq, i);
 		WM_Q_EVCNT_DETACH(rxq, ipsum, rxq, i);
 		WM_Q_EVCNT_DETACH(rxq, tusum, rxq, i);
 		if ((sc->sc_type >= WM_T_82575) && !WM_IS_ICHPCH(sc))
 			WM_Q_EVCNT_DETACH(rxq, qdrop, rxq, i);
 #endif /* WM_EVENT_COUNTERS */
 		wm_free_rx_buffer(sc, rxq);
 		wm_free_rx_descs(sc, rxq);
 		if (rxq->rxq_lock)
 			mutex_obj_free(rxq->rxq_lock);
+	}
 	for (i = 0; i < sc->sc_nqueues; i++) {
 		struct wm_txqueue *txq = &sc->sc_queue[i].wmq_txq;
 		struct mbuf *m;
 #ifdef WM_EVENT_COUNTERS
 		int j;
 		WM_Q_EVCNT_DETACH(txq, txsstall, txq, i);
 		WM_Q_EVCNT_DETACH(txq, txdstall, txq, i);
 		WM_Q_EVCNT_DETACH(txq, fifo_stall, txq, i);
 		WM_Q_EVCNT_DETACH(txq, txdw, txq, i);
 		WM_Q_EVCNT_DETACH(txq, txqe, txq, i);
 		WM_Q_EVCNT_DETACH(txq, ipsum, txq, i);
 		WM_Q_EVCNT_DETACH(txq, tusum, txq, i);
 		WM_Q_EVCNT_DETACH(txq, tusum6, txq, i);
 		WM_Q_EVCNT_DETACH(txq, tso, txq, i);
 		WM_Q_EVCNT_DETACH(txq, tso6, txq, i);
 		WM_Q_EVCNT_DETACH(txq, tsopain, txq, i);
 		for (j = 0; j < WM_NTXSEGS; j++)
 			evcnt_detach(&txq->txq_ev_txseg[j]);
 		WM_Q_EVCNT_DETACH(txq, pcqdrop, txq, i);
 		WM_Q_EVCNT_DETACH(txq, descdrop, txq, i);
 		WM_Q_EVCNT_DETACH(txq, toomanyseg, txq, i);
 		WM_Q_EVCNT_DETACH(txq, defrag, txq, i);
 		if (sc->sc_type <= WM_T_82544)
 			WM_Q_EVCNT_DETACH(txq, underrun, txq, i);
 		WM_Q_EVCNT_DETACH(txq, skipcontext, txq, i);
 #endif /* WM_EVENT_COUNTERS */
 		/* Drain txq_interq */
 		while ((m = pcq_get(txq->txq_interq)) != NULL)
 			m_freem(m);
 		pcq_destroy(txq->txq_interq);
 		wm_free_tx_buffer(sc, txq);
 		wm_free_tx_descs(sc, txq);
 		if (txq->txq_lock)
 			mutex_obj_free(txq->txq_lock);
+	}
 	kmem_free(sc->sc_queue, sizeof(struct wm_queue) * sc->sc_nqueues);
+}
 static void
 wm_init_tx_descs(struct wm_softc *sc __unused, struct wm_txqueue *txq)
+{
 	KASSERT(mutex_owned(txq->txq_lock));
 	/* Initialize the transmit descriptor ring. */
 	memset(txq->txq_descs, 0, WM_TXDESCS_SIZE(txq));
 	wm_cdtxsync(txq, 0, WM_NTXDESC(txq),
 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 	txq->txq_free = WM_NTXDESC(txq);
 	txq->txq_next = 0;
+}
 static void
 wm_init_tx_regs(struct wm_softc *sc, struct wm_queue *wmq,
     struct wm_txqueue *txq)
+{
 	DPRINTF(sc, WM_DEBUG_INIT, ("%s: %s called\n",
 		device_xname(sc->sc_dev), __func__));
 	KASSERT(mutex_owned(txq->txq_lock));
 	if (sc->sc_type < WM_T_82543) {
 		CSR_WRITE(sc, WMREG_OLD_TDBAH, WM_CDTXADDR_HI(txq, 0));
 		CSR_WRITE(sc, WMREG_OLD_TDBAL, WM_CDTXADDR_LO(txq, 0));
 		CSR_WRITE(sc, WMREG_OLD_TDLEN, WM_TXDESCS_SIZE(txq));
 		CSR_WRITE(sc, WMREG_OLD_TDH, 0);
 		CSR_WRITE(sc, WMREG_OLD_TDT, 0);
 		CSR_WRITE(sc, WMREG_OLD_TIDV, 128);
 	} else {
 		int qid = wmq->wmq_id;
 		CSR_WRITE(sc, WMREG_TDBAH(qid), WM_CDTXADDR_HI(txq, 0));
 		CSR_WRITE(sc, WMREG_TDBAL(qid), WM_CDTXADDR_LO(txq, 0));
 		CSR_WRITE(sc, WMREG_TDLEN(qid), WM_TXDESCS_SIZE(txq));
 		CSR_WRITE(sc, WMREG_TDH(qid), 0);
 		if ((sc->sc_flags & WM_F_NEWQUEUE) != 0)
 			/*
 			 * Don't write TDT before TCTL.EN is set.
 			 * See the document.
 			 */
 			CSR_WRITE(sc, WMREG_TXDCTL(qid), TXDCTL_QUEUE_ENABLE
 			    | TXDCTL_PTHRESH(0) | TXDCTL_HTHRESH(0)
 			    | TXDCTL_WTHRESH(0));
 		else {
 			/* XXX should update with AIM? */
 			CSR_WRITE(sc, WMREG_TIDV, wmq->wmq_itr / 4);
 			if (sc->sc_type >= WM_T_82540) {
 				/* Should be the same */
 				CSR_WRITE(sc, WMREG_TADV, wmq->wmq_itr / 4);
+			}
 			CSR_WRITE(sc, WMREG_TDT(qid), 0);
 			CSR_WRITE(sc, WMREG_TXDCTL(qid), TXDCTL_PTHRESH(0) |
 			    TXDCTL_HTHRESH(0) | TXDCTL_WTHRESH(0));
+		}
+	}
+}
 static void
 wm_init_tx_buffer(struct wm_softc *sc __unused, struct wm_txqueue *txq)
+{
 	int i;
 	KASSERT(mutex_owned(txq->txq_lock));
 	/* Initialize the transmit job descriptors. */
 	for (i = 0; i < WM_TXQUEUELEN(txq); i++)
 		txq->txq_soft[i].txs_mbuf = NULL;
 	txq->txq_sfree = WM_TXQUEUELEN(txq);
 	txq->txq_snext = 0;
 	txq->txq_sdirty = 0;
+}
 static void
 wm_init_tx_queue(struct wm_softc *sc, struct wm_queue *wmq,
     struct wm_txqueue *txq)
+{
 	KASSERT(mutex_owned(txq->txq_lock));
 	/*
 	 * Set up some register offsets that are different between
 	 * the i82542 and the i82543 and later chips.
 	 */
 	if (sc->sc_type < WM_T_82543)
 		txq->txq_tdt_reg = WMREG_OLD_TDT;
 	else
 		txq->txq_tdt_reg = WMREG_TDT(wmq->wmq_id);
 	wm_init_tx_descs(sc, txq);
 	wm_init_tx_regs(sc, wmq, txq);
 	wm_init_tx_buffer(sc, txq);
 	/* Clear other than WM_TXQ_LINKDOWN_DISCARD */
 	txq->txq_flags &= WM_TXQ_LINKDOWN_DISCARD;
 	txq->txq_sending = false;
+}
 static void
 wm_init_rx_regs(struct wm_softc *sc, struct wm_queue *wmq,
     struct wm_rxqueue *rxq)
+{
 	KASSERT(mutex_owned(rxq->rxq_lock));
 	/*
 	 * Initialize the receive descriptor and receive job
 	 * descriptor rings.
 	 */
 	if (sc->sc_type < WM_T_82543) {
 		CSR_WRITE(sc, WMREG_OLD_RDBAH0, WM_CDRXADDR_HI(rxq, 0));
 		CSR_WRITE(sc, WMREG_OLD_RDBAL0, WM_CDRXADDR_LO(rxq, 0));
 		CSR_WRITE(sc, WMREG_OLD_RDLEN0,
 		    rxq->rxq_descsize * rxq->rxq_ndesc);
 		CSR_WRITE(sc, WMREG_OLD_RDH0, 0);
 		CSR_WRITE(sc, WMREG_OLD_RDT0, 0);
 		CSR_WRITE(sc, WMREG_OLD_RDTR0, 28 | RDTR_FPD);
 		CSR_WRITE(sc, WMREG_OLD_RDBA1_HI, 0);
 		CSR_WRITE(sc, WMREG_OLD_RDBA1_LO, 0);
 		CSR_WRITE(sc, WMREG_OLD_RDLEN1, 0);
 		CSR_WRITE(sc, WMREG_OLD_RDH1, 0);
 		CSR_WRITE(sc, WMREG_OLD_RDT1, 0);
 		CSR_WRITE(sc, WMREG_OLD_RDTR1, 0);
 	} else {
 		int qid = wmq->wmq_id;
 		CSR_WRITE(sc, WMREG_RDBAH(qid), WM_CDRXADDR_HI(rxq, 0));
 		CSR_WRITE(sc, WMREG_RDBAL(qid), WM_CDRXADDR_LO(rxq, 0));
 		CSR_WRITE(sc, WMREG_RDLEN(qid),
 		    rxq->rxq_descsize * rxq->rxq_ndesc);
 		if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) {
 			uint32_t srrctl;
 			if (MCLBYTES & ((1 << SRRCTL_BSIZEPKT_SHIFT) - 1))
 				panic("%s: MCLBYTES %d unsupported for 82575 "
 				    "or higher\n", __func__, MCLBYTES);
 			/*
 			 * Currently, support SRRCTL_DESCTYPE_ADV_ONEBUF
 			 * only.
 			 */
-			CSR_WRITE(sc, WMREG_SRRCTL(qid),
+			srrctl = SRRCTL_DESCTYPE_ADV_ONEBUF
-			    SRRCTL_DESCTYPE_ADV_ONEBUF
+			    | (MCLBYTES >> SRRCTL_BSIZEPKT_SHIFT);
-			    | (MCLBYTES >> SRRCTL_BSIZEPKT_SHIFT));
+			/*
 			 * Drop frames if the RX descriptor ring has no room.
 			 * This is enabled only on multiqueue system to avoid
 			 * bad influence to other queues.
 			 */
 			if (sc->sc_nqueues > 1)
 				srrctl |= SRRCTL_DROP_EN;
 			CSR_WRITE(sc, WMREG_SRRCTL(qid), srrctl);
 			CSR_WRITE(sc, WMREG_RXDCTL(qid), RXDCTL_QUEUE_ENABLE
 			    | RXDCTL_PTHRESH(16) | RXDCTL_HTHRESH(8)
 			    | RXDCTL_WTHRESH(1));
 			CSR_WRITE(sc, WMREG_RDH(qid), 0);
 			CSR_WRITE(sc, WMREG_RDT(qid), 0);
 		} else {
 			CSR_WRITE(sc, WMREG_RDH(qid), 0);
 			CSR_WRITE(sc, WMREG_RDT(qid), 0);
 			/* XXX should update with AIM? */
 			CSR_WRITE(sc, WMREG_RDTR,
 			    (wmq->wmq_itr / 4) | RDTR_FPD);
 			/* MUST be same */
 			CSR_WRITE(sc, WMREG_RADV, wmq->wmq_itr / 4);
 			CSR_WRITE(sc, WMREG_RXDCTL(qid), RXDCTL_PTHRESH(0) |
 			    RXDCTL_HTHRESH(0) | RXDCTL_WTHRESH(1));
+		}
+	}
+}
 static int
 wm_init_rx_buffer(struct wm_softc *sc, struct wm_rxqueue *rxq)
+{
 	struct wm_rxsoft *rxs;
 	int error, i;
 	KASSERT(mutex_owned(rxq->rxq_lock));
 	for (i = 0; i < rxq->rxq_ndesc; i++) {
 		rxs = &rxq->rxq_soft[i];
 		if (rxs->rxs_mbuf == NULL) {
 			if ((error = wm_add_rxbuf(rxq, i)) != 0) {
 				log(LOG_ERR, "%s: unable to allocate or map "
 				    "rx buffer %d, error = %d\n",
 				    device_xname(sc->sc_dev), i, error);
 				/*
 				 * XXX Should attempt to run with fewer receive
 				 * XXX buffers instead of just failing.
 				 */
 				wm_rxdrain(rxq);
 				return ENOMEM;
+			}
 		} else {
 			/*
 			 * For 82575 and 82576, the RX descriptors must be
 			 * initialized after the setting of RCTL.EN in
 			 * wm_set_filter()
 			 */
 			if ((sc->sc_flags & WM_F_NEWQUEUE) == 0)
 				wm_init_rxdesc(rxq, i);
+		}
+	}
 	rxq->rxq_ptr = 0;
 	rxq->rxq_discard = 0;
 	WM_RXCHAIN_RESET(rxq);
 	return 0;
+}
 static int
 wm_init_rx_queue(struct wm_softc *sc, struct wm_queue *wmq,
     struct wm_rxqueue *rxq)
+{
 	KASSERT(mutex_owned(rxq->rxq_lock));
 	/*
 	 * Set up some register offsets that are different between
 	 * the i82542 and the i82543 and later chips.
 	 */
 	if (sc->sc_type < WM_T_82543)
 		rxq->rxq_rdt_reg = WMREG_OLD_RDT0;
 	else
 		rxq->rxq_rdt_reg = WMREG_RDT(wmq->wmq_id);
 	wm_init_rx_regs(sc, wmq, rxq);
 	return wm_init_rx_buffer(sc, rxq);
+}
 /*
  * wm_init_quques:
  *	Initialize {tx,rx}descs and {tx,rx} buffers
  */
 static int
 wm_init_txrx_queues(struct wm_softc *sc)
+{
 	int i, error = 0;
 	DPRINTF(sc, WM_DEBUG_INIT, ("%s: %s called\n",
 		device_xname(sc->sc_dev), __func__));
 	for (i = 0; i < sc->sc_nqueues; i++) {
 		struct wm_queue *wmq = &sc->sc_queue[i];
 		struct wm_txqueue *txq = &wmq->wmq_txq;
 		struct wm_rxqueue *rxq = &wmq->wmq_rxq;
 		/*
 		 * TODO
 		 * Currently, use constant variable instead of AIM.
 		 * Furthermore, the interrupt interval of multiqueue which use
 		 * polling mode is less than default value.
 		 * More tuning and AIM are required.
 		 */
 		if (wm_is_using_multiqueue(sc))
 			wmq->wmq_itr = 50;
 		else
 			wmq->wmq_itr = sc->sc_itr_init;
 		wmq->wmq_set_itr = true;
 		mutex_enter(txq->txq_lock);
 		wm_init_tx_queue(sc, wmq, txq);
 		mutex_exit(txq->txq_lock);
 		mutex_enter(rxq->rxq_lock);
 		error = wm_init_rx_queue(sc, wmq, rxq);
 		mutex_exit(rxq->rxq_lock);
 		if (error)
 			break;
+	}
 	return error;
+}
 /*
  * wm_tx_offload:
+ *
  *	Set up TCP/IP checksumming parameters for the
  *	specified packet.
  */
 static void
 wm_tx_offload(struct wm_softc *sc, struct wm_txqueue *txq,
     struct wm_txsoft *txs, uint32_t *cmdp, uint8_t *fieldsp)
+{
 	struct mbuf *m0 = txs->txs_mbuf;
 	struct livengood_tcpip_ctxdesc *t;
 	uint32_t ipcs, tucs, cmd, cmdlen, seg;
 	uint32_t ipcse;
 	struct ether_header *eh;
 	int offset, iphl;
 	uint8_t fields;
 	/*
 	 * XXX It would be nice if the mbuf pkthdr had offset
 	 * fields for the protocol headers.
 	 */
 	eh = mtod(m0, struct ether_header *);
 	switch (htons(eh->ether_type)) {
 	case ETHERTYPE_IP:
 	case ETHERTYPE_IPV6:
 		offset = ETHER_HDR_LEN;
 		break;
 	case ETHERTYPE_VLAN:
 		offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
 		break;
 	default:
 		/* Don't support this protocol or encapsulation. */
 		txq->txq_last_hw_cmd = txq->txq_last_hw_fields = 0;
 		txq->txq_last_hw_ipcs = 0;
 		txq->txq_last_hw_tucs = 0;
 		*fieldsp = 0;
 		*cmdp = 0;
 		return;
+	}
 	if ((m0->m_pkthdr.csum_flags &
 	    (M_CSUM_TSOv4 | M_CSUM_UDPv4 | M_CSUM_TCPv4 | M_CSUM_IPv4)) != 0) {
 		iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data);
 	} else
 		iphl = M_CSUM_DATA_IPv6_HL(m0->m_pkthdr.csum_data);
 	ipcse = offset + iphl - 1;
 	cmd = WTX_CMD_DEXT | WTX_DTYP_D;
 	cmdlen = WTX_CMD_DEXT | WTX_DTYP_C | WTX_CMD_IDE;
 	seg = 0;
 	fields = 0;
 	if ((m0->m_pkthdr.csum_flags & (M_CSUM_TSOv4 | M_CSUM_TSOv6)) != 0) {
 		int hlen = offset + iphl;
 		bool v4 = (m0->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0;
 		if (__predict_false(m0->m_len <
 				    (hlen + sizeof(struct tcphdr)))) {
 			/*
 			 * TCP/IP headers are not in the first mbuf; we need
 			 * to do this the slow and painful way. Let's just
 			 * hope this doesn't happen very often.
 			 */
 			struct tcphdr th;
 			WM_Q_EVCNT_INCR(txq, tsopain);
 			m_copydata(m0, hlen, sizeof(th), &th);
 			if (v4) {
 				struct ip ip;
 				m_copydata(m0, offset, sizeof(ip), &ip);
 				ip.ip_len = 0;
 				m_copyback(m0,
 				    offset + offsetof(struct ip, ip_len),
 				    sizeof(ip.ip_len), &ip.ip_len);
 				th.th_sum = in_cksum_phdr(ip.ip_src.s_addr,
 				    ip.ip_dst.s_addr, htons(IPPROTO_TCP));
 			} else {
 				struct ip6_hdr ip6;
 				m_copydata(m0, offset, sizeof(ip6), &ip6);
 				ip6.ip6_plen = 0;
 				m_copyback(m0,
 				    offset + offsetof(struct ip6_hdr, ip6_plen),
 				    sizeof(ip6.ip6_plen), &ip6.ip6_plen);
 				th.th_sum = in6_cksum_phdr(&ip6.ip6_src,
 				    &ip6.ip6_dst, 0, htonl(IPPROTO_TCP));
+			}
 			m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum),
 			    sizeof(th.th_sum), &th.th_sum);
 			hlen += th.th_off << 2;
 		} else {
 			/*
 			 * TCP/IP headers are in the first mbuf; we can do
 			 * this the easy way.
 			 */
 			struct tcphdr *th;
 			if (v4) {
 				struct ip *ip =
 				    (void *)(mtod(m0, char *) + offset);
 				th = (void *)(mtod(m0, char *) + hlen);
 				ip->ip_len = 0;
 				th->th_sum = in_cksum_phdr(ip->ip_src.s_addr,
 				    ip->ip_dst.s_addr, htons(IPPROTO_TCP));
 			} else {
 				struct ip6_hdr *ip6 =
 				    (void *)(mtod(m0, char *) + offset);
 				th = (void *)(mtod(m0, char *) + hlen);
 				ip6->ip6_plen = 0;
 				th->th_sum = in6_cksum_phdr(&ip6->ip6_src,
 				    &ip6->ip6_dst, 0, htonl(IPPROTO_TCP));
+			}
 			hlen += th->th_off << 2;
+		}
 		if (v4) {
 			WM_Q_EVCNT_INCR(txq, tso);
 			cmdlen |= WTX_TCPIP_CMD_IP;
 		} else {
 			WM_Q_EVCNT_INCR(txq, tso6);
 			ipcse = 0;
+		}
 		cmd |= WTX_TCPIP_CMD_TSE;
 		cmdlen |= WTX_TCPIP_CMD_TSE |
 		    WTX_TCPIP_CMD_TCP | (m0->m_pkthdr.len - hlen);
 		seg = WTX_TCPIP_SEG_HDRLEN(hlen) |
 		    WTX_TCPIP_SEG_MSS(m0->m_pkthdr.segsz);
+	}
 	/*
 	 * NOTE: Even if we're not using the IP or TCP/UDP checksum
 	 * offload feature, if we load the context descriptor, we
 	 * MUST provide valid values for IPCSS and TUCSS fields.
 	 */
 	ipcs = WTX_TCPIP_IPCSS(offset) |
 	    WTX_TCPIP_IPCSO(offset + offsetof(struct ip, ip_sum)) |
 	    WTX_TCPIP_IPCSE(ipcse);
 	if (m0->m_pkthdr.csum_flags & (M_CSUM_IPv4 | M_CSUM_TSOv4)) {
 		WM_Q_EVCNT_INCR(txq, ipsum);
 		fields |= WTX_IXSM;
+	}
 	offset += iphl;
 	if (m0->m_pkthdr.csum_flags &
 	    (M_CSUM_TCPv4 | M_CSUM_UDPv4 | M_CSUM_TSOv4)) {
 		WM_Q_EVCNT_INCR(txq, tusum);
 		fields |= WTX_TXSM;
 		tucs = WTX_TCPIP_TUCSS(offset) |
 		    WTX_TCPIP_TUCSO(offset +
 			M_CSUM_DATA_IPv4_OFFSET(m0->m_pkthdr.csum_data)) |
 		    WTX_TCPIP_TUCSE(0) /* Rest of packet */;
 	} else if ((m0->m_pkthdr.csum_flags &
 	    (M_CSUM_TCPv6 | M_CSUM_UDPv6 | M_CSUM_TSOv6)) != 0) {
 		WM_Q_EVCNT_INCR(txq, tusum6);
 		fields |= WTX_TXSM;
 		tucs = WTX_TCPIP_TUCSS(offset) |
 		    WTX_TCPIP_TUCSO(offset +
 			M_CSUM_DATA_IPv6_OFFSET(m0->m_pkthdr.csum_data)) |
 		    WTX_TCPIP_TUCSE(0) /* Rest of packet */;
 	} else {
 		/* Just initialize it to a valid TCP context. */
 		tucs = WTX_TCPIP_TUCSS(offset) |
 		    WTX_TCPIP_TUCSO(offset + offsetof(struct tcphdr, th_sum)) |
 		    WTX_TCPIP_TUCSE(0) /* Rest of packet */;
+	}
 	*cmdp = cmd;
 	*fieldsp = fields;
 	/*
 	 * We don't have to write context descriptor for every packet
 	 * except for 82574. For 82574, we must write context descriptor
 	 * for every packet when we use two descriptor queues.
+	 *
 	 * The 82574L can only remember the *last* context used
 	 * regardless of queue that it was use for.  We cannot reuse
 	 * contexts on this hardware platform and must generate a new
 	 * context every time.  82574L hardware spec, section 7.2.6,
 	 * second note.
 	 */
 	if (sc->sc_nqueues < 2) {
 		/*
 		 * Setting up new checksum offload context for every
 		 * frames takes a lot of processing time for hardware.
 		 * This also reduces performance a lot for small sized
 		 * frames so avoid it if driver can use previously
 		 * configured checksum offload context.
 		 * For TSO, in theory we can use the same TSO context only if
 		 * frame is the same type(IP/TCP) and the same MSS. However
 		 * checking whether a frame has the same IP/TCP structure is a
 		 * hard thing so just ignore that and always restablish a
 		 * new TSO context.
 		 */
 		if ((m0->m_pkthdr.csum_flags & (M_CSUM_TSOv4 | M_CSUM_TSOv6))
 		    == 0) {
 			if (txq->txq_last_hw_cmd == cmd &&
 			    txq->txq_last_hw_fields == fields &&
 			    txq->txq_last_hw_ipcs == (ipcs & 0xffff) &&
 			    txq->txq_last_hw_tucs == (tucs & 0xffff)) {
 				WM_Q_EVCNT_INCR(txq, skipcontext);
 				return;
+			}
+		}
 		txq->txq_last_hw_cmd = cmd;
 		txq->txq_last_hw_fields = fields;
 		txq->txq_last_hw_ipcs = (ipcs & 0xffff);
 		txq->txq_last_hw_tucs = (tucs & 0xffff);
+	}
 	/* Fill in the context descriptor. */
 	t = (struct livengood_tcpip_ctxdesc *)
 	    &txq->txq_descs[txq->txq_next];
 	t->tcpip_ipcs = htole32(ipcs);
 	t->tcpip_tucs = htole32(tucs);
 	t->tcpip_cmdlen = htole32(cmdlen);
 	t->tcpip_seg = htole32(seg);
 	wm_cdtxsync(txq, txq->txq_next, 1, BUS_DMASYNC_PREWRITE);
 	txq->txq_next = WM_NEXTTX(txq, txq->txq_next);
 	txs->txs_ndesc++;
+}
 static inline int
 wm_select_txqueue(struct ifnet *ifp, struct mbuf *m)
+{
 	struct wm_softc *sc = ifp->if_softc;
 	u_int cpuid = cpu_index(curcpu());
 	/*
 	 * Currently, simple distribute strategy.
 	 * TODO:
 	 * distribute by flowid(RSS has value).
 	 */
 	return ((cpuid + ncpu - sc->sc_affinity_offset) % ncpu) % sc->sc_nqueues;
+}
 static inline bool
 wm_linkdown_discard(struct wm_txqueue *txq)
+{
 	if ((txq->txq_flags & WM_TXQ_LINKDOWN_DISCARD) != 0)
 		return true;
 	return false;
+}
 /*
  * wm_start:		[ifnet interface function]
+ *
  *	Start packet transmission on the interface.
  */
 static void
 wm_start(struct ifnet *ifp)
+{
 	struct wm_softc *sc = ifp->if_softc;
 	struct wm_txqueue *txq = &sc->sc_queue[0].wmq_txq;
 #ifdef WM_MPSAFE
 	KASSERT(if_is_mpsafe(ifp));
 #endif
 	/*
 	 * ifp->if_obytes and ifp->if_omcasts are added in if_transmit()@if.c.
 	 */
 	mutex_enter(txq->txq_lock);
 	if (!txq->txq_stopping)
 		wm_start_locked(ifp);
 	mutex_exit(txq->txq_lock);
+}
 static void
 wm_start_locked(struct ifnet *ifp)
+{
 	struct wm_softc *sc = ifp->if_softc;
 	struct wm_txqueue *txq = &sc->sc_queue[0].wmq_txq;
 	wm_send_common_locked(ifp, txq, false);
+}
 static int
 wm_transmit(struct ifnet *ifp, struct mbuf *m)
+{
 	int qid;
 	struct wm_softc *sc = ifp->if_softc;
 	struct wm_txqueue *txq;
 	qid = wm_select_txqueue(ifp, m);
 	txq = &sc->sc_queue[qid].wmq_txq;
 	if (__predict_false(!pcq_put(txq->txq_interq, m))) {
 		m_freem(m);
 		WM_Q_EVCNT_INCR(txq, pcqdrop);
 		return ENOBUFS;
+	}
 	/* XXX NOMPSAFE: ifp->if_data should be percpu. */
 	ifp->if_obytes += m->m_pkthdr.len;
 	if (m->m_flags & M_MCAST)
 		ifp->if_omcasts++;
 	if (mutex_tryenter(txq->txq_lock)) {
 		if (!txq->txq_stopping)
 			wm_transmit_locked(ifp, txq);
 		mutex_exit(txq->txq_lock);
+	}
 	return 0;
+}
 static void
 wm_transmit_locked(struct ifnet *ifp, struct wm_txqueue *txq)
+{
 	wm_send_common_locked(ifp, txq, true);
+}
 static void
 wm_send_common_locked(struct ifnet *ifp, struct wm_txqueue *txq,
     bool is_transmit)
+{
 	struct wm_softc *sc = ifp->if_softc;
 	struct mbuf *m0;
 	struct wm_txsoft *txs;
 	bus_dmamap_t dmamap;
 	int error, nexttx, lasttx = -1, ofree, seg, segs_needed, use_tso;
 	bus_addr_t curaddr;
 	bus_size_t seglen, curlen;
 	uint32_t cksumcmd;
 	uint8_t cksumfields;
 	bool remap = true;
 	KASSERT(mutex_owned(txq->txq_lock));
 	if ((ifp->if_flags & IFF_RUNNING) == 0)
 		return;
 	if ((ifp->if_flags & IFF_OACTIVE) != 0 && !is_transmit)
 		return;
 	if ((txq->txq_flags & WM_TXQ_NO_SPACE) != 0)
 		return;
 	if (__predict_false(wm_linkdown_discard(txq))) {
 		do {
 			if (is_transmit)
 				m0 = pcq_get(txq->txq_interq);
 			else
 				IFQ_DEQUEUE(&ifp->if_snd, m0);
 			/*
 			 * increment successed packet counter as in the case
 			 * which the packet is discarded by link down PHY.
 			 */
 			if (m0 != NULL) {
 				ifp->if_opackets++;
 				m_freem(m0);
+			}
 		} while (m0 != NULL);
 		return;
+	}
 	/* Remember the previous number of free descriptors. */
 	ofree = txq->txq_free;
 	/*
 	 * Loop through the send queue, setting up transmit descriptors
 	 * until we drain the queue, or use up all available transmit
 	 * descriptors.
 	 */
 	for (;;) {
 		m0 = NULL;
 		/* Get a work queue entry. */
 		if (txq->txq_sfree < WM_TXQUEUE_GC(txq)) {
 			wm_txeof(txq, UINT_MAX);
 			if (txq->txq_sfree == 0) {
 				DPRINTF(sc, WM_DEBUG_TX,
 				    ("%s: TX: no free job descriptors\n",
 					device_xname(sc->sc_dev)));
 				WM_Q_EVCNT_INCR(txq, txsstall);
 				break;
+			}
+		}
 		/* Grab a packet off the queue. */
 		if (is_transmit)
 			m0 = pcq_get(txq->txq_interq);
 		else
 			IFQ_DEQUEUE(&ifp->if_snd, m0);
 		if (m0 == NULL)
 			break;
 		DPRINTF(sc, WM_DEBUG_TX,
 		    ("%s: TX: have packet to transmit: %p\n",
 			device_xname(sc->sc_dev), m0));
 		txs = &txq->txq_soft[txq->txq_snext];
 		dmamap = txs->txs_dmamap;
 		use_tso = (m0->m_pkthdr.csum_flags &
 		    (M_CSUM_TSOv4 | M_CSUM_TSOv6)) != 0;
 		/*
 		 * So says the Linux driver:
 		 * The controller does a simple calculation to make sure
 		 * there is enough room in the FIFO before initiating the
 		 * DMA for each buffer. The calc is:
 		 *	4 = ceil(buffer len / MSS)
 		 * To make sure we don't overrun the FIFO, adjust the max
 		 * buffer len if the MSS drops.
 		 */
 		dmamap->dm_maxsegsz =
 		    (use_tso && (m0->m_pkthdr.segsz << 2) < WTX_MAX_LEN)
 		    ? m0->m_pkthdr.segsz << 2
 		    : WTX_MAX_LEN;
 		/*
 		 * Load the DMA map.  If this fails, the packet either
 		 * didn't fit in the allotted number of segments, or we
 		 * were short on resources.  For the too-many-segments
 		 * case, we simply report an error and drop the packet,
 		 * since we can't sanely copy a jumbo packet to a single
 		 * buffer.
 		 */
 retry:
 		error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0,
 		    BUS_DMA_WRITE | BUS_DMA_NOWAIT);
 		if (__predict_false(error)) {
 			if (error == EFBIG) {
 				if (remap == true) {
 					struct mbuf *m;
 					remap = false;
 					m = m_defrag(m0, M_NOWAIT);
 					if (m != NULL) {
 						WM_Q_EVCNT_INCR(txq, defrag);
 						m0 = m;
 						goto retry;
+					}
+				}
 				WM_Q_EVCNT_INCR(txq, toomanyseg);
 				log(LOG_ERR, "%s: Tx packet consumes too many "
 				    "DMA segments, dropping...\n",
 				    device_xname(sc->sc_dev));
 				wm_dump_mbuf_chain(sc, m0);
 				m_freem(m0);
 				continue;
+			}
 			/* Short on resources, just stop for now. */
 			DPRINTF(sc, WM_DEBUG_TX,
 			    ("%s: TX: dmamap load failed: %d\n",
 				device_xname(sc->sc_dev), error));
 			break;
+		}
 		segs_needed = dmamap->dm_nsegs;
 		if (use_tso) {
 			/* For sentinel descriptor; see below. */
 			segs_needed++;
+		}
 		/*
 		 * Ensure we have enough descriptors free to describe
 		 * the packet. Note, we always reserve one descriptor
 		 * at the end of the ring due to the semantics of the
 		 * TDT register, plus one more in the event we need
 		 * to load offload context.
 		 */
 		if (segs_needed > txq->txq_free - 2) {
 			/*
 			 * Not enough free descriptors to transmit this
 			 * packet.  We haven't committed anything yet,
 			 * so just unload the DMA map, put the packet
 			 * pack on the queue, and punt. Notify the upper
 			 * layer that there are no more slots left.
 			 */
 			DPRINTF(sc, WM_DEBUG_TX,
 			    ("%s: TX: need %d (%d) descriptors, have %d\n",
 				device_xname(sc->sc_dev), dmamap->dm_nsegs,
 				segs_needed, txq->txq_free - 1));
 			if (!is_transmit)
 				ifp->if_flags |= IFF_OACTIVE;
 			txq->txq_flags |= WM_TXQ_NO_SPACE;
 			bus_dmamap_unload(sc->sc_dmat, dmamap);
 			WM_Q_EVCNT_INCR(txq, txdstall);
 			break;
+		}
 		/*
 		 * Check for 82547 Tx FIFO bug. We need to do this
 		 * once we know we can transmit the packet, since we
 		 * do some internal FIFO space accounting here.
 		 */
 		if (sc->sc_type == WM_T_82547 &&
 		    wm_82547_txfifo_bugchk(sc, m0)) {
 			DPRINTF(sc, WM_DEBUG_TX,
 			    ("%s: TX: 82547 Tx FIFO bug detected\n",
 				device_xname(sc->sc_dev)));
 			if (!is_transmit)
 				ifp->if_flags |= IFF_OACTIVE;
 			txq->txq_flags |= WM_TXQ_NO_SPACE;
 			bus_dmamap_unload(sc->sc_dmat, dmamap);
 			WM_Q_EVCNT_INCR(txq, fifo_stall);
 			break;
+		}
 		/* WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. */
 		DPRINTF(sc, WM_DEBUG_TX,
 		    ("%s: TX: packet has %d (%d) DMA segments\n",
 		    device_xname(sc->sc_dev), dmamap->dm_nsegs, segs_needed));
 		WM_EVCNT_INCR(&txq->txq_ev_txseg[dmamap->dm_nsegs - 1]);
 		/*
 		 * Store a pointer to the packet so that we can free it
 		 * later.
+		 *
 		 * Initially, we consider the number of descriptors the
 		 * packet uses the number of DMA segments.  This may be
 		 * incremented by 1 if we do checksum offload (a descriptor
 		 * is used to set the checksum context).
 		 */
 		txs->txs_mbuf = m0;
 		txs->txs_firstdesc = txq->txq_next;
 		txs->txs_ndesc = segs_needed;
 		/* Set up offload parameters for this packet. */
 		if (m0->m_pkthdr.csum_flags &
 		    (M_CSUM_TSOv4 | M_CSUM_TSOv6 |
 		    M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4 |
 		    M_CSUM_TCPv6 | M_CSUM_UDPv6)) {
 			wm_tx_offload(sc, txq, txs, &cksumcmd, &cksumfields);
 		} else {
 			txq->txq_last_hw_cmd = txq->txq_last_hw_fields = 0;
 			txq->txq_last_hw_ipcs = txq->txq_last_hw_tucs = 0;
 			cksumcmd = 0;
 			cksumfields = 0;
+		}
 		cksumcmd |= WTX_CMD_IDE | WTX_CMD_IFCS;
 		/* Sync the DMA map. */
 		bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize,
 		    BUS_DMASYNC_PREWRITE);
 		/* Initialize the transmit descriptor. */
 		for (nexttx = txq->txq_next, seg = 0;
 		     seg < dmamap->dm_nsegs; seg++) {
 			for (seglen = dmamap->dm_segs[seg].ds_len,
 			     curaddr = dmamap->dm_segs[seg].ds_addr;
 			     seglen != 0;
 			     curaddr += curlen, seglen -= curlen,
 			     nexttx = WM_NEXTTX(txq, nexttx)) {
 				curlen = seglen;
 				/*
 				 * So says the Linux driver:
 				 * Work around for premature descriptor
 				 * write-backs in TSO mode.  Append a
 				 * 4-byte sentinel descriptor.
 				 */
 				if (use_tso && seg == dmamap->dm_nsegs - 1 &&
 				    curlen > 8)
 					curlen -= 4;
 				wm_set_dma_addr(
 				    &txq->txq_descs[nexttx].wtx_addr, curaddr);
 				txq->txq_descs[nexttx].wtx_cmdlen
 				    = htole32(cksumcmd | curlen);
 				txq->txq_descs[nexttx].wtx_fields.wtxu_status
 				    = 0;
 				txq->txq_descs[nexttx].wtx_fields.wtxu_options
 				    = cksumfields;
 				txq->txq_descs[nexttx].wtx_fields.wtxu_vlan =0;
 				lasttx = nexttx;
 				DPRINTF(sc, WM_DEBUG_TX,
 				    ("%s: TX: desc %d: low %#" PRIx64 ", "
 					"len %#04zx\n",
 					device_xname(sc->sc_dev), nexttx,
 					(uint64_t)curaddr, curlen));
+			}
+		}
 		KASSERT(lasttx != -1);
 		/*
 		 * Set up the command byte on the last descriptor of
 		 * the packet. If we're in the interrupt delay window,
 		 * delay the interrupt.
 		 */
 		txq->txq_descs[lasttx].wtx_cmdlen |=
 		    htole32(WTX_CMD_EOP | WTX_CMD_RS);
 		/*
 		 * If VLANs are enabled and the packet has a VLAN tag, set
 		 * up the descriptor to encapsulate the packet for us.
+		 *
 		 * This is only valid on the last descriptor of the packet.
 		 */
 		if (vlan_has_tag(m0)) {
 			txq->txq_descs[lasttx].wtx_cmdlen |=
 			    htole32(WTX_CMD_VLE);
 			txq->txq_descs[lasttx].wtx_fields.wtxu_vlan
 			    = htole16(vlan_get_tag(m0));
+		}
 		txs->txs_lastdesc = lasttx;
 		DPRINTF(sc, WM_DEBUG_TX,
 		    ("%s: TX: desc %d: cmdlen 0x%08x\n",
 			device_xname(sc->sc_dev),
 			lasttx, le32toh(txq->txq_descs[lasttx].wtx_cmdlen)));
 		/* Sync the descriptors we're using. */
 		wm_cdtxsync(txq, txq->txq_next, txs->txs_ndesc,
 		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 		/* Give the packet to the chip. */
 		CSR_WRITE(sc, txq->txq_tdt_reg, nexttx);
 		DPRINTF(sc, WM_DEBUG_TX,
 		    ("%s: TX: TDT -> %d\n", device_xname(sc->sc_dev), nexttx));
 		DPRINTF(sc, WM_DEBUG_TX,
 		    ("%s: TX: finished transmitting packet, job %d\n",
 			device_xname(sc->sc_dev), txq->txq_snext));
 		/* Advance the tx pointer. */
 		txq->txq_free -= txs->txs_ndesc;
 		txq->txq_next = nexttx;
 		txq->txq_sfree--;
 		txq->txq_snext = WM_NEXTTXS(txq, txq->txq_snext);
 		/* Pass the packet to any BPF listeners. */
 		bpf_mtap(ifp, m0);
+	}
 	if (m0 != NULL) {
 		if (!is_transmit)
 			ifp->if_flags |= IFF_OACTIVE;
 		txq->txq_flags |= WM_TXQ_NO_SPACE;
 		WM_Q_EVCNT_INCR(txq, descdrop);
 		DPRINTF(sc, WM_DEBUG_TX, ("%s: TX: error after IFQ_DEQUEUE\n",
 			__func__));
 		m_freem(m0);
+	}
 	if (txq->txq_sfree == 0 || txq->txq_free <= 2) {
 		/* No more slots; notify upper layer. */
 		if (!is_transmit)
 			ifp->if_flags |= IFF_OACTIVE;
 		txq->txq_flags |= WM_TXQ_NO_SPACE;
+	}
 	if (txq->txq_free != ofree) {
 		/* Set a watchdog timer in case the chip flakes out. */
 		txq->txq_lastsent = time_uptime;
 		txq->txq_sending = true;
+	}
+}
 /*
  * wm_nq_tx_offload:
+ *
  *	Set up TCP/IP checksumming parameters for the
  *	specified packet, for NEWQUEUE devices
  */
 static void
 wm_nq_tx_offload(struct wm_softc *sc, struct wm_txqueue *txq,
     struct wm_txsoft *txs, uint32_t *cmdlenp, uint32_t *fieldsp, bool *do_csum)
+{
 	struct mbuf *m0 = txs->txs_mbuf;
 	uint32_t vl_len, mssidx, cmdc;
 	struct ether_header *eh;
 	int offset, iphl;
 	/*
 	 * XXX It would be nice if the mbuf pkthdr had offset
 	 * fields for the protocol headers.
 	 */
 	*cmdlenp = 0;
 	*fieldsp = 0;
 	eh = mtod(m0, struct ether_header *);
 	switch (htons(eh->ether_type)) {
 	case ETHERTYPE_IP:
 	case ETHERTYPE_IPV6:
 		offset = ETHER_HDR_LEN;
 		break;
 	case ETHERTYPE_VLAN:
 		offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
 		break;
 	default:
 		/* Don't support this protocol or encapsulation. */
 		*do_csum = false;
 		return;
+	}
 	*do_csum = true;
 	*cmdlenp = NQTX_DTYP_D | NQTX_CMD_DEXT | NQTX_CMD_IFCS;
 	cmdc = NQTX_DTYP_C | NQTX_CMD_DEXT;
 	vl_len = (offset << NQTXC_VLLEN_MACLEN_SHIFT);
 	KASSERT((offset & ~NQTXC_VLLEN_MACLEN_MASK) == 0);
 	if ((m0->m_pkthdr.csum_flags &
 	    (M_CSUM_TSOv4 | M_CSUM_UDPv4 | M_CSUM_TCPv4 | M_CSUM_IPv4)) != 0) {
 		iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data);
 	} else {
 		iphl = M_CSUM_DATA_IPv6_HL(m0->m_pkthdr.csum_data);
+	}
 	vl_len |= (iphl << NQTXC_VLLEN_IPLEN_SHIFT);
 	KASSERT((iphl & ~NQTXC_VLLEN_IPLEN_MASK) == 0);
 	if (vlan_has_tag(m0)) {
 		vl_len |= ((vlan_get_tag(m0) & NQTXC_VLLEN_VLAN_MASK)
 		    << NQTXC_VLLEN_VLAN_SHIFT);
 		*cmdlenp |= NQTX_CMD_VLE;
+	}
 	mssidx = 0;
 	if ((m0->m_pkthdr.csum_flags & (M_CSUM_TSOv4 | M_CSUM_TSOv6)) != 0) {
 		int hlen = offset + iphl;
 		int tcp_hlen;
 		bool v4 = (m0->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0;
 		if (__predict_false(m0->m_len <
 				    (hlen + sizeof(struct tcphdr)))) {
 			/*
 			 * TCP/IP headers are not in the first mbuf; we need
 			 * to do this the slow and painful way. Let's just
 			 * hope this doesn't happen very often.
 			 */
 			struct tcphdr th;
 			WM_Q_EVCNT_INCR(txq, tsopain);
 			m_copydata(m0, hlen, sizeof(th), &th);
 			if (v4) {
 				struct ip ip;
 				m_copydata(m0, offset, sizeof(ip), &ip);
 				ip.ip_len = 0;
 				m_copyback(m0,
 				    offset + offsetof(struct ip, ip_len),
 				    sizeof(ip.ip_len), &ip.ip_len);
 				th.th_sum = in_cksum_phdr(ip.ip_src.s_addr,
 				    ip.ip_dst.s_addr, htons(IPPROTO_TCP));
 			} else {
 				struct ip6_hdr ip6;
 				m_copydata(m0, offset, sizeof(ip6), &ip6);
 				ip6.ip6_plen = 0;
 				m_copyback(m0,
 				    offset + offsetof(struct ip6_hdr, ip6_plen),
 				    sizeof(ip6.ip6_plen), &ip6.ip6_plen);
 				th.th_sum = in6_cksum_phdr(&ip6.ip6_src,
 				    &ip6.ip6_dst, 0, htonl(IPPROTO_TCP));
+			}
 			m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum),
 			    sizeof(th.th_sum), &th.th_sum);
 			tcp_hlen = th.th_off << 2;
 		} else {
 			/*
 			 * TCP/IP headers are in the first mbuf; we can do
 			 * this the easy way.
 			 */
 			struct tcphdr *th;
 			if (v4) {
 				struct ip *ip =
 				    (void *)(mtod(m0, char *) + offset);
 				th = (void *)(mtod(m0, char *) + hlen);
 				ip->ip_len = 0;
 				th->th_sum = in_cksum_phdr(ip->ip_src.s_addr,
 				    ip->ip_dst.s_addr, htons(IPPROTO_TCP));
 			} else {
 				struct ip6_hdr *ip6 =
 				    (void *)(mtod(m0, char *) + offset);
 				th = (void *)(mtod(m0, char *) + hlen);
 				ip6->ip6_plen = 0;
 				th->th_sum = in6_cksum_phdr(&ip6->ip6_src,
 				    &ip6->ip6_dst, 0, htonl(IPPROTO_TCP));
+			}
 			tcp_hlen = th->th_off << 2;
+		}
 		hlen += tcp_hlen;
 		*cmdlenp |= NQTX_CMD_TSE;
 		if (v4) {
 			WM_Q_EVCNT_INCR(txq, tso);
 			*fieldsp |= NQTXD_FIELDS_IXSM | NQTXD_FIELDS_TUXSM;
 		} else {
 			WM_Q_EVCNT_INCR(txq, tso6);
 			*fieldsp |= NQTXD_FIELDS_TUXSM;
+		}
 		*fieldsp |= ((m0->m_pkthdr.len - hlen) << NQTXD_FIELDS_PAYLEN_SHIFT);
 		KASSERT(((m0->m_pkthdr.len - hlen) & ~NQTXD_FIELDS_PAYLEN_MASK) == 0);
 		mssidx |= (m0->m_pkthdr.segsz << NQTXC_MSSIDX_MSS_SHIFT);
 		KASSERT((m0->m_pkthdr.segsz & ~NQTXC_MSSIDX_MSS_MASK) == 0);
 		mssidx |= (tcp_hlen << NQTXC_MSSIDX_L4LEN_SHIFT);
 		KASSERT((tcp_hlen & ~NQTXC_MSSIDX_L4LEN_MASK) == 0);
 	} else {
 		*fieldsp |= (m0->m_pkthdr.len << NQTXD_FIELDS_PAYLEN_SHIFT);
 		KASSERT((m0->m_pkthdr.len & ~NQTXD_FIELDS_PAYLEN_MASK) == 0);
+	}
 	if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) {
 		*fieldsp |= NQTXD_FIELDS_IXSM;
 		cmdc |= NQTXC_CMD_IP4;
+	}
 	if (m0->m_pkthdr.csum_flags &
 	    (M_CSUM_UDPv4 | M_CSUM_TCPv4 | M_CSUM_TSOv4)) {
 		WM_Q_EVCNT_INCR(txq, tusum);
 		if (m0->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_TSOv4))
 			cmdc |= NQTXC_CMD_TCP;
 		else
 			cmdc |= NQTXC_CMD_UDP;
 		cmdc |= NQTXC_CMD_IP4;
 		*fieldsp |= NQTXD_FIELDS_TUXSM;
+	}
 	if (m0->m_pkthdr.csum_flags &
 	    (M_CSUM_UDPv6 | M_CSUM_TCPv6 | M_CSUM_TSOv6)) {
 		WM_Q_EVCNT_INCR(txq, tusum6);
 		if (m0->m_pkthdr.csum_flags & (M_CSUM_TCPv6 | M_CSUM_TSOv6))
 			cmdc |= NQTXC_CMD_TCP;
 		else
 			cmdc |= NQTXC_CMD_UDP;
 		cmdc |= NQTXC_CMD_IP6;
 		*fieldsp |= NQTXD_FIELDS_TUXSM;
+	}
 	/*
 	 * We don't have to write context descriptor for every packet to
 	 * NEWQUEUE controllers, that is 82575, 82576, 82580, I350, I354,
 	 * I210 and I211. It is enough to write once per a Tx queue for these
 	 * controllers.
 	 * It would be overhead to write context descriptor for every packet,
 	 * however it does not cause problems.
 	 */
 	/* Fill in the context descriptor. */
 	txq->txq_nq_descs[txq->txq_next].nqtx_ctx.nqtxc_vl_len =
 	    htole32(vl_len);
 	txq->txq_nq_descs[txq->txq_next].nqtx_ctx.nqtxc_sn = 0;
 	txq->txq_nq_descs[txq->txq_next].nqtx_ctx.nqtxc_cmd =
 	    htole32(cmdc);
 	txq->txq_nq_descs[txq->txq_next].nqtx_ctx.nqtxc_mssidx =
 	    htole32(mssidx);
 	wm_cdtxsync(txq, txq->txq_next, 1, BUS_DMASYNC_PREWRITE);
 	DPRINTF(sc, WM_DEBUG_TX,
 	    ("%s: TX: context desc %d 0x%08x%08x\n", device_xname(sc->sc_dev),
 		txq->txq_next, 0, vl_len));
 	DPRINTF(sc, WM_DEBUG_TX, ("\t0x%08x%08x\n", mssidx, cmdc));
 	txq->txq_next = WM_NEXTTX(txq, txq->txq_next);
 	txs->txs_ndesc++;
+}
 @@ -9947,2001 +9983,2001 @@ wm_rxdesc_is_set_status(struct wm_softc
+{
 	if (sc->sc_type == WM_T_82574)
 		return (status & ext_bit) != 0;
 	else if ((sc->sc_flags & WM_F_NEWQUEUE) != 0)
 		return (status & nq_bit) != 0;
 	else
 		return (status & legacy_bit) != 0;
+}
 static inline bool
 wm_rxdesc_is_set_error(struct wm_softc *sc, uint32_t error,
     uint32_t legacy_bit, uint32_t ext_bit, uint32_t nq_bit)
+{
 	if (sc->sc_type == WM_T_82574)
 		return (error & ext_bit) != 0;
 	else if ((sc->sc_flags & WM_F_NEWQUEUE) != 0)
 		return (error & nq_bit) != 0;
 	else
 		return (error & legacy_bit) != 0;
+}
 static inline bool
 wm_rxdesc_is_eop(struct wm_rxqueue *rxq, uint32_t status)
+{
 	if (wm_rxdesc_is_set_status(rxq->rxq_sc, status,
 		WRX_ST_EOP, EXTRXC_STATUS_EOP, NQRXC_STATUS_EOP))
 		return true;
 	else
 		return false;
+}
 static inline bool
 wm_rxdesc_has_errors(struct wm_rxqueue *rxq, uint32_t errors)
+{
 	struct wm_softc *sc = rxq->rxq_sc;
 	/* XXX missing error bit for newqueue? */
 	if (wm_rxdesc_is_set_error(sc, errors,
 		WRX_ER_CE | WRX_ER_SE | WRX_ER_SEQ | WRX_ER_CXE | WRX_ER_RXE,
 		EXTRXC_ERROR_CE | EXTRXC_ERROR_SE | EXTRXC_ERROR_SEQ
 		| EXTRXC_ERROR_CXE | EXTRXC_ERROR_RXE,
 		NQRXC_ERROR_RXE)) {
 		if (wm_rxdesc_is_set_error(sc, errors, WRX_ER_SE,
 		    EXTRXC_ERROR_SE, 0))
 			log(LOG_WARNING, "%s: symbol error\n",
 			    device_xname(sc->sc_dev));
 		else if (wm_rxdesc_is_set_error(sc, errors, WRX_ER_SEQ,
 		    EXTRXC_ERROR_SEQ, 0))
 			log(LOG_WARNING, "%s: receive sequence error\n",
 			    device_xname(sc->sc_dev));
 		else if (wm_rxdesc_is_set_error(sc, errors, WRX_ER_CE,
 		    EXTRXC_ERROR_CE, 0))
 			log(LOG_WARNING, "%s: CRC error\n",
 			    device_xname(sc->sc_dev));
 		return true;
+	}
 	return false;
+}
 static inline bool
 wm_rxdesc_dd(struct wm_rxqueue *rxq, int idx, uint32_t status)
+{
 	struct wm_softc *sc = rxq->rxq_sc;
 	if (!wm_rxdesc_is_set_status(sc, status, WRX_ST_DD, EXTRXC_STATUS_DD,
 		NQRXC_STATUS_DD)) {
 		/* We have processed all of the receive descriptors. */
 		wm_cdrxsync(rxq, idx, BUS_DMASYNC_PREREAD);
 		return false;
+	}
 	return true;
+}
 static inline bool
 wm_rxdesc_input_vlantag(struct wm_rxqueue *rxq, uint32_t status,
     uint16_t vlantag, struct mbuf *m)
+{
 	if (wm_rxdesc_is_set_status(rxq->rxq_sc, status,
 		WRX_ST_VP, EXTRXC_STATUS_VP, NQRXC_STATUS_VP)) {
 		vlan_set_tag(m, le16toh(vlantag));
+	}
 	return true;
+}
 static inline void
 wm_rxdesc_ensure_checksum(struct wm_rxqueue *rxq, uint32_t status,
     uint32_t errors, struct mbuf *m)
+{
 	struct wm_softc *sc = rxq->rxq_sc;
 	if (!wm_rxdesc_is_set_status(sc, status, WRX_ST_IXSM, 0, 0)) {
 		if (wm_rxdesc_is_set_status(sc, status,
 		    WRX_ST_IPCS, EXTRXC_STATUS_IPCS, NQRXC_STATUS_IPCS)) {
 			WM_Q_EVCNT_INCR(rxq, ipsum);
 			m->m_pkthdr.csum_flags |= M_CSUM_IPv4;
 			if (wm_rxdesc_is_set_error(sc, errors,
 			    WRX_ER_IPE, EXTRXC_ERROR_IPE, NQRXC_ERROR_IPE))
 				m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD;
+		}
 		if (wm_rxdesc_is_set_status(sc, status,
 		    WRX_ST_TCPCS, EXTRXC_STATUS_TCPCS, NQRXC_STATUS_L4I)) {
 			/*
 			 * Note: we don't know if this was TCP or UDP,
 			 * so we just set both bits, and expect the
 			 * upper layers to deal.
 			 */
 			WM_Q_EVCNT_INCR(rxq, tusum);
 			m->m_pkthdr.csum_flags |=
 			    M_CSUM_TCPv4 | M_CSUM_UDPv4 |
 			    M_CSUM_TCPv6 | M_CSUM_UDPv6;
 			if (wm_rxdesc_is_set_error(sc, errors, WRX_ER_TCPE,
 			    EXTRXC_ERROR_TCPE, NQRXC_ERROR_L4E))
 				m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD;
+		}
+	}
+}
 /*
  * wm_rxeof:
+ *
  *	Helper; handle receive interrupts.
  */
 static bool
 wm_rxeof(struct wm_rxqueue *rxq, u_int limit)
+{
 	struct wm_softc *sc = rxq->rxq_sc;
 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
 	struct wm_rxsoft *rxs;
 	struct mbuf *m;
 	int i, len;
 	int count = 0;
 	uint32_t status, errors;
 	uint16_t vlantag;
 	bool more = false;
 	KASSERT(mutex_owned(rxq->rxq_lock));
 	for (i = rxq->rxq_ptr;; i = WM_NEXTRX(i)) {
 		rxs = &rxq->rxq_soft[i];
 		DPRINTF(sc, WM_DEBUG_RX,
 		    ("%s: RX: checking descriptor %d\n",
 			device_xname(sc->sc_dev), i));
 		wm_cdrxsync(rxq, i,
 		    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
 		status = wm_rxdesc_get_status(rxq, i);
 		errors = wm_rxdesc_get_errors(rxq, i);
 		len = le16toh(wm_rxdesc_get_pktlen(rxq, i));
 		vlantag = wm_rxdesc_get_vlantag(rxq, i);
 #ifdef WM_DEBUG
 		uint32_t rsshash = le32toh(wm_rxdesc_get_rsshash(rxq, i));
 		uint8_t rsstype = wm_rxdesc_get_rsstype(rxq, i);
 #endif
 		if (!wm_rxdesc_dd(rxq, i, status))
 			break;
 		if (limit-- == 0) {
 			more = true;
 			DPRINTF(sc, WM_DEBUG_RX,
 			    ("%s: RX: loop limited, descriptor %d is not processed\n",
 				device_xname(sc->sc_dev), i));
 			break;
+		}
 		count++;
 		if (__predict_false(rxq->rxq_discard)) {
 			DPRINTF(sc, WM_DEBUG_RX,
 			    ("%s: RX: discarding contents of descriptor %d\n",
 				device_xname(sc->sc_dev), i));
 			wm_init_rxdesc(rxq, i);
 			if (wm_rxdesc_is_eop(rxq, status)) {
 				/* Reset our state. */
 				DPRINTF(sc, WM_DEBUG_RX,
 				    ("%s: RX: resetting rxdiscard -> 0\n",
 					device_xname(sc->sc_dev)));
 				rxq->rxq_discard = 0;
+			}
 			continue;
+		}
 		bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0,
 		    rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
 		m = rxs->rxs_mbuf;
 		/*
 		 * Add a new receive buffer to the ring, unless of
 		 * course the length is zero. Treat the latter as a
 		 * failed mapping.
 		 */
 		if ((len == 0) || (wm_add_rxbuf(rxq, i) != 0)) {
 			/*
 			 * Failed, throw away what we've done so
 			 * far, and discard the rest of the packet.
 			 */
 			ifp->if_ierrors++;
 			bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0,
 			    rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
 			wm_init_rxdesc(rxq, i);
 			if (!wm_rxdesc_is_eop(rxq, status))
 				rxq->rxq_discard = 1;
 			if (rxq->rxq_head != NULL)
 				m_freem(rxq->rxq_head);
 			WM_RXCHAIN_RESET(rxq);
 			DPRINTF(sc, WM_DEBUG_RX,
 			    ("%s: RX: Rx buffer allocation failed, "
 			    "dropping packet%s\n", device_xname(sc->sc_dev),
 				rxq->rxq_discard ? " (discard)" : ""));
 			continue;
+		}
 		m->m_len = len;
 		rxq->rxq_len += len;
 		DPRINTF(sc, WM_DEBUG_RX,
 		    ("%s: RX: buffer at %p len %d\n",
 			device_xname(sc->sc_dev), m->m_data, len));
 		/* If this is not the end of the packet, keep looking. */
 		if (!wm_rxdesc_is_eop(rxq, status)) {
 			WM_RXCHAIN_LINK(rxq, m);
 			DPRINTF(sc, WM_DEBUG_RX,
 			    ("%s: RX: not yet EOP, rxlen -> %d\n",
 				device_xname(sc->sc_dev), rxq->rxq_len));
 			continue;
+		}
 		/*
 		 * Okay, we have the entire packet now. The chip is
 		 * configured to include the FCS except I35[04], I21[01].
 		 * (not all chips can be configured to strip it), so we need
 		 * to trim it. Those chips have an eratta, the RCTL_SECRC bit
 		 * in RCTL register is always set, so we don't trim it.
 		 * PCH2 and newer chip also not include FCS when jumbo
 		 * frame is used to do workaround an errata.
 		 * May need to adjust length of previous mbuf in the
 		 * chain if the current mbuf is too short.
 		 */
 		if ((sc->sc_flags & WM_F_CRC_STRIP) == 0) {
 			if (m->m_len < ETHER_CRC_LEN) {
 				rxq->rxq_tail->m_len
 				    -= (ETHER_CRC_LEN - m->m_len);
 				m->m_len = 0;
 			} else
 				m->m_len -= ETHER_CRC_LEN;
 			len = rxq->rxq_len - ETHER_CRC_LEN;
 		} else
 			len = rxq->rxq_len;
 		WM_RXCHAIN_LINK(rxq, m);
 		*rxq->rxq_tailp = NULL;
 		m = rxq->rxq_head;
 		WM_RXCHAIN_RESET(rxq);
 		DPRINTF(sc, WM_DEBUG_RX,
 		    ("%s: RX: have entire packet, len -> %d\n",
 			device_xname(sc->sc_dev), len));
 		/* If an error occurred, update stats and drop the packet. */
 		if (wm_rxdesc_has_errors(rxq, errors)) {
 			m_freem(m);
 			continue;
+		}
 		/* No errors.  Receive the packet. */
 		m_set_rcvif(m, ifp);
 		m->m_pkthdr.len = len;
 		/*
 		 * TODO
 		 * should be save rsshash and rsstype to this mbuf.
 		 */
 		DPRINTF(sc, WM_DEBUG_RX,
 		    ("%s: RX: RSS type=%" PRIu8 ", RSS hash=%" PRIu32 "\n",
 			device_xname(sc->sc_dev), rsstype, rsshash));
 		/*
 		 * If VLANs are enabled, VLAN packets have been unwrapped
 		 * for us.  Associate the tag with the packet.
 		 */
 		if (!wm_rxdesc_input_vlantag(rxq, status, vlantag, m))
 			continue;
 		/* Set up checksum info for this packet. */
 		wm_rxdesc_ensure_checksum(rxq, status, errors, m);
 		rxq->rxq_packets++;
 		rxq->rxq_bytes += len;
 		/* Pass it on. */
 		if_percpuq_enqueue(sc->sc_ipq, m);
 		if (rxq->rxq_stopping)
 			break;
+	}
 	rxq->rxq_ptr = i;
 	DPRINTF(sc, WM_DEBUG_RX,
 	    ("%s: RX: rxptr -> %d\n", device_xname(sc->sc_dev), i));
 	return more;
+}
 /*
  * wm_linkintr_gmii:
+ *
  *	Helper; handle link interrupts for GMII.
  */
 static void
 wm_linkintr_gmii(struct wm_softc *sc, uint32_t icr)
+{
 	uint32_t status, reg;
 	bool link;
 	bool dopoll = true;
 	KASSERT(WM_CORE_LOCKED(sc));
 	DPRINTF(sc, WM_DEBUG_LINK, ("%s: %s:\n", device_xname(sc->sc_dev),
 		__func__));
 	if ((icr & ICR_LSC) == 0) {
 		if (icr & ICR_RXSEQ)
 			DPRINTF(sc, WM_DEBUG_LINK,
 			    ("%s: LINK Receive sequence error\n",
 				device_xname(sc->sc_dev)));
 		return;
+	}
 	/* Link status changed */
 	status = CSR_READ(sc, WMREG_STATUS);
 	link = status & STATUS_LU;
 	if (link) {
 		DPRINTF(sc, WM_DEBUG_LINK, ("%s: LINK: LSC -> up %s\n",
 			device_xname(sc->sc_dev),
 			(status & STATUS_FD) ? "FDX" : "HDX"));
 		if (wm_phy_need_linkdown_discard(sc)) {
 			DPRINTF(sc, WM_DEBUG_LINK,
 			    ("%s: linkintr: Clear linkdown discard flag\n",
 				device_xname(sc->sc_dev)));
 			wm_clear_linkdown_discard(sc);
+		}
 	} else {
 		DPRINTF(sc, WM_DEBUG_LINK, ("%s: LINK: LSC -> down\n",
 			device_xname(sc->sc_dev)));
 		if (wm_phy_need_linkdown_discard(sc)) {
 			DPRINTF(sc, WM_DEBUG_LINK,
 			    ("%s: linkintr: Set linkdown discard flag\n",
 				device_xname(sc->sc_dev)));
 			wm_set_linkdown_discard(sc);
+		}
+	}
 	if ((sc->sc_type == WM_T_ICH8) && (link == false))
 		wm_gig_downshift_workaround_ich8lan(sc);
 	if ((sc->sc_type == WM_T_ICH8) && (sc->sc_phytype == WMPHY_IGP_3))
 		wm_kmrn_lock_loss_workaround_ich8lan(sc);
 	DPRINTF(sc, WM_DEBUG_LINK, ("%s: LINK: LSC -> mii_pollstat\n",
 		device_xname(sc->sc_dev)));
 	if ((sc->sc_flags & WM_F_DELAY_LINKUP) != 0) {
 		if (link) {
 			/* Wait 1 second. */
 			dopoll = false;
 			getmicrotime(&sc->sc_linkup_delay_time);
 			sc->sc_linkup_delay_time.tv_sec += 1;
 		} else if (sc->sc_linkup_delay_time.tv_sec != 0) {
 			/*
 			 * Simplify by checking tv_sec only. It's enough.
+			 *
 			 * Currently, it's not required to clear the time.
 			 * It's just to know the timer is stopped
 			 * (for debugging).
 			 */
 			sc->sc_linkup_delay_time.tv_sec = 0;
 			sc->sc_linkup_delay_time.tv_usec = 0;
+		}
+	}
 	/*
 	 * Call mii_pollstat().
+	 *
 	 * Some (not all) systems use I35[04] or I21[01] don't send packet soon
 	 * after linkup. The MAC send a packet to the PHY and any error is not
 	 * observed. This behavior causes a problem that gratuitous ARP and/or
 	 * IPv6 DAD packet are silently dropped. To avoid this problem, don't
 	 * call mii_pollstat() here which will send LINK_STATE_UP notification
 	 * to the upper layer. Instead, mii_pollstat() will be called in
 	 * wm_gmii_mediastatus() or mii_tick() will be called in wm_tick().
 	 */
 	if (dopoll)
 		mii_pollstat(&sc->sc_mii);
 	/* Do some workarounds soon after link status is changed. */
 	if (sc->sc_type == WM_T_82543) {
 		int miistatus, active;
 		/*
 		 * With 82543, we need to force speed and
 		 * duplex on the MAC equal to what the PHY
 		 * speed and duplex configuration is.
 		 */
 		miistatus = sc->sc_mii.mii_media_status;
 		if (miistatus & IFM_ACTIVE) {
 			active = sc->sc_mii.mii_media_active;
 			sc->sc_ctrl &= ~(CTRL_SPEED_MASK | CTRL_FD);
 			switch (IFM_SUBTYPE(active)) {
 			case IFM_10_T:
 				sc->sc_ctrl |= CTRL_SPEED_10;
 				break;
 			case IFM_100_TX:
 				sc->sc_ctrl |= CTRL_SPEED_100;
 				break;
 			case IFM_1000_T:
 				sc->sc_ctrl |= CTRL_SPEED_1000;
 				break;
 			default:
 				/*
 				 * Fiber?
 				 * Shoud not enter here.
 				 */
 				device_printf(sc->sc_dev,
 				    "unknown media (%x)\n", active);
 				break;
+			}
 			if (active & IFM_FDX)
 				sc->sc_ctrl |= CTRL_FD;
 			CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
+		}
 	} else if (sc->sc_type == WM_T_PCH) {
 		wm_k1_gig_workaround_hv(sc,
 		    ((sc->sc_mii.mii_media_status & IFM_ACTIVE) != 0));
+	}
 	/*
 	 * I217 Packet Loss issue:
 	 * ensure that FEXTNVM4 Beacon Duration is set correctly
 	 * on power up.
 	 * Set the Beacon Duration for I217 to 8 usec
 	 */
 	if (sc->sc_type >= WM_T_PCH_LPT) {
 		reg = CSR_READ(sc, WMREG_FEXTNVM4);
 		reg &= ~FEXTNVM4_BEACON_DURATION;
 		reg |= FEXTNVM4_BEACON_DURATION_8US;
 		CSR_WRITE(sc, WMREG_FEXTNVM4, reg);
+	}
 	/* Work-around I218 hang issue */
 	if ((sc->sc_pcidevid == PCI_PRODUCT_INTEL_I218_LM) ||
 	    (sc->sc_pcidevid == PCI_PRODUCT_INTEL_I218_V) ||
 	    (sc->sc_pcidevid == PCI_PRODUCT_INTEL_I218_LM3) ||
 	    (sc->sc_pcidevid == PCI_PRODUCT_INTEL_I218_V3))
 		wm_k1_workaround_lpt_lp(sc, link);
 	if (sc->sc_type >= WM_T_PCH_LPT) {
 		/*
 		 * Set platform power management values for Latency
 		 * Tolerance Reporting (LTR)
 		 */
 		wm_platform_pm_pch_lpt(sc,
 		    ((sc->sc_mii.mii_media_status & IFM_ACTIVE) != 0));
+	}
 	/* FEXTNVM6 K1-off workaround */
 	if (sc->sc_type == WM_T_PCH_SPT) {
 		reg = CSR_READ(sc, WMREG_FEXTNVM6);
 		if (CSR_READ(sc, WMREG_PCIEANACFG) & FEXTNVM6_K1_OFF_ENABLE)
 			reg |= FEXTNVM6_K1_OFF_ENABLE;
 		else
 			reg &= ~FEXTNVM6_K1_OFF_ENABLE;
 		CSR_WRITE(sc, WMREG_FEXTNVM6, reg);
+	}
 	if (!link)
 		return;
 	switch (sc->sc_type) {
 	case WM_T_PCH2:
 		wm_k1_workaround_lv(sc);
 		/* FALLTHROUGH */
 	case WM_T_PCH:
 		if (sc->sc_phytype == WMPHY_82578)
 			wm_link_stall_workaround_hv(sc);
 		break;
 	default:
 		break;
+	}
+}
 /*
  * wm_linkintr_tbi:
+ *
  *	Helper; handle link interrupts for TBI mode.
  */
 static void
 wm_linkintr_tbi(struct wm_softc *sc, uint32_t icr)
+{
 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
 	uint32_t status;
 	DPRINTF(sc, WM_DEBUG_LINK, ("%s: %s:\n", device_xname(sc->sc_dev),
 		__func__));
 	status = CSR_READ(sc, WMREG_STATUS);
 	if (icr & ICR_LSC) {
 		wm_check_for_link(sc);
 		if (status & STATUS_LU) {
 			DPRINTF(sc, WM_DEBUG_LINK, ("%s: LINK: LSC -> up %s\n",
 				device_xname(sc->sc_dev),
 				(status & STATUS_FD) ? "FDX" : "HDX"));
 			/*
 			 * NOTE: CTRL will update TFCE and RFCE automatically,
 			 * so we should update sc->sc_ctrl
 			 */
 			sc->sc_ctrl = CSR_READ(sc, WMREG_CTRL);
 			sc->sc_tctl &= ~TCTL_COLD(0x3ff);
 			sc->sc_fcrtl &= ~FCRTL_XONE;
 			if (status & STATUS_FD)
 				sc->sc_tctl |=
 				    TCTL_COLD(TX_COLLISION_DISTANCE_FDX);
 			else
 				sc->sc_tctl |=
 				    TCTL_COLD(TX_COLLISION_DISTANCE_HDX);
 			if (sc->sc_ctrl & CTRL_TFCE)
 				sc->sc_fcrtl |= FCRTL_XONE;
 			CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl);
 			CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ?
 			    WMREG_OLD_FCRTL : WMREG_FCRTL, sc->sc_fcrtl);
 			sc->sc_tbi_linkup = 1;
 			if_link_state_change(ifp, LINK_STATE_UP);
 		} else {
 			DPRINTF(sc, WM_DEBUG_LINK, ("%s: LINK: LSC -> down\n",
 				device_xname(sc->sc_dev)));
 			sc->sc_tbi_linkup = 0;
 			if_link_state_change(ifp, LINK_STATE_DOWN);
+		}
 		/* Update LED */
 		wm_tbi_serdes_set_linkled(sc);
 	} else if (icr & ICR_RXSEQ)
 		DPRINTF(sc, WM_DEBUG_LINK,
 		    ("%s: LINK: Receive sequence error\n",
 			device_xname(sc->sc_dev)));
+}
 /*
  * wm_linkintr_serdes:
+ *
  *	Helper; handle link interrupts for TBI mode.
  */
 static void
 wm_linkintr_serdes(struct wm_softc *sc, uint32_t icr)
+{
 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
 	struct mii_data *mii = &sc->sc_mii;
 	struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
 	uint32_t pcs_adv, pcs_lpab, reg;
 	DPRINTF(sc, WM_DEBUG_LINK, ("%s: %s:\n", device_xname(sc->sc_dev),
 		__func__));
 	if (icr & ICR_LSC) {
 		/* Check PCS */
 		reg = CSR_READ(sc, WMREG_PCS_LSTS);
 		if ((reg & PCS_LSTS_LINKOK) != 0) {
 			DPRINTF(sc, WM_DEBUG_LINK, ("%s: LINK: LSC -> up\n",
 				device_xname(sc->sc_dev)));
 			mii->mii_media_status |= IFM_ACTIVE;
 			sc->sc_tbi_linkup = 1;
 			if_link_state_change(ifp, LINK_STATE_UP);
 		} else {
 			DPRINTF(sc, WM_DEBUG_LINK, ("%s: LINK: LSC -> down\n",
 				device_xname(sc->sc_dev)));
 			mii->mii_media_status |= IFM_NONE;
 			sc->sc_tbi_linkup = 0;
 			if_link_state_change(ifp, LINK_STATE_DOWN);
 			wm_tbi_serdes_set_linkled(sc);
 			return;
+		}
 		mii->mii_media_active |= IFM_1000_SX;
 		if ((reg & PCS_LSTS_FDX) != 0)
 			mii->mii_media_active |= IFM_FDX;
 		else
 			mii->mii_media_active |= IFM_HDX;
 		if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) {
 			/* Check flow */
 			reg = CSR_READ(sc, WMREG_PCS_LSTS);
 			if ((reg & PCS_LSTS_AN_COMP) == 0) {
 				DPRINTF(sc, WM_DEBUG_LINK,
 				    ("XXX LINKOK but not ACOMP\n"));
 				return;
+			}
 			pcs_adv = CSR_READ(sc, WMREG_PCS_ANADV);
 			pcs_lpab = CSR_READ(sc, WMREG_PCS_LPAB);
 			DPRINTF(sc, WM_DEBUG_LINK,
 			    ("XXX AN result %08x, %08x\n", pcs_adv, pcs_lpab));
 			if ((pcs_adv & TXCW_SYM_PAUSE)
 			    && (pcs_lpab & TXCW_SYM_PAUSE)) {
 				mii->mii_media_active |= IFM_FLOW
 				    | IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE;
 			} else if (((pcs_adv & TXCW_SYM_PAUSE) == 0)
 			    && (pcs_adv & TXCW_ASYM_PAUSE)
 			    && (pcs_lpab & TXCW_SYM_PAUSE)
 			    && (pcs_lpab & TXCW_ASYM_PAUSE))
 				mii->mii_media_active |= IFM_FLOW
 				    | IFM_ETH_TXPAUSE;
 			else if ((pcs_adv & TXCW_SYM_PAUSE)
 			    && (pcs_adv & TXCW_ASYM_PAUSE)
 			    && ((pcs_lpab & TXCW_SYM_PAUSE) == 0)
 			    && (pcs_lpab & TXCW_ASYM_PAUSE))
 				mii->mii_media_active |= IFM_FLOW
 				    | IFM_ETH_RXPAUSE;
+		}
 		/* Update LED */
 		wm_tbi_serdes_set_linkled(sc);
 	} else
 		DPRINTF(sc, WM_DEBUG_LINK,
 		    ("%s: LINK: Receive sequence error\n",
 		    device_xname(sc->sc_dev)));
+}
 /*
  * wm_linkintr:
+ *
  *	Helper; handle link interrupts.
  */
 static void
 wm_linkintr(struct wm_softc *sc, uint32_t icr)
+{
 	KASSERT(WM_CORE_LOCKED(sc));
 	if (sc->sc_flags & WM_F_HAS_MII)
 		wm_linkintr_gmii(sc, icr);
 	else if ((sc->sc_mediatype == WM_MEDIATYPE_SERDES)
 	    && ((sc->sc_type >= WM_T_82575) && (sc->sc_type <= WM_T_I211)))
 		wm_linkintr_serdes(sc, icr);
 	else
 		wm_linkintr_tbi(sc, icr);
+}
 static inline void
 wm_sched_handle_queue(struct wm_softc *sc, struct wm_queue *wmq)
+{
 	if (wmq->wmq_txrx_use_workqueue) {
 		if (!wmq->wmq_wq_enqueued) {
 			wmq->wmq_wq_enqueued = true;
 			workqueue_enqueue(sc->sc_queue_wq, &wmq->wmq_cookie,
 			    curcpu());
+		}
 	} else
 		softint_schedule(wmq->wmq_si);
+}
 static inline void
 wm_legacy_intr_disable(struct wm_softc *sc)
+{
 	CSR_WRITE(sc, WMREG_IMC, 0xffffffffU);
+}
 static inline void
 wm_legacy_intr_enable(struct wm_softc *sc)
+{
 	CSR_WRITE(sc, WMREG_IMS, sc->sc_icr);
+}
 /*
  * wm_intr_legacy:
+ *
  *	Interrupt service routine for INTx and MSI.
  */
 static int
 wm_intr_legacy(void *arg)
+{
 	struct wm_softc *sc = arg;
 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
 	struct wm_queue *wmq = &sc->sc_queue[0];
 	struct wm_txqueue *txq = &wmq->wmq_txq;
 	struct wm_rxqueue *rxq = &wmq->wmq_rxq;
 	u_int txlimit = sc->sc_tx_intr_process_limit;
 	u_int rxlimit = sc->sc_rx_intr_process_limit;
 	uint32_t icr, rndval = 0;
 	bool more = false;
 	icr = CSR_READ(sc, WMREG_ICR);
 	if ((icr & sc->sc_icr) == 0)
 		return 0;
 	DPRINTF(sc, WM_DEBUG_TX,
 	    ("%s: INTx: got intr\n",device_xname(sc->sc_dev)));
 	if (rndval == 0)
 		rndval = icr;
 	mutex_enter(txq->txq_lock);
 	if (txq->txq_stopping) {
 		mutex_exit(txq->txq_lock);
 		return 1;
+	}
 #if defined(WM_DEBUG) || defined(WM_EVENT_COUNTERS)
 	if (icr & ICR_TXDW) {
 		DPRINTF(sc, WM_DEBUG_TX,
 		    ("%s: TX: got TXDW interrupt\n",
 			device_xname(sc->sc_dev)));
 		WM_Q_EVCNT_INCR(txq, txdw);
+	}
 #endif
 	if (txlimit > 0) {
 		more |= wm_txeof(txq, txlimit);
 		if (!IF_IS_EMPTY(&ifp->if_snd))
 			more = true;
 	} else
 		more = true;
 	mutex_exit(txq->txq_lock);
 	mutex_enter(rxq->rxq_lock);
 	if (rxq->rxq_stopping) {
 		mutex_exit(rxq->rxq_lock);
 		return 1;
+	}
 #if defined(WM_DEBUG) || defined(WM_EVENT_COUNTERS)
 	if (icr & (ICR_RXDMT0 | ICR_RXT0)) {
 		DPRINTF(sc, WM_DEBUG_RX,
 		    ("%s: RX: got Rx intr %#" __PRIxBIT "\n",
 			device_xname(sc->sc_dev),
 			icr & (ICR_RXDMT0 | ICR_RXT0)));
 		WM_Q_EVCNT_INCR(rxq, intr);
+	}
 #endif
 	if (rxlimit > 0) {
 		/*
 		 * wm_rxeof() does *not* call upper layer functions directly,
 		 * as if_percpuq_enqueue() just call softint_schedule().
 		 * So, we can call wm_rxeof() in interrupt context.
 		 */
 		more = wm_rxeof(rxq, rxlimit);
 	} else
 		more = true;
 	/* Fill lower bits with RX index. See below for the upper. */
 	rndval |= rxq->rxq_ptr & WM_NRXDESC_MASK;
 	mutex_exit(rxq->rxq_lock);
 	WM_CORE_LOCK(sc);
 	if (sc->sc_core_stopping) {
 		WM_CORE_UNLOCK(sc);
 		return 1;
+	}
 	if (icr & (ICR_LSC | ICR_RXSEQ)) {
 		WM_EVCNT_INCR(&sc->sc_ev_linkintr);
 		wm_linkintr(sc, icr);
+	}
 	if ((icr & ICR_GPI(0)) != 0)
 		device_printf(sc->sc_dev, "got module interrupt\n");
 	WM_CORE_UNLOCK(sc);
 	if (icr & ICR_RXO) {
 #if defined(WM_DEBUG)
 		log(LOG_WARNING, "%s: Receive overrun\n",
 		    device_xname(sc->sc_dev));
 #endif /* defined(WM_DEBUG) */
+	}
 	rnd_add_uint32(&sc->sc_queue[0].rnd_source, rndval);
 	if (more) {
 		/* Try to get more packets going. */
 		wm_legacy_intr_disable(sc);
 		wmq->wmq_txrx_use_workqueue = sc->sc_txrx_use_workqueue;
 		wm_sched_handle_queue(sc, wmq);
+	}
 	return 1;
+}
 static inline void
 wm_txrxintr_disable(struct wm_queue *wmq)
+{
 	struct wm_softc *sc = wmq->wmq_txq.txq_sc;
 	if (__predict_false(!wm_is_using_msix(sc))) {
 		wm_legacy_intr_disable(sc);
 		return;
+	}
 	if (sc->sc_type == WM_T_82574)
 		CSR_WRITE(sc, WMREG_IMC,
 		    ICR_TXQ(wmq->wmq_id) | ICR_RXQ(wmq->wmq_id));
 	else if (sc->sc_type == WM_T_82575)
 		CSR_WRITE(sc, WMREG_EIMC,
 		    EITR_TX_QUEUE(wmq->wmq_id) | EITR_RX_QUEUE(wmq->wmq_id));
 	else
 		CSR_WRITE(sc, WMREG_EIMC, 1 << wmq->wmq_intr_idx);
+}
 static inline void
 wm_txrxintr_enable(struct wm_queue *wmq)
+{
 	struct wm_softc *sc = wmq->wmq_txq.txq_sc;
 	wm_itrs_calculate(sc, wmq);
 	if (__predict_false(!wm_is_using_msix(sc))) {
 		wm_legacy_intr_enable(sc);
 		return;
+	}
 	/*
 	 * ICR_OTHER which is disabled in wm_linkintr_msix() is enabled here.
 	 * There is no need to care about which of RXQ(0) and RXQ(1) enable
 	 * ICR_OTHER in first, because each RXQ/TXQ interrupt is disabled
 	 * while each wm_handle_queue(wmq) is runnig.
 	 */
 	if (sc->sc_type == WM_T_82574)
 		CSR_WRITE(sc, WMREG_IMS,
 		    ICR_TXQ(wmq->wmq_id) | ICR_RXQ(wmq->wmq_id) | ICR_OTHER);
 	else if (sc->sc_type == WM_T_82575)
 		CSR_WRITE(sc, WMREG_EIMS,
 		    EITR_TX_QUEUE(wmq->wmq_id) | EITR_RX_QUEUE(wmq->wmq_id));
 	else
 		CSR_WRITE(sc, WMREG_EIMS, 1 << wmq->wmq_intr_idx);
+}
 static int
 wm_txrxintr_msix(void *arg)
+{
 	struct wm_queue *wmq = arg;
 	struct wm_txqueue *txq = &wmq->wmq_txq;
 	struct wm_rxqueue *rxq = &wmq->wmq_rxq;
 	struct wm_softc *sc = txq->txq_sc;
 	u_int txlimit = sc->sc_tx_intr_process_limit;
 	u_int rxlimit = sc->sc_rx_intr_process_limit;
 	uint32_t rndval = 0;
 	bool txmore;
 	bool rxmore;
 	KASSERT(wmq->wmq_intr_idx == wmq->wmq_id);
 	DPRINTF(sc, WM_DEBUG_TX,
 	    ("%s: TX: got Tx intr\n", device_xname(sc->sc_dev)));
 	wm_txrxintr_disable(wmq);
 	mutex_enter(txq->txq_lock);
 	if (txq->txq_stopping) {
 		mutex_exit(txq->txq_lock);
 		return 1;
+	}
 	WM_Q_EVCNT_INCR(txq, txdw);
 	/* Fill upper bits with TX index. See below for the lower. */
 	rndval = txq->txq_next * WM_NRXDESC;
 	if (txlimit > 0) {
 		txmore = wm_txeof(txq, txlimit);
 		/* wm_deferred start() is done in wm_handle_queue(). */
 	} else
 		txmore = true;
 	mutex_exit(txq->txq_lock);
 	DPRINTF(sc, WM_DEBUG_RX,
 	    ("%s: RX: got Rx intr\n", device_xname(sc->sc_dev)));
 	mutex_enter(rxq->rxq_lock);
 	if (rxq->rxq_stopping) {
 		mutex_exit(rxq->rxq_lock);
 		return 1;
+	}
 	WM_Q_EVCNT_INCR(rxq, intr);
 	if (rxlimit > 0) {
 		rxmore = wm_rxeof(rxq, rxlimit);
 	} else
 		rxmore = true;
 	/* Fill lower bits with RX index. See above for the upper. */
 	rndval |= rxq->rxq_ptr & WM_NRXDESC_MASK;
 	mutex_exit(rxq->rxq_lock);
 	wm_itrs_writereg(sc, wmq);
 	/*
 	 * This function is called in the hardware interrupt context and
 	 * per-CPU, so it's not required to take a lock.
 	 */
 	if (rndval != 0)
 		rnd_add_uint32(&sc->sc_queue[wmq->wmq_id].rnd_source, rndval);
 	if (txmore || rxmore) {
 		wmq->wmq_txrx_use_workqueue = sc->sc_txrx_use_workqueue;
 		wm_sched_handle_queue(sc, wmq);
 	} else
 		wm_txrxintr_enable(wmq);
 	return 1;
+}
 static void
 wm_handle_queue(void *arg)
+{
 	struct wm_queue *wmq = arg;
 	struct wm_txqueue *txq = &wmq->wmq_txq;
 	struct wm_rxqueue *rxq = &wmq->wmq_rxq;
 	struct wm_softc *sc = txq->txq_sc;
 	u_int txlimit = sc->sc_tx_process_limit;
 	u_int rxlimit = sc->sc_rx_process_limit;
 	bool txmore;
 	bool rxmore;
 	mutex_enter(txq->txq_lock);
 	if (txq->txq_stopping) {
 		mutex_exit(txq->txq_lock);
 		return;
+	}
 	txmore = wm_txeof(txq, txlimit);
 	wm_deferred_start_locked(txq);
 	mutex_exit(txq->txq_lock);
 	mutex_enter(rxq->rxq_lock);
 	if (rxq->rxq_stopping) {
 		mutex_exit(rxq->rxq_lock);
 		return;
+	}
 	WM_Q_EVCNT_INCR(rxq, defer);
 	rxmore = wm_rxeof(rxq, rxlimit);
 	mutex_exit(rxq->rxq_lock);
 	if (txmore || rxmore) {
 		wmq->wmq_txrx_use_workqueue = sc->sc_txrx_use_workqueue;
 		wm_sched_handle_queue(sc, wmq);
 	} else
 		wm_txrxintr_enable(wmq);
+}
 static void
 wm_handle_queue_work(struct work *wk, void *context)
+{
 	struct wm_queue *wmq = container_of(wk, struct wm_queue, wmq_cookie);
 	/*
 	 * Some qemu environment workaround.  They don't stop interrupt
 	 * immediately.
 	 */
 	wmq->wmq_wq_enqueued = false;
 	wm_handle_queue(wmq);
+}
 /*
  * wm_linkintr_msix:
+ *
  *	Interrupt service routine for link status change for MSI-X.
  */
 static int
 wm_linkintr_msix(void *arg)
+{
 	struct wm_softc *sc = arg;
 	uint32_t reg;
 	bool has_rxo;
 	reg = CSR_READ(sc, WMREG_ICR);
 	WM_CORE_LOCK(sc);
 	DPRINTF(sc, WM_DEBUG_LINK,
 	    ("%s: LINK: got link intr. ICR = %08x\n",
 		device_xname(sc->sc_dev), reg));
 	if (sc->sc_core_stopping)
 		goto out;
 	if ((reg & ICR_LSC) != 0) {
 		WM_EVCNT_INCR(&sc->sc_ev_linkintr);
 		wm_linkintr(sc, ICR_LSC);
+	}
 	if ((reg & ICR_GPI(0)) != 0)
 		device_printf(sc->sc_dev, "got module interrupt\n");
 	/*
 	 * XXX 82574 MSI-X mode workaround
+	 *
-	 * 82574 MSI-X mode causes receive overrun(RXO) interrupt as ICR_OTHER
+	 * 82574 MSI-X mode causes a receive overrun(RXO) interrupt as an
-	 * MSI-X vector, furthermore it does not cause neigher ICR_RXQ(0) nor
+	 * ICR_OTHER MSI-X vector; furthermore it causes neither ICR_RXQ(0)
-	 * ICR_RXQ(1) vector. So, we generate ICR_RXQ(0) and ICR_RXQ(1)
+	 * nor ICR_RXQ(1) vectors. So, we generate ICR_RXQ(0) and ICR_RXQ(1)
 	 * interrupts by writing WMREG_ICS to process receive packets.
 	 */
 	if (sc->sc_type == WM_T_82574 && ((reg & ICR_RXO) != 0)) {
 #if defined(WM_DEBUG)
 		log(LOG_WARNING, "%s: Receive overrun\n",
 		    device_xname(sc->sc_dev));
 #endif /* defined(WM_DEBUG) */
 		has_rxo = true;
 		/*
 		 * The RXO interrupt is very high rate when receive traffic is
 		 * high rate. We use polling mode for ICR_OTHER like Tx/Rx
 		 * interrupts. ICR_OTHER will be enabled at the end of
 		 * wm_txrxintr_msix() which is kicked by both ICR_RXQ(0) and
 		 * ICR_RXQ(1) interrupts.
 		 */
 		CSR_WRITE(sc, WMREG_IMC, ICR_OTHER);
 		CSR_WRITE(sc, WMREG_ICS, ICR_RXQ(0) | ICR_RXQ(1));
+	}
 out:
 	WM_CORE_UNLOCK(sc);
 	if (sc->sc_type == WM_T_82574) {
 		if (!has_rxo)
 			CSR_WRITE(sc, WMREG_IMS, ICR_OTHER | ICR_LSC);
 		else
 			CSR_WRITE(sc, WMREG_IMS, ICR_LSC);
 	} else if (sc->sc_type == WM_T_82575)
 		CSR_WRITE(sc, WMREG_EIMS, EITR_OTHER);
 	else
 		CSR_WRITE(sc, WMREG_EIMS, 1 << sc->sc_link_intr_idx);
 	return 1;
+}
 /*
  * Media related.
  * GMII, SGMII, TBI (and SERDES)
  */
 /* Common */
 /*
  * wm_tbi_serdes_set_linkled:
+ *
  *	Update the link LED on TBI and SERDES devices.
  */
 static void
 wm_tbi_serdes_set_linkled(struct wm_softc *sc)
+{
 	if (sc->sc_tbi_linkup)
 		sc->sc_ctrl |= CTRL_SWDPIN(0);
 	else
 		sc->sc_ctrl &= ~CTRL_SWDPIN(0);
 	/* 82540 or newer devices are active low */
 	sc->sc_ctrl ^= (sc->sc_type >= WM_T_82540) ? CTRL_SWDPIN(0) : 0;
 	CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
+}
 /* GMII related */
 /*
  * wm_gmii_reset:
+ *
  *	Reset the PHY.
  */
 static void
 wm_gmii_reset(struct wm_softc *sc)
+{
 	uint32_t reg;
 	int rv;
 	DPRINTF(sc, WM_DEBUG_INIT, ("%s: %s called\n",
 		device_xname(sc->sc_dev), __func__));
 	rv = sc->phy.acquire(sc);
 	if (rv != 0) {
 		aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n",
 		    __func__);
 		return;
+	}
 	switch (sc->sc_type) {
 	case WM_T_82542_2_0:
 	case WM_T_82542_2_1:
 		/* null */
 		break;
 	case WM_T_82543:
 		/*
 		 * With 82543, we need to force speed and duplex on the MAC
 		 * equal to what the PHY speed and duplex configuration is.
 		 * In addition, we need to perform a hardware reset on the PHY
 		 * to take it out of reset.
 		 */
 		sc->sc_ctrl |= CTRL_FRCSPD | CTRL_FRCFDX;
 		CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
 		/* The PHY reset pin is active-low. */
 		reg = CSR_READ(sc, WMREG_CTRL_EXT);
 		reg &= ~((CTRL_EXT_SWDPIO_MASK << CTRL_EXT_SWDPIO_SHIFT) |
 		    CTRL_EXT_SWDPIN(4));
 		reg |= CTRL_EXT_SWDPIO(4);
 		CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
 		CSR_WRITE_FLUSH(sc);
 		delay(10*1000);
 		CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_SWDPIN(4));
 		CSR_WRITE_FLUSH(sc);
 		delay(150);
 #if 0
 		sc->sc_ctrl_ext = reg | CTRL_EXT_SWDPIN(4);
 #endif
 		delay(20*1000);	/* XXX extra delay to get PHY ID? */
 		break;
 	case WM_T_82544:	/* Reset 10000us */
 	case WM_T_82540:
 	case WM_T_82545:
 	case WM_T_82545_3:
 	case WM_T_82546:
 	case WM_T_82546_3:
 	case WM_T_82541:
 	case WM_T_82541_2:
 	case WM_T_82547:
 	case WM_T_82547_2:
 	case WM_T_82571:	/* Reset 100us */
 	case WM_T_82572:
 	case WM_T_82573:
 	case WM_T_82574:
 	case WM_T_82575:
 	case WM_T_82576:
 	case WM_T_82580:
 	case WM_T_I350:
 	case WM_T_I354:
 	case WM_T_I210:
 	case WM_T_I211:
 	case WM_T_82583:
 	case WM_T_80003:
 		/* Generic reset */
 		CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl | CTRL_PHY_RESET);
 		CSR_WRITE_FLUSH(sc);
 		delay(20000);
 		CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
 		CSR_WRITE_FLUSH(sc);
 		delay(20000);
 		if ((sc->sc_type == WM_T_82541)
 		    || (sc->sc_type == WM_T_82541_2)
 		    || (sc->sc_type == WM_T_82547)
 		    || (sc->sc_type == WM_T_82547_2)) {
 			/* Workaround for igp are done in igp_reset() */
 			/* XXX add code to set LED after phy reset */
+		}
 		break;
 	case WM_T_ICH8:
 	case WM_T_ICH9:
 	case WM_T_ICH10:
 	case WM_T_PCH:
 	case WM_T_PCH2:
 	case WM_T_PCH_LPT:
 	case WM_T_PCH_SPT:
 	case WM_T_PCH_CNP:
 	case WM_T_PCH_TGP:
 		/* Generic reset */
 		CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl | CTRL_PHY_RESET);
 		CSR_WRITE_FLUSH(sc);
 		delay(100);
 		CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
 		CSR_WRITE_FLUSH(sc);
 		delay(150);
 		break;
 	default:
 		panic("%s: %s: unknown type\n", device_xname(sc->sc_dev),
 		    __func__);
 		break;
+	}
 	sc->phy.release(sc);
 	/* get_cfg_done */
 	wm_get_cfg_done(sc);
 	/* Extra setup */
 	switch (sc->sc_type) {
 	case WM_T_82542_2_0:
 	case WM_T_82542_2_1:
 	case WM_T_82543:
 	case WM_T_82544:
 	case WM_T_82540:
 	case WM_T_82545:
 	case WM_T_82545_3:
 	case WM_T_82546:
 	case WM_T_82546_3:
 	case WM_T_82541_2:
 	case WM_T_82547_2:
 	case WM_T_82571:
 	case WM_T_82572:
 	case WM_T_82573:
 	case WM_T_82574:
 	case WM_T_82583:
 	case WM_T_82575:
 	case WM_T_82576:
 	case WM_T_82580:
 	case WM_T_I350:
 	case WM_T_I354:
 	case WM_T_I210:
 	case WM_T_I211:
 	case WM_T_80003:
 		/* Null */
 		break;
 	case WM_T_82541:
 	case WM_T_82547:
 		/* XXX Configure actively LED after PHY reset */
 		break;
 	case WM_T_ICH8:
 	case WM_T_ICH9:
 	case WM_T_ICH10:
 	case WM_T_PCH:
 	case WM_T_PCH2:
 	case WM_T_PCH_LPT:
 	case WM_T_PCH_SPT:
 	case WM_T_PCH_CNP:
 	case WM_T_PCH_TGP:
 		wm_phy_post_reset(sc);
 		break;
 	default:
 		panic("%s: unknown type\n", __func__);
 		break;
+	}
+}
 /*
  * Set up sc_phytype and mii_{read|write}reg.
+ *
  *  To identify PHY type, correct read/write function should be selected.
  * To select correct read/write function, PCI ID or MAC type are required
  * without accessing PHY registers.
+ *
  *  On the first call of this function, PHY ID is not known yet. Check
  * PCI ID or MAC type. The list of the PCI ID may not be perfect, so the
  * result might be incorrect.
+ *
  *  In the second call, PHY OUI and model is used to identify PHY type.
  * It might not be perfect because of the lack of compared entry, but it
  * would be better than the first call.
+ *
  *  If the detected new result and previous assumption is different,
  * a diagnostic message will be printed.
  */
 static void
 wm_gmii_setup_phytype(struct wm_softc *sc, uint32_t phy_oui,
     uint16_t phy_model)
+{
 	device_t dev = sc->sc_dev;
 	struct mii_data *mii = &sc->sc_mii;
 	uint16_t new_phytype = WMPHY_UNKNOWN;
 	uint16_t doubt_phytype = WMPHY_UNKNOWN;
 	mii_readreg_t new_readreg;
 	mii_writereg_t new_writereg;
 	bool dodiag = true;
 	DPRINTF(sc, WM_DEBUG_INIT, ("%s: %s called\n",
 		device_xname(sc->sc_dev), __func__));
 	/*
 	 * 1000BASE-T SFP uses SGMII and the first asumed PHY type is always
 	 * incorrect. So don't print diag output when it's 2nd call.
 	 */
 	if ((sc->sc_sfptype != 0) && (phy_oui == 0) && (phy_model == 0))
 		dodiag = false;
 	if (mii->mii_readreg == NULL) {
 		/*
 		 *  This is the first call of this function. For ICH and PCH
 		 * variants, it's difficult to determine the PHY access method
 		 * by sc_type, so use the PCI product ID for some devices.
 		 */
 		switch (sc->sc_pcidevid) {
 		case PCI_PRODUCT_INTEL_PCH_M_LM:
 		case PCI_PRODUCT_INTEL_PCH_M_LC:
 			/* 82577 */
 			new_phytype = WMPHY_82577;
 			break;
 		case PCI_PRODUCT_INTEL_PCH_D_DM:
 		case PCI_PRODUCT_INTEL_PCH_D_DC:
 			/* 82578 */
 			new_phytype = WMPHY_82578;
 			break;
 		case PCI_PRODUCT_INTEL_PCH2_LV_LM:
 		case PCI_PRODUCT_INTEL_PCH2_LV_V:
 			/* 82579 */
 			new_phytype = WMPHY_82579;
 			break;
 		case PCI_PRODUCT_INTEL_82801H_82567V_3:
 		case PCI_PRODUCT_INTEL_82801I_BM:
 		case PCI_PRODUCT_INTEL_82801I_IGP_M_AMT: /* Not IGP but BM */
 		case PCI_PRODUCT_INTEL_82801J_R_BM_LM:
 		case PCI_PRODUCT_INTEL_82801J_R_BM_LF:
 		case PCI_PRODUCT_INTEL_82801J_D_BM_LM:
 		case PCI_PRODUCT_INTEL_82801J_D_BM_LF:
 		case PCI_PRODUCT_INTEL_82801J_R_BM_V:
 			/* ICH8, 9, 10 with 82567 */
 			new_phytype = WMPHY_BM;
 			break;
 		default:
 			break;
+		}
 	} else {
 		/* It's not the first call. Use PHY OUI and model */
 		switch (phy_oui) {
 		case MII_OUI_ATTANSIC: /* atphy(4) */
 			switch (phy_model) {
 			case MII_MODEL_ATTANSIC_AR8021:
 				new_phytype = WMPHY_82578;
 				break;
 			default:
 				break;
+			}
 			break;
 		case MII_OUI_xxMARVELL:
 			switch (phy_model) {
 			case MII_MODEL_xxMARVELL_I210:
 				new_phytype = WMPHY_I210;
 				break;
 			case MII_MODEL_xxMARVELL_E1011:
 			case MII_MODEL_xxMARVELL_E1000_3:
 			case MII_MODEL_xxMARVELL_E1000_5:
 			case MII_MODEL_xxMARVELL_E1112:
 				new_phytype = WMPHY_M88;
 				break;
 			case MII_MODEL_xxMARVELL_E1149:
 				new_phytype = WMPHY_BM;
 				break;
 			case MII_MODEL_xxMARVELL_E1111:
 			case MII_MODEL_xxMARVELL_I347:
 			case MII_MODEL_xxMARVELL_E1512:
 			case MII_MODEL_xxMARVELL_E1340M:
 			case MII_MODEL_xxMARVELL_E1543:
 				new_phytype = WMPHY_M88;
 				break;
 			case MII_MODEL_xxMARVELL_I82563:
 				new_phytype = WMPHY_GG82563;
 				break;
 			default:
 				break;
+			}
 			break;
 		case MII_OUI_INTEL:
 			switch (phy_model) {
 			case MII_MODEL_INTEL_I82577:
 				new_phytype = WMPHY_82577;
 				break;
 			case MII_MODEL_INTEL_I82579:
 				new_phytype = WMPHY_82579;
 				break;
 			case MII_MODEL_INTEL_I217:
 				new_phytype = WMPHY_I217;
 				break;
 			case MII_MODEL_INTEL_I82580:
 				new_phytype = WMPHY_82580;
 				break;
 			case MII_MODEL_INTEL_I350:
 				new_phytype = WMPHY_I350;
 				break;
 			default:
 				break;
+			}
 			break;
 		case MII_OUI_yyINTEL:
 			switch (phy_model) {
 			case MII_MODEL_yyINTEL_I82562G:
 			case MII_MODEL_yyINTEL_I82562EM:
 			case MII_MODEL_yyINTEL_I82562ET:
 				new_phytype = WMPHY_IFE;
 				break;
 			case MII_MODEL_yyINTEL_IGP01E1000:
 				new_phytype = WMPHY_IGP;
 				break;
 			case MII_MODEL_yyINTEL_I82566:
 				new_phytype = WMPHY_IGP_3;
 				break;
 			default:
 				break;
+			}
 			break;
 		default:
 			break;
+		}
 		if (dodiag) {
 			if (new_phytype == WMPHY_UNKNOWN)
 				aprint_verbose_dev(dev,
 				    "%s: Unknown PHY model. OUI=%06x, "
 				    "model=%04x\n", __func__, phy_oui,
 				    phy_model);
 			if ((sc->sc_phytype != WMPHY_UNKNOWN)
 			    && (sc->sc_phytype != new_phytype)) {
 				aprint_error_dev(dev, "Previously assumed PHY "
 				    "type(%u) was incorrect. PHY type from PHY"
 				    "ID = %u\n", sc->sc_phytype, new_phytype);
+			}
+		}
+	}
 	/* Next, use sc->sc_flags and sc->sc_type to set read/write funcs. */
 	if (((sc->sc_flags & WM_F_SGMII) != 0) && !wm_sgmii_uses_mdio(sc)) {
 		/* SGMII */
 		new_readreg = wm_sgmii_readreg;
 		new_writereg = wm_sgmii_writereg;
 	} else if ((sc->sc_type == WM_T_82574) || (sc->sc_type == WM_T_82583)){
 		/* BM2 (phyaddr == 1) */
 		if ((sc->sc_phytype != WMPHY_UNKNOWN)
 		    && (new_phytype != WMPHY_BM)
 		    && (new_phytype != WMPHY_UNKNOWN))
 			doubt_phytype = new_phytype;
 		new_phytype = WMPHY_BM;
 		new_readreg = wm_gmii_bm_readreg;
 		new_writereg = wm_gmii_bm_writereg;
 	} else if (sc->sc_type >= WM_T_PCH) {
 		/* All PCH* use _hv_ */
 		new_readreg = wm_gmii_hv_readreg;
 		new_writereg = wm_gmii_hv_writereg;
 	} else if (sc->sc_type >= WM_T_ICH8) {
 		/* non-82567 ICH8, 9 and 10 */
 		new_readreg = wm_gmii_i82544_readreg;
 		new_writereg = wm_gmii_i82544_writereg;
 	} else if (sc->sc_type >= WM_T_80003) {
 		/* 80003 */
 		if ((sc->sc_phytype != WMPHY_UNKNOWN)
 		    && (new_phytype != WMPHY_GG82563)
 		    && (new_phytype != WMPHY_UNKNOWN))
 			doubt_phytype = new_phytype;
 		new_phytype = WMPHY_GG82563;
 		new_readreg = wm_gmii_i80003_readreg;
 		new_writereg = wm_gmii_i80003_writereg;
 	} else if (sc->sc_type >= WM_T_I210) {
 		/* I210 and I211 */
 		if ((sc->sc_phytype != WMPHY_UNKNOWN)
 		    && (new_phytype != WMPHY_I210)
 		    && (new_phytype != WMPHY_UNKNOWN))
 			doubt_phytype = new_phytype;
 		new_phytype = WMPHY_I210;
 		new_readreg = wm_gmii_gs40g_readreg;
 		new_writereg = wm_gmii_gs40g_writereg;
 	} else if (sc->sc_type >= WM_T_82580) {
 		/* 82580, I350 and I354 */
 		new_readreg = wm_gmii_82580_readreg;
 		new_writereg = wm_gmii_82580_writereg;
 	} else if (sc->sc_type >= WM_T_82544) {
 		/* 82544, 0, [56], [17], 8257[1234] and 82583 */
 		new_readreg = wm_gmii_i82544_readreg;
 		new_writereg = wm_gmii_i82544_writereg;
 	} else {
 		new_readreg = wm_gmii_i82543_readreg;
 		new_writereg = wm_gmii_i82543_writereg;
+	}
 	if (new_phytype == WMPHY_BM) {
 		/* All BM use _bm_ */
 		new_readreg = wm_gmii_bm_readreg;
 		new_writereg = wm_gmii_bm_writereg;
+	}
 	if ((sc->sc_type >= WM_T_PCH) && (sc->sc_type <= WM_T_PCH_TGP)) {
 		/* All PCH* use _hv_ */
 		new_readreg = wm_gmii_hv_readreg;
 		new_writereg = wm_gmii_hv_writereg;
+	}
 	/* Diag output */
 	if (dodiag) {
 		if (doubt_phytype != WMPHY_UNKNOWN)
 			aprint_error_dev(dev, "Assumed new PHY type was "
 			    "incorrect. old = %u, new = %u\n", sc->sc_phytype,
 			    new_phytype);
 		else if ((sc->sc_phytype != WMPHY_UNKNOWN)
 		    && (sc->sc_phytype != new_phytype))
 			aprint_error_dev(dev, "Previously assumed PHY type(%u)"
 			    "was incorrect. New PHY type = %u\n",
 			    sc->sc_phytype, new_phytype);
 		if ((mii->mii_readreg != NULL) &&
 		    (new_phytype == WMPHY_UNKNOWN))
 			aprint_error_dev(dev, "PHY type is still unknown.\n");
 		if ((mii->mii_readreg != NULL) &&
 		    (mii->mii_readreg != new_readreg))
 			aprint_error_dev(dev, "Previously assumed PHY "
 			    "read/write function was incorrect.\n");
+	}
 	/* Update now */
 	sc->sc_phytype = new_phytype;
 	mii->mii_readreg = new_readreg;
 	mii->mii_writereg = new_writereg;
 	if (new_readreg == wm_gmii_hv_readreg) {
 		sc->phy.readreg_locked = wm_gmii_hv_readreg_locked;
 		sc->phy.writereg_locked = wm_gmii_hv_writereg_locked;
 	} else if (new_readreg == wm_gmii_i82544_readreg) {
 		sc->phy.readreg_locked = wm_gmii_i82544_readreg_locked;
 		sc->phy.writereg_locked = wm_gmii_i82544_writereg_locked;
+	}
+}
 /*
  * wm_get_phy_id_82575:
+ *
  * Return PHY ID. Return -1 if it failed.
  */
 static int
 wm_get_phy_id_82575(struct wm_softc *sc)
+{
 	uint32_t reg;
 	int phyid = -1;
 	/* XXX */
 	if ((sc->sc_flags & WM_F_SGMII) == 0)
 		return -1;
 	if (wm_sgmii_uses_mdio(sc)) {
 		switch (sc->sc_type) {
 		case WM_T_82575:
 		case WM_T_82576:
 			reg = CSR_READ(sc, WMREG_MDIC);
 			phyid = (reg & MDIC_PHY_MASK) >> MDIC_PHY_SHIFT;
 			break;
 		case WM_T_82580:
 		case WM_T_I350:
 		case WM_T_I354:
 		case WM_T_I210:
 		case WM_T_I211:
 			reg = CSR_READ(sc, WMREG_MDICNFG);
 			phyid = (reg & MDICNFG_PHY_MASK) >> MDICNFG_PHY_SHIFT;
 			break;
 		default:
 			return -1;
+		}
+	}
 	return phyid;
+}
 /*
  * wm_gmii_mediainit:
+ *
  *	Initialize media for use on 1000BASE-T devices.
  */
 static void
 wm_gmii_mediainit(struct wm_softc *sc, pci_product_id_t prodid)
+{
 	device_t dev = sc->sc_dev;
 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
 	struct mii_data *mii = &sc->sc_mii;
 	DPRINTF(sc, WM_DEBUG_GMII, ("%s: %s called\n",
 		device_xname(sc->sc_dev), __func__));
 	/* We have GMII. */
 	sc->sc_flags |= WM_F_HAS_MII;
 	if (sc->sc_type == WM_T_80003)
 		sc->sc_tipg =  TIPG_1000T_80003_DFLT;
 	else
 		sc->sc_tipg = TIPG_1000T_DFLT;
 	/*
 	 * Let the chip set speed/duplex on its own based on
 	 * signals from the PHY.
 	 * XXXbouyer - I'm not sure this is right for the 80003,
 	 * the em driver only sets CTRL_SLU here - but it seems to work.
 	 */
 	sc->sc_ctrl |= CTRL_SLU;
 	CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
 	/* Initialize our media structures and probe the GMII. */
 	mii->mii_ifp = ifp;
 	mii->mii_statchg = wm_gmii_statchg;
 	/* get PHY control from SMBus to PCIe */
 	if ((sc->sc_type == WM_T_PCH) || (sc->sc_type == WM_T_PCH2)
 	    || (sc->sc_type == WM_T_PCH_LPT) || (sc->sc_type == WM_T_PCH_SPT)
 	    || (sc->sc_type == WM_T_PCH_CNP) || (sc->sc_type == WM_T_PCH_TGP))
 		wm_init_phy_workarounds_pchlan(sc);
 	wm_gmii_reset(sc);
 	sc->sc_ethercom.ec_mii = &sc->sc_mii;
 	ifmedia_init(&mii->mii_media, IFM_IMASK, wm_gmii_mediachange,
 	    wm_gmii_mediastatus);
 	/* Setup internal SGMII PHY for SFP */
 	wm_sgmii_sfp_preconfig(sc);
 	if ((sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576)
 	    || (sc->sc_type == WM_T_82580)
 	    || (sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354)
 	    || (sc->sc_type == WM_T_I210) || (sc->sc_type == WM_T_I211)) {
 		if ((sc->sc_flags & WM_F_SGMII) == 0) {
 			/* Attach only one port */
 			mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, 1,
 			    MII_OFFSET_ANY, MIIF_DOPAUSE);
 		} else {
 			int i, id;
 			uint32_t ctrl_ext;
 			id = wm_get_phy_id_82575(sc);
 			if (id != -1) {
 				mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff,
 				    id, MII_OFFSET_ANY, MIIF_DOPAUSE);
+			}
 			if ((id == -1)
 			    || (LIST_FIRST(&mii->mii_phys) == NULL)) {
 				/* Power on sgmii phy if it is disabled */
 				ctrl_ext = CSR_READ(sc, WMREG_CTRL_EXT);
 				CSR_WRITE(sc, WMREG_CTRL_EXT,
 				    ctrl_ext &~ CTRL_EXT_SWDPIN(3));
 				CSR_WRITE_FLUSH(sc);
 				delay(300*1000); /* XXX too long */
 				/*
 				 * From 1 to 8.
+				 *
 				 * I2C access fails with I2C register's ERROR
 				 * bit set, so prevent error message while
 				 * scanning.
 				 */
 				sc->phy.no_errprint = true;
 				for (i = 1; i < 8; i++)
 					mii_attach(sc->sc_dev, &sc->sc_mii,
 xffffffff, i, MII_OFFSET_ANY,
 					    MIIF_DOPAUSE);
 				sc->phy.no_errprint = false;
 				/* Restore previous sfp cage power state */
 				CSR_WRITE(sc, WMREG_CTRL_EXT, ctrl_ext);
+			}
+		}
 	} else
 		mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY,
 		    MII_OFFSET_ANY, MIIF_DOPAUSE);
 	/*
 	 * If the MAC is PCH2 or PCH_LPT and failed to detect MII PHY, call
 	 * wm_set_mdio_slow_mode_hv() for a workaround and retry.
 	 */
 	if (((sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT) ||
 		(sc->sc_type == WM_T_PCH_SPT) || (sc->sc_type == WM_T_PCH_CNP)
 		|| (sc->sc_type == WM_T_PCH_TGP))
 	    && (LIST_FIRST(&mii->mii_phys) == NULL)) {
 		wm_set_mdio_slow_mode_hv(sc);
 		mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY,
 		    MII_OFFSET_ANY, MIIF_DOPAUSE);
+	}
 	/*
 	 * (For ICH8 variants)
 	 * If PHY detection failed, use BM's r/w function and retry.
 	 */
 	if (LIST_FIRST(&mii->mii_phys) == NULL) {
 		/* if failed, retry with *_bm_* */
 		aprint_verbose_dev(dev, "Assumed PHY access function "
 		    "(type = %d) might be incorrect. Use BM and retry.\n",
 		    sc->sc_phytype);
 		sc->sc_phytype = WMPHY_BM;
 		mii->mii_readreg = wm_gmii_bm_readreg;
 		mii->mii_writereg = wm_gmii_bm_writereg;
 		mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY,
 		    MII_OFFSET_ANY, MIIF_DOPAUSE);
+	}
 	if (LIST_FIRST(&mii->mii_phys) == NULL) {
 		/* Any PHY wasn't found */
 		ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL);
 		ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE);
 		sc->sc_phytype = WMPHY_NONE;
 	} else {
 		struct mii_softc *child = LIST_FIRST(&mii->mii_phys);
 		/*
 		 * PHY found! Check PHY type again by the second call of
 		 * wm_gmii_setup_phytype.
 		 */
 		wm_gmii_setup_phytype(sc, child->mii_mpd_oui,
 		    child->mii_mpd_model);
 		ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO);
+	}
+}
 /*
  * wm_gmii_mediachange:	[ifmedia interface function]
+ *
  *	Set hardware to newly-selected media on a 1000BASE-T device.
  */
 static int
 wm_gmii_mediachange(struct ifnet *ifp)
+{
 	struct wm_softc *sc = ifp->if_softc;
 	struct ifmedia_entry *ife = sc->sc_mii.mii_media.ifm_cur;
 	uint32_t reg;
 	int rc;
 	DPRINTF(sc, WM_DEBUG_GMII, ("%s: %s called\n",
 		device_xname(sc->sc_dev), __func__));
 	if ((ifp->if_flags & IFF_UP) == 0)
 		return 0;
 	/* XXX Not for I354? FreeBSD's e1000_82575.c doesn't include it */
 	if ((sc->sc_type == WM_T_82580)
 	    || (sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I210)
 	    || (sc->sc_type == WM_T_I211)) {
 		reg = CSR_READ(sc, WMREG_PHPM);
 		reg &= ~PHPM_GO_LINK_D;
 		CSR_WRITE(sc, WMREG_PHPM, reg);
+	}
 	/* Disable D0 LPLU. */
 	wm_lplu_d0_disable(sc);
 	sc->sc_ctrl &= ~(CTRL_SPEED_MASK | CTRL_FD);
 	sc->sc_ctrl |= CTRL_SLU;
 	if ((IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO)
 	    || (sc->sc_type > WM_T_82543)) {
 		sc->sc_ctrl &= ~(CTRL_FRCSPD | CTRL_FRCFDX);
 	} else {
 		sc->sc_ctrl &= ~CTRL_ASDE;
 		sc->sc_ctrl |= CTRL_FRCSPD | CTRL_FRCFDX;
 		if (ife->ifm_media & IFM_FDX)
 			sc->sc_ctrl |= CTRL_FD;
 		switch (IFM_SUBTYPE(ife->ifm_media)) {
 		case IFM_10_T:
 			sc->sc_ctrl |= CTRL_SPEED_10;
 			break;
 		case IFM_100_TX:
 			sc->sc_ctrl |= CTRL_SPEED_100;
 			break;
 		case IFM_1000_T:
 			sc->sc_ctrl |= CTRL_SPEED_1000;
 			break;
 		case IFM_NONE:
 			/* There is no specific setting for IFM_NONE */
 			break;
 		default:
 			panic("wm_gmii_mediachange: bad media 0x%x",
 			    ife->ifm_media);
+		}
+	}
 	CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
 	CSR_WRITE_FLUSH(sc);
 	if ((sc->sc_type >= WM_T_82575) && (sc->sc_type <= WM_T_I211))
 		wm_serdes_mediachange(ifp);
 	if (sc->sc_type <= WM_T_82543)
 		wm_gmii_reset(sc);
 	else if ((sc->sc_type >= WM_T_82575) && (sc->sc_type <= WM_T_I211)
 	    && ((sc->sc_flags & WM_F_SGMII) != 0)) {
 		/* allow time for SFP cage time to power up phy */
 		delay(300 * 1000);
 		wm_gmii_reset(sc);
+	}
 	if ((rc = mii_mediachg(&sc->sc_mii)) == ENXIO)
 		return 0;
 	return rc;
+}
 /*
  * wm_gmii_mediastatus:	[ifmedia interface function]
+ *
  *	Get the current interface media status on a 1000BASE-T device.
  */
 static void
 wm_gmii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
+{
 	struct wm_softc *sc = ifp->if_softc;
 	struct ethercom *ec = &sc->sc_ethercom;
 	struct mii_data *mii;
 	bool dopoll = true;
 	KASSERT(ec->ec_mii != NULL);
 	mii = ec->ec_mii;
 	if ((sc->sc_flags & WM_F_DELAY_LINKUP) != 0) {
 		struct timeval now;
 		getmicrotime(&now);
 		if (timercmp(&now, &sc->sc_linkup_delay_time, <))
 			dopoll = false;
 		else if (sc->sc_linkup_delay_time.tv_sec != 0) {
 			/* Simplify by checking tv_sec only. It's enough. */
 			sc->sc_linkup_delay_time.tv_sec = 0;
 			sc->sc_linkup_delay_time.tv_usec = 0;
+		}
+	}
 	/*
 	 * Don't call mii_pollstat() while doing workaround.
 	 * See also wm_linkintr_gmii() and wm_tick().
 	 */
 	if (dopoll)
 		mii_pollstat(mii);
 	ifmr->ifm_active = mii->mii_media_active;
 	ifmr->ifm_status = mii->mii_media_status;
 	ifmr->ifm_active = (ifmr->ifm_active & ~IFM_ETH_FMASK)
 	    | sc->sc_flowflags;
+}
 #define	MDI_IO		CTRL_SWDPIN(2)
 #define	MDI_DIR		CTRL_SWDPIO(2)	/* host -> PHY */
 #define	MDI_CLK		CTRL_SWDPIN(3)
 static void
 wm_i82543_mii_sendbits(struct wm_softc *sc, uint32_t data, int nbits)
+{
 	uint32_t i, v;
 	v = CSR_READ(sc, WMREG_CTRL);
 	v &= ~(MDI_IO | MDI_CLK | (CTRL_SWDPIO_MASK << CTRL_SWDPIO_SHIFT));
 	v |= MDI_DIR | CTRL_SWDPIO(3);
 	for (i = __BIT(nbits - 1); i != 0; i >>= 1) {
 		if (data & i)
 			v |= MDI_IO;
 		else
 			v &= ~MDI_IO;
 		CSR_WRITE(sc, WMREG_CTRL, v);
 		CSR_WRITE_FLUSH(sc);
 		delay(10);
 		CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK);
 		CSR_WRITE_FLUSH(sc);
 		delay(10);
 		CSR_WRITE(sc, WMREG_CTRL, v);
 		CSR_WRITE_FLUSH(sc);
 		delay(10);
+	}
+}
 static uint32_t
 wm_i82543_mii_recvbits(struct wm_softc *sc)
+{
 	uint32_t v, i, data = 0;
 	v = CSR_READ(sc, WMREG_CTRL);
 	v &= ~(MDI_IO | MDI_CLK | (CTRL_SWDPIO_MASK << CTRL_SWDPIO_SHIFT));
 	v |= CTRL_SWDPIO(3);
 	CSR_WRITE(sc, WMREG_CTRL, v);
 	CSR_WRITE_FLUSH(sc);
 	delay(10);
 	CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK);
 	CSR_WRITE_FLUSH(sc);
 	delay(10);
 	CSR_WRITE(sc, WMREG_CTRL, v);
 	CSR_WRITE_FLUSH(sc);
 	delay(10);
 	for (i = 0; i < 16; i++) {
 		data <<= 1;
 		CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK);
 		CSR_WRITE_FLUSH(sc);
 		delay(10);
 		if (CSR_READ(sc, WMREG_CTRL) & MDI_IO)
 			data |= 1;
 		CSR_WRITE(sc, WMREG_CTRL, v);
 		CSR_WRITE_FLUSH(sc);
 		delay(10);
+	}
 	CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK);
 	CSR_WRITE_FLUSH(sc);
 	delay(10);
 	CSR_WRITE(sc, WMREG_CTRL, v);
 	CSR_WRITE_FLUSH(sc);
 	delay(10);
 	return data;
+}
 #undef MDI_IO
 #undef MDI_DIR
 #undef MDI_CLK
 /*
  * wm_gmii_i82543_readreg:	[mii interface function]
+ *
  *	Read a PHY register on the GMII (i82543 version).
  */
 static int
 wm_gmii_i82543_readreg(device_t dev, int phy, int reg)
+{
 	struct wm_softc *sc = device_private(dev);
 	int rv;
 	wm_i82543_mii_sendbits(sc, 0xffffffffU, 32);
 	wm_i82543_mii_sendbits(sc, reg | (phy << 5) |
 	    (MII_COMMAND_READ << 10) | (MII_COMMAND_START << 12), 14);
 	rv = wm_i82543_mii_recvbits(sc) & 0xffff;
 	DPRINTF(sc, WM_DEBUG_GMII, ("%s: GMII: read phy %d reg %d -> 0x%04x\n",
 		device_xname(dev), phy, reg, rv));
 	return rv;
+}
 /*
  * wm_gmii_i82543_writereg:	[mii interface function]
+ *
  *	Write a PHY register on the GMII (i82543 version).
  */
 static void
 wm_gmii_i82543_writereg(device_t dev, int phy, int reg, int val)
+{
 	struct wm_softc *sc = device_private(dev);
 	wm_i82543_mii_sendbits(sc, 0xffffffffU, 32);
 	wm_i82543_mii_sendbits(sc, val | (MII_COMMAND_ACK << 16) |
 	    (reg << 18) | (phy << 23) | (MII_COMMAND_WRITE << 28) |
 	    (MII_COMMAND_START << 30), 32);
+}
 /*
  * wm_gmii_mdic_readreg:	[mii interface function]
+ *
  *	Read a PHY register on the GMII.
  */
 static int
 wm_gmii_mdic_readreg(device_t dev, int phy, int reg)
+{
 	struct wm_softc *sc = device_private(dev);
 	uint32_t mdic = 0;
 	int i, rv;
 	if ((sc->sc_phytype != WMPHY_82579) && (sc->sc_phytype != WMPHY_I217)
 	    && (reg > MII_ADDRMASK)) {
 		device_printf(dev, "%s: PHYTYPE = %d, addr 0x%x > 0x1f\n",
 		    __func__, sc->sc_phytype, reg);
 		reg &= MII_ADDRMASK;
+	}
 	CSR_WRITE(sc, WMREG_MDIC, MDIC_OP_READ | MDIC_PHYADD(phy) |
 	    MDIC_REGADD(reg));
 	for (i = 0; i < WM_GEN_POLL_TIMEOUT * 3; i++) {
 		delay(50);
 		mdic = CSR_READ(sc, WMREG_MDIC);
 		if (mdic & MDIC_READY)
 			break;
+	}
 	if ((mdic & MDIC_READY) == 0) {
 		log(LOG_WARNING, "%s: MDIC read timed out: phy %d reg %d\n",
 		    device_xname(dev), phy, reg);
 		return 0;
 	} else if (mdic & MDIC_E) {
 #if 0 /* This is normal if no PHY is present. */
 		log(LOG_WARNING, "%s: MDIC read error: phy %d reg %d\n",
 		    device_xname(dev), phy, reg);
 #endif
 		return 0;
 	} else {
 		rv = MDIC_DATA(mdic);
 		if (rv == 0xffff)
 			rv = 0;
+	}
 	/*
 	 * Allow some time after each MDIC transaction to avoid
 	 * reading duplicate data in the next MDIC transaction.
 	 */
 	if (sc->sc_type == WM_T_PCH2)
 		delay(100);
 	return rv;
+}
 /*
  * wm_gmii_mdic_writereg:	[mii interface function]
+ *
  *	Write a PHY register on the GMII.
  */
 static void
 wm_gmii_mdic_writereg(device_t dev, int phy, int reg, int val)
+{
 	struct wm_softc *sc = device_private(dev);
 	uint32_t mdic = 0;
 	int i;
 @@ -13977,2008 +14013,2009 @@ wm_nvm_set_addrbits_size_eecd(struct wm_
  *	Wait for a SPI EEPROM to be ready for commands.
  */
 static int
 wm_nvm_ready_spi(struct wm_softc *sc)
+{
 	uint32_t val;
 	int usec;
 	DPRINTF(sc, WM_DEBUG_NVM, ("%s: %s called\n",
 		device_xname(sc->sc_dev), __func__));
 	for (usec = 0; usec < SPI_MAX_RETRIES; delay(5), usec += 5) {
 		wm_eeprom_sendbits(sc, SPI_OPC_RDSR, 8);
 		wm_eeprom_recvbits(sc, &val, 8);
 		if ((val & SPI_SR_RDY) == 0)
 			break;
+	}
 	if (usec >= SPI_MAX_RETRIES) {
 		aprint_error_dev(sc->sc_dev,"EEPROM failed to become ready\n");
 		return -1;
+	}
 	return 0;
+}
 /*
  * wm_nvm_read_spi:
+ *
  *	Read a work from the EEPROM using the SPI protocol.
  */
 static int
 wm_nvm_read_spi(struct wm_softc *sc, int word, int wordcnt, uint16_t *data)
+{
 	uint32_t reg, val;
 	int i;
 	uint8_t opc;
 	int rv;
 	DPRINTF(sc, WM_DEBUG_NVM, ("%s: %s called\n",
 		device_xname(sc->sc_dev), __func__));
 	rv = sc->nvm.acquire(sc);
 	if (rv != 0)
 		return rv;
 	/* Clear SK and CS. */
 	reg = CSR_READ(sc, WMREG_EECD) & ~(EECD_SK | EECD_CS);
 	CSR_WRITE(sc, WMREG_EECD, reg);
 	CSR_WRITE_FLUSH(sc);
 	delay(2);
 	if ((rv = wm_nvm_ready_spi(sc)) != 0)
 		goto out;
 	/* Toggle CS to flush commands. */
 	CSR_WRITE(sc, WMREG_EECD, reg | EECD_CS);
 	CSR_WRITE_FLUSH(sc);
 	delay(2);
 	CSR_WRITE(sc, WMREG_EECD, reg);
 	CSR_WRITE_FLUSH(sc);
 	delay(2);
 	opc = SPI_OPC_READ;
 	if (sc->sc_nvm_addrbits == 8 && word >= 128)
 		opc |= SPI_OPC_A8;
 	wm_eeprom_sendbits(sc, opc, 8);
 	wm_eeprom_sendbits(sc, word << 1, sc->sc_nvm_addrbits);
 	for (i = 0; i < wordcnt; i++) {
 		wm_eeprom_recvbits(sc, &val, 16);
 		data[i] = ((val >> 8) & 0xff) | ((val & 0xff) << 8);
+	}
 	/* Raise CS and clear SK. */
 	reg = (CSR_READ(sc, WMREG_EECD) & ~EECD_SK) | EECD_CS;
 	CSR_WRITE(sc, WMREG_EECD, reg);
 	CSR_WRITE_FLUSH(sc);
 	delay(2);
 out:
 	sc->nvm.release(sc);
 	return rv;
+}
 /* Using with EERD */
 static int
 wm_poll_eerd_eewr_done(struct wm_softc *sc, int rw)
+{
 	uint32_t attempts = 100000;
 	uint32_t i, reg = 0;
 	int32_t done = -1;
 	for (i = 0; i < attempts; i++) {
 		reg = CSR_READ(sc, rw);
 		if (reg & EERD_DONE) {
 			done = 0;
 			break;
+		}
 		delay(5);
+	}
 	return done;
+}
 static int
 wm_nvm_read_eerd(struct wm_softc *sc, int offset, int wordcnt, uint16_t *data)
+{
 	int i, eerd = 0;
 	int rv;
 	DPRINTF(sc, WM_DEBUG_NVM, ("%s: %s called\n",
 		device_xname(sc->sc_dev), __func__));
 	rv = sc->nvm.acquire(sc);
 	if (rv != 0)
 		return rv;
 	for (i = 0; i < wordcnt; i++) {
 		eerd = ((offset + i) << EERD_ADDR_SHIFT) | EERD_START;
 		CSR_WRITE(sc, WMREG_EERD, eerd);
 		rv = wm_poll_eerd_eewr_done(sc, WMREG_EERD);
 		if (rv != 0) {
 			aprint_error_dev(sc->sc_dev, "EERD polling failed: "
 			    "offset=%d. wordcnt=%d\n", offset, wordcnt);
 			break;
+		}
 		data[i] = (CSR_READ(sc, WMREG_EERD) >> EERD_DATA_SHIFT);
+	}
 	sc->nvm.release(sc);
 	return rv;
+}
 /* Flash */
 static int
 wm_nvm_valid_bank_detect_ich8lan(struct wm_softc *sc, unsigned int *bank)
+{
 	uint32_t eecd;
 	uint32_t act_offset = ICH_NVM_SIG_WORD * 2 + 1;
 	uint32_t bank1_offset = sc->sc_ich8_flash_bank_size * sizeof(uint16_t);
 	uint32_t nvm_dword = 0;
 	uint8_t sig_byte = 0;
 	int rv;
 	switch (sc->sc_type) {
 	case WM_T_PCH_SPT:
 	case WM_T_PCH_CNP:
 	case WM_T_PCH_TGP:
 		bank1_offset = sc->sc_ich8_flash_bank_size * 2;
 		act_offset = ICH_NVM_SIG_WORD * 2;
 		/* Set bank to 0 in case flash read fails. */
 		*bank = 0;
 		/* Check bank 0 */
 		rv = wm_read_ich8_dword(sc, act_offset, &nvm_dword);
 		if (rv != 0)
 			return rv;
 		sig_byte = (uint8_t)((nvm_dword & 0xFF00) >> 8);
 		if ((sig_byte & ICH_NVM_VALID_SIG_MASK) == ICH_NVM_SIG_VALUE) {
 			*bank = 0;
 			return 0;
+		}
 		/* Check bank 1 */
 		rv = wm_read_ich8_dword(sc, act_offset + bank1_offset,
 		    &nvm_dword);
 		sig_byte = (uint8_t)((nvm_dword & 0xFF00) >> 8);
 		if ((sig_byte & ICH_NVM_VALID_SIG_MASK) == ICH_NVM_SIG_VALUE) {
 			*bank = 1;
 			return 0;
+		}
 		aprint_error_dev(sc->sc_dev,
 		    "%s: no valid NVM bank present (%u)\n", __func__, *bank);
 		return -1;
 	case WM_T_ICH8:
 	case WM_T_ICH9:
 		eecd = CSR_READ(sc, WMREG_EECD);
 		if ((eecd & EECD_SEC1VAL_VALMASK) == EECD_SEC1VAL_VALMASK) {
 			*bank = ((eecd & EECD_SEC1VAL) != 0) ? 1 : 0;
 			return 0;
+		}
 		/* FALLTHROUGH */
 	default:
 		/* Default to 0 */
 		*bank = 0;
 		/* Check bank 0 */
 		wm_read_ich8_byte(sc, act_offset, &sig_byte);
 		if ((sig_byte & ICH_NVM_VALID_SIG_MASK) == ICH_NVM_SIG_VALUE) {
 			*bank = 0;
 			return 0;
+		}
 		/* Check bank 1 */
 		wm_read_ich8_byte(sc, act_offset + bank1_offset,
 		    &sig_byte);
 		if ((sig_byte & ICH_NVM_VALID_SIG_MASK) == ICH_NVM_SIG_VALUE) {
 			*bank = 1;
 			return 0;
+		}
+	}
 	DPRINTF(sc, WM_DEBUG_NVM, ("%s: No valid NVM bank present\n",
 		device_xname(sc->sc_dev)));
 	return -1;
+}
 /******************************************************************************
  * This function does initial flash setup so that a new read/write/erase cycle
  * can be started.
+ *
  * sc - The pointer to the hw structure
  ****************************************************************************/
 static int32_t
 wm_ich8_cycle_init(struct wm_softc *sc)
+{
 	uint16_t hsfsts;
 	int32_t error = 1;
 	int32_t i     = 0;
 	if (sc->sc_type >= WM_T_PCH_SPT)
 		hsfsts = ICH8_FLASH_READ32(sc, ICH_FLASH_HSFSTS) & 0xffffUL;
 	else
 		hsfsts = ICH8_FLASH_READ16(sc, ICH_FLASH_HSFSTS);
 	/* May be check the Flash Des Valid bit in Hw status */
 	if ((hsfsts & HSFSTS_FLDVAL) == 0)
 		return error;
 	/* Clear FCERR in Hw status by writing 1 */
 	/* Clear DAEL in Hw status by writing a 1 */
 	hsfsts |= HSFSTS_ERR | HSFSTS_DAEL;
 	if (sc->sc_type >= WM_T_PCH_SPT)
 		ICH8_FLASH_WRITE32(sc, ICH_FLASH_HSFSTS, hsfsts & 0xffffUL);
 	else
 		ICH8_FLASH_WRITE16(sc, ICH_FLASH_HSFSTS, hsfsts);
 	/*
 	 * Either we should have a hardware SPI cycle in progress bit to check
 	 * against, in order to start a new cycle or FDONE bit should be
 	 * changed in the hardware so that it is 1 after hardware reset, which
 	 * can then be used as an indication whether a cycle is in progress or
 	 * has been completed .. we should also have some software semaphore
 	 * mechanism to guard FDONE or the cycle in progress bit so that two
 	 * threads access to those bits can be sequentiallized or a way so that
 	 * 2 threads don't start the cycle at the same time
 	 */
 	if ((hsfsts & HSFSTS_FLINPRO) == 0) {
 		/*
 		 * There is no cycle running at present, so we can start a
 		 * cycle
 		 */
 		/* Begin by setting Flash Cycle Done. */
 		hsfsts |= HSFSTS_DONE;
 		if (sc->sc_type >= WM_T_PCH_SPT)
 			ICH8_FLASH_WRITE32(sc, ICH_FLASH_HSFSTS,
 			    hsfsts & 0xffffUL);
 		else
 			ICH8_FLASH_WRITE16(sc, ICH_FLASH_HSFSTS, hsfsts);
 		error = 0;
 	} else {
 		/*
 		 * Otherwise poll for sometime so the current cycle has a
 		 * chance to end before giving up.
 		 */
 		for (i = 0; i < ICH_FLASH_COMMAND_TIMEOUT; i++) {
 			if (sc->sc_type >= WM_T_PCH_SPT)
 				hsfsts = ICH8_FLASH_READ32(sc,
 				    ICH_FLASH_HSFSTS) & 0xffffUL;
 			else
 				hsfsts = ICH8_FLASH_READ16(sc,
 				    ICH_FLASH_HSFSTS);
 			if ((hsfsts & HSFSTS_FLINPRO) == 0) {
 				error = 0;
 				break;
+			}
 			delay(1);
+		}
 		if (error == 0) {
 			/*
 			 * Successful in waiting for previous cycle to timeout,
 			 * now set the Flash Cycle Done.
 			 */
 			hsfsts |= HSFSTS_DONE;
 			if (sc->sc_type >= WM_T_PCH_SPT)
 				ICH8_FLASH_WRITE32(sc, ICH_FLASH_HSFSTS,
 				    hsfsts & 0xffffUL);
 			else
 				ICH8_FLASH_WRITE16(sc, ICH_FLASH_HSFSTS,
 				    hsfsts);
+		}
+	}
 	return error;
+}
 /******************************************************************************
  * This function starts a flash cycle and waits for its completion
+ *
  * sc - The pointer to the hw structure
  ****************************************************************************/
 static int32_t
 wm_ich8_flash_cycle(struct wm_softc *sc, uint32_t timeout)
+{
 	uint16_t hsflctl;
 	uint16_t hsfsts;
 	int32_t error = 1;
 	uint32_t i = 0;
 	/* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
 	if (sc->sc_type >= WM_T_PCH_SPT)
 		hsflctl = ICH8_FLASH_READ32(sc, ICH_FLASH_HSFSTS) >> 16;
 	else
 		hsflctl = ICH8_FLASH_READ16(sc, ICH_FLASH_HSFCTL);
 	hsflctl |= HSFCTL_GO;
 	if (sc->sc_type >= WM_T_PCH_SPT)
 		ICH8_FLASH_WRITE32(sc, ICH_FLASH_HSFSTS,
 		    (uint32_t)hsflctl << 16);
 	else
 		ICH8_FLASH_WRITE16(sc, ICH_FLASH_HSFCTL, hsflctl);
 	/* Wait till FDONE bit is set to 1 */
 	do {
 		if (sc->sc_type >= WM_T_PCH_SPT)
 			hsfsts = ICH8_FLASH_READ32(sc, ICH_FLASH_HSFSTS)
 			    & 0xffffUL;
 		else
 			hsfsts = ICH8_FLASH_READ16(sc, ICH_FLASH_HSFSTS);
 		if (hsfsts & HSFSTS_DONE)
 			break;
 		delay(1);
 		i++;
 	} while (i < timeout);
 	if ((hsfsts & HSFSTS_DONE) == 1 && (hsfsts & HSFSTS_ERR) == 0)
 		error = 0;
 	return error;
+}
 /******************************************************************************
  * Reads a byte or (d)word from the NVM using the ICH8 flash access registers.
+ *
  * sc - The pointer to the hw structure
  * index - The index of the byte or word to read.
  * size - Size of data to read, 1=byte 2=word, 4=dword
  * data - Pointer to the word to store the value read.
  *****************************************************************************/
 static int32_t
 wm_read_ich8_data(struct wm_softc *sc, uint32_t index,
     uint32_t size, uint32_t *data)
+{
 	uint16_t hsfsts;
 	uint16_t hsflctl;
 	uint32_t flash_linear_address;
 	uint32_t flash_data = 0;
 	int32_t error = 1;
 	int32_t count = 0;
 	if (size < 1  || size > 4 || data == 0x0 ||
 	    index > ICH_FLASH_LINEAR_ADDR_MASK)
 		return error;
 	flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) +
 	    sc->sc_ich8_flash_base;
 	do {
 		delay(1);
 		/* Steps */
 		error = wm_ich8_cycle_init(sc);
 		if (error)
 			break;
 		if (sc->sc_type >= WM_T_PCH_SPT)
 			hsflctl = ICH8_FLASH_READ32(sc, ICH_FLASH_HSFSTS)
 			    >> 16;
 		else
 			hsflctl = ICH8_FLASH_READ16(sc, ICH_FLASH_HSFCTL);
 		/* 0b/1b corresponds to 1 or 2 byte size, respectively. */
 		hsflctl |=  ((size - 1) << HSFCTL_BCOUNT_SHIFT)
 		    & HSFCTL_BCOUNT_MASK;
 		hsflctl |= ICH_CYCLE_READ << HSFCTL_CYCLE_SHIFT;
 		if (sc->sc_type >= WM_T_PCH_SPT) {
 			/*
 			 * In SPT, This register is in Lan memory space, not
 			 * flash. Therefore, only 32 bit access is supported.
 			 */
 			ICH8_FLASH_WRITE32(sc, ICH_FLASH_HSFSTS,
 			    (uint32_t)hsflctl << 16);
 		} else
 			ICH8_FLASH_WRITE16(sc, ICH_FLASH_HSFCTL, hsflctl);
 		/*
 		 * Write the last 24 bits of index into Flash Linear address
 		 * field in Flash Address
 		 */
 		/* TODO: TBD maybe check the index against the size of flash */
 		ICH8_FLASH_WRITE32(sc, ICH_FLASH_FADDR, flash_linear_address);
 		error = wm_ich8_flash_cycle(sc, ICH_FLASH_COMMAND_TIMEOUT);
 		/*
 		 * Check if FCERR is set to 1, if set to 1, clear it and try
 		 * the whole sequence a few more times, else read in (shift in)
 		 * the Flash Data0, the order is least significant byte first
 		 * msb to lsb
 		 */
 		if (error == 0) {
 			flash_data = ICH8_FLASH_READ32(sc, ICH_FLASH_FDATA0);
 			if (size == 1)
 				*data = (uint8_t)(flash_data & 0x000000FF);
 			else if (size == 2)
 				*data = (uint16_t)(flash_data & 0x0000FFFF);
 			else if (size == 4)
 				*data = (uint32_t)flash_data;
 			break;
 		} else {
 			/*
 			 * If we've gotten here, then things are probably
 			 * completely hosed, but if the error condition is
 			 * detected, it won't hurt to give it another try...
 			 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
 			 */
 			if (sc->sc_type >= WM_T_PCH_SPT)
 				hsfsts = ICH8_FLASH_READ32(sc,
 				    ICH_FLASH_HSFSTS) & 0xffffUL;
 			else
 				hsfsts = ICH8_FLASH_READ16(sc,
 				    ICH_FLASH_HSFSTS);
 			if (hsfsts & HSFSTS_ERR) {
 				/* Repeat for some time before giving up. */
 				continue;
 			} else if ((hsfsts & HSFSTS_DONE) == 0)
 				break;
+		}
 	} while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
 	return error;
+}
 /******************************************************************************
  * Reads a single byte from the NVM using the ICH8 flash access registers.
+ *
  * sc - pointer to wm_hw structure
  * index - The index of the byte to read.
  * data - Pointer to a byte to store the value read.
  *****************************************************************************/
 static int32_t
 wm_read_ich8_byte(struct wm_softc *sc, uint32_t index, uint8_t* data)
+{
 	int32_t status;
 	uint32_t word = 0;
 	status = wm_read_ich8_data(sc, index, 1, &word);
 	if (status == 0)
 		*data = (uint8_t)word;
 	else
 		*data = 0;
 	return status;
+}
 /******************************************************************************
  * Reads a word from the NVM using the ICH8 flash access registers.
+ *
  * sc - pointer to wm_hw structure
  * index - The starting byte index of the word to read.
  * data - Pointer to a word to store the value read.
  *****************************************************************************/
 static int32_t
 wm_read_ich8_word(struct wm_softc *sc, uint32_t index, uint16_t *data)
+{
 	int32_t status;
 	uint32_t word = 0;
 	status = wm_read_ich8_data(sc, index, 2, &word);
 	if (status == 0)
 		*data = (uint16_t)word;
 	else
 		*data = 0;
 	return status;
+}
 /******************************************************************************
  * Reads a dword from the NVM using the ICH8 flash access registers.
+ *
  * sc - pointer to wm_hw structure
  * index - The starting byte index of the word to read.
  * data - Pointer to a word to store the value read.
  *****************************************************************************/
 static int32_t
 wm_read_ich8_dword(struct wm_softc *sc, uint32_t index, uint32_t *data)
+{
 	int32_t status;
 	status = wm_read_ich8_data(sc, index, 4, data);
 	return status;
+}
 /******************************************************************************
  * Reads a 16 bit word or words from the EEPROM using the ICH8's flash access
  * register.
+ *
  * sc - Struct containing variables accessed by shared code
  * offset - offset of word in the EEPROM to read
  * data - word read from the EEPROM
  * words - number of words to read
  *****************************************************************************/
 static int
 wm_nvm_read_ich8(struct wm_softc *sc, int offset, int words, uint16_t *data)
+{
 	int rv;
 	uint32_t flash_bank = 0;
 	uint32_t act_offset = 0;
 	uint32_t bank_offset = 0;
 	uint16_t word = 0;
 	uint16_t i = 0;
 	DPRINTF(sc, WM_DEBUG_NVM, ("%s: %s called\n",
 		device_xname(sc->sc_dev), __func__));
 	rv = sc->nvm.acquire(sc);
 	if (rv != 0)
 		return rv;
 	/*
 	 * We need to know which is the valid flash bank.  In the event
 	 * that we didn't allocate eeprom_shadow_ram, we may not be
 	 * managing flash_bank. So it cannot be trusted and needs
 	 * to be updated with each read.
 	 */
 	rv = wm_nvm_valid_bank_detect_ich8lan(sc, &flash_bank);
 	if (rv) {
 		DPRINTF(sc, WM_DEBUG_NVM, ("%s: failed to detect NVM bank\n",
 			device_xname(sc->sc_dev)));
 		flash_bank = 0;
+	}
 	/*
 	 * Adjust offset appropriately if we're on bank 1 - adjust for word
 	 * size
 	 */
 	bank_offset = flash_bank * (sc->sc_ich8_flash_bank_size * 2);
 	for (i = 0; i < words; i++) {
 		/* The NVM part needs a byte offset, hence * 2 */
 		act_offset = bank_offset + ((offset + i) * 2);
 		rv = wm_read_ich8_word(sc, act_offset, &word);
 		if (rv) {
 			aprint_error_dev(sc->sc_dev,
 			    "%s: failed to read NVM\n", __func__);
 			break;
+		}
 		data[i] = word;
+	}
 	sc->nvm.release(sc);
 	return rv;
+}
 /******************************************************************************
  * Reads a 16 bit word or words from the EEPROM using the SPT's flash access
  * register.
+ *
  * sc - Struct containing variables accessed by shared code
  * offset - offset of word in the EEPROM to read
  * data - word read from the EEPROM
  * words - number of words to read
  *****************************************************************************/
 static int
 wm_nvm_read_spt(struct wm_softc *sc, int offset, int words, uint16_t *data)
+{
 	int  rv;
 	uint32_t flash_bank = 0;
 	uint32_t act_offset = 0;
 	uint32_t bank_offset = 0;
 	uint32_t dword = 0;
 	uint16_t i = 0;
 	DPRINTF(sc, WM_DEBUG_NVM, ("%s: %s called\n",
 		device_xname(sc->sc_dev), __func__));
 	rv = sc->nvm.acquire(sc);
 	if (rv != 0)
 		return rv;
 	/*
 	 * We need to know which is the valid flash bank.  In the event
 	 * that we didn't allocate eeprom_shadow_ram, we may not be
 	 * managing flash_bank. So it cannot be trusted and needs
 	 * to be updated with each read.
 	 */
 	rv = wm_nvm_valid_bank_detect_ich8lan(sc, &flash_bank);
 	if (rv) {
 		DPRINTF(sc, WM_DEBUG_NVM, ("%s: failed to detect NVM bank\n",
 			device_xname(sc->sc_dev)));
 		flash_bank = 0;
+	}
 	/*
 	 * Adjust offset appropriately if we're on bank 1 - adjust for word
 	 * size
 	 */
 	bank_offset = flash_bank * (sc->sc_ich8_flash_bank_size * 2);
 	for (i = 0; i < words; i++) {
 		/* The NVM part needs a byte offset, hence * 2 */
 		act_offset = bank_offset + ((offset + i) * 2);
 		/* but we must read dword aligned, so mask ... */
 		rv = wm_read_ich8_dword(sc, act_offset & ~0x3, &dword);
 		if (rv) {
 			aprint_error_dev(sc->sc_dev,
 			    "%s: failed to read NVM\n", __func__);
 			break;
+		}
 		/* ... and pick out low or high word */
 		if ((act_offset & 0x2) == 0)
 			data[i] = (uint16_t)(dword & 0xFFFF);
 		else
 			data[i] = (uint16_t)((dword >> 16) & 0xFFFF);
+	}
 	sc->nvm.release(sc);
 	return rv;
+}
 /* iNVM */
 static int
 wm_nvm_read_word_invm(struct wm_softc *sc, uint16_t address, uint16_t *data)
+{
 	int32_t	 rv = 0;
 	uint32_t invm_dword;
 	uint16_t i;
 	uint8_t record_type, word_address;
 	DPRINTF(sc, WM_DEBUG_NVM, ("%s: %s called\n",
 		device_xname(sc->sc_dev), __func__));
 	for (i = 0; i < INVM_SIZE; i++) {
 		invm_dword = CSR_READ(sc, WM_INVM_DATA_REG(i));
 		/* Get record type */
 		record_type = INVM_DWORD_TO_RECORD_TYPE(invm_dword);
 		if (record_type == INVM_UNINITIALIZED_STRUCTURE)
 			break;
 		if (record_type == INVM_CSR_AUTOLOAD_STRUCTURE)
 			i += INVM_CSR_AUTOLOAD_DATA_SIZE_IN_DWORDS;
 		if (record_type == INVM_RSA_KEY_SHA256_STRUCTURE)
 			i += INVM_RSA_KEY_SHA256_DATA_SIZE_IN_DWORDS;
 		if (record_type == INVM_WORD_AUTOLOAD_STRUCTURE) {
 			word_address = INVM_DWORD_TO_WORD_ADDRESS(invm_dword);
 			if (word_address == address) {
 				*data = INVM_DWORD_TO_WORD_DATA(invm_dword);
 				rv = 0;
 				break;
+			}
+		}
+	}
 	return rv;
+}
 static int
 wm_nvm_read_invm(struct wm_softc *sc, int offset, int words, uint16_t *data)
+{
 	int i, rv;
 	DPRINTF(sc, WM_DEBUG_NVM, ("%s: %s called\n",
 		device_xname(sc->sc_dev), __func__));
 	rv = sc->nvm.acquire(sc);
 	if (rv != 0)
 		return rv;
 	for (i = 0; i < words; i++) {
 		switch (offset + i) {
 		case NVM_OFF_MACADDR:
 		case NVM_OFF_MACADDR1:
 		case NVM_OFF_MACADDR2:
 			rv = wm_nvm_read_word_invm(sc, offset + i, &data[i]);
 			if (rv != 0) {
 				data[i] = 0xffff;
 				rv = -1;
+			}
 			break;
 		case NVM_OFF_CFG1: /* == INVM_AUTOLOAD */
 			rv = wm_nvm_read_word_invm(sc, offset, data);
 			if (rv != 0) {
 				*data = INVM_DEFAULT_AL;
 				rv = 0;
+			}
 			break;
 		case NVM_OFF_CFG2:
 			rv = wm_nvm_read_word_invm(sc, offset, data);
 			if (rv != 0) {
 				*data = NVM_INIT_CTRL_2_DEFAULT_I211;
 				rv = 0;
+			}
 			break;
 		case NVM_OFF_CFG4:
 			rv = wm_nvm_read_word_invm(sc, offset, data);
 			if (rv != 0) {
 				*data = NVM_INIT_CTRL_4_DEFAULT_I211;
 				rv = 0;
+			}
 			break;
 		case NVM_OFF_LED_1_CFG:
 			rv = wm_nvm_read_word_invm(sc, offset, data);
 			if (rv != 0) {
 				*data = NVM_LED_1_CFG_DEFAULT_I211;
 				rv = 0;
+			}
 			break;
 		case NVM_OFF_LED_0_2_CFG:
 			rv = wm_nvm_read_word_invm(sc, offset, data);
 			if (rv != 0) {
 				*data = NVM_LED_0_2_CFG_DEFAULT_I211;
 				rv = 0;
+			}
 			break;
 		case NVM_OFF_ID_LED_SETTINGS:
 			rv = wm_nvm_read_word_invm(sc, offset, data);
 			if (rv != 0) {
 				*data = ID_LED_RESERVED_FFFF;
 				rv = 0;
+			}
 			break;
 		default:
 			DPRINTF(sc, WM_DEBUG_NVM,
 			    ("NVM word 0x%02x is not mapped.\n", offset));
 			*data = NVM_RESERVED_WORD;
 			break;
+		}
+	}
 	sc->nvm.release(sc);
 	return rv;
+}
 /* Lock, detecting NVM type, validate checksum, version and read */
 static int
 wm_nvm_is_onboard_eeprom(struct wm_softc *sc)
+{
 	uint32_t eecd = 0;
 	if (sc->sc_type == WM_T_82573 || sc->sc_type == WM_T_82574
 	    || sc->sc_type == WM_T_82583) {
 		eecd = CSR_READ(sc, WMREG_EECD);
 		/* Isolate bits 15 & 16 */
 		eecd = ((eecd >> 15) & 0x03);
 		/* If both bits are set, device is Flash type */
 		if (eecd == 0x03)
 			return 0;
+	}
 	return 1;
+}
 static int
 wm_nvm_flash_presence_i210(struct wm_softc *sc)
+{
 	uint32_t eec;
 	eec = CSR_READ(sc, WMREG_EEC);
 	if ((eec & EEC_FLASH_DETECTED) != 0)
 		return 1;
 	return 0;
+}
 /*
  * wm_nvm_validate_checksum
+ *
  * The checksum is defined as the sum of the first 64 (16 bit) words.
  */
 static int
 wm_nvm_validate_checksum(struct wm_softc *sc)
+{
 	uint16_t checksum;
 	uint16_t eeprom_data;
 #ifdef WM_DEBUG
 	uint16_t csum_wordaddr, valid_checksum;
 #endif
 	int i;
 	checksum = 0;
 	/* Don't check for I211 */
 	if (sc->sc_type == WM_T_I211)
 		return 0;
 #ifdef WM_DEBUG
 	if ((sc->sc_type == WM_T_PCH_LPT) || (sc->sc_type == WM_T_PCH_SPT) ||
 	    (sc->sc_type == WM_T_PCH_CNP) || (sc->sc_type == WM_T_PCH_TGP)) {
 		csum_wordaddr = NVM_OFF_COMPAT;
 		valid_checksum = NVM_COMPAT_VALID_CHECKSUM;
 	} else {
 		csum_wordaddr = NVM_OFF_FUTURE_INIT_WORD1;
 		valid_checksum = NVM_FUTURE_INIT_WORD1_VALID_CHECKSUM;
+	}
 	/* Dump EEPROM image for debug */
 	if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
 	    || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH)
 	    || (sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT)) {
 		/* XXX PCH_SPT? */
 		wm_nvm_read(sc, csum_wordaddr, 1, &eeprom_data);
 		if ((eeprom_data & valid_checksum) == 0)
 			DPRINTF(sc, WM_DEBUG_NVM,
 			    ("%s: NVM need to be updated (%04x != %04x)\n",
 				device_xname(sc->sc_dev), eeprom_data,
 				valid_checksum));
+	}
 	if ((sc->sc_debug & WM_DEBUG_NVM) != 0) {
 		printf("%s: NVM dump:\n", device_xname(sc->sc_dev));
 		for (i = 0; i < NVM_SIZE; i++) {
 			if (wm_nvm_read(sc, i, 1, &eeprom_data))
 				printf("XXXX ");
 			else
 				printf("%04hx ", eeprom_data);
 			if (i % 8 == 7)
 				printf("\n");
+		}
+	}
 #endif /* WM_DEBUG */
 	for (i = 0; i < NVM_SIZE; i++) {
 		if (wm_nvm_read(sc, i, 1, &eeprom_data))
 			return -1;
 		checksum += eeprom_data;
+	}
 	if (checksum != (uint16_t) NVM_CHECKSUM) {
 #ifdef WM_DEBUG
 		printf("%s: NVM checksum mismatch (%04x != %04x)\n",
 		    device_xname(sc->sc_dev), checksum, NVM_CHECKSUM);
 #endif
+	}
 	return 0;
+}
 static void
 wm_nvm_version_invm(struct wm_softc *sc)
+{
 	uint32_t dword;
 	/*
 	 * Linux's code to decode version is very strange, so we don't
 	 * obey that algorithm and just use word 61 as the document.
 	 * Perhaps it's not perfect though...
+	 *
 	 * Example:
+	 *
 	 *   Word61: 00800030 -> Version 0.6 (I211 spec update notes about 0.6)
 	 */
 	dword = CSR_READ(sc, WM_INVM_DATA_REG(61));
 	dword = __SHIFTOUT(dword, INVM_VER_1);
 	sc->sc_nvm_ver_major = __SHIFTOUT(dword, INVM_MAJOR);
 	sc->sc_nvm_ver_minor = __SHIFTOUT(dword, INVM_MINOR);
+}
 static void
 wm_nvm_version(struct wm_softc *sc)
+{
 	uint16_t major, minor, build, patch;
 	uint16_t uid0, uid1;
 	uint16_t nvm_data;
 	uint16_t off;
 	bool check_version = false;
 	bool check_optionrom = false;
 	bool have_build = false;
 	bool have_uid = true;
 	/*
 	 * Version format:
+	 *
 	 * XYYZ
 	 * X0YZ
 	 * X0YY
+	 *
 	 * Example:
+	 *
 	 *	82571	0x50a2	5.10.2?	(the spec update notes about 5.6-5.10)
 	 *	82571	0x50a6	5.10.6?
 	 *	82572	0x506a	5.6.10?
 	 *	82572EI	0x5069	5.6.9?
 	 *	82574L	0x1080	1.8.0?	(the spec update notes about 2.1.4)
 	 *		0x2013	2.1.3?
 	 *	82583	0x10a0	1.10.0? (document says it's default value)
 	 * ICH8+82567	0x0040	0.4.0?
 	 * ICH9+82566	0x1040	1.4.0?
 	 *ICH10+82567	0x0043	0.4.3?
 	 *  PCH+82577	0x00c1	0.12.1?
 	 * PCH2+82579	0x00d3	0.13.3?
 	 *		0x00d4	0.13.4?
 	 *  LPT+I218	0x0023	0.2.3?
 	 *  SPT+I219	0x0084	0.8.4?
 	 *  CNP+I219	0x0054	0.5.4?
 	 */
 	/*
 	 * XXX
 	 * Qemu's e1000e emulation (82574L)'s SPI has only 64 words.
 	 * I've never seen real 82574 hardware with such small SPI ROM.
 	 */
 	if ((sc->sc_nvm_wordsize < NVM_OFF_IMAGE_UID1)
 	    || (wm_nvm_read(sc, NVM_OFF_IMAGE_UID1, 1, &uid1) != 0))
 		have_uid = false;
 	switch (sc->sc_type) {
 	case WM_T_82571:
 	case WM_T_82572:
 	case WM_T_82574:
 	case WM_T_82583:
 		check_version = true;
 		check_optionrom = true;
 		have_build = true;
 		break;
 	case WM_T_ICH8:
 	case WM_T_ICH9:
 	case WM_T_ICH10:
 	case WM_T_PCH:
 	case WM_T_PCH2:
 	case WM_T_PCH_LPT:
 	case WM_T_PCH_SPT:
 	case WM_T_PCH_CNP:
 	case WM_T_PCH_TGP:
 		check_version = true;
 		have_build = true;
 		have_uid = false;
 		break;
 	case WM_T_82575:
 	case WM_T_82576:
 	case WM_T_82580:
 		if (have_uid && (uid1 & NVM_MAJOR_MASK) != NVM_UID_VALID)
 			check_version = true;
 		break;
 	case WM_T_I211:
 		wm_nvm_version_invm(sc);
 		have_uid = false;
 		goto printver;
 	case WM_T_I210:
 		if (!wm_nvm_flash_presence_i210(sc)) {
 			wm_nvm_version_invm(sc);
 			have_uid = false;
 			goto printver;
+		}
 		/* FALLTHROUGH */
 	case WM_T_I350:
 	case WM_T_I354:
 		check_version = true;
 		check_optionrom = true;
 		break;
 	default:
 		return;
+	}
 	if (check_version
 	    && (wm_nvm_read(sc, NVM_OFF_VERSION, 1, &nvm_data) == 0)) {
 		major = (nvm_data & NVM_MAJOR_MASK) >> NVM_MAJOR_SHIFT;
 		if (have_build || ((nvm_data & 0x0f00) != 0x0000)) {
 			minor = (nvm_data & NVM_MINOR_MASK) >> NVM_MINOR_SHIFT;
 			build = nvm_data & NVM_BUILD_MASK;
 			have_build = true;
 		} else
 			minor = nvm_data & 0x00ff;
 		/* Decimal */
 		minor = (minor / 16) * 10 + (minor % 16);
 		sc->sc_nvm_ver_major = major;
 		sc->sc_nvm_ver_minor = minor;
 printver:
 		aprint_verbose(", version %d.%d", sc->sc_nvm_ver_major,
 		    sc->sc_nvm_ver_minor);
 		if (have_build) {
 			sc->sc_nvm_ver_build = build;
 			aprint_verbose(".%d", build);
+		}
+	}
 	/* Assume the Option ROM area is at avove NVM_SIZE */
 	if ((sc->sc_nvm_wordsize > NVM_SIZE) && check_optionrom
 	    && (wm_nvm_read(sc, NVM_OFF_COMB_VER_PTR, 1, &off) == 0)) {
 		/* Option ROM Version */
 		if ((off != 0x0000) && (off != 0xffff)) {
 			int rv;
 			uint16_t oid0, oid1;
 			off += NVM_COMBO_VER_OFF;
-			rv = wm_nvm_read(sc, off + 1, 1, &uid1);
+			rv = wm_nvm_read(sc, off + 1, 1, &oid1);
-			rv |= wm_nvm_read(sc, off, 1, &uid0);
+			rv |= wm_nvm_read(sc, off, 1, &oid0);
-			if ((rv == 0) && (uid0 != 0) && (uid0 != 0xffff)
+			if ((rv == 0) && (oid0 != 0) && (oid0 != 0xffff)
-			    && (uid1 != 0) && (uid1 != 0xffff)) {
+			    && (oid1 != 0) && (oid1 != 0xffff)) {
 				/* 16bits */
-				major = uid0 >> 8;
+				major = oid0 >> 8;
-				build = (uid0 << 8) | (uid1 >> 8);
+				build = (oid0 << 8) | (oid1 >> 8);
-				patch = uid1 & 0x00ff;
+				patch = oid1 & 0x00ff;
 				aprint_verbose(", option ROM Version %d.%d.%d",
 				    major, build, patch);
+			}
+		}
+	}
 	if (have_uid && (wm_nvm_read(sc, NVM_OFF_IMAGE_UID0, 1, &uid0) == 0))
 		aprint_verbose(", Image Unique ID %08x",
 		    ((uint32_t)uid1 << 16) | uid0);
+}
 /*
  * wm_nvm_read:
+ *
  *	Read data from the serial EEPROM.
  */
 static int
 wm_nvm_read(struct wm_softc *sc, int word, int wordcnt, uint16_t *data)
+{
 	int rv;
 	DPRINTF(sc, WM_DEBUG_NVM, ("%s: %s called\n",
 		device_xname(sc->sc_dev), __func__));
 	if (sc->sc_flags & WM_F_EEPROM_INVALID)
 		return -1;
 	rv = sc->nvm.read(sc, word, wordcnt, data);
 	return rv;
+}
 /*
  * Hardware semaphores.
  * Very complexed...
  */
 static int
 wm_get_null(struct wm_softc *sc)
+{
 	DPRINTF(sc, WM_DEBUG_LOCK, ("%s: %s called\n",
 		device_xname(sc->sc_dev), __func__));
 	return 0;
+}
 static void
 wm_put_null(struct wm_softc *sc)
+{
 	DPRINTF(sc, WM_DEBUG_LOCK, ("%s: %s called\n",
 		device_xname(sc->sc_dev), __func__));
 	return;
+}
 static int
 wm_get_eecd(struct wm_softc *sc)
+{
 	uint32_t reg;
 	int x;
 	DPRINTF(sc, WM_DEBUG_LOCK | WM_DEBUG_NVM, ("%s: %s called\n",
 		device_xname(sc->sc_dev), __func__));
 	reg = CSR_READ(sc, WMREG_EECD);
 	/* Request EEPROM access. */
 	reg |= EECD_EE_REQ;
 	CSR_WRITE(sc, WMREG_EECD, reg);
 	/* ..and wait for it to be granted. */
 	for (x = 0; x < 1000; x++) {
 		reg = CSR_READ(sc, WMREG_EECD);
 		if (reg & EECD_EE_GNT)
 			break;
 		delay(5);
+	}
 	if ((reg & EECD_EE_GNT) == 0) {
 		aprint_error_dev(sc->sc_dev,
 		    "could not acquire EEPROM GNT\n");
 		reg &= ~EECD_EE_REQ;
 		CSR_WRITE(sc, WMREG_EECD, reg);
 		return -1;
+	}
 	return 0;
+}
 static void
 wm_nvm_eec_clock_raise(struct wm_softc *sc, uint32_t *eecd)
+{
 	*eecd |= EECD_SK;
 	CSR_WRITE(sc, WMREG_EECD, *eecd);
 	CSR_WRITE_FLUSH(sc);
 	if ((sc->sc_flags & WM_F_EEPROM_SPI) != 0)
 		delay(1);
 	else
 		delay(50);
+}
 static void
 wm_nvm_eec_clock_lower(struct wm_softc *sc, uint32_t *eecd)
+{
 	*eecd &= ~EECD_SK;
 	CSR_WRITE(sc, WMREG_EECD, *eecd);
 	CSR_WRITE_FLUSH(sc);
 	if ((sc->sc_flags & WM_F_EEPROM_SPI) != 0)
 		delay(1);
 	else
 		delay(50);
+}
 static void
 wm_put_eecd(struct wm_softc *sc)
+{
 	uint32_t reg;
 	DPRINTF(sc, WM_DEBUG_LOCK, ("%s: %s called\n",
 		device_xname(sc->sc_dev), __func__));
 	/* Stop nvm */
 	reg = CSR_READ(sc, WMREG_EECD);
 	if ((sc->sc_flags & WM_F_EEPROM_SPI) != 0) {
 		/* Pull CS high */
 		reg |= EECD_CS;
 		wm_nvm_eec_clock_lower(sc, &reg);
 	} else {
 		/* CS on Microwire is active-high */
 		reg &= ~(EECD_CS | EECD_DI);
 		CSR_WRITE(sc, WMREG_EECD, reg);
 		wm_nvm_eec_clock_raise(sc, &reg);
 		wm_nvm_eec_clock_lower(sc, &reg);
+	}
 	reg = CSR_READ(sc, WMREG_EECD);
 	reg &= ~EECD_EE_REQ;
 	CSR_WRITE(sc, WMREG_EECD, reg);
 	return;
+}
 /*
  * Get hardware semaphore.
  * Same as e1000_get_hw_semaphore_generic()
  */
 static int
 wm_get_swsm_semaphore(struct wm_softc *sc)
+{
 	int32_t timeout;
 	uint32_t swsm;
 	DPRINTF(sc, WM_DEBUG_LOCK, ("%s: %s called\n",
 		device_xname(sc->sc_dev), __func__));
 	KASSERT(sc->sc_nvm_wordsize > 0);
 retry:
 	/* Get the SW semaphore. */
 	timeout = sc->sc_nvm_wordsize + 1;
 	while (timeout) {
 		swsm = CSR_READ(sc, WMREG_SWSM);
 		if ((swsm & SWSM_SMBI) == 0)
 			break;
 		delay(50);
 		timeout--;
+	}
 	if (timeout == 0) {
 		if ((sc->sc_flags & WM_F_WA_I210_CLSEM) != 0) {
 			/*
 			 * In rare circumstances, the SW semaphore may already
 			 * be held unintentionally. Clear the semaphore once
 			 * before giving up.
 			 */
 			sc->sc_flags &= ~WM_F_WA_I210_CLSEM;
 			wm_put_swsm_semaphore(sc);
 			goto retry;
+		}
 		aprint_error_dev(sc->sc_dev, "could not acquire SWSM SMBI\n");
 		return -1;
+	}
 	/* Get the FW semaphore. */
 	timeout = sc->sc_nvm_wordsize + 1;
 	while (timeout) {
 		swsm = CSR_READ(sc, WMREG_SWSM);
 		swsm |= SWSM_SWESMBI;
 		CSR_WRITE(sc, WMREG_SWSM, swsm);
 		/* If we managed to set the bit we got the semaphore. */
 		swsm = CSR_READ(sc, WMREG_SWSM);
 		if (swsm & SWSM_SWESMBI)
 			break;
 		delay(50);
 		timeout--;
+	}
 	if (timeout == 0) {
 		aprint_error_dev(sc->sc_dev,
 		    "could not acquire SWSM SWESMBI\n");
 		/* Release semaphores */
 		wm_put_swsm_semaphore(sc);
 		return -1;
+	}
 	return 0;
+}
 /*
  * Put hardware semaphore.
  * Same as e1000_put_hw_semaphore_generic()
  */
 static void
 wm_put_swsm_semaphore(struct wm_softc *sc)
+{
 	uint32_t swsm;
 	DPRINTF(sc, WM_DEBUG_LOCK, ("%s: %s called\n",
 		device_xname(sc->sc_dev), __func__));
 	swsm = CSR_READ(sc, WMREG_SWSM);
 	swsm &= ~(SWSM_SMBI | SWSM_SWESMBI);
 	CSR_WRITE(sc, WMREG_SWSM, swsm);
+}
 /*
  * Get SW/FW semaphore.
  * Same as e1000_acquire_swfw_sync_{80003es2lan,82575}().
  */
 static int
 wm_get_swfw_semaphore(struct wm_softc *sc, uint16_t mask)
+{
 	uint32_t swfw_sync;
 	uint32_t swmask = mask << SWFW_SOFT_SHIFT;
 	uint32_t fwmask = mask << SWFW_FIRM_SHIFT;
 	int timeout;
 	DPRINTF(sc, WM_DEBUG_LOCK, ("%s: %s called\n",
 		device_xname(sc->sc_dev), __func__));
 	if (sc->sc_type == WM_T_80003)
 		timeout = 50;
 	else
 		timeout = 200;
 	while (timeout) {
 		if (wm_get_swsm_semaphore(sc)) {
 			aprint_error_dev(sc->sc_dev,
 			    "%s: failed to get semaphore\n",
 			    __func__);
 			return -1;
+		}
 		swfw_sync = CSR_READ(sc, WMREG_SW_FW_SYNC);
 		if ((swfw_sync & (swmask | fwmask)) == 0) {
 			swfw_sync |= swmask;
 			CSR_WRITE(sc, WMREG_SW_FW_SYNC, swfw_sync);
 			wm_put_swsm_semaphore(sc);
 			return 0;
+		}
 		wm_put_swsm_semaphore(sc);
 		delay(5000);
 		timeout--;
+	}
 	device_printf(sc->sc_dev,
 	    "failed to get swfw semaphore mask 0x%x swfw 0x%x\n",
 	    mask, swfw_sync);
 	return -1;
+}
 static void
 wm_put_swfw_semaphore(struct wm_softc *sc, uint16_t mask)
+{
 	uint32_t swfw_sync;
 	DPRINTF(sc, WM_DEBUG_LOCK, ("%s: %s called\n",
 		device_xname(sc->sc_dev), __func__));
 	while (wm_get_swsm_semaphore(sc) != 0)
 		continue;
 	swfw_sync = CSR_READ(sc, WMREG_SW_FW_SYNC);
 	swfw_sync &= ~(mask << SWFW_SOFT_SHIFT);
 	CSR_WRITE(sc, WMREG_SW_FW_SYNC, swfw_sync);
 	wm_put_swsm_semaphore(sc);
+}
 static int
 wm_get_nvm_80003(struct wm_softc *sc)
+{
 	int rv;
 	DPRINTF(sc, WM_DEBUG_LOCK | WM_DEBUG_NVM, ("%s: %s called\n",
 		device_xname(sc->sc_dev), __func__));
 	if ((rv = wm_get_swfw_semaphore(sc, SWFW_EEP_SM)) != 0) {
 		aprint_error_dev(sc->sc_dev,
 		    "%s: failed to get semaphore(SWFW)\n", __func__);
 		return rv;
+	}
 	if (((sc->sc_flags & WM_F_LOCK_EECD) != 0)
 	    && (rv = wm_get_eecd(sc)) != 0) {
 		aprint_error_dev(sc->sc_dev,
 		    "%s: failed to get semaphore(EECD)\n", __func__);
 		wm_put_swfw_semaphore(sc, SWFW_EEP_SM);
 		return rv;
+	}
 	return 0;
+}
 static void
 wm_put_nvm_80003(struct wm_softc *sc)
+{
 	DPRINTF(sc, WM_DEBUG_LOCK, ("%s: %s called\n",
 		device_xname(sc->sc_dev), __func__));
 	if ((sc->sc_flags & WM_F_LOCK_EECD) != 0)
 		wm_put_eecd(sc);
 	wm_put_swfw_semaphore(sc, SWFW_EEP_SM);
+}
 static int
 wm_get_nvm_82571(struct wm_softc *sc)
+{
 	int rv;
 	DPRINTF(sc, WM_DEBUG_LOCK, ("%s: %s called\n",
 		device_xname(sc->sc_dev), __func__));
 	if ((rv = wm_get_swsm_semaphore(sc)) != 0)
 		return rv;
 	switch (sc->sc_type) {
 	case WM_T_82573:
 		break;
 	default:
 		if ((sc->sc_flags & WM_F_LOCK_EECD) != 0)
 			rv = wm_get_eecd(sc);
 		break;
+	}
 	if (rv != 0) {
 		aprint_error_dev(sc->sc_dev,
 		    "%s: failed to get semaphore\n",
 		    __func__);
 		wm_put_swsm_semaphore(sc);
+	}
 	return rv;
+}
 static void
 wm_put_nvm_82571(struct wm_softc *sc)
+{
 	DPRINTF(sc, WM_DEBUG_LOCK, ("%s: %s called\n",
 		device_xname(sc->sc_dev), __func__));
 	switch (sc->sc_type) {
 	case WM_T_82573:
 		break;
 	default:
 		if ((sc->sc_flags & WM_F_LOCK_EECD) != 0)
 			wm_put_eecd(sc);
 		break;
+	}
 	wm_put_swsm_semaphore(sc);
+}
 static int
 wm_get_phy_82575(struct wm_softc *sc)
+{
 	DPRINTF(sc, WM_DEBUG_LOCK, ("%s: %s called\n",
 		device_xname(sc->sc_dev), __func__));
 	return wm_get_swfw_semaphore(sc, swfwphysem[sc->sc_funcid]);
+}
 static void
 wm_put_phy_82575(struct wm_softc *sc)
+{
 	DPRINTF(sc, WM_DEBUG_LOCK, ("%s: %s called\n",
 		device_xname(sc->sc_dev), __func__));
 	wm_put_swfw_semaphore(sc, swfwphysem[sc->sc_funcid]);
+}
 static int
 wm_get_swfwhw_semaphore(struct wm_softc *sc)
+{
 	uint32_t ext_ctrl;
 	int timeout = 200;
 	DPRINTF(sc, WM_DEBUG_LOCK, ("%s: %s called\n",
 		device_xname(sc->sc_dev), __func__));
 	mutex_enter(sc->sc_ich_phymtx); /* Use PHY mtx for both PHY and NVM */
 	for (timeout = 0; timeout < 200; timeout++) {
 		ext_ctrl = CSR_READ(sc, WMREG_EXTCNFCTR);
 		ext_ctrl |= EXTCNFCTR_MDIO_SW_OWNERSHIP;
 		CSR_WRITE(sc, WMREG_EXTCNFCTR, ext_ctrl);
 		ext_ctrl = CSR_READ(sc, WMREG_EXTCNFCTR);
 		if (ext_ctrl & EXTCNFCTR_MDIO_SW_OWNERSHIP)
 			return 0;
 		delay(5000);
+	}
 	device_printf(sc->sc_dev,
 	    "failed to get swfwhw semaphore ext_ctrl 0x%x\n", ext_ctrl);
 	mutex_exit(sc->sc_ich_phymtx); /* Use PHY mtx for both PHY and NVM */
 	return -1;
+}
 static void
 wm_put_swfwhw_semaphore(struct wm_softc *sc)
+{
 	uint32_t ext_ctrl;
 	DPRINTF(sc, WM_DEBUG_LOCK, ("%s: %s called\n",
 		device_xname(sc->sc_dev), __func__));
 	ext_ctrl = CSR_READ(sc, WMREG_EXTCNFCTR);
 	ext_ctrl &= ~EXTCNFCTR_MDIO_SW_OWNERSHIP;
 	CSR_WRITE(sc, WMREG_EXTCNFCTR, ext_ctrl);
 	mutex_exit(sc->sc_ich_phymtx); /* Use PHY mtx for both PHY and NVM */
+}
 static int
 wm_get_swflag_ich8lan(struct wm_softc *sc)
+{
 	uint32_t ext_ctrl;
 	int timeout;
 	DPRINTF(sc, WM_DEBUG_LOCK, ("%s: %s called\n",
 		device_xname(sc->sc_dev), __func__));
 	mutex_enter(sc->sc_ich_phymtx);
 	for (timeout = 0; timeout < WM_PHY_CFG_TIMEOUT; timeout++) {
 		ext_ctrl = CSR_READ(sc, WMREG_EXTCNFCTR);
 		if ((ext_ctrl & EXTCNFCTR_MDIO_SW_OWNERSHIP) == 0)
 			break;
 		delay(1000);
+	}
 	if (timeout >= WM_PHY_CFG_TIMEOUT) {
 		device_printf(sc->sc_dev,
 		    "SW has already locked the resource\n");
 		goto out;
+	}
 	ext_ctrl |= EXTCNFCTR_MDIO_SW_OWNERSHIP;
 	CSR_WRITE(sc, WMREG_EXTCNFCTR, ext_ctrl);
 	for (timeout = 0; timeout < 1000; timeout++) {
 		ext_ctrl = CSR_READ(sc, WMREG_EXTCNFCTR);
 		if (ext_ctrl & EXTCNFCTR_MDIO_SW_OWNERSHIP)
 			break;
 		delay(1000);
+	}
 	if (timeout >= 1000) {
 		device_printf(sc->sc_dev, "failed to acquire semaphore\n");
 		ext_ctrl &= ~EXTCNFCTR_MDIO_SW_OWNERSHIP;
 		CSR_WRITE(sc, WMREG_EXTCNFCTR, ext_ctrl);
 		goto out;
+	}
 	return 0;
 out:
 	mutex_exit(sc->sc_ich_phymtx);
 	return -1;
+}
 static void
 wm_put_swflag_ich8lan(struct wm_softc *sc)
+{
 	uint32_t ext_ctrl;
 	DPRINTF(sc, WM_DEBUG_LOCK, ("%s: %s called\n",
 		device_xname(sc->sc_dev), __func__));
 	ext_ctrl = CSR_READ(sc, WMREG_EXTCNFCTR);
 	if (ext_ctrl & EXTCNFCTR_MDIO_SW_OWNERSHIP) {
 		ext_ctrl &= ~EXTCNFCTR_MDIO_SW_OWNERSHIP;
 		CSR_WRITE(sc, WMREG_EXTCNFCTR, ext_ctrl);
 	} else
 		device_printf(sc->sc_dev, "Semaphore unexpectedly released\n");
 	mutex_exit(sc->sc_ich_phymtx);
+}
 static int
 wm_get_nvm_ich8lan(struct wm_softc *sc)
+{
 	DPRINTF(sc, WM_DEBUG_LOCK, ("%s: %s called\n",
 		device_xname(sc->sc_dev), __func__));
 	mutex_enter(sc->sc_ich_nvmmtx);
 	return 0;
+}
 static void
 wm_put_nvm_ich8lan(struct wm_softc *sc)
+{
 	DPRINTF(sc, WM_DEBUG_LOCK, ("%s: %s called\n",
 		device_xname(sc->sc_dev), __func__));
 	mutex_exit(sc->sc_ich_nvmmtx);
+}
 static int
 wm_get_hw_semaphore_82573(struct wm_softc *sc)
+{
 	int i = 0;
 	uint32_t reg;
 	DPRINTF(sc, WM_DEBUG_LOCK, ("%s: %s called\n",
 		device_xname(sc->sc_dev), __func__));
 	reg = CSR_READ(sc, WMREG_EXTCNFCTR);
 	do {
 		CSR_WRITE(sc, WMREG_EXTCNFCTR,
 		    reg | EXTCNFCTR_MDIO_SW_OWNERSHIP);
 		reg = CSR_READ(sc, WMREG_EXTCNFCTR);
 		if ((reg & EXTCNFCTR_MDIO_SW_OWNERSHIP) != 0)
 			break;
 		delay(2*1000);
 		i++;
 	} while (i < WM_MDIO_OWNERSHIP_TIMEOUT);
 	if (i == WM_MDIO_OWNERSHIP_TIMEOUT) {
 		wm_put_hw_semaphore_82573(sc);
 		log(LOG_ERR, "%s: Driver can't access the PHY\n",
 		    device_xname(sc->sc_dev));
 		return -1;
+	}
 	return 0;
+}
 static void
 wm_put_hw_semaphore_82573(struct wm_softc *sc)
+{
 	uint32_t reg;
 	DPRINTF(sc, WM_DEBUG_LOCK, ("%s: %s called\n",
 		device_xname(sc->sc_dev), __func__));
 	reg = CSR_READ(sc, WMREG_EXTCNFCTR);
 	reg &= ~EXTCNFCTR_MDIO_SW_OWNERSHIP;
 	CSR_WRITE(sc, WMREG_EXTCNFCTR, reg);
+}
 /*
  * Management mode and power management related subroutines.
  * BMC, AMT, suspend/resume and EEE.
  */
 #ifdef WM_WOL
 static int
 wm_check_mng_mode(struct wm_softc *sc)
+{
 	int rv;
 	switch (sc->sc_type) {
 	case WM_T_ICH8:
 	case WM_T_ICH9:
 	case WM_T_ICH10:
 	case WM_T_PCH:
 	case WM_T_PCH2:
 	case WM_T_PCH_LPT:
 	case WM_T_PCH_SPT:
 	case WM_T_PCH_CNP:
 	case WM_T_PCH_TGP:
 		rv = wm_check_mng_mode_ich8lan(sc);
 		break;
 	case WM_T_82574:
 	case WM_T_82583:
 		rv = wm_check_mng_mode_82574(sc);
 		break;
 	case WM_T_82571:
 	case WM_T_82572:
 	case WM_T_82573:
 	case WM_T_80003:
 		rv = wm_check_mng_mode_generic(sc);
 		break;
 	default:
 		/* Noting to do */
 		rv = 0;
 		break;
+	}
 	return rv;
+}
 static int
 wm_check_mng_mode_ich8lan(struct wm_softc *sc)
+{
 	uint32_t fwsm;
 	fwsm = CSR_READ(sc, WMREG_FWSM);
 	if (((fwsm & FWSM_FW_VALID) != 0)
 	    && (__SHIFTOUT(fwsm, FWSM_MODE) == MNG_ICH_IAMT_MODE))
 		return 1;
 	return 0;
+}
 static int
 wm_check_mng_mode_82574(struct wm_softc *sc)
+{
 	uint16_t data;
 	wm_nvm_read(sc, NVM_OFF_CFG2, 1, &data);
 	if ((data & NVM_CFG2_MNGM_MASK) != 0)
 		return 1;
 	return 0;
+}
 static int
 wm_check_mng_mode_generic(struct wm_softc *sc)
+{
 	uint32_t fwsm;
 	fwsm = CSR_READ(sc, WMREG_FWSM);
 	if (__SHIFTOUT(fwsm, FWSM_MODE) == MNG_IAMT_MODE)
 		return 1;
 	return 0;
+}
 #endif /* WM_WOL */
 static int
 wm_enable_mng_pass_thru(struct wm_softc *sc)
+{
 	uint32_t manc, fwsm, factps;
 	if ((sc->sc_flags & WM_F_ASF_FIRMWARE_PRES) == 0)
 		return 0;
 	manc = CSR_READ(sc, WMREG_MANC);
 	DPRINTF(sc, WM_DEBUG_MANAGE, ("%s: MANC (%08x)\n",
 		device_xname(sc->sc_dev), manc));
 	if ((manc & MANC_RECV_TCO_EN) == 0)
 		return 0;
 	if ((sc->sc_flags & WM_F_ARC_SUBSYS_VALID) != 0) {
 		fwsm = CSR_READ(sc, WMREG_FWSM);
 		factps = CSR_READ(sc, WMREG_FACTPS);
 		if (((factps & FACTPS_MNGCG) == 0)
 		    && (__SHIFTOUT(fwsm, FWSM_MODE) == MNG_ICH_IAMT_MODE))
 			return 1;
 	} else if ((sc->sc_type == WM_T_82574) || (sc->sc_type == WM_T_82583)){
 		uint16_t data;
 		factps = CSR_READ(sc, WMREG_FACTPS);
 		wm_nvm_read(sc, NVM_OFF_CFG2, 1, &data);
 		DPRINTF(sc, WM_DEBUG_MANAGE, ("%s: FACTPS = %08x, CFG2=%04x\n",
 			device_xname(sc->sc_dev), factps, data));
 		if (((factps & FACTPS_MNGCG) == 0)
 		    && ((data & NVM_CFG2_MNGM_MASK)
 			== (NVM_CFG2_MNGM_PT << NVM_CFG2_MNGM_SHIFT)))
 			return 1;
 	} else if (((manc & MANC_SMBUS_EN) != 0)
 	    && ((manc & MANC_ASF_EN) == 0))
 		return 1;
 	return 0;
+}
 static bool
 wm_phy_resetisblocked(struct wm_softc *sc)
+{
 	bool blocked = false;
 	uint32_t reg;
 	int i = 0;
 	DPRINTF(sc, WM_DEBUG_INIT, ("%s: %s called\n",
 		device_xname(sc->sc_dev), __func__));
 	switch (sc->sc_type) {
 	case WM_T_ICH8:
 	case WM_T_ICH9:
 	case WM_T_ICH10:
 	case WM_T_PCH:
 	case WM_T_PCH2:
 	case WM_T_PCH_LPT:
 	case WM_T_PCH_SPT:
 	case WM_T_PCH_CNP:
 	case WM_T_PCH_TGP:
 		do {
 			reg = CSR_READ(sc, WMREG_FWSM);
 			if ((reg & FWSM_RSPCIPHY) == 0) {
 				blocked = true;
 				delay(10*1000);
 				continue;
+			}
 			blocked = false;
 		} while (blocked && (i++ < 30));
 		return blocked;
 		break;
 	case WM_T_82571:
 	case WM_T_82572:
 	case WM_T_82573:
 	case WM_T_82574:
 	case WM_T_82583:
 	case WM_T_80003:
 		reg = CSR_READ(sc, WMREG_MANC);
 		if ((reg & MANC_BLK_PHY_RST_ON_IDE) != 0)
 			return true;
 		else
 			return false;
 		break;
 	default:
 		/* No problem */
 		break;
+	}
 	return false;
+}
 static void
 wm_get_hw_control(struct wm_softc *sc)
+{
 	uint32_t reg;
 	DPRINTF(sc, WM_DEBUG_LOCK, ("%s: %s called\n",
 		device_xname(sc->sc_dev), __func__));
 	if (sc->sc_type == WM_T_82573) {
 		reg = CSR_READ(sc, WMREG_SWSM);
 		CSR_WRITE(sc, WMREG_SWSM, reg | SWSM_DRV_LOAD);
 	} else if (sc->sc_type >= WM_T_82571) {
 		reg = CSR_READ(sc, WMREG_CTRL_EXT);
 		CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_DRV_LOAD);
+	}
+}
 static void
 wm_release_hw_control(struct wm_softc *sc)
+{
 	uint32_t reg;
 	DPRINTF(sc, WM_DEBUG_LOCK, ("%s: %s called\n",
 		device_xname(sc->sc_dev), __func__));
 	if (sc->sc_type == WM_T_82573) {
 		reg = CSR_READ(sc, WMREG_SWSM);
 		CSR_WRITE(sc, WMREG_SWSM, reg & ~SWSM_DRV_LOAD);
 	} else if (sc->sc_type >= WM_T_82571) {
 		reg = CSR_READ(sc, WMREG_CTRL_EXT);
 		CSR_WRITE(sc, WMREG_CTRL_EXT, reg & ~CTRL_EXT_DRV_LOAD);
+	}
+}
 static void
 wm_gate_hw_phy_config_ich8lan(struct wm_softc *sc, bool gate)
+{
 	uint32_t reg;
 	DPRINTF(sc, WM_DEBUG_INIT, ("%s: %s called\n",
 		device_xname(sc->sc_dev), __func__));
 	if (sc->sc_type < WM_T_PCH2)
 		return;
 	reg = CSR_READ(sc, WMREG_EXTCNFCTR);
 	if (gate)
 		reg |= EXTCNFCTR_GATE_PHY_CFG;
 	else
 		reg &= ~EXTCNFCTR_GATE_PHY_CFG;
 	CSR_WRITE(sc, WMREG_EXTCNFCTR, reg);
+}
 static int
 wm_init_phy_workarounds_pchlan(struct wm_softc *sc)
+{
 	uint32_t fwsm, reg;
 	int rv;
 	DPRINTF(sc, WM_DEBUG_INIT, ("%s: %s called\n",
 		device_xname(sc->sc_dev), __func__));
 	/* Gate automatic PHY configuration by hardware on non-managed 82579 */
 	wm_gate_hw_phy_config_ich8lan(sc, true);
 	/* Disable ULP */
 	wm_ulp_disable(sc);
 	/* Acquire PHY semaphore */
 	rv = sc->phy.acquire(sc);
 	if (rv != 0) {
 		DPRINTF(sc, WM_DEBUG_INIT,
 		    ("%s: %s: failed\n", device_xname(sc->sc_dev), __func__));
 		return rv;
+	}
 	/* The MAC-PHY interconnect may be in SMBus mode.  If the PHY is
 	 * inaccessible and resetting the PHY is not blocked, toggle the
 	 * LANPHYPC Value bit to force the interconnect to PCIe mode.
 	 */
 	fwsm = CSR_READ(sc, WMREG_FWSM);
 	switch (sc->sc_type) {
 	case WM_T_PCH_LPT:
 	case WM_T_PCH_SPT:
 	case WM_T_PCH_CNP:
 	case WM_T_PCH_TGP:
 		if (wm_phy_is_accessible_pchlan(sc))
 			break;
 		/* Before toggling LANPHYPC, see if PHY is accessible by
 		 * forcing MAC to SMBus mode first.
 		 */
 		reg = CSR_READ(sc, WMREG_CTRL_EXT);
 		reg |= CTRL_EXT_FORCE_SMBUS;
 		CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
 #if 0
 		/* XXX Isn't this required??? */
 		CSR_WRITE_FLUSH(sc);
 #endif
 		/* Wait 50 milliseconds for MAC to finish any retries
 		 * that it might be trying to perform from previous
 		 * attempts to acknowledge any phy read requests.
 		 */
 		delay(50 * 1000);
 		/* FALLTHROUGH */
 	case WM_T_PCH2:
 		if (wm_phy_is_accessible_pchlan(sc) == true)
 			break;
 		/* FALLTHROUGH */
 	case WM_T_PCH:
 		if (sc->sc_type == WM_T_PCH)
 			if ((fwsm & FWSM_FW_VALID) != 0)
 				break;
 		if (wm_phy_resetisblocked(sc) == true) {
 			device_printf(sc->sc_dev, "XXX reset is blocked(2)\n");
 			break;
+		}
 		/* Toggle LANPHYPC Value bit */
 		wm_toggle_lanphypc_pch_lpt(sc);
 		if (sc->sc_type >= WM_T_PCH_LPT) {
 			if (wm_phy_is_accessible_pchlan(sc) == true)
 				break;
 			/* Toggling LANPHYPC brings the PHY out of SMBus mode
 			 * so ensure that the MAC is also out of SMBus mode
 			 */
 			reg = CSR_READ(sc, WMREG_CTRL_EXT);
 			reg &= ~CTRL_EXT_FORCE_SMBUS;
 			CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
 			if (wm_phy_is_accessible_pchlan(sc) == true)
 				break;
 			rv = -1;
+		}
 		break;
 	default:
 		break;
+	}
 	/* Release semaphore */
 	sc->phy.release(sc);
 	if (rv == 0) {
 		/* Check to see if able to reset PHY.  Print error if not */
 		if (wm_phy_resetisblocked(sc)) {
 			device_printf(sc->sc_dev, "XXX reset is blocked(3)\n");
 			goto out;
+		}
 		/* Reset the PHY before any access to it.  Doing so, ensures
 		 * that the PHY is in a known good state before we read/write
 		 * PHY registers.  The generic reset is sufficient here,
 		 * because we haven't determined the PHY type yet.
 		 */
 		if (wm_reset_phy(sc) != 0)
 			goto out;
 		/* On a successful reset, possibly need to wait for the PHY
 		 * to quiesce to an accessible state before returning control
 		 * to the calling function.  If the PHY does not quiesce, then
 		 * return E1000E_BLK_PHY_RESET, as this is the condition that
 		 *  the PHY is in.
 		 */
 		if (wm_phy_resetisblocked(sc))
 			device_printf(sc->sc_dev, "XXX reset is blocked(4)\n");
+	}
 out:
 	/* Ungate automatic PHY configuration on non-managed 82579 */
 	if ((sc->sc_type == WM_T_PCH2) && ((fwsm & FWSM_FW_VALID) == 0)) {
 		delay(10*1000);
 		wm_gate_hw_phy_config_ich8lan(sc, false);
+	}
 	return 0;
+}
 static void
 wm_init_manageability(struct wm_softc *sc)
+{
 	DPRINTF(sc, WM_DEBUG_INIT, ("%s: %s called\n",
 		device_xname(sc->sc_dev), __func__));
 	if (sc->sc_flags & WM_F_HAS_MANAGE) {
 		uint32_t manc2h = CSR_READ(sc, WMREG_MANC2H);
 		uint32_t manc = CSR_READ(sc, WMREG_MANC);
 		/* Disable hardware interception of ARP */
 		manc &= ~MANC_ARP_EN;
 		/* Enable receiving management packets to the host */
 		if (sc->sc_type >= WM_T_82571) {
 			manc |= MANC_EN_MNG2HOST;
 			manc2h |= MANC2H_PORT_623 | MANC2H_PORT_624;
 			CSR_WRITE(sc, WMREG_MANC2H, manc2h);
+		}
 		CSR_WRITE(sc, WMREG_MANC, manc);
+	}
+}
 static void
 wm_release_manageability(struct wm_softc *sc)
+{
 	if (sc->sc_flags & WM_F_HAS_MANAGE) {
 		uint32_t manc = CSR_READ(sc, WMREG_MANC);
 		manc |= MANC_ARP_EN;
 		if (sc->sc_type >= WM_T_82571)
 			manc &= ~MANC_EN_MNG2HOST;
 		CSR_WRITE(sc, WMREG_MANC, manc);
+	}
+}
 static void
 wm_get_wakeup(struct wm_softc *sc)
+{
 	/* 0: HAS_AMT, ARC_SUBSYS_VALID, ASF_FIRMWARE_PRES */
 	switch (sc->sc_type) {
 	case WM_T_82573:
 	case WM_T_82583:
 		sc->sc_flags |= WM_F_HAS_AMT;
 		/* FALLTHROUGH */
 	case WM_T_80003:
 	case WM_T_82575:
 	case WM_T_82576:
 	case WM_T_82580:
 	case WM_T_I350:
 	case WM_T_I354:
 		if ((CSR_READ(sc, WMREG_FWSM) & FWSM_MODE) != 0)
 			sc->sc_flags |= WM_F_ARC_SUBSYS_VALID;
 		/* FALLTHROUGH */
 	case WM_T_82541:
 	case WM_T_82541_2:
 	case WM_T_82547:
 	case WM_T_82547_2:
 	case WM_T_82571:
 	case WM_T_82572:
 	case WM_T_82574:
 		sc->sc_flags |= WM_F_ASF_FIRMWARE_PRES;
 		break;
 	case WM_T_ICH8:
 	case WM_T_ICH9:
 	case WM_T_ICH10:
 	case WM_T_PCH:
 	case WM_T_PCH2:
 	case WM_T_PCH_LPT:
 	case WM_T_PCH_SPT:
 	case WM_T_PCH_CNP:
 	case WM_T_PCH_TGP:
 		sc->sc_flags |= WM_F_HAS_AMT;
 		sc->sc_flags |= WM_F_ASF_FIRMWARE_PRES;
 		break;
 	default:
 		break;
+	}
 	/* 1: HAS_MANAGE */
 	if (wm_enable_mng_pass_thru(sc) != 0)
 		sc->sc_flags |= WM_F_HAS_MANAGE;
 	/*

 @@ -1,1785 +1,1788 @@
-/*	$NetBSD: if_wmreg.h,v 1.98.6.18 2023/10/18 14:41:54 martin Exp $	*/
+/*	$NetBSD: if_wmreg.h,v 1.98.6.19 2024/02/29 10:46:28 martin Exp $	*/
 /*
  * Copyright (c) 2001 Wasabi Systems, Inc.
  * All rights reserved.
+ *
  * Written by Jason R. Thorpe for Wasabi Systems, Inc.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  * 3. All advertising materials mentioning features or use of this software
  *    must display the following acknowledgement:
  *	This product includes software developed for the NetBSD Project by
  *	Wasabi Systems, Inc.
  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
  *    or promote products derived from this software without specific prior
  *    written permission.
+ *
  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 /******************************************************************************
   Copyright (c) 2001-2012, Intel Corporation
   All rights reserved.
   Redistribution and use in source and binary forms, with or without
   modification, are permitted provided that the following conditions are met:
 . Redistributions of source code must retain the above copyright notice,
       this list of conditions and the following disclaimer.
 . Redistributions in binary form must reproduce the above copyright
       notice, this list of conditions and the following disclaimer in the
       documentation and/or other materials provided with the distribution.
 . Neither the name of the Intel Corporation nor the names of its
       contributors may be used to endorse or promote products derived from
       this software without specific prior written permission.
   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE.
 ******************************************************************************/
 /*
  * Register description for the Intel i82542 (``Wiseman''),
  * i82543 (``Livengood''), and i82544 (``Cordova'') Gigabit
  * Ethernet chips.
  */
 /*
  * The wiseman supports 64-bit PCI addressing.  This structure
  * describes the address in descriptors.
  */
 typedef struct wiseman_addr {
 	uint32_t	wa_low;		/* low-order 32 bits */
 	uint32_t	wa_high;	/* high-order 32 bits */
 } __packed wiseman_addr_t;
 /*
  * The Wiseman receive descriptor.
+ *
  * The receive descriptor ring must be aligned to a 4K boundary,
  * and there must be an even multiple of 8 descriptors in the ring.
  */
 typedef struct wiseman_rxdesc {
 	volatile wiseman_addr_t	wrx_addr;	/* buffer address */
 	volatile uint16_t	wrx_len;	/* buffer length */
 	volatile uint16_t	wrx_cksum;	/* checksum (starting at PCSS)*/
 	volatile uint8_t	wrx_status;	/* Rx status */
 	volatile uint8_t	wrx_errors;	/* Rx errors */
 	volatile uint16_t	wrx_special;	/* special field (VLAN, etc.) */
 } __packed wiseman_rxdesc_t;
 /* wrx_status bits */
 #define	WRX_ST_DD	__BIT(0)	/* descriptor done */
 #define	WRX_ST_EOP	__BIT(1)	/* end of packet */
 #define	WRX_ST_IXSM	__BIT(2)	/* ignore checksum indication */
 #define	WRX_ST_VP	__BIT(3)	/* VLAN packet */
 #define	WRX_ST_BPDU	__BIT(4)	/* ??? */
 #define	WRX_ST_TCPCS	__BIT(5)	/* TCP checksum performed */
 #define	WRX_ST_IPCS	__BIT(6)	/* IP checksum performed */
 #define	WRX_ST_PIF	__BIT(7)	/* passed in-exact filter */
 /* wrx_error bits */
 #define	WRX_ER_CE	__BIT(0)	/* CRC error */
 #define	WRX_ER_SE	__BIT(1)	/* symbol error */
 #define	WRX_ER_SEQ	__BIT(2)	/* sequence error */
 #define	WRX_ER_ICE	__BIT(3)	/* ??? */
 #define	WRX_ER_CXE	__BIT(4)	/* carrier extension error */
 #define	WRX_ER_TCPE	__BIT(5)	/* TCP checksum error */
 #define	WRX_ER_IPE	__BIT(6)	/* IP checksum error */
 #define	WRX_ER_RXE	__BIT(7)	/* Rx data error */
 /* wrx_special field for VLAN packets */
 #define	WRX_VLAN_ID(x)	((x) & 0x0fff)	/* VLAN identifier */
 #define	WRX_VLAN_CFI	__BIT(12)	/* Canonical Form Indicator */
 #define	WRX_VLAN_PRI(x)	(((x) >> 13) & 7)/* VLAN priority field */
 /* extended RX descriptor for 82574 */
 typedef union ext_rxdesc {
 	struct {
 		uint64_t erxd_addr;	/* Packet Buffer Address */
 		uint64_t erxd_dd;	/* 63:1 reserved, 0 DD */
 	} erx_data;
 	struct {
 		uint32_t erxc_mrq;	/*
 					 * 31:13 reserved
 					 * 12:8 Rx queue associated with the packet
 					 * 7:4 reserved 3:0 RSS Type
 					 */
 		uint32_t erxc_rsshash;	/* RSS Hash or {Fragment Checksum, IP identification } */
 		uint32_t erxc_err_stat;	/* 31:20 Extended Error, 19:0 Extened Status */
 		uint16_t erxc_pktlen;	/* PKT_LEN */
 		uint16_t erxc_vlan;	/* VLAN Tag */
 	} erx_ctx;
 } __packed ext_rxdesc_t;
 #define	EXTRXD_DD_MASK		__BIT(0)
 /*
  * erxc_rsshash is used for below 2 patterns
  *     (1) Fragment Checksum and IP identification
  *         - Fragment Checksum is valid
  *           when RXCSUM.PCSD cleared and RXCSUM.IPPCSE bit is set
  *         - IP identification is valid
  *           when RXCSUM.PCSD cleared and RXCSUM.IPPCSE bit is set
  *     (2) RSS Hash
  *         when RXCSUM.PCSD bit is set
  */
 #define	EXTRXC_IP_ID_MASK	__BITS(15,0)
 #define	EXTRXC_FRAG_CSUM_MASK	__BITS(31,16)
 #define	EXTRXC_IP_ID(rsshash)	__SHIFTOUT(rsshash,ERXC_IP_ID_MASK)
 #define	EXTRXC_FRAG_CSUM(rsshash) __SHIFTOUT(rsshash,ERXC_FRAG_CSUM_MASK)
 /* macros for nrxc_mrq */
 #define	EXTRXC_RSS_TYPE_MASK		__BITS(3,0)
 /* __BITS(7,4) is reserved */
 #define	EXTRXC_QUEUE_MASK		__BITS(12,8)
 /* __BITS(31,13) is reserved */
 #define	EXTRXC_RSS_TYPE(mrq)	__SHIFTOUT(mrq,EXTRXC_RSS_TYPE_MASK)
 #define	EXTRXC_QUEUE(mrq)	__SHIFTOUT(mrq,EXTRXC_QUEUE_MASK)
 #define	EXTRXC_RSS_TYPE_NONE		0x0 /* No hash computation done. */
 #define	EXTRXC_RSS_TYPE_TCP_IPV4	0x1
 #define	EXTRXC_RSS_TYPE_IPV4		0x2
 #define	EXTRXC_RSS_TYPE_TCP_IPV6	0x3
 #define	EXTRXC_RSS_TYPE_IPV6_EX		0x4
 #define	EXTRXC_RSS_TYPE_IPV6		0x5
 /*0x6:0xF is reserved. */
 #define	EXTRXC_STATUS_MASK	__BITS(19,0)
 #define	EXTRXC_ERROR_MASK	__BITS(31,20)
 #define	EXTRXC_STATUS(err_stat)	__SHIFTOUT(err_stat,EXTRXC_STATUS_MASK)
 #define	EXTRXC_ERROR(err_stat)	__SHIFTOUT(err_stat,EXTRXC_ERROR_MASK)
 /* 3:0 is reserved. */
 #define	EXTRXC_ERROR_CE		__BIT(4) /* The same as WRX_ER_CE. */
 #define	EXTRXC_ERROR_SE		__BIT(5) /* The same as WRX_ER_SE. */
 #define	EXTRXC_ERROR_SEQ	__BIT(6) /* The same as WRX_ER_SEQ. */
 /* 7 is reserved. */
 #define	EXTRXC_ERROR_CXE	__BIT(8) /* The same as WRX_ER_CXE. */
 #define	EXTRXC_ERROR_TCPE	__BIT(9) /* The same as WRX_ER_TCPE. */
 #define	EXTRXC_ERROR_IPE	__BIT(10) /* The same as WRX_ER_IPE. */
 #define	EXTRXC_ERROR_RXE	__BIT(11) /* The same as WRX_ER_RXE. */
 #define	EXTRXC_STATUS_DD		__BIT(0) /* The same as WRX_ST_DD. */
 #define	EXTRXC_STATUS_EOP		__BIT(1) /* The same as WRX_ST_EOP. */
 /* 2 is reserved. */
 #define	EXTRXC_STATUS_VP		__BIT(3) /* The same as WRX_ST_VP. */
 #define	EXTRXC_STATUS_UDPCS		__BIT(4) /* UDP checksum calculated on packet. */
 #define	EXTRXC_STATUS_TCPCS		__BIT(5) /* The same as WRX_ST_TCPCS. */
 #define	EXTRXC_STATUS_IPCS		__BIT(6) /* The same as WRX_ST_IPCS. */
 /* 7 is reserved. */
 #define	EXTRXC_STATUS_TST		__BIT(8) /* Time stamp taken. */
 #define	EXTRXC_STATUS_IPIDV		__BIT(9) /* IP identification valid. */
 #define	EXTRXC_STATUS_UDPV		__BIT(10) /* Valid UDP XSUM. */
 /* 14:11 is reserved. */
 #define	EXTRXC_STATUS_ACK		__BIT(15) /* ACK packet indication. */
 #define	EXTRXC_STATUS_PKTTYPE_MASK	__BITS(19,16)
 #define	EXTRXC_STATUS_PKTTYPE(status)	__SHIFTOUT(status,EXTRXC_STATUS_PKTTYPE_MASK)
 /* advanced RX descriptor for 82575 and newer */
 typedef union nq_rxdesc {
 	struct {
 		uint64_t nrxd_paddr;	/* 63:1 Packet Buffer Address, 0 A0/NSE */
 		uint64_t nrxd_haddr;	/* 63:1 HEader Buffer Address, 0 DD */
 	} nqrx_data;
 	struct {
 		uint32_t nrxc_misc;	/*
 					 * 31: SPH, 30:21 HDR_LEN[9:0],
 					 * 20:19 HDR_LEN[11:10], 18:17 RSV,
 					 * 16:4 Packet Type 3:0 RSS Type
 					 */
 		uint32_t nrxc_rsshash;	/* RSS Hash or {Fragment Checksum, IP identification } */
 		uint32_t nrxc_err_stat;	/* 31:20 Extended Error, 19:0 Extened Status */
 		uint16_t nrxc_pktlen;	/* PKT_LEN */
 		uint16_t nrxc_vlan;	/* VLAN Tag */
 	} nqrx_ctx;
 } __packed nq_rxdesc_t;
 /* for nrxd_paddr macros */
 #define	NQRXD_A0_MASK		__BIT(0)
 #define	NQRXD_NSE_MASK		__BIT(0)
 #define	NQRXD_ADDR_MASK		__BITS(63,1)
 /* for nrxd_haddr macros */
 #define	NQRXD_DD_MASK		__BIT(0)
 /*
  * nrxc_rsshash is used for below 2 patterns
  *     (1) Fragment Checksum and IP identification
  *         - Fragment Checksum is valid
  *           when RXCSUM.PCSD cleared and RXCSUM.IPPCSE bit is set
  *         - IP identification is valid
  *           when RXCSUM.PCSD cleared and RXCSUM.IPPCSE bit is set
  *     (2) RSS Hash
  *         when RXCSUM.PCSD bit is set
  */
 #define	NQRXC_IP_ID_MASK	__BITS(15,0)
 #define	NQRXC_FRAG_CSUM_MASK	__BITS(31,16)
 #define	NQRXC_IP_ID(rsshash)	__SHIFTOUT(rsshash,NRXC_IP_ID_MASK)
 #define	NQRXC_FRAG_CSUM(rsshash) __SHIFTOUT(rsshash,NRXC_FRAG_CSUM_MASK)
 /* macros for nrxc_misc */
 #define	NQRXC_RSS_TYPE_MASK		__BITS(3,0)
 #define	NQRXC_PKT_TYPE_ID_MASK		__BITS(11,4)
 #define	NQRXC_PKT_TYPE_ETQF_INDEX_MASK	__BITS(11,4)
 #define	NQRXC_PKT_TYPE_ETQF_VALID_MASK	__BIT(15)
 #define	NQRXC_PKT_TYPE_VLAN_MASK 	__BIT(16)
 #define	NQRXC_PKT_TYPE_MASK		__BITS(16,4)
 /* __BITS(18,17) is reserved */
 #define	NQRXC_HDRLEN_HIGH_MASK		__BITS(20,19)
 #define	NQRXC_HDRLEN_LOW_MASK		__BITS(30,21)
 #define	NQRXC_SPH_MASK			__BIT(31)
 #define	NQRXC_RSS_TYPE(misc)	__SHIFTOUT(misc,NQRXC_RSS_TYPE_MASK)
 #define	NQRXC_PKT_TYPE_ID(pkttype) \
 		__SHIFTOUT(pkttype,NQRXC_PKT_TYPE_ID_MASK)
 #define	NQRXC_PKT_TYPE(misc)	__SHIFTOUT(misc,NQRXC_PKT_TYPE_MASK)
 #define	NQRXC_PKT_TYPE_ETQF_INDEX(pkttype) \
 		__SHIFTOUT(pkttype,NQRXC_PKT_TYPE_ETQF_INDEX_MASK)
 #define	NQRXC_PKT_TYPE_ETQF_VALID NQRXC_PKT_TYPE_ETQF_VALID_MASK
 #define	NQRXC_PKT_TYPE_VLAN	NQRXC_PKT_TYPE_VLAN_MASK
 #define	NQRXC_HEADER_LEN(misc)	(__SHIFTOUT(misc,NQRXC_HDRLEN_LOW_MASK) \
 		| __SHIFTOUT(misc,NQRXC_HDRLEN_HIGH_MASK) << 10)
 #define	NQRXC_SPH		NQRXC_SPH_MASK
 #define	NQRXC_RSS_TYPE_NONE		0x0 /* No hash computation done. */
 #define	NQRXC_RSS_TYPE_TCP_IPV4		0x1
 #define	NQRXC_RSS_TYPE_IPV4		0x2
 #define	NQRXC_RSS_TYPE_TCP_IPV6		0x3
 #define	NQRXC_RSS_TYPE_IPV6_EX		0x4
 #define	NQRXC_RSS_TYPE_IPV6		0x5
 #define	NQRXC_RSS_TYPE_TCP_IPV6_EX	0x6
 #define	NQRXC_RSS_TYPE_UDP_IPV4		0x7
 #define	NQRXC_RSS_TYPE_UDP_IPV6		0x8
 #define	NQRXC_RSS_TYPE_UDP_IPV6_EX	0x9
 /*0xA:0xF is reserved. */
 #define	NQRXC_PKT_TYPE_IPV4		__BIT(0)
 #define	NQRXC_PKT_TYPE_IPV4E		__BIT(1)
 #define	NQRXC_PKT_TYPE_IPV6		__BIT(2)
 #define	NQRXC_PKT_TYPE_IPV6E		__BIT(3)
 #define	NQRXC_PKT_TYPE_TCP		__BIT(4)
 #define	NQRXC_PKT_TYPE_UDP		__BIT(5)
 #define	NQRXC_PKT_TYPE_SCTP		__BIT(6)
 #define	NQRXC_PKT_TYPE_NFS		__BIT(7)
 #define	NQRXC_STATUS_MASK	__BITS(19,0)
 #define	NQRXC_ERROR_MASK	__BITS(31,20)
 #define	NQRXC_STATUS(err_stat)	__SHIFTOUT(err_stat,NQRXC_STATUS_MASK)
 #define	NQRXC_ERROR(err_stat)	__SHIFTOUT(err_stat,NQRXC_ERROR_MASK)
 /* 2:0 is reserved. */
 #define	NQRXC_ERROR_HB0		__BIT(3) /* Header Buffer Overflow. */
 /* 6:4 is reserved. */
 /* 8:7 is reserved. */
 #define	NQRXC_ERROR_L4E		__BIT(9) /* L4 error indication. */
 #define	NQRXC_ERROR_IPE		__BIT(10) /* The same as WRX_ER_IPE. */
 #define	NQRXC_ERROR_RXE		__BIT(11) /* The same as WRX_ER_RXE. */
 /* XXX Where is WRX_ER_CE, WRX_ER_SE, WRX_ER_SEQ, WRX_ER_CXE error? */
 #define	NQRXC_STATUS_DD		__BIT(0) /* The same as WRX_ST_DD. */
 #define	NQRXC_STATUS_EOP	__BIT(1) /* The same as WRX_ST_EOP. */
 /* 2 is reserved */
 #define	NQRXC_STATUS_VP		__BIT(3) /* The same as WRX_ST_VP. */
 #define	NQRXC_STATUS_UDPCS	__BIT(4) /* UDP checksum or IP payload checksum. */
 					 /* XXX in I210 spec, this bit is the same as WRX_ST_BPDU(is "???" comment) */
 #define	NQRXC_STATUS_L4I	__BIT(5) /* L4 integrity check was done. */
 #define	NQRXC_STATUS_IPCS	__BIT(6) /* The same as WRX_ST_IPCS. */
 #define	NQRXC_STATUS_PIF	__BIT(7) /* The same as WRX_ST_PIF. */
 /* 8 is reserved */
 #define	NQRXC_STATUS_VEXT	__BIT(9) /* First VLAN is found on a bouble VLAN packet. */
 #define	NQRXC_STATUS_UDPV	__BIT(10) /* The packet contains a valid checksum field in a first fragment UDP IPv4 packet. */
 #define	NQRXC_STATUS_LLINT	__BIT(11) /* The packet caused an immediate interrupt. */
 #define	NQRXC_STATUS_STRIPCRC	__BIT(12) /* Ethernet CRC is stripped. */
 /* 14:13 is reserved */
 #define	NQRXC_STATUS_TSIP	__BIT(15) /* Timestamp in packet. */
 #define	NQRXC_STATUS_TS		__BIT(16) /* Time stamped packet. */
 /* 17 is reserved */
 #define	NQRXC_STATUS_LB		__BIT(18) /* Sent by a local virtual machine (VM to VM switch indication). */
 #define	NQRXC_STATUS_MC		__BIT(19) /* Packet received from Manageability Controller */
 					  /* "MBC" in i350 spec */
 /*
  * The Wiseman transmit descriptor.
+ *
  * The transmit descriptor ring must be aligned to a 4K boundary,
  * and there must be an even multiple of 8 descriptors in the ring.
  */
 typedef struct wiseman_tx_fields {
 	uint8_t wtxu_status;		/* Tx status */
 	uint8_t wtxu_options;		/* options */
 	uint16_t wtxu_vlan;		/* VLAN info */
 } __packed wiseman_txfields_t;
 typedef struct wiseman_txdesc {
 	wiseman_addr_t	wtx_addr;	/* buffer address */
 	uint32_t	wtx_cmdlen;	/* command and length */
 	wiseman_txfields_t wtx_fields;	/* fields; see below */
 } __packed wiseman_txdesc_t;
 /* Commands for wtx_cmdlen */
 #define	WTX_CMD_EOP	__BIT(24)	/* end of packet */
 #define	WTX_CMD_IFCS	__BIT(25)	/* insert FCS */
 #define	WTX_CMD_RS	__BIT(27)	/* report status */
 #define	WTX_CMD_RPS	__BIT(28)	/* report packet sent */
 #define	WTX_CMD_DEXT	__BIT(29)	/* descriptor extension */
 #define	WTX_CMD_VLE	__BIT(30)	/* VLAN enable */
 #define	WTX_CMD_IDE	__BIT(31)	/* interrupt delay enable */
 /* Descriptor types (if DEXT is set) */
 #define	WTX_DTYP_MASK	__BIT(20)
 #define	WTX_DTYP_C	__SHIFTIN(0, WTX_DTYP_MASK)	/* context */
 #define	WTX_DTYP_D	__SHIFTIN(1, WTX_DTYP_MASK)	/* data */
 /* wtx_fields status bits */
 #define	WTX_ST_DD	__BIT(0)	/* descriptor done */
 #define	WTX_ST_EC	__BIT(1)	/* excessive collisions */
 #define	WTX_ST_LC	__BIT(2)	/* late collision */
 #define	WTX_ST_TU	__BIT(3)	/* transmit underrun */
 /* wtx_fields option bits for IP/TCP/UDP checksum offload */
 #define	WTX_IXSM	__BIT(0)	/* IP checksum offload */
 #define	WTX_TXSM	__BIT(1)	/* TCP/UDP checksum offload */
 /* Maximum payload per Tx descriptor */
 #define	WTX_MAX_LEN	4096
 /*
  * The Livengood TCP/IP context descriptor.
  */
 struct livengood_tcpip_ctxdesc {
 	uint32_t	tcpip_ipcs;	/* IP checksum context */
 	uint32_t	tcpip_tucs;	/* TCP/UDP checksum context */
 	uint32_t	tcpip_cmdlen;
 	uint32_t	tcpip_seg;	/* TCP segmentation context */
 };
 /* commands for context descriptors */
 #define	WTX_TCPIP_CMD_TCP	__BIT(24)	/* 1 = TCP, 0 = UDP */
 #define	WTX_TCPIP_CMD_IP	__BIT(25)	/* 1 = IPv4, 0 = IPv6 */
 #define	WTX_TCPIP_CMD_TSE	__BIT(26)	/* segmentation context valid */
 #define	WTX_TCPIP_IPCSS(x)	((x) << 0)	/* checksum start */
 #define	WTX_TCPIP_IPCSO(x)	((x) << 8)	/* checksum value offset */
 #define	WTX_TCPIP_IPCSE(x)	((x) << 16)	/* checksum end */
 #define	WTX_TCPIP_TUCSS(x)	((x) << 0)	/* checksum start */
 #define	WTX_TCPIP_TUCSO(x)	((x) << 8)	/* checksum value offset */
 #define	WTX_TCPIP_TUCSE(x)	((x) << 16)	/* checksum end */
 #define	WTX_TCPIP_SEG_STATUS(x)	((x) << 0)
 #define	WTX_TCPIP_SEG_HDRLEN(x)	((x) << 8)
 #define	WTX_TCPIP_SEG_MSS(x)	((x) << 16)
 /*
  * PCI config registers used by the Wiseman.
  */
 #define	WM_PCI_MMBA	PCI_MAPREG_START
 /* registers for FLASH access on ICH8 */
 #define	WM_ICH8_FLASH	0x0014
 #define	WM_PCI_LTR_CAP_LPT	0xa8
 /* XXX Only for PCH_SPT? */
 #define	WM_PCI_DESCRING_STATUS	0xe4
 #define	DESCRING_STATUS_FLUSH_REQ	__BIT(8)
 /*
  * Wiseman Control/Status Registers.
  */
 #define	WMREG_CTRL	0x0000	/* Device Control Register */
 #define	CTRL_FD		__BIT(0)	/* full duplex */
 #define	CTRL_BEM	__BIT(1)	/* big-endian mode */
 #define	CTRL_PRIOR	__BIT(2)	/* 0 = receive, 1 = fair */
 #define	CTRL_GIO_M_DIS	__BIT(2)	/* disabl PCI master access */
 #define	CTRL_LRST	__BIT(3)	/* link reset */
 #define	CTRL_ASDE	__BIT(5)	/* auto speed detect enable */
 #define	CTRL_SLU	__BIT(6)	/* set link up */
 #define	CTRL_ILOS	__BIT(7)	/* invert loss of signal */
 #define	CTRL_SPEED(x)	((x) << 8)	/* speed (Livengood) */
 #define	CTRL_SPEED_10	CTRL_SPEED(0)
 #define	CTRL_SPEED_100	CTRL_SPEED(1)
 #define	CTRL_SPEED_1000	CTRL_SPEED(2)
 #define	CTRL_SPEED_MASK	CTRL_SPEED(3)
 #define	CTRL_FRCSPD	__BIT(11)	/* force speed (Livengood) */
 #define	CTRL_FRCFDX	__BIT(12)	/* force full-duplex (Livengood) */
 #define	CTRL_D_UD_EN	__BIT(13)	/* Dock/Undock enable */
 #define	CTRL_D_UD_POL	__BIT(14)	/* Defined polarity of Dock/Undock indication in SDP[0] */
 #define	CTRL_F_PHY_R 	__BIT(15)	/* Reset both PHY ports, through PHYRST_N pin */
 #define	CTRL_EXTLINK_EN __BIT(16)	/* enable link status from external LINK_0 and LINK_1 pins */
 #define	CTRL_LANPHYPC_OVERRIDE __BIT(16) /* SW control of LANPHYPC */
 #define	CTRL_LANPHYPC_VALUE __BIT(17)	/* SW value of LANPHYPC */
 #define	CTRL_SWDPINS_SHIFT	18
 #define	CTRL_SWDPINS_MASK	0x0f
 #define	CTRL_SWDPIN(x)		(1U << (CTRL_SWDPINS_SHIFT + (x)))
 #define	CTRL_SWDPIO_SHIFT	22
 #define	CTRL_SWDPIO_MASK	0x0f
 #define	CTRL_SWDPIO(x)		(1U << (CTRL_SWDPIO_SHIFT + (x)))
 #define	CTRL_MEHE	__BIT(19)	/* Memory Error Handling Enable(I217)*/
 #define	CTRL_RST	__BIT(26)	/* device reset */
 #define	CTRL_RFCE	__BIT(27)	/* Rx flow control enable */
 #define	CTRL_TFCE	__BIT(28)	/* Tx flow control enable */
 #define	CTRL_VME	__BIT(30)	/* VLAN Mode Enable */
 #define	CTRL_PHY_RESET	__BIT(31)	/* PHY reset (Cordova) */
 #define	WMREG_CTRL_SHADOW 0x0004	/* Device Control Register (shadow) */
 #define	WMREG_STATUS	0x0008	/* Device Status Register */
 #define	STATUS_FD	__BIT(0)	/* full duplex */
 #define	STATUS_LU	__BIT(1)	/* link up */
 #define	STATUS_TCKOK	__BIT(2)	/* Tx clock running */
 #define	STATUS_RBCOK	__BIT(3)	/* Rx clock running */
 #define	STATUS_FUNCID_SHIFT 2		/* 82546 function ID */
 #define	STATUS_FUNCID_MASK  3		/* ... */
 #define	STATUS_TXOFF	__BIT(4)	/* Tx paused */
 #define	STATUS_TBIMODE	__BIT(5)	/* fiber mode (Livengood) */
 #define	STATUS_SPEED	__BITS(7, 6)	/* speed indication */
 #define	STATUS_SPEED_10	  0
 #define	STATUS_SPEED_100  1
 #define	STATUS_SPEED_1000 2
 #define	STATUS_ASDV(x)	((x) << 8)	/* auto speed det. val. (Livengood) */
 #define	STATUS_LAN_INIT_DONE __BIT(9)	/* Lan Init Completion by NVM */
 #define	STATUS_MTXCKOK	__BIT(10)	/* MTXD clock running */
 #define	STATUS_PHYRA	__BIT(10)	/* PHY Reset Asserted (PCH) */
 #define	STATUS_PCI66	__BIT(11)	/* 66MHz bus (Livengood) */
 #define	STATUS_BUS64	__BIT(12)	/* 64-bit bus (Livengood) */
 #define	STATUS_2P5_SKU	__BIT(12)	/* Value of the 2.5GBE SKU strap */
 #define	STATUS_PCIX_MODE __BIT(13)	/* PCIX mode (Cordova) */
 #define	STATUS_2P5_SKU_OVER __BIT(13)	/* Value of the 2.5GBE SKU override */
 #define	STATUS_PCIXSPD(x) ((x) << 14)	/* PCIX speed indication (Cordova) */
 #define	STATUS_PCIXSPD_50_66   STATUS_PCIXSPD(0)
 #define	STATUS_PCIXSPD_66_100  STATUS_PCIXSPD(1)
 #define	STATUS_PCIXSPD_100_133 STATUS_PCIXSPD(2)
 #define	STATUS_PCIXSPD_MASK    STATUS_PCIXSPD(3)
 #define	STATUS_GIO_M_ENA __BIT(19)	/* GIO master enable */
 #define	STATUS_DEV_RST_SET __BIT(20)	/* Device Reset Set */
 /* Strapping Option Register (PCH_SPT and newer) */
 #define	WMREG_STRAP	0x000c
 #define	STRAP_NVMSIZE	__BITS(1, 6)
 #define	STRAP_FREQ	__BITS(12, 13)
 #define	STRAP_SMBUSADDR	__BITS(17, 23)
 #define	WMREG_EECD	0x0010	/* EEPROM Control Register */
 #define	EECD_SK		__BIT(0)	/* clock */
 #define	EECD_CS		__BIT(1)	/* chip select */
 #define	EECD_DI		__BIT(2)	/* data in */
 #define	EECD_DO		__BIT(3)	/* data out */
 #define	EECD_FWE(x)	((x) << 4)	/* flash write enable control */
 #define	EECD_FWE_DISABLED EECD_FWE(1)
 #define	EECD_FWE_ENABLED  EECD_FWE(2)
 #define	EECD_EE_REQ	__BIT(6)	/* (shared) EEPROM request */
 #define	EECD_EE_GNT	__BIT(7)	/* (shared) EEPROM grant */
 #define	EECD_EE_PRES	__BIT(8)	/* EEPROM present */
 #define	EECD_EE_SIZE	__BIT(9)	/* EEPROM size
 					   (0 = 64 word, 1 = 256 word) */
 #define	EECD_EE_AUTORD	__BIT(9)	/* auto read done */
 #define	EECD_EE_ABITS	__BIT(10)	/* EEPROM address bits
 					   (based on type) */
 #define	EECD_EE_SIZE_EX_MASK __BITS(14,11) /* EEPROM size for new devices */
 #define	EECD_EE_TYPE	__BIT(13)	/* EEPROM type
 					   (0 = Microwire, 1 = SPI) */
 #define	EECD_SEC1VAL	__BIT(22)	/* Sector One Valid */
 #define	EECD_SEC1VAL_VALMASK (EECD_EE_AUTORD | EECD_EE_PRES) /* Valid Mask */
 #define	WMREG_FEXTNVM6	0x0010	/* Future Extended NVM 6 */
 #define	FEXTNVM6_REQ_PLL_CLK	__BIT(8)
 #define	FEXTNVM6_ENABLE_K1_ENTRY_CONDITION __BIT(9)
 #define	FEXTNVM6_K1_OFF_ENABLE	__BIT(31)
 #define	WMREG_EERD	0x0014	/* EEPROM read */
 #define	EERD_DONE	0x02    /* done bit */
 #define	EERD_START	0x01	/* First bit for telling part to start operation */
 #define	EERD_ADDR_SHIFT	2	/* Shift to the address bits */
 #define	EERD_DATA_SHIFT	16	/* Offset to data in EEPROM read/write registers */
 #define	WMREG_CTRL_EXT	0x0018	/* Extended Device Control Register */
 #define	CTRL_EXT_NSICR		__BIT(0) /* Non Interrupt clear on read */
 #define	CTRL_EXT_GPI_EN(x)	(1U << (x)) /* gpin interrupt enable */
 #define	CTRL_EXT_NVMVS		__BITS(0, 1) /* NVM valid sector */
 #define	CTRL_EXT_LPCD		__BIT(2) /* LCD Power Cycle Done */
 #define	CTRL_EXT_SWDPINS_SHIFT	4
 #define	CTRL_EXT_SWDPINS_MASK	0x0d
 /* The bit order of the SW Definable pin is not 6543 but 3654! */
 #define	CTRL_EXT_SWDPIN(x)	(1U << (CTRL_EXT_SWDPINS_SHIFT \
 		+ ((x) == 3 ? 3 : ((x) - 4))))
 #define	CTRL_EXT_SWDPIO_SHIFT	8
 #define	CTRL_EXT_SWDPIO_MASK	0x0d
 #define	CTRL_EXT_SWDPIO(x)	(1U << (CTRL_EXT_SWDPIO_SHIFT \
 		+ ((x) == 3 ? 3 : ((x) - 4))))
 #define	CTRL_EXT_FORCE_SMBUS	__BIT(11)  /* Force SMBus mode */
 #define	CTRL_EXT_ASDCHK		__BIT(12) /* ASD check */
 #define	CTRL_EXT_EE_RST		__BIT(13) /* EEPROM reset */
 #define	CTRL_EXT_IPS		__BIT(14) /* invert power state bit 0 */
 #define	CTRL_EXT_SPD_BYPS	__BIT(15) /* speed select bypass */
 #define	CTRL_EXT_IPS1		__BIT(16) /* invert power state bit 1 */
 #define	CTRL_EXT_RO_DIS		__BIT(17) /* relaxed ordering disabled */
 #define	CTRL_EXT_SDLPE		__BIT(18) /* SerDes Low Power Enable */
 #define	CTRL_EXT_DMA_DYN_CLK	__BIT(19) /* DMA Dynamic Gating Enable */
 #define	CTRL_EXT_PHYPDEN	__BIT(20)
 #define	CTRL_EXT_LINK_MODE_MASK		0x00c00000
 #define	CTRL_EXT_LINK_MODE_GMII		0x00000000
 #define	CTRL_EXT_LINK_MODE_KMRN		0x00000000
 #define	CTRL_EXT_LINK_MODE_1000KX	0x00400000
 #define	CTRL_EXT_LINK_MODE_SGMII	0x00800000
 #define	CTRL_EXT_LINK_MODE_PCIX_SERDES	0x00800000
 #define	CTRL_EXT_LINK_MODE_TBI		0x00c00000
 #define	CTRL_EXT_LINK_MODE_PCIE_SERDES	0x00c00000
 #define	CTRL_EXT_EIAME		__BIT(24) /* Extended Interrupt Auto Mask En */
 #define	CTRL_EXT_I2C_ENA	0x02000000  /* I2C enable */
 #define	CTRL_EXT_DRV_LOAD	0x10000000
 #define	CTRL_EXT_PBA		__BIT(31) /* PBA Support */
 #define	WMREG_MDIC	0x0020	/* MDI Control Register */
 #define	MDIC_DATA(x)	((x) & 0xffff)
 #define	MDIC_REGADD(x)	((x) << 16)
 #define	MDIC_PHY_SHIFT	21
 #define	MDIC_PHY_MASK	__BITS(25, 21)
 #define	MDIC_PHYADD(x)	((x) << 21)
 #define	MDIC_OP_RW_MASK	__BITS(27, 26)
 #define	MDIC_OP_WRITE	__SHIFTIN(1, MDIC_OP_RW_MASK)
 #define	MDIC_OP_READ	__SHIFTIN(2, MDIC_OP_RW_MASK)
 #define	MDIC_READY	__BIT(28)
 #define	MDIC_I		__BIT(29)	/* interrupt on MDI complete */
 #define	MDIC_E		__BIT(30)	/* MDI error */
 #define	MDIC_DEST	__BIT(31)	/* Destination */
 #define	WMREG_SCTL	0x0024	/* SerDes Control - RW */
 /*
  * These 4 macros are also used for other 8bit control registers on the
  * 82575
  */
 #define	SCTL_CTL_READY  __BIT(31)
 #define	SCTL_CTL_DATA_MASK 0x000000ff
 #define	SCTL_CTL_ADDR_SHIFT 8
 #define	SCTL_CTL_POLL_TIMEOUT 640
 #define	SCTL_DISABLE_SERDES_LOOPBACK 0x0400
 #define	WMREG_FEXTNVM4	0x0024	/* Future Extended NVM 4 - RW */
 #define	FEXTNVM4_BEACON_DURATION	__BITS(2, 0)
 #define	FEXTNVM4_BEACON_DURATION_8US	0x7
 #define	FEXTNVM4_BEACON_DURATION_16US	0x3
 #define	WMREG_FCAL	0x0028	/* Flow Control Address Low */
 #define	FCAL_CONST	0x00c28001	/* Flow Control MAC addr low */
 #define	WMREG_FEXTNVM	0x0028	/* Future Extended NVM register */
 #define	FEXTNVM_SW_CONFIG	__BIT(0)  /* SW PHY Config En (ICH8 B0) */
 #define	FEXTNVM_SW_CONFIG_ICH8M	__BIT(27) /* SW PHY Config En (>= ICH8 B1) */
 #define	WMREG_FCAH	0x002c	/* Flow Control Address High */
 #define	FCAH_CONST	0x00000100	/* Flow Control MAC addr high */
 #define	WMREG_FCT	0x0030	/* Flow Control Type */
 #define	WMREG_KUMCTRLSTA 0x0034	/* MAC-PHY interface - RW */
 #define	KUMCTRLSTA_MASK			0x0000ffff
 #define	KUMCTRLSTA_OFFSET		0x001f0000
 #define	KUMCTRLSTA_OFFSET_SHIFT		16
 #define	KUMCTRLSTA_REN			0x00200000
 #define	KUMCTRLSTA_OFFSET_FIFO_CTRL	0x00000000
 #define	KUMCTRLSTA_OFFSET_CTRL		0x00000001
 #define	KUMCTRLSTA_OFFSET_INB_CTRL	0x00000002
 #define	KUMCTRLSTA_OFFSET_DIAG		0x00000003
 #define	KUMCTRLSTA_OFFSET_TIMEOUTS	0x00000004
 #define	KUMCTRLSTA_OFFSET_K1_CONFIG	0x00000007
 #define	KUMCTRLSTA_OFFSET_INB_PARAM	0x00000009
 #define	KUMCTRLSTA_OFFSET_HD_CTRL	0x00000010
 #define	KUMCTRLSTA_OFFSET_M2P_SERDES	0x0000001e
 #define	KUMCTRLSTA_OFFSET_M2P_MODES	0x0000001f
 /* FIFO Control */
 #define	KUMCTRLSTA_FIFO_CTRL_RX_BYPASS	0x0008
 #define	KUMCTRLSTA_FIFO_CTRL_TX_BYPASS	0x0800
 /* In-Band Control */
 #define	KUMCTRLSTA_INB_CTRL_LINK_TMOUT_DFLT 0x0500
 #define	KUMCTRLSTA_INB_CTRL_DIS_PADDING	0x0010
 /* Diag */
 #define	KUMCTRLSTA_DIAG_NELPBK	0x1000
 /* K1 Config */
 #define	KUMCTRLSTA_K1_ENABLE	0x0002
 /* Half-Duplex Control */
 #define	KUMCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004
 #define	KUMCTRLSTA_HD_CTRL_1000_DEFAULT	0x0000
 /* M2P Modes */
 #define	KUMCTRLSTA_OPMODE_MASK	0x000c
 #define	KUMCTRLSTA_OPMODE_INBAND_MDIO 0x0004
 #define	WMREG_CONNSW	0x0034	/* Copper/Fiber Switch Control (>= 82575) */
 #define	CONNSW_AUTOSENSE_EN	__BIT(0)	/* Auto Sense Enable */
 #define	CONNSW_AUTOSENSE_CONF	__BIT(1)	/* Auto Sense Config Mode */
 #define	CONNSW_ENRGSRC		__BIT(2)	/* SerDes Energy Detect Src */
 #define	CONNSW_SERDESD		__BIT(9)	/* SerDes Signal Detect Ind. */
 #define	CONNSW_PHYSD		__BIT(10)	/* PHY Signal Detect Ind. */
 #define	CONNSW_PHY_PDN		__BIT(11)	/* Internal PHY in powerdown */
 #define	WMREG_VET	0x0038	/* VLAN Ethertype */
 #define	WMREG_MDPHYA	0x003c	/* PHY address - RW */
 #define	WMREG_FEXTNVM3	0x003c	/* Future Extended NVM 3 */
 #define	FEXTNVM3_PHY_CFG_COUNTER_MASK	__BITS(27, 26)
 #define	FEXTNVM3_PHY_CFG_COUNTER_50MS	__BIT(27)
 #define	WMREG_RAL(x)		(0x0040	+ ((x) * 8)) /* Receive Address List */
 #define	WMREG_RAH(x)		(WMREG_RAL(x) + 4)
 #define	WMREG_CORDOVA_RAL(x)	(((x) <= 15) ? (0x5400 + ((x) * 8)) : \
 	    (0x54e0 + (((x) - 16) * 8)))
 #define	WMREG_CORDOVA_RAH(x)	(WMREG_CORDOVA_RAL(x) + 4)
 #define	WMREG_SHRAL(x)		(0x5438 + ((x) * 8))
 #define	WMREG_SHRAH(x)		(WMREG_PCH_LPT_SHRAL(x) + 4)
 #define	WMREG_PCH_LPT_SHRAL(x)	(0x5408 + ((x) * 8))
 #define	WMREG_PCH_LPT_SHRAH(x)	(WMREG_PCH_LPT_SHRAL(x) + 4)
 #define	WMREG_RAL_LO(b, x) ((b) + ((x) << 3))
 #define	WMREG_RAL_HI(b, x) (WMREG_RAL_LO(b, x) + 4)
 	/*
 	 * Receive Address List: The LO part is the low-order 32-bits
 	 * of the MAC address.  The HI part is the high-order 16-bits
 	 * along with a few control bits.
 	 */
 #define	RAL_AS(x)	((x) << 16)	/* address select */
 #define	RAL_AS_DEST	RAL_AS(0)	/* (cordova?) */
 #define	RAL_AS_SOURCE	RAL_AS(1)	/* (cordova?) */
 #define	RAL_RDR1	__BIT(30)	/* put packet in alt. rx ring */
 #define	RAL_AV		__BIT(31)	/* entry is valid */
 #define	WM_RAL_TABSIZE		15	/* RAL size for old devices */
 #define	WM_RAL_TABSIZE_ICH8	7	/* RAL size for ICH* and PCH* */
 #define	WM_RAL_TABSIZE_PCH2	5	/* RAL size for PCH2 */
 #define	WM_RAL_TABSIZE_PCH_LPT	12	/* RAL size for PCH_LPT */
 #define	WM_RAL_TABSIZE_82575	16	/* RAL size for 82575 */
 #define	WM_RAL_TABSIZE_82576	24	/* RAL size for 82576 and 82580 */
 #define	WM_RAL_TABSIZE_I350	32	/* RAL size for I350 */
 #define	WMREG_ICR	0x00c0	/* Interrupt Cause Register */
 #define	ICR_TXDW	__BIT(0)	/* Tx desc written back */
 #define	ICR_TXQE	__BIT(1)	/* Tx queue empty */
 #define	ICR_LSC		__BIT(2)	/* link status change */
 #define	ICR_RXSEQ	__BIT(3)	/* receive sequence error */
 #define	ICR_RXDMT0	__BIT(4)	/* Rx ring 0 nearly empty */
 #define	ICR_RXO		__BIT(6)	/* Rx overrun */
 #define	ICR_RXT0	__BIT(7)	/* Rx ring 0 timer */
 #define	ICR_MDAC	__BIT(9)	/* MDIO access complete */
 #define	ICR_RXCFG	__BIT(10)	/* Receiving /C/ */
 #define	ICR_GPI(x)	__BIT(11+(x))	/* general purpose interrupts */
 #define	ICR_RXQ(x)	__BIT(20+(x))	/* 82574: Rx queue x interrupt x=0,1 */
 #define	ICR_TXQ(x)	__BIT(22+(x))	/* 82574: Tx queue x interrupt x=0,1 */
 #define	ICR_OTHER	__BIT(24)	/* 82574: Other interrupt */
 #define	ICR_INT		__BIT(31)	/* device generated an interrupt */
 #define	WMREG_ITR	0x00c4	/* Interrupt Throttling Register */
 #define	ITR_IVAL_MASK	0xffff		/* Interval mask */
 #define	ITR_IVAL_SHIFT	0		/* Interval shift */
 #define	WMREG_ICS	0x00c8	/* Interrupt Cause Set Register */
 	/* See ICR bits. */
 #define	WMREG_IMS	0x00d0	/* Interrupt Mask Set Register */
 	/* See ICR bits. */
 #define	WMREG_IMC	0x00d8	/* Interrupt Mask Clear Register */
 	/* See ICR bits. */
 #define	WMREG_EIAC_82574 0x00dc	/* Interrupt Auto Clear Register */
 #define	WMREG_EIAC_82574_MSIX_MASK	(ICR_RXQ(0) | ICR_RXQ(1)	\
 	    | ICR_TXQ(0) | ICR_TXQ(1) | ICR_OTHER)
 #define	WMREG_FEXTNVM7	0x00e4  /* Future Extended NVM 7 */
 #define	FEXTNVM7_SIDE_CLK_UNGATE __BIT(2)
 #define	FEXTNVM7_DIS_SMB_PERST	__BIT(5)
 #define	FEXTNVM7_DIS_PB_READ	__BIT(18)
 #define	WMREG_IVAR	0x00e4  /* Interrupt Vector Allocation Register */
 #define	WMREG_IVAR0	0x01700 /* Interrupt Vector Allocation */
 #define	IVAR_ALLOC_MASK  __BITS(0, 6)	/* Bit 5 and 6 are reserved */
 #define	IVAR_VALID       __BIT(7)
 /* IVAR definitions for 82580 and newer */
 #define	WMREG_IVAR_Q(x)	(WMREG_IVAR0 + ((x) / 2) * 4)
 #define	IVAR_TX_MASK_Q(x) (0x000000ffUL << (((x) % 2) == 0 ? 8 : 24))
 #define	IVAR_RX_MASK_Q(x) (0x000000ffUL << (((x) % 2) == 0 ? 0 : 16))
 /* IVAR definitions for 82576 */
 #define	WMREG_IVAR_Q_82576(x)	(WMREG_IVAR0 + ((x) & 0x7) * 4)
 #define	IVAR_TX_MASK_Q_82576(x) (0x000000ffUL << (((x) / 8) == 0 ? 8 : 24))
 #define	IVAR_RX_MASK_Q_82576(x) (0x000000ffUL << (((x) / 8) == 0 ? 0 : 16))
 /* IVAR definitions for 82574 */
 #define	IVAR_ALLOC_MASK_82574	__BITS(0, 2)
 #define	IVAR_VALID_82574	__BIT(3)
 #define	IVAR_TX_MASK_Q_82574(x) (0x0000000fUL << ((x) == 0 ? 8 : 12))
 #define	IVAR_RX_MASK_Q_82574(x) (0x0000000fUL << ((x) == 0 ? 0 : 4))
 #define	IVAR_OTHER_MASK		__BITS(16, 19)
 #define	IVAR_INT_ON_ALL_WB	__BIT(31)
 #define	WMREG_IVAR_MISC	0x01740 /* IVAR for other causes */
 #define	IVAR_MISC_TCPTIMER __BITS(0, 7)
 #define	IVAR_MISC_OTHER	__BITS(8, 15)
 #define	WMREG_SVCR	0x00f0
 #define	SVCR_OFF_EN		__BIT(0)
 #define	SVCR_OFF_MASKINT	__BIT(12)
 #define	WMREG_SVT	0x00f4
 #define	SVT_OFF_HWM		__BITS(4, 0)
 #define	WMREG_LTRV	0x00f8	/* Latency Tolerance Reporting */
 #define	LTRV_VALUE	__BITS(9, 0)
 #define	LTRV_SCALE	__BITS(12, 10)
 #define	LTRV_SCALE_MAX	5
 #define	LTRV_SNOOP_REQ	__BIT(15)
 #define	LTRV_SEND	__BIT(30)
 #define	LTRV_NONSNOOP	__BITS(31, 16)
 #define	LTRV_NONSNOOP_REQ __BIT(31)
 #define	WMREG_RCTL	0x0100	/* Receive Control */
 #define	RCTL_EN		__BIT(1)	/* receiver enable */
 #define	RCTL_SBP	__BIT(2)	/* store bad packets */
 #define	RCTL_UPE	__BIT(3)	/* unicast promisc. enable */
 #define	RCTL_MPE	__BIT(4)	/* multicast promisc. enable */
 #define	RCTL_LPE	__BIT(5)	/* large packet enable */
 #define	RCTL_LBM(x)	((x) << 6)	/* loopback mode */
 #define	RCTL_LBM_NONE	RCTL_LBM(0)
 #define	RCTL_LBM_PHY	RCTL_LBM(3)
 #define	RCTL_RDMTS(x)	((x) << 8)	/* receive desc. min thresh size */
 #define	RCTL_RDMTS_1_2	RCTL_RDMTS(0)
 #define	RCTL_RDMTS_1_4	RCTL_RDMTS(1)
 #define	RCTL_RDMTS_1_8	RCTL_RDMTS(2)
 #define	RCTL_RDMTS_MASK	RCTL_RDMTS(3)
 #define	RCTL_DTYP_MASK	__BITS(11,10)	/* descriptor type. 82574 only */
 #define	RCTL_DTYP(x)	__SHIFTIN(x,RCTL_DTYP_MASK)
 #define	RCTL_DTYP_ONEBUF RCTL_DTYP(0)	/* use one buffer(not split header). */
 #define	RCTL_DTYP_SPH	RCTL_DTYP(1)	/* split header buffer. */
 					/* RCTL_DTYP(2) and RCTL_DTYP(3) are reserved. */
 #define	RCTL_MO		__BITS(13, 12)	/* multicast offset */
 #define	RCTL_BAM	__BIT(15)	/* broadcast accept mode */
 #define	RCTL_RDMTS_HEX	__BIT(16)
 #define	RCTL_2k		(0 << 16)	/* 2k Rx buffers */
 #define	RCTL_1k		(1 << 16)	/* 1k Rx buffers */
 #define	RCTL_512	(2 << 16)	/* 512 byte Rx buffers */
 #define	RCTL_256	(3 << 16)	/* 256 byte Rx buffers */
 #define	RCTL_BSEX_16k	(1 << 16)	/* 16k Rx buffers (BSEX) */
 #define	RCTL_BSEX_8k	(2 << 16)	/* 8k Rx buffers (BSEX) */
 #define	RCTL_BSEX_4k	(3 << 16)	/* 4k Rx buffers (BSEX) */
 #define	RCTL_DPF	__BIT(22)	/* discard pause frames */
 #define	RCTL_PMCF	__BIT(23)	/* pass MAC control frames */
 #define	RCTL_BSEX	__BIT(25)	/* buffer size extension (Livengood) */
 #define	RCTL_SECRC	__BIT(26)	/* strip Ethernet CRC */
 #define	WMREG_OLD_RDTR0	0x0108	/* Receive Delay Timer (ring 0) */
 #define	WMREG_RDTR	0x2820
 #define	RDTR_FPD	__BIT(31)	/* flush partial descriptor */
 #define	WMREG_LTRC	0x01a0	/* Latency Tolerance Reportiong Control */
 #define	WMREG_OLD_RDBAL0 0x0110	/* Receive Descriptor Base Low (ring 0) */
 #define	WMREG_RDBAL(x) \
 	((x) < 4 ? (0x02800 + ((x) * 0x100)) :	\
 	    (0x0c000 + ((x) * 0x40)))
 #define	WMREG_OLD_RDBAH0 0x0114	/* Receive Descriptor Base High (ring 0) */
 #define	WMREG_RDBAH(x) \
 	((x) < 4 ? (0x02804 + ((x) * 0x100)) :	\
 	    (0x0c004 + ((x) * 0x40)))
 #define	WMREG_OLD_RDLEN0 0x0118	/* Receive Descriptor Length (ring 0) */
 #define	WMREG_RDLEN(x) \
 	((x) < 4 ? (0x02808 + ((x) * 0x100)) :  \
 	    (0x0c008 + ((x) * 0x40)))
 #define	WMREG_SRRCTL(x) \
 	((x) < 4 ? (0x0280c + ((x) * 0x100)) :	\
 	    (0x0c00c + ((x) * 0x40)))	/* additional recv control used in 82575 ... */
 #define	SRRCTL_BSIZEPKT_MASK		0x0000007f
 #define	SRRCTL_BSIZEPKT_SHIFT		10	/* Shift _right_ */
 #define	SRRCTL_BSIZEHDRSIZE_MASK	0x00000f00
 #define	SRRCTL_BSIZEHDRSIZE_SHIFT	2	/* Shift _left_ */
 #define	SRRCTL_DESCTYPE_LEGACY		0x00000000
 #define	SRRCTL_DESCTYPE_ADV_ONEBUF	(1U << 25)
 #define	SRRCTL_DESCTYPE_HDR_SPLIT	(2U << 25)
 #define	SRRCTL_DESCTYPE_HDR_REPLICATION	(3U << 25)
 #define	SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT (4U << 25)
 #define	SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS (5U << 25) /* 82575 only */
 #define	SRRCTL_DESCTYPE_MASK		(7U << 25)
 #define	SRRCTL_DROP_EN			0x80000000
 #define	WMREG_OLD_RDH0	0x0120	/* Receive Descriptor Head (ring 0) */
 #define	WMREG_RDH(x) \
 	((x) < 4 ? (0x02810 + ((x) * 0x100)) :  \
 	    (0x0c010 + ((x) * 0x40)))
 #define	WMREG_OLD_RDT0	0x0128	/* Receive Descriptor Tail (ring 0) */
 #define	WMREG_RDT(x) \
 	((x) < 4 ? (0x02818 + ((x) * 0x100)) :	\
 	    (0x0c018 + ((x) * 0x40)))
 #define	WMREG_RXDCTL(x) \
 	((x) < 4 ? (0x02828 + ((x) * 0x100)) :	\
 	    (0x0c028 + ((x) * 0x40)))	/* Receive Descriptor Control */
 #define	RXDCTL_PTHRESH(x) ((x) << 0)	/* prefetch threshold */
 #define	RXDCTL_HTHRESH(x) ((x) << 8)	/* host threshold */
 #define	RXDCTL_WTHRESH(x) ((x) << 16)	/* write back threshold */
 #define	RXDCTL_GRAN	__BIT(24)	/* 0 = cacheline, 1 = descriptor */
 /* flags used starting with 82575 ... */
 #define	RXDCTL_QUEUE_ENABLE  0x02000000 /* Enable specific Tx Queue */
 #define	RXDCTL_SWFLSH        0x04000000 /* Rx Desc. write-back flushing */
 #define	WMREG_RQDPC(x)	(((x) < 4) ? (0x2830 + (0x100 * (x))) :		\
 	    (0xc030 + (0x40 * (x)))) /* Receive Queue Drop Packet Count */
 #define	WMREG_OLD_RDTR1	0x0130	/* Receive Delay Timer (ring 1) */
 #define	WMREG_OLD_RDBA1_LO 0x0138 /* Receive Descriptor Base Low (ring 1) */
 #define	WMREG_OLD_RDBA1_HI 0x013c /* Receive Descriptor Base High (ring 1) */
 #define	WMREG_OLD_RDLEN1 0x0140	/* Receive Drscriptor Length (ring 1) */
 #define	WMREG_OLD_RDH1	0x0148
 #define	WMREG_OLD_RDT1	0x0150
 #define	WMREG_OLD_FCRTH 0x0160	/* Flow Control Rx Threshold Hi (OLD) */
 #define	WMREG_FCRTH	0x2168	/* Flow Control Rx Threhsold Hi */
 #define	FCRTH_DFLT	0x00008000
 #define	WMREG_OLD_FCRTL 0x0168	/* Flow Control Rx Threshold Lo (OLD) */
 #define	WMREG_FCRTL	0x2160	/* Flow Control Rx Threshold Lo */
 #define	FCRTL_DFLT	0x00004000
 #define	FCRTL_XONE	0x80000000	/* Enable XON frame transmission */
 #define	WMREG_FCTTV	0x0170	/* Flow Control Transmit Timer Value */
 #define	FCTTV_DFLT	0x00000600
 #define	WMREG_TXCW	0x0178	/* Transmit Configuration Word (TBI mode) */
 	/* See MII ANAR_X bits. */
 #define	TXCW_FD		__BIT(5)	/* Full Duplex */
 #define	TXCW_HD		__BIT(6)	/* Half Duplex */
 #define	TXCW_SYM_PAUSE	__BIT(7)	/* sym pause request */
 #define	TXCW_ASYM_PAUSE	__BIT(8)	/* asym pause request */
 #define	TXCW_TxConfig	__BIT(30)	/* Tx Config */
 #define	TXCW_ANE	__BIT(31)	/* Autonegotiate */
 #define	WMREG_RXCW	0x0180	/* Receive Configuration Word (TBI mode) */
 	/* See MII ANLPAR_X bits. */
 #define	RXCW_NC		__BIT(26)	/* no carrier */
 #define	RXCW_IV		__BIT(27)	/* config invalid */
 #define	RXCW_CC		__BIT(28)	/* config change */
 #define	RXCW_C		__BIT(29)	/* /C/ reception */
 #define	RXCW_SYNCH	__BIT(30)	/* synchronized */
 #define	RXCW_ANC	__BIT(31)	/* autonegotiation complete */
 #define	WMREG_MTA	0x0200	/* Multicast Table Array */
 #define	WMREG_CORDOVA_MTA 0x5200
 #define	WMREG_TCTL	0x0400	/* Transmit Control Register */
 #define	TCTL_EN		__BIT(1)	/* transmitter enable */
 #define	TCTL_PSP	__BIT(3)	/* pad short packets */
 #define	TCTL_CT(x)	(((x) & 0xff) << 4)   /* 4:11 - collision threshold */
 #define	TCTL_COLD(x)	(((x) & 0x3ff) << 12) /* 12:21 - collision distance */
 #define	TCTL_SWXOFF	__BIT(22)	/* software XOFF */
 #define	TCTL_RTLC	__BIT(24)	/* retransmit on late collision */
 #define	TCTL_NRTU	__BIT(25)	/* no retransmit on underrun */
 #define	TCTL_MULR	__BIT(28)	/* multiple request */
 #define	TX_COLLISION_THRESHOLD		15
 #define	TX_COLLISION_DISTANCE_HDX	512
 #define	TX_COLLISION_DISTANCE_FDX	64
 #define	WMREG_TCTL_EXT	0x0404	/* Transmit Control Register */
 #define	TCTL_EXT_BST_MASK	0x000003ff /* Backoff Slot Time */
 #define	TCTL_EXT_GCEX_MASK	0x000ffc00 /* Gigabit Carry Extend Padding */
 #define	DEFAULT_80003ES2LAN_TCTL_EXT_GCEX 0x00010000
 #define	WMREG_TIPG	0x0410	/* Transmit IPG Register */
 #define	TIPG_IPGT(x)	(x)		/* IPG transmit time */
 #define	TIPG_IPGR1(x)	((x) << 10)	/* IPG receive time 1 */
 #define	TIPG_IPGR2(x)	((x) << 20)	/* IPG receive time 2 */
 #define	TIPG_WM_DFLT	(TIPG_IPGT(0x0a) | TIPG_IPGR1(0x02) | TIPG_IPGR2(0x0a))
 #define	TIPG_LG_DFLT	(TIPG_IPGT(0x06) | TIPG_IPGR1(0x08) | TIPG_IPGR2(0x06))
 #define	TIPG_1000T_DFLT	(TIPG_IPGT(0x08) | TIPG_IPGR1(0x08) | TIPG_IPGR2(0x06))
 #define	TIPG_1000T_80003_DFLT \
     (TIPG_IPGT(0x08) | TIPG_IPGR1(0x02) | TIPG_IPGR2(0x07))
 #define	TIPG_10_100_80003_DFLT \
     (TIPG_IPGT(0x09) | TIPG_IPGR1(0x02) | TIPG_IPGR2(0x07))
 #define	WMREG_TQC	0x0418
 #define	WMREG_OLD_TDBAL	0x0420	/* Transmit Descriptor Base Lo */
 #define	WMREG_TDBAL(x) \
 	((x) < 4 ? (0x03800 + ((x) * 0x100)) :	\
 	    (0x0e000 + ((x) * 0x40)))
 #define	WMREG_OLD_TDBAH	0x0424	/* Transmit Descriptor Base Hi */
 #define	WMREG_TDBAH(x)\
 	((x) < 4 ? (0x03804 + ((x) * 0x100)) :	\
 	    (0x0e004 + ((x) * 0x40)))
 #define	WMREG_OLD_TDLEN	0x0428	/* Transmit Descriptor Length */
 #define	WMREG_TDLEN(x) \
 	((x) < 4 ? (0x03808 + ((x) * 0x100)) :	\
 	    (0x0e008 + ((x) * 0x40)))
 #define	WMREG_OLD_TDH	0x0430	/* Transmit Descriptor Head */
 #define	WMREG_TDH(x) \
 	((x) < 4 ? (0x03810 + ((x) * 0x100)) :	\
 	    (0x0e010 + ((x) * 0x40)))
 #define	WMREG_OLD_TDT	0x0438	/* Transmit Descriptor Tail */
 #define	WMREG_TDT(x) \
 	((x) < 4 ? (0x03818 + ((x) * 0x100)) :	\
 	    (0x0e018 + ((x) * 0x40)))
 #define	WMREG_OLD_TIDV	0x0440	/* Transmit Delay Interrupt Value */
 #define	WMREG_TIDV	0x3820
 #define	WMREG_AIT	0x0458	/* Adaptive IFS Throttle */
 #define	WMREG_VFTA	0x0600
 #define	WMREG_LEDCTL	0x0e00	/* LED Control - RW */
 #define	WMREG_MDICNFG	0x0e04	/* MDC/MDIO Configuration Register */
 #define	MDICNFG_PHY_SHIFT	21
 #define	MDICNFG_PHY_MASK	__BITS(25, 21)
 #define	MDICNFG_COM_MDIO	__BIT(30)
 #define	MDICNFG_DEST		__BIT(31)
 #define	WM_MC_TABSIZE	128
 #define	WM_ICH8_MC_TABSIZE 32
 #define	WM_VLAN_TABSIZE	128
 #define	WMREG_PHPM	0x0e14	/* PHY Power Management */
 #define	PHPM_SPD_EN		__BIT(0)	/* Smart Power Down */
 #define	PHPM_D0A_LPLU		__BIT(1)	/* D0 Low Power Link Up */
 #define	PHPM_NOND0A_LPLU	__BIT(2)	/* Non-D0a LPLU */
 #define	PHPM_NOND0A_GBE_DIS	__BIT(3)	/* Disable 1G in non-D0a */
 #define	PHPM_GO_LINK_D		__BIT(5)	/* Go Link Disconnect */
 #define	WMREG_EEER	0x0e30	/* Energy Efficiency Ethernet "EEE" */
 #define	EEER_TX_LPI_EN		0x00010000 /* EEER Tx LPI Enable */
 #define	EEER_RX_LPI_EN		0x00020000 /* EEER Rx LPI Enable */
 #define	EEER_LPI_FC		0x00040000 /* EEER Ena on Flow Cntrl */
 #define	EEER_EEER_NEG		0x20000000 /* EEER capability nego */
 #define	EEER_EEER_RX_LPI_STATUS	0x40000000 /* EEER Rx in LPI state */
 #define	EEER_EEER_TX_LPI_STATUS	0x80000000 /* EEER Tx in LPI state */
 #define	WMREG_EEE_SU	0x0e34	/* EEE Setup */
 #define	WMREG_IPCNFG	0x0e38	/* Internal PHY Configuration */
 #define	IPCNFG_10BASE_TE	0x00000002 /* IPCNFG 10BASE-Te low power op. */
 #define	IPCNFG_EEE_100M_AN	0x00000004 /* IPCNFG EEE Ena 100M AN */
 #define	IPCNFG_EEE_1G_AN	0x00000008 /* IPCNFG EEE Ena 1G AN */
 #define	WMREG_EXTCNFCTR	0x0f00  /* Extended Configuration Control */
 #define	EXTCNFCTR_PCIE_WRITE_ENABLE	0x00000001
 #define	EXTCNFCTR_OEM_WRITE_ENABLE	0x00000008
 #define	EXTCNFCTR_MDIO_SW_OWNERSHIP	0x00000020
 #define	EXTCNFCTR_MDIO_HW_OWNERSHIP	0x00000040
 #define	EXTCNFCTR_GATE_PHY_CFG		0x00000080
 #define	EXTCNFCTR_EXT_CNF_POINTER	0x0fff0000
 #define	WMREG_EXTCNFSIZE 0x0f08  /* Extended Configuration Size */
 #define	EXTCNFSIZE_LENGTH	__BITS(23, 16)
 #define	WMREG_PHY_CTRL	0x0f10	/* PHY control */
 #define	PHY_CTRL_SPD_EN		(1 << 0)
 #define	PHY_CTRL_D0A_LPLU	(1 << 1)
 #define	PHY_CTRL_NOND0A_LPLU	(1 << 2)
 #define	PHY_CTRL_NOND0A_GBE_DIS	(1 << 3)
 #define	PHY_CTRL_GBE_DIS	(1 << 6)
 #define	WMREG_PCIEANACFG 0x0f18	/* PCIE Analog Config */
 #define	WMREG_IOSFPC	0x0f28	/* Tx corrupted data */
 #define	WMREG_PBA	0x1000	/* Packet Buffer Allocation */
 #define	PBA_BYTE_SHIFT	10		/* KB -> bytes */
 #define	PBA_ADDR_SHIFT	7		/* KB -> quadwords */
 #define	PBA_8K		0x0008
 #define	PBA_10K		0x000a
 #define	PBA_12K		0x000c
 #define	PBA_14K		0x000e
 #define	PBA_16K		0x0010		/* 16K, default Tx allocation */
 #define	PBA_20K		0x0014
 #define	PBA_22K		0x0016
 #define	PBA_24K		0x0018
 #define	PBA_26K		0x001a
 #define	PBA_30K		0x001e
 #define	PBA_32K		0x0020
 #define	PBA_34K		0x0022
 #define	PBA_35K		0x0023
 #define	PBA_40K		0x0028
 #define	PBA_48K		0x0030		/* 48K, default Rx allocation */
 #define	PBA_64K		0x0040
 #define	PBA_RXA_MASK	__BITS(15, 0)
 #define	WMREG_PBS	0x1008	/* Packet Buffer Size (ICH) */
 #define	WMREG_PBECCSTS	0x100c	/* Packet Buffer ECC Status (PCH_LPT) */
 #define	PBECCSTS_CORR_ERR_CNT_MASK	0x000000ff
 #define	PBECCSTS_UNCORR_ERR_CNT_MASK	0x0000ff00
 #define	PBECCSTS_UNCORR_ECC_ENABLE	0x00010000
 #define	WMREG_EEMNGCTL	0x1010	/* MNG EEprom Control */
 #define	EEMNGCTL_CFGDONE_0 0x040000	/* MNG config cycle done */
 #define	EEMNGCTL_CFGDONE_1 0x080000	/*  2nd port */
 #define	WMREG_I2CCMD	0x1028	/* SFPI2C Command Register - RW */
 #define	I2CCMD_REG_ADDR_SHIFT	16
 #define	I2CCMD_REG_ADDR		0x00ff0000
 #define	I2CCMD_PHY_ADDR_SHIFT	24
 #define	I2CCMD_PHY_ADDR		0x07000000
 #define	I2CCMD_OPCODE_READ	0x08000000
 #define	I2CCMD_OPCODE_WRITE	0x00000000
 #define	I2CCMD_RESET		0x10000000
 #define	I2CCMD_READY		0x20000000
 #define	I2CCMD_INTERRUPT_ENA	0x40000000
 #define	I2CCMD_ERROR		0x80000000
 #define	MAX_SGMII_PHY_REG_ADDR	255
 #define	I2CCMD_PHY_TIMEOUT	200
 #define	WMREG_EEWR	0x102c	/* EEPROM write */
 #define	WMREG_PBA_ECC	0x01100	/* PBA ECC */
 #define	PBA_ECC_COUNTER_MASK	0xfff00000 /* ECC counter mask */
 #define	PBA_ECC_COUNTER_SHIFT	20	   /* ECC counter shift value */
 #define	PBA_ECC_CORR_EN		0x00000001 /* Enable ECC error correction */
 #define	PBA_ECC_STAT_CLR	0x00000002 /* Clear ECC error counter */
 #define	PBA_ECC_INT_EN		0x00000004 /* Enable ICR bit 5 on ECC error */
 #define	WMREG_GPIE	0x01514 /* General Purpose Interrupt Enable */
 #define	GPIE_NSICR	__BIT(0)	/* Non Selective Interrupt Clear */
 #define	GPIE_MULTI_MSIX	__BIT(4)	/* Multiple MSIX */
 #define	GPIE_EIAME	__BIT(30)	/* Extended Interrupt Auto Mask Ena. */
 #define	GPIE_PBA	__BIT(31)	/* PBA support */
 #define	WMREG_EICS	0x01520  /* Ext. Interrupt Cause Set - WO */
 #define	WMREG_EIMS	0x01524  /* Ext. Interrupt Mask Set/Read - RW */
 #define	WMREG_EIMC	0x01528  /* Ext. Interrupt Mask Clear - WO */
 #define	WMREG_EIAC	0x0152c  /* Ext. Interrupt Auto Clear - RW */
 #define	WMREG_EIAM	0x01530  /* Ext. Interrupt Ack Auto Clear Mask - RW */
 #define	WMREG_EICR	0x01580  /* Ext. Interrupt Cause Read - R/clr */
 #define	WMREG_MSIXBM(x)	(0x1600 + (x) * 4) /* MSI-X Allocation */
 #define	EITR_RX_QUEUE(x)	__BIT(0+(x)) /* Rx Queue x Interrupt x=[0-3] */
 #define	EITR_TX_QUEUE(x)	__BIT(8+(x)) /* Tx Queue x Interrupt x=[0-3] */
 #define	EITR_TCP_TIMER	0x40000000 /* TCP Timer */
 #define	EITR_OTHER	0x80000000 /* Interrupt Cause Active */
 #define	WMREG_EITR(x)	(0x01680 + (0x4 * (x)))
 #define	EITR_ITR_INT_MASK	__BITS(14,2)
 #define	EITR_COUNTER_MASK_82575	__BITS(31,16)
 #define	EITR_CNT_INGR		__BIT(31) /* does not overwrite counter */
 #define	WMREG_EITR_82574(x)	(0x000e8 + (0x4 * (x)))
 #define	EITR_ITR_INT_MASK_82574	__BITS(15, 0)
 #define	WMREG_RXPBS	0x2404	/* Rx Packet Buffer Size  */
 #define	RXPBS_SIZE_MASK_82576	0x0000007f
 #define	WMREG_RDFH	0x2410	/* Receive Data FIFO Head */
 #define	WMREG_RDFT	0x2418	/* Receive Data FIFO Tail */
 #define	WMREG_RDFHS	0x2420	/* Receive Data FIFO Head Saved */
 #define	WMREG_RDFTS	0x2428	/* Receive Data FIFO Tail Saved */
 #define	WMREG_RADV	0x282c	/* Receive Interrupt Absolute Delay Timer */
 #define	WMREG_TXDMAC	0x3000	/* Transfer DMA Control */
 #define	TXDMAC_DPP	__BIT(0)	/* disable packet prefetch */
 #define	WMREG_KABGTXD	0x3004	/* AFE and Gap Transmit Ref Data */
 #define	KABGTXD_BGSQLBIAS 0x00050000
 #define	WMREG_TDFH	0x3410	/* Transmit Data FIFO Head */
 #define	WMREG_TDFT	0x3418	/* Transmit Data FIFO Tail */
 #define	WMREG_TDFHS	0x3420	/* Transmit Data FIFO Head Saved */
 #define	WMREG_TDFTS	0x3428	/* Transmit Data FIFO Tail Saved */
 #define	WMREG_TDFPC	0x3430	/* Transmit Data FIFO Packet Count */
 #define	WMREG_TXDCTL(n)		/* Trandmit Descriptor Control */ \
 	(((n) < 4) ? (0x3828 + ((n) * 0x100)) : (0xe028 + ((n) * 0x40)))
 #define	TXDCTL_PTHRESH(x) ((x) << 0)	/* prefetch threshold */
 #define	TXDCTL_HTHRESH(x) ((x) << 8)	/* host threshold */
 #define	TXDCTL_WTHRESH(x) ((x) << 16)	/* write back threshold */
 /* flags used starting with 82575 ... */
 #define	TXDCTL_COUNT_DESC	__BIT(22) /* Enable the counting of desc.
 					   still to be processed. */
 #define	TXDCTL_QUEUE_ENABLE  0x02000000 /* Enable specific Tx Queue */
 #define	TXDCTL_SWFLSH        0x04000000 /* Tx Desc. write-back flushing */
 #define	TXDCTL_PRIORITY      0x08000000
 #define	WMREG_TADV	0x382c	/* Transmit Absolute Interrupt Delay Timer */
 #define	WMREG_TSPMT	0x3830	/* TCP Segmentation Pad and Minimum
 				   Threshold (Cordova) */
 #define	TSPMT_TSMT(x)	(x)		/* TCP seg min transfer */
 #define	TSPMT_TSPBP(x)	((x) << 16)	/* TCP seg pkt buf padding */
 #define	WMREG_TARC0	0x3840	/* Tx arbitration count (0) */
 #define	WMREG_TARC1	0x3940	/* Tx arbitration count (1) */
 #define	WMREG_CRCERRS	0x4000	/* CRC Error Count */
 #define	WMREG_ALGNERRC	0x4004	/* Alignment Error Count */
 #define	WMREG_SYMERRC	0x4008	/* Symbol Error Count */
 #define	WMREG_RXERRC	0x400c	/* Receive error Count - R/clr */
 #define	WMREG_MPC	0x4010	/* Missed Packets Count - R/clr */
 #define	WMREG_SCC	0x4014	/* Single Collision Count - R/clr */
 #define	WMREG_ECOL	0x4018	/* Excessive Collisions Count - R/clr */
 #define	WMREG_MCC	0x401c	/* Multiple Collision Count - R/clr */
 #define	WMREG_LATECOL	0x4020	/* Late Collisions Count - R/clr */
 #define	WMREG_COLC	0x4028	/* Collision Count - R/clr */
 #define	WMREG_CBTMPC	0x402c	/* Circuit Breaker Tx Manageability Packet */
 #define	WMREG_DC	0x4030	/* Defer Count - R/clr */
 #define	WMREG_TNCRS	0x4034	/* Tx with No CRS - R/clr */
 #define	WMREG_SEC	0x4038	/* Sequence Error Count */
 /* Old */
 #define	WMREG_CEXTERR	0x403c	/* Carrier Extension Error Count */
 /* New */
 #define	WMREG_HTDPMC	0x403c	/* Host Tx Discarded Packets by MAC Count */
 #define	WMREG_RLEC	0x4040	/* Receive Length Error Count */
 #define	WMREG_CBRDPC	0x4044	/* Circuit Breaker Rx Dropped Packet Count */
 #define	WMREG_XONRXC	0x4048	/* XON Rx Count - R/clr */
 #define	WMREG_XONTXC	0x404c	/* XON Tx Count - R/clr */
 #define	WMREG_XOFFRXC	0x4050	/* XOFF Rx Count - R/clr */
 #define	WMREG_XOFFTXC	0x4054	/* XOFF Tx Count - R/clr */
 #define	WMREG_FCRUC	0x4058	/* Flow Control Rx Unsupported Count - R/clr */
 #define	WMREG_PRC64	0x405c	/* Packets Rx (64 bytes) - R/clr */
 #define	WMREG_PRC127	0x4060	/* Packets Rx (65-127 bytes) - R/clr */
 #define	WMREG_PRC255	0x4064	/* Packets Rx (128-255 bytes) - R/clr */
 #define	WMREG_PRC511	0x4068	/* Packets Rx (255-511 bytes) - R/clr */
 #define	WMREG_PRC1023	0x406c	/* Packets Rx (512-1023 bytes) - R/clr */
 #define	WMREG_PRC1522	0x4070	/* Packets Rx (1024-1522 bytes) - R/clr */
 #define	WMREG_GPRC	0x4074	/* Good Packets Rx Count - R/clr */
 #define	WMREG_BPRC	0x4078	/* Broadcast Packets Rx Count - R/clr */
 #define	WMREG_MPRC	0x407c	/* Multicast Packets Rx Count - R/clr */
 #define	WMREG_GPTC	0x4080	/* Good Packets Tx Count - R/clr */
 #define	WMREG_GORCL	0x4088	/* Good Octets Rx Count Low - R/clr */
 #define	WMREG_GORCH	0x408c	/* Good Octets Rx Count High - R/clr */
 #define	WMREG_GOTCL	0x4090	/* Good Octets Tx Count Low - R/clr */
 #define	WMREG_GOTCH	0x4094	/* Good Octets Tx Count High - R/clr */
 #define	WMREG_RNBC	0x40a0	/* Receive No Buffers Count */
 #define	WMREG_RUC	0x40a4	/* Rx Undersize Count - R/clr */
 #define	WMREG_RFC	0x40a8	/* Rx Fragment Count - R/clr */
 #define	WMREG_ROC	0x40ac	/* Rx Oversize Count - R/clr */
 #define	WMREG_RJC	0x40b0	/* Rx Jabber Count - R/clr */
 #define	WMREG_MGTPRC	0x40b4	/* Management Packets RX Count - R/clr */
 #define	WMREG_MGTPDC	0x40b8	/* Management Packets Dropped Count - R/clr */
 #define	WMREG_MGTPTC	0x40bc	/* Management Packets TX Count - R/clr */
 #define	WMREG_TORL	0x40c0	/* Total Octets Rx Low - R/clr */
 #define	WMREG_TORH	0x40c4	/* Total Octets Rx High - R/clr */
 #define	WMREG_TOTL	0x40c8	/* Total Octets Tx Low - R/clr */
 #define	WMREG_TOTH	0x40cc	/* Total Octets Tx High - R/clr */
 #define	WMREG_TPR	0x40d0	/* Total Packets Rx - R/clr */
 #define	WMREG_TPT	0x40d4	/* Total Packets Tx - R/clr */
 #define	WMREG_PTC64	0x40d8	/* Packets Tx (64 bytes) - R/clr */
 #define	WMREG_PTC127	0x40dc	/* Packets Tx (65-127 bytes) - R/clr */
 #define	WMREG_PTC255	0x40e0	/* Packets Tx (128-255 bytes) - R/clr */
 #define	WMREG_PTC511	0x40e4	/* Packets Tx (256-511 bytes) - R/clr */
 #define	WMREG_PTC1023	0x40e8	/* Packets Tx (512-1023 bytes) - R/clr */
 #define	WMREG_PTC1522	0x40ec	/* Packets Tx (1024-1522 Bytes) - R/clr */
 #define	WMREG_MPTC	0x40f0	/* Multicast Packets Tx Count - R/clr */
 #define	WMREG_BPTC	0x40f4	/* Broadcast Packets Tx Count */
 #define	WMREG_TSCTC	0x40f8	/* TCP Segmentation Context Tx */
 /* Old */
 #define	WMREG_TSCTFC	0x40fc	/* TCP Segmentation Context Tx Fail */
 /* New */
 #define	WMREG_CBRMPC	0x40fc	/* Circuit Breaker Rx Manageability Packet */
 #define	WMREG_IAC	0x4100	/* Interrupt Assertion Count */
 /* Old */
 #define	WMREG_ICRXPTC	0x4104	/* Interrupt Cause Rx Pkt Timer Expire Count */
 #define	WMREG_ICRXATC	0x4108	/* Interrupt Cause Rx Abs Timer Expire Count */
 #define	WMREG_ICTXPTC	0x410c	/* Interrupt Cause Tx Pkt Timer Expire Count */
 #define	WMREG_ICTXATC	0x4110	/* Interrupt Cause Tx Abs Timer Expire Count */
 #define	WMREG_ICTXQEC	0x4118	/* Interrupt Cause Tx Queue Empty Count */
 #define	WMREG_ICTXQMTC	0x411c	/* Interrupt Cause Tx Queue Min Thresh Count */
 #define	WMREG_ICRXDMTC	0x4120	/* Interrupt Cause Rx Desc Min Thresh Count */
 #define	WMREG_ICRXOC	0x4124	/* Interrupt Cause Receiver Overrun Count */
 /* New */
 #define	WMREG_RPTHC	0x4104	/* Rx Pkt To Host Count */
 #define	WMREG_DEBUG1	0x4108	/* Debug Counter 1 */
 #define	WMREG_DEBUG2	0x410c	/* Debug Counter 2 */
 #define	WMREG_DEBUG3	0x4110	/* Debug Counter 3 */
 #define	WMREG_HGPTC	0x4118	/* Host Good Packets Tx Count (>=82576?) */
 #define	WMREG_DEBUG4	0x411c	/* Debug Counter 4 */
 #define	WMREG_RXDMTC	0x4120	/* Rx Desc Min Thresh Count */
 #define	WMREG_HTCBDPC	0x4124	/* Host Tx Circuit Breaker Dropped Pkt. Cnt. */
 #define	WMREG_HGORCL	0x4128	/* Host Good Octets Rx Count Low (>=82576?) */
 #define	WMREG_HGORCH	0x412c	/* Host Good Octets Rx Count High (>=82576?) */
 #define	WMREG_HGOTCL	0x4130	/* Host Good Octets Tx Count Low (>=82576?) */
 #define	WMREG_HGOTCH	0x4134	/* Host Good Octets Tx Count High (>=82576?) */
 #define	WMREG_LENERRS	0x4138	/* Length Errors Count (>=82576?) */
 #define	WMREG_TLPIC	0x4148	/* EEE Tx LPI Count */
 #define	WMREG_RLPIC	0x414c	/* EEE Rx LPI Count */
 #define	WMREG_B2OGPRC	0x4158	/* BMC2OS packets received by host */
 #define	WMREG_O2BSPC	0x415c	/* OS2BMC packets transmitted by host */
 #define	WMREG_PCS_CFG	0x4200	/* PCS Configuration */
 #define	PCS_CFG_PCS_EN	__BIT(3)
 #define	WMREG_PCS_LCTL	0x4208	/* PCS Link Control */
 #define	PCS_LCTL_FLV_LINK_UP	__BIT(0)	/* Forced Link Value */
 #define	PCS_LCTL_FSV_MASK	__BITS(2, 1)	/* Forced Speed Value */
 #define	PCS_LCTL_FSV_10			0		/* 10Mbps */
 #define	PCS_LCTL_FSV_100		__BIT(1)	/* 100Mbps */
 #define	PCS_LCTL_FSV_1000		__BIT(2)	/* 1Gpbs */
 #define	PCS_LCTL_FDV_FULL	__BIT(3)	/* Force Duplex Value */
 #define	PCS_LCTL_FSD		__BIT(4)	/* Force Speed and Duplex */
 #define	PCS_LCTL_FORCE_LINK	__BIT(5)	/* Force Link */
 #define	PCS_LCTL_LINK_LATCH_LOW	__BIT(6)	/* Link Latch Low */
 #define	PCS_LCTL_FORCE_FC	__BIT(7)	/* Force Flow Control */
 #define	PCS_LCTL_AN_ENABLE	__BIT(16)	/* AN enable */
 #define	PCS_LCTL_AN_RESTART	__BIT(17)	/* AN restart */
 #define	PCS_LCTL_AN_TIMEOUT	__BIT(18)	/* AN Timeout Enable */
 #define	PCS_LCTL_AN_SGMII_BYP	__BIT(19)	/* AN SGMII Bypass */
 #define	PCS_LCTL_AN_SGMII_TRIG	__BIT(20)	/* AN SGMII Trigger */
 #define	PCS_LCTL_FAST_LINKTIMER	__BIT(24)	/* Fast Link Timer */
 #define	PCS_LCTL_LINK_OK_FIX_EN	__BIT(25)	/* Link OK Fix Enable */
 #define	WMREG_PCS_LSTS	0x420c	/* PCS Link Status */
 #define	PCS_LSTS_LINKOK	__BIT(0)
 #define	PCS_LSTS_SPEED	__BITS(2, 1)
 #define	PCS_LSTS_SPEED_10	0
 #define	PCS_LSTS_SPEED_100	1
 #define	PCS_LSTS_SPEED_1000	2
 #define	PCS_LSTS_FDX	__BIT(3)
 #define	PCS_LSTS_AN_COMP __BIT(16)
 #define	WMREG_PCS_ANADV	0x4218	/* AN Advertsement */
 #define	WMREG_PCS_LPAB	0x421c	/* Link Partnet Ability */
 #define	WMREG_PCS_NPTX	0x4220	/* Next Page Transmit */
 #define	WMREG_SCVPC	0x4228	/* SerDes/SGMII Code Violation Packet Count */
 #define	WMREG_RXCSUM	0x5000	/* Receive Checksum register */
 #define	RXCSUM_PCSS	0x000000ff	/* Packet Checksum Start */
 #define	RXCSUM_IPOFL	__BIT(8)	/* IP checksum offload */
 #define	RXCSUM_TUOFL	__BIT(9)	/* TCP/UDP checksum offload */
 #define	RXCSUM_IPV6OFL	__BIT(10)	/* IPv6 checksum offload */
 #define	RXCSUM_CRCOFL	__BIT(11)	/* SCTP CRC32 checksum offload */
 #define	RXCSUM_IPPCSE	__BIT(12)	/* IP payload checksum enable */
 #define	RXCSUM_PCSD	__BIT(13)	/* packet checksum disabled */
 #define	WMREG_RLPML	0x5004	/* Rx Long Packet Max Length */
 #define	WMREG_RFCTL	0x5008	/* Receive Filter Control */
 #define	WMREG_RFCTL_NFSWDIS	__BIT(6)  /* NFS Write Disable */
 #define	WMREG_RFCTL_NFSRDIS	__BIT(7)  /* NFS Read Disable */
 #define	WMREG_RFCTL_ACKDIS	__BIT(12) /* ACK Accelerate Disable */
 #define	WMREG_RFCTL_ACKD_DIS	__BIT(13) /* ACK data Disable */
 #define	WMREG_RFCTL_EXSTEN	__BIT(15) /* Extended status Enable. 82574 only. */
 #define	WMREG_RFCTL_IPV6EXDIS	__BIT(16) /* IPv6 Extension Header Disable */
 #define	WMREG_RFCTL_NEWIPV6EXDIS __BIT(17) /* New IPv6 Extension Header */
 #define	WMREG_WUC	0x5800	/* Wakeup Control */
 #define	WUC_APME		0x00000001 /* APM Enable */
 #define	WUC_PME_EN		0x00000002 /* PME Enable */
 #define	WUC_PME_STATUS		0x00000004 /* PME Status */
 #define	WUC_APMPME		0x00000008 /* Assert PME on APM Wakeup */
 #define	WUC_PHY_WAKE		0x00000100 /* if PHY supports wakeup */
 #define	WMREG_WUFC	0x5808	/* Wakeup Filter Control */
 #define	WUFC_LNKC	__BIT(0)	/* Link Status Change Wakeup Enable */
 #define	WUFC_MAG	__BIT(1)	/* Magic Packet Wakeup Enable */
 #define	WUFC_EX		__BIT(2)	/* Directed Exact Wakeup Enable */
 #define	WUFC_MC		__BIT(3)	/* Directed Multicast Wakeup En */
 #define	WUFC_BC		__BIT(4)	/* Broadcast Wakeup Enable */
 #define	WUFC_ARPDIR	__BIT(5)	/* ARP Request Packet Wakeup En */
 #define	WUFC_IPV4	__BIT(6)	/* Directed IPv4 Packet Wakeup En */
 #define	WUFC_IPV6	__BIT(7)	/* Directed IPv6 Packet Wakeup En */
 #define	WUFC_NS		__BIT(9)	/* NS Wakeup En */
 #define	WUFC_NSDIR	__BIT(10)	/* NS Directed En */
 #define	WUFC_ARP	__BIT(11)	/* ARP request En */
 #define	WUFC_FLEX_HQ	__BIT(14)	/* Flex Filters Host Queueing En */
 #define	WUFC_NOTCO	__BIT(15)	/* ? */
 #define	WUFC_FLX	__BITS(23, 16)	/* Flexible Filter [0-7] En */
 #define	WUFC_FLXACT	__BITS(27, 24)	/* Flexible Filter [0-3] Action */
 #define	WUFC_FW_RST_WK	__BIT(31)	/* Wake on Firmware Reset Assert En */
 #define	WMREG_WUS	0x5810	/* Wakeup Status (R/W1C) */
 	/* Bit 30-24 and 15-12 are reserved */
 #define	WUS_MNG		__BIT(8)	/* Manageability event */
 #define	WUS_FLAGS	"\20"						\
 	"\1LINKC"	"\2MAG"		"\3EX"		"\4MC"		\
 	"\5BC"		"\6ARPDIR"	"\7IPV4"	"\10IPV6"	\
 	"\11MNG"	"\12NS"		"\13NSDIR"	"\14ARP"	\
 	"\21FLX0"	"\22FLX1"	"\23FLX2"	"\24FLX3"	\
 	"\25FLX4"	"\26FLX5"	"\27FLX6"	"\30FLX7"	\
 							"\40FW_RST_WK"
 #define	WMREG_MRQC	0x5818	/* Multiple Receive Queues Command */
 #define	MRQC_DISABLE_RSS	0x00000000
 #define	MRQC_ENABLE_RSS_MQ_82574	__BIT(0) /* enable RSS for 82574 */
 #define	MRQC_ENABLE_RSS_MQ	__BIT(1) /* enable hardware max RSS without VMDq */
 #define	MRQC_ENABLE_RSS_VMDQ	__BITS(1, 0) /* enable RSS with VMDq */
 #define	MRQC_DEFQ_MASK		__BITS(5, 3)
 				/*
 				 * Defines the default queue in non VMDq
 				 * mode according to value of the Multiple Receive
 				 * Queues Enable field.
 				 */
 #define	MRQC_DEFQ_NOT_RSS_FLT	__SHFTIN(__BIT(1), MRQC_DEFQ_MASK)
 				/*
 				 * the destination of all packets
 				 * not forwarded by RSS or filters
 				 */
 #define	MRQC_DEFQ_NOT_MAC_ETH	__SHFTIN(__BITS(1, 0), MRQC_DEFQ_MASK)
 				/*
 				 * Def_Q field is ignored. Queueing
 				 * decision of all packets not forwarded
 				 * by MAC address and Ether-type filters
 				 * is according to VT_CTL.DEF_PL field.
 				 */
 #define	MRQC_DEFQ_IGNORED1	__SHFTIN(__BIT(2), MRQC_DEFQ_MASK)
 				/* Def_Q field is ignored */
 #define	MRQC_DEFQ_IGNORED2	__SHFTIN(__BIT(2)|__BIT(0), MRQC_DEFQ_MASK)
 				/* Def_Q field is ignored */
 #define	MRQC_DEFQ_VMDQ		__SHFTIN(__BITS(2, 1), MRQC_DEFQ_MASK)
 				/* for VMDq mode */
 #define	MRQC_RSS_FIELD_IPV4_TCP		__BIT(16)
 #define	MRQC_RSS_FIELD_IPV4		__BIT(17)
 #define	MRQC_RSS_FIELD_IPV6_TCP_EX	__BIT(18)
 #define	MRQC_RSS_FIELD_IPV6_EX		__BIT(19)
 #define	MRQC_RSS_FIELD_IPV6		__BIT(20)
 #define	MRQC_RSS_FIELD_IPV6_TCP		__BIT(21)
 #define	MRQC_RSS_FIELD_IPV4_UDP		__BIT(22)
 #define	MRQC_RSS_FIELD_IPV6_UDP		__BIT(23)
 #define	MRQC_RSS_FIELD_IPV6_UDP_EX	__BIT(24)
 #define	WMREG_RETA_Q(x)		(0x5c00 + ((x) >> 2) * 4) /* Redirection Table */
 #define	RETA_NUM_ENTRIES	128
 #define	RETA_ENTRY_MASK_Q(x)	(0x000000ffUL << (((x) % 4) * 8)) /* Redirection Table */
 #define	RETA_ENT_QINDEX_MASK		__BITS(3,0) /*queue index for 82580 and newer */
 #define	RETA_ENT_QINDEX0_MASK_82575	__BITS(3,2) /*queue index for pool0 */
 #define	RETA_ENT_QINDEX1_MASK_82575	__BITS(7,6) /*queue index for pool1 and regular RSS */
 #define	RETA_ENT_QINDEX_MASK_82574	__BIT(7) /*queue index for 82574 */
 #define	WMREG_RSSRK(x)		(0x5c80 + (x) * 4) /* RSS Random Key Register */
 #define	RSSRK_NUM_REGS		10
 #define	WMREG_MANC	0x5820	/* Management Control */
 #define	MANC_SMBUS_EN		__BIT(0)
 #define	MANC_ASF_EN		__BIT(1)
 #define	MANC_ARP_EN		__BIT(13)
 #define	MANC_RECV_TCO_RESET	__BIT(16)
 #define	MANC_RECV_TCO_EN	__BIT(17)
 #define	MANC_BLK_PHY_RST_ON_IDE	__BIT(18)
 #define	MANC_RECV_ALL		__BIT(19)
 #define	MANC_EN_MAC_ADDR_FILTER	__BIT(20)
 #define	MANC_EN_MNG2HOST	__BIT(21)
 #define	MANC_EN_BMC2OS		__BIT(28)
 #define	WMREG_MANC2H	0x5860	/* Management Control To Host - RW */
 #define	MANC2H_PORT_623		(1 << 5)
 #define	MANC2H_PORT_624		(1 << 6)
 #define	WMREG_GCR	0x5b00	/* PCIe Control */
 #define	GCR_RXD_NO_SNOOP	0x00000001
 #define	GCR_RXDSCW_NO_SNOOP	0x00000002
 #define	GCR_RXDSCR_NO_SNOOP	0x00000004
 #define	GCR_TXD_NO_SNOOP	0x00000008
 #define	GCR_TXDSCW_NO_SNOOP	0x00000010
 #define	GCR_TXDSCR_NO_SNOOP	0x00000020
 #define	GCR_CMPL_TMOUT_MASK	0x0000f000
 #define	GCR_CMPL_TMOUT_10MS	0x00001000
 #define	GCR_CMPL_TMOUT_RESEND	0x00010000
 #define	GCR_CAP_VER2		0x00040000
 #define	GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000
 #define	GCR_NO_SNOOP_ALL (GCR_RXD_NO_SNOOP | \
 	    GCR_RXDSCW_NO_SNOOP |	     \
 	    GCR_RXDSCR_NO_SNOOP |	     \
 	    GCR_TXD_NO_SNOOP |		     \
 	    GCR_TXDSCW_NO_SNOOP |	     \
 	    GCR_TXDSCR_NO_SNOOP)
 #define	WMREG_FACTPS	0x5b30	/* Function Active and Power State to MNG */
 #define	FACTPS_MNGCG		0x20000000
 #define	FACTPS_LFS		0x40000000	/* LAN Function Select */
 #define	WMREG_GIOCTL	0x5b44	/* GIO Analog Control Register */
 #define	WMREG_CCMCTL	0x5b48	/* CCM Control Register */
 #define	WMREG_SCCTL	0x5b4c	/* PCIc PLL Configuration Register */
 #define	WMREG_SWSM	0x5b50	/* SW Semaphore */
 #define	SWSM_SMBI	0x00000001	/* Driver Semaphore bit */
 #define	SWSM_SWESMBI	0x00000002	/* FW Semaphore bit */
 #define	SWSM_WMNG	0x00000004	/* Wake MNG Clock */
 #define	SWSM_DRV_LOAD	0x00000008	/* Driver Loaded Bit */
 /* Intel driver defines H2ME register at 0x5b50 */
 #define	WMREG_H2ME	0x5b50	/* SW Semaphore */
 #define	H2ME_ULP		__BIT(11)
 #define	H2ME_ENFORCE_SETTINGS	__BIT(12)
 #define	WMREG_FWSM	0x5b54	/* FW Semaphore */
 #define	FWSM_MODE		__BITS(1, 3)
 #define	MNG_ICH_IAMT_MODE	0x2	/* PT mode? */
 #define	MNG_IAMT_MODE		0x3
 #define	FWSM_RSPCIPHY		__BIT(6)  /* Reset PHY on PCI reset */
 #define	FWSM_WLOCK_MAC		__BITS(7, 9)
 #define	FWSM_ULP_CFG_DONE	__BIT(10)
 #define	FWSM_FW_VALID		__BIT(15) /* FW established a valid mode */
 #define	WMREG_SWSM2	0x5b58	/* SW Semaphore 2 */
 #define	SWSM2_LOCK		0x00000002 /* Secondary driver semaphore bit */
 #define	WMREG_SW_FW_SYNC 0x5b5c	/* software-firmware semaphore */
 #define	SWFW_EEP_SM		0x0001 /* eeprom access */
 #define	SWFW_PHY0_SM		0x0002 /* first ctrl phy access */
 #define	SWFW_PHY1_SM		0x0004 /* second ctrl phy access */
 #define	SWFW_MAC_CSR_SM		0x0008
 #define	SWFW_PHY2_SM		0x0020 /* first ctrl phy access */
 #define	SWFW_PHY3_SM		0x0040 /* first ctrl phy access */
 #define	SWFW_SOFT_SHIFT		0	/* software semaphores */
 #define	SWFW_FIRM_SHIFT		16	/* firmware semaphores */
 #define	WMREG_GCR2	0x5b64	/* 3GPIO Control Register 2 */
 #define	WMREG_FEXTNVM9	0x5bb4	/* Future Extended NVM 9 */
 #define	FEXTNVM9_IOSFSB_CLKGATE_DIS __BIT(11)
 #define	FEXTNVM9_IOSFSB_CLKREQ_DIS __BIT(12)
 #define	WMREG_FEXTNVM11	0x5bbc	/* Future Extended NVM 11 */
 #define	FEXTNVM11_DIS_MULRFIX	__BIT(13)	/* Disable MULR fix */
 #define	WMREG_FFLT_DBG	0x05F04 /* Debug Register */
 #define	WMREG_CRC_OFFSET 0x5f50
 #define	WMREG_B2OSPC	0x8fe0	/* BMC2OS packets sent by BMC */
 #define	WMREG_O2BGPTC	0x8fe4	/* OS2BMC packets received by BMC */
 #define	WMREG_HRMPC	0xa018	/* Header Redirection Missed Packet Count */
 #define	WMREG_EEC	0x12010
 #define	EEC_FLASH_DETECTED __BIT(19)	/* FLASH */
 #define	EEC_FLUPD	__BIT(23)	/* Update FLASH */
 #define	WMREG_EEARBC_I210 0x12024
 /*
  * NVM related values.
  *  Microwire, SPI, and flash
  */
 #define	UWIRE_OPC_ERASE	0x04		/* MicroWire "erase" opcode */
 #define	UWIRE_OPC_WRITE	0x05		/* MicroWire "write" opcode */
 #define	UWIRE_OPC_READ	0x06		/* MicroWire "read" opcode */
 #define	SPI_OPC_WRITE	0x02		/* SPI "write" opcode */
 #define	SPI_OPC_READ	0x03		/* SPI "read" opcode */
 #define	SPI_OPC_A8	0x08		/* opcode bit 3 == address bit 8 */
 #define	SPI_OPC_WREN	0x06		/* SPI "set write enable" opcode */
 #define	SPI_OPC_WRDI	0x04		/* SPI "clear write enable" opcode */
 #define	SPI_OPC_RDSR	0x05		/* SPI "read status" opcode */
 #define	SPI_OPC_WRSR	0x01		/* SPI "write status" opcode */
 #define	SPI_MAX_RETRIES	5000		/* max wait of 5ms for RDY signal */
 #define	SPI_SR_RDY	0x01
 #define	SPI_SR_WEN	0x02
 #define	SPI_SR_BP0	0x04
 #define	SPI_SR_BP1	0x08
 #define	SPI_SR_WPEN	0x80
 #define	NVM_CHECKSUM		0xBABA
 #define	NVM_SIZE		0x0040
 #define	NVM_WORD_SIZE_BASE_SHIFT 6
 #define	NVM_OFF_MACADDR		0x0000	/* MAC address offset 0 */
 #define	NVM_OFF_MACADDR1	0x0001	/* MAC address offset 1 */
 #define	NVM_OFF_MACADDR2	0x0002	/* MAC address offset 2 */
 #define	NVM_OFF_COMPAT		0x0003
 #define	NVM_OFF_ID_LED_SETTINGS	0x0004
 #define	NVM_OFF_VERSION		0x0005
 #define	NVM_OFF_CFG1		0x000a	/* config word 1 */
 #define	NVM_OFF_CFG2		0x000f	/* config word 2 */
 #define	NVM_OFF_EEPROM_SIZE	0x0012	/* NVM SIZE */
 #define	NVM_OFF_CFG4		0x0013	/* config word 4 */
 #define	NVM_OFF_CFG3_PORTB	0x0014	/* config word 3 */
 #define	NVM_OFF_FUTURE_INIT_WORD1 0x0019
 #define	NVM_OFF_INIT_3GIO_3	0x001a	/* PCIe Initial Configuration Word 3 */
 #define	NVM_OFF_K1_CONFIG	0x001b	/* NVM K1 Config */
 #define	NVM_OFF_LED_1_CFG	0x001c
 #define	NVM_OFF_LED_0_2_CFG	0x001f
 #define	NVM_OFF_SWDPIN		0x0020	/* SWD Pins (Cordova) */
 #define	NVM_OFF_CFG3_PORTA	0x0024	/* config word 3 */
 #define	NVM_OFF_ALT_MAC_ADDR_PTR 0x0037	/* to the alternative MAC addresses */
 #define	NVM_OFF_COMB_VER_PTR	0x003d
 #define	NVM_OFF_IMAGE_UID0	0x0042
 #define	NVM_OFF_IMAGE_UID1	0x0043
 #define	NVM_COMPAT_VALID_CHECKSUM	0x0001
 #define	NVM_CFG1_LVDID		__BIT(0)
 #define	NVM_CFG1_LSSID		__BIT(1)
 #define	NVM_CFG1_PME_CLOCK	__BIT(2)
 #define	NVM_CFG1_PM		__BIT(3)
 #define	NVM_CFG1_ILOS		__BIT(4)	/* Invert loss of signal */
 #define	NVM_CFG1_SWDPIO_SHIFT	5
 #define	NVM_CFG1_SWDPIO_MASK	(0xf << NVM_CFG1_SWDPIO_SHIFT)
 #define	NVM_CFG1_IPS1		__BIT(8)
 #define	NVM_CFG1_LRST		__BIT(9)
 #define	NVM_CFG1_FD		__BIT(10)
 #define	NVM_CFG1_FRCSPD		__BIT(11)
 #define	NVM_CFG1_IPS0		__BIT(12)
 #define	NVM_CFG1_64_32_BAR	__BIT(13)
 #define	NVM_CFG2_CSR_RD_SPLIT	__BIT(1)
 #define	NVM_CFG2_82544_APM_EN	__BIT(2)
 #define	NVM_CFG2_64_BIT		__BIT(3)
 #define	NVM_CFG2_MAX_READ	__BIT(4)
 #define	NVM_CFG2_DMCR_MAP	__BIT(5)
 #define	NVM_CFG2_133_CAP	__BIT(6)
 #define	NVM_CFG2_MSI_DIS	__BIT(7)
 #define	NVM_CFG2_FLASH_DIS	__BIT(8)
 #define	NVM_CFG2_FLASH_SIZE(x)	(((x) & 3) >> 9)
 #define	NVM_CFG2_APM_EN		__BIT(10)
 #define	NVM_CFG2_ANE		__BIT(11)
 #define	NVM_CFG2_PAUSE(x)	(((x) & 3) >> 12)
 #define	NVM_CFG2_ASDE		__BIT(14)
 #define	NVM_CFG2_APM_PME	__BIT(15)
 #define	NVM_CFG2_SWDPIO_SHIFT	4
 #define	NVM_CFG2_SWDPIO_MASK	(0xf << NVM_CFG2_SWDPIO_SHIFT)
 #define	NVM_CFG2_MNGM_SHIFT	13	/* Manageability Operation mode */
 #define	NVM_CFG2_MNGM_MASK	(3U << NVM_CFG2_MNGM_SHIFT)
 #define	NVM_CFG2_MNGM_DIS	0
 #define	NVM_CFG2_MNGM_NCSI	1
 #define	NVM_CFG2_MNGM_PT	2
 #define	NVM_COMPAT_MAS_EN(x)		__BIT(x) /* Media Auto Sense Enable */
 #define	NVM_COMPAT_SERDES_FORCE_MODE	__BIT(14) /* Don't use autonego */
 #define	NVM_FUTURE_INIT_WORD1_VALID_CHECKSUM	0x0040
 #define	NVM_K1_CONFIG_ENABLE	0x01
 #define	NVM_SWDPIN_MASK		0xdf
 #define	NVM_SWDPIN_SWDPIN_SHIFT 0
 #define	NVM_SWDPIN_SWDPIO_SHIFT 8
 #define	NVM_3GIO_3_ASPM_MASK	(0x3 << 2)	/* Active State PM Support */
 #define	NVM_CFG3_PORTA_EXT_MDIO	__BIT(2)	/* External MDIO Interface */
 #define	NVM_CFG3_PORTA_COM_MDIO	__BIT(3)	/* MDIO Interface is shared */
 #define	NVM_CFG3_APME		__BIT(10)	/* APM Enable */
 #define	NVM_CFG3_ILOS		__BIT(13)	/* Invert loss of signal */
 #define	NVM_OFF_MACADDR_82571(x)	(3 * (x))
 /*
  * EEPROM Partitioning. See Table 6-1, "EEPROM Top Level Partitioning"
  * in 82580's datasheet.
  */
 #define	NVM_OFF_LAN_FUNC_82580(x)	((x) ? (0x40 + (0x40 * (x))) : 0)
 #define	NVM_COMBO_VER_OFF	0x0083
 #define	NVM_MAJOR_MASK		0xf000
 #define	NVM_MAJOR_SHIFT		12
 #define	NVM_MINOR_MASK		0x0ff0
 #define	NVM_MINOR_SHIFT		4
 #define	NVM_BUILD_MASK		0x000f
 #define	NVM_UID_VALID		0x8000
 /* iNVM Registers for i21[01] */
 #define	WM_INVM_DATA_REG(reg)	(0x12120 + 4*(reg))
 #define	INVM_SIZE			64 /* Number of INVM Data Registers */
 /* iNVM default value */
 #define	NVM_INIT_CTRL_2_DEFAULT_I211	0x7243
 #define	NVM_INIT_CTRL_4_DEFAULT_I211	0x00c1
 #define	NVM_LED_1_CFG_DEFAULT_I211	0x0184
 #define	NVM_LED_0_2_CFG_DEFAULT_I211	0x200c
 #define	NVM_RESERVED_WORD		0xffff
 #define	INVM_DWORD_TO_RECORD_TYPE(dword)	((dword) & 0x7)
 #define	INVM_DWORD_TO_WORD_ADDRESS(dword)	(((dword) & 0x0000FE00) >> 9)
 #define	INVM_DWORD_TO_WORD_DATA(dword)		(((dword) & 0xFFFF0000) >> 16)
 #define	INVM_UNINITIALIZED_STRUCTURE		0x0
 #define	INVM_WORD_AUTOLOAD_STRUCTURE		0x1
 #define	INVM_CSR_AUTOLOAD_STRUCTURE		0x2
 #define	INVM_PHY_REGISTER_AUTOLOAD_STRUCTURE	0x3
 #define	INVM_RSA_KEY_SHA256_STRUCTURE		0x4
 #define	INVM_INVALIDATED_STRUCTURE		0xf
 #define	INVM_RSA_KEY_SHA256_DATA_SIZE_IN_DWORDS	8
 #define	INVM_CSR_AUTOLOAD_DATA_SIZE_IN_DWORDS	1
 #define	INVM_DEFAULT_AL		0x202f
 #define	INVM_AUTOLOAD		0x0a
 #define	INVM_PLL_WO_VAL		0x0010
 /* Version and Image Type field */
 #define	INVM_VER_1	__BITS(12,3)
 #define	INVM_VER_2	__BITS(22,13)
 #define	INVM_IMGTYPE	__BITS(28,23)
 #define	INVM_MINOR	__BITS(3,0)
 #define	INVM_MAJOR	__BITS(9,4)
 /* Word definitions for ID LED Settings */
 #define	ID_LED_RESERVED_FFFF 0xffff
 /* ich8 flash control */
 #define	ICH_FLASH_COMMAND_TIMEOUT            5000    /* 5000 uSecs - adjusted */
 #define	ICH_FLASH_ERASE_TIMEOUT              3000000 /* Up to 3 seconds - worst case */
 #define	ICH_FLASH_CYCLE_REPEAT_COUNT         10      /* 10 cycles */
 #define	ICH_FLASH_SEG_SIZE_256               256
 #define	ICH_FLASH_SEG_SIZE_4K                4096
 #define	ICH_FLASH_SEG_SIZE_64K               65536
 #define	ICH_CYCLE_READ                       0x0
 #define	ICH_CYCLE_RESERVED                   0x1
 #define	ICH_CYCLE_WRITE                      0x2
 #define	ICH_CYCLE_ERASE                      0x3
 #define	ICH_FLASH_GFPREG   0x0000
 #define	ICH_FLASH_HSFSTS   0x0004 /* Flash Status Register */
 #define	HSFSTS_DONE		0x0001 /* Flash Cycle Done */
 #define	HSFSTS_ERR		0x0002 /* Flash Cycle Error */
 #define	HSFSTS_DAEL		0x0004 /* Direct Access error Log */
 #define	HSFSTS_ERSZ_MASK	0x0018 /* Block/Sector Erase Size */
 #define	HSFSTS_ERSZ_SHIFT	3
 #define	HSFSTS_FLINPRO		0x0020 /* flash SPI cycle in Progress */
 #define	HSFSTS_FLDVAL		0x4000 /* Flash Descriptor Valid */
 #define	HSFSTS_FLLK		0x8000 /* Flash Configuration Lock-Down */
 #define	ICH_FLASH_HSFCTL   0x0006 /* Flash control Register */
 #define	HSFCTL_GO		0x0001 /* Flash Cycle Go */
 #define	HSFCTL_CYCLE_MASK	0x0006 /* Flash Cycle */
 #define	HSFCTL_CYCLE_SHIFT	1
 #define	HSFCTL_BCOUNT_MASK	0x0300 /* Data Byte Count */
 #define	HSFCTL_BCOUNT_SHIFT	8
 #define	ICH_FLASH_FADDR    0x0008
 #define	ICH_FLASH_FDATA0   0x0010
 #define	ICH_FLASH_FRACC    0x0050
 #define	ICH_FLASH_FREG0    0x0054
 #define	ICH_FLASH_FREG1    0x0058
 #define	ICH_FLASH_FREG2    0x005c
 #define	ICH_FLASH_FREG3    0x0060
 #define	ICH_FLASH_FPR0     0x0074
 #define	ICH_FLASH_FPR1     0x0078
 #define	ICH_FLASH_SSFSTS   0x0090
 #define	ICH_FLASH_SSFCTL   0x0092
 #define	ICH_FLASH_PREOP    0x0094
 #define	ICH_FLASH_OPTYPE   0x0096
 #define	ICH_FLASH_OPMENU   0x0098
 #define	ICH_FLASH_REG_MAPSIZE      0x00a0
 #define	ICH_FLASH_SECTOR_SIZE      4096
 #define	ICH_GFPREG_BASE_MASK       0x1fff
 #define	ICH_FLASH_LINEAR_ADDR_MASK 0x00ffffff
 #define	ICH_NVM_SIG_WORD	0x13
 #define	ICH_NVM_SIG_MASK	0xc000
 #define	ICH_NVM_VALID_SIG_MASK	0xc0
 #define	ICH_NVM_SIG_VALUE	0x80
 #define	NVM_SIZE_MULTIPLIER 4096	/* multiplier for NVMS field */
 #define	WM_PCH_SPT_FLASHOFFSET	0xe000	/* offset of NVM access regs(PCH_SPT)*/
 /* for PCI express Capability registers */
 #define	WM_PCIE_DCSR2_16MS	0x00000005
 /* SFF SFP ROM data */
 #define	SFF_SFP_ID_OFF		0x00
 #define	SFF_SFP_ID_UNKNOWN	0x00	/* Unknown */
 #define	SFF_SFP_ID_SFF		0x02	/* Module soldered to motherboard */
 #define	SFF_SFP_ID_SFP		0x03	/* SFP transceiver */
 #define	SFF_SFP_ETH_FLAGS_OFF	0x06
 #define	SFF_SFP_ETH_FLAGS_1000SX	0x01
 #define	SFF_SFP_ETH_FLAGS_1000LX	0x02
 #define	SFF_SFP_ETH_FLAGS_1000CX	0x04
 #define	SFF_SFP_ETH_FLAGS_1000T		0x08
 #define	SFF_SFP_ETH_FLAGS_100LX		0x10
 #define	SFF_SFP_ETH_FLAGS_100FX		0x20
 /* I21[01] PHY related definitions */
 #define	GS40G_PAGE_SELECT	0x16
 #define	GS40G_PAGE_SHIFT	16
 #define	GS40G_OFFSET_MASK	0xffff
 #define	GS40G_PHY_PLL_FREQ_PAGE	0xfc0000
 #define	GS40G_PHY_PLL_FREQ_REG	0x000e
 #define	GS40G_PHY_PLL_UNCONF	0xff
 /* advanced TX descriptor for 82575 and newer */
 typedef union nq_txdesc {
 	struct {
 		uint64_t nqtxd_addr;
 		uint32_t nqtxd_cmdlen;
 		uint32_t nqtxd_fields;
 	} nqtx_data;
 	struct {
 		uint32_t nqtxc_vl_len;
 		uint32_t nqtxc_sn;
 		uint32_t nqtxc_cmd;
 		uint32_t nqtxc_mssidx;
 	} nqtx_ctx;
 } __packed nq_txdesc_t;
 /* Commands for nqtxd_cmdlen and nqtxc_cmd */
 #define	NQTX_CMD_EOP	__BIT(24)	/* end of packet */
 #define	NQTX_CMD_IFCS	__BIT(25)	/* insert FCS */
 #define	NQTX_CMD_RS	__BIT(27)	/* report status */
 #define	NQTX_CMD_DEXT	__BIT(29)	/* descriptor extension */
 #define	NQTX_CMD_VLE	__BIT(30)	/* VLAN enable */
 #define	NQTX_CMD_TSE	__BIT(31)	/* TCP segmentation enable */
 /* Descriptor types (if DEXT is set) */
 #define	NQTX_DTYP_C	(2U << 20)	/* context */
 #define	NQTX_DTYP_D	(3U << 20)	/* data */
 #define	NQTXD_FIELDS_IDX_SHIFT		4	/* context index shift */
 #define	NQTXD_FIELDS_IDX_MASK		0xf
 #define	NQTXD_FIELDS_PAYLEN_SHIFT	14	/* payload len shift */
 #define	NQTXD_FIELDS_PAYLEN_MASK	0x3ffff
 #define	NQTXD_FIELDS_IXSM		__BIT(8) /* do IP checksum */
 #define	NQTXD_FIELDS_TUXSM		__BIT(9) /* do TCP/UDP checksum */
 #define	NQTXC_VLLEN_IPLEN_SHIFT		0	/* IP header len */
 #define	NQTXC_VLLEN_IPLEN_MASK		0x1ff
 #define	NQTXC_VLLEN_MACLEN_SHIFT	9	/* MAC header len */
 #define	NQTXC_VLLEN_MACLEN_MASK		0x7f
 #define	NQTXC_VLLEN_VLAN_SHIFT		16	/* vlan number */
 #define	NQTXC_VLLEN_VLAN_MASK		0xffff
 #define	NQTXC_CMD_MKRLOC_SHIFT		0	/* IP checksum offset */
 #define	NQTXC_CMD_MKRLOC_MASK		0x1ff
 #define	NQTXC_CMD_SNAP			__BIT(9)
 #define	NQTXC_CMD_IPV_MASK		__BIT(10)
 #define	NQTXC_CMD_IP4			__SHIFTIN(1, NQTXC_CMD_IPV_MASK)
 #define	NQTXC_CMD_IP6			__SHIFTIN(0, NQTXC_CMD_IPV_MASK)
 #define	NQTXC_CMD_TP_MASK		__BIT(11)
 #define	NQTXC_CMD_TCP			__SHIFTIN(1, NQTXC_CMD_TP_MASK)
 #define	NQTXC_CMD_UDP			__SHIFTIN(0, NQTXC_CMD_TP_MASK)
 #define	NQTXC_MSSIDX_IDX_SHIFT		4	/* context index shift */
 #define	NQTXC_MSSIDX_IDX_MASK		0xf
 #define	NQTXC_MSSIDX_L4LEN_SHIFT	8	/* L4 header len shift */
 #define	NQTXC_MSSIDX_L4LEN_MASK		0xff
 #define	NQTXC_MSSIDX_MSS_SHIFT		16	/* MSS */
 #define	NQTXC_MSSIDX_MSS_MASK		0xffff