---
- branch: MAIN
  date: Wed Apr  1 17:26:07 UTC 2009
  files:
  - new: '1.5'
    old: '1.4'
    path: pkgsrc/cad/MyHDL-iverilog/Makefile
    pathrev: pkgsrc/cad/MyHDL-iverilog/Makefile@1.5
    type: modified
  id: 20090401T172607Z.54b92b672d70fe9cfb5df23bc737cfa35015f0ab
  log: |
    this needs verilog-current to build
  module: pkgsrc
  subject: 'CVS commit: pkgsrc/cad/MyHDL-iverilog'
  unixtime: '1238606767'
  user: drochner