--- - branch: MAIN date: Sun Oct 9 03:15:58 UTC 2016 files: - new: '1.9' old: '1.8' path: pkgsrc/cad/MyHDL-gplcver/Makefile pathrev: pkgsrc/cad/MyHDL-gplcver/Makefile@1.9 type: modified - new: '0' old: '1.5' path: pkgsrc/cad/MyHDL-gplcver/distinfo pathrev: pkgsrc/cad/MyHDL-gplcver/distinfo@0 type: deleted - new: '0' old: '1.3' path: pkgsrc/cad/MyHDL-gplcver/patches/patch-aa pathrev: pkgsrc/cad/MyHDL-gplcver/patches/patch-aa@0 type: deleted - new: '1.10' old: '1.9' path: pkgsrc/cad/MyHDL-iverilog/Makefile pathrev: pkgsrc/cad/MyHDL-iverilog/Makefile@1.10 type: modified - new: '1.2' old: 1.1.1.1 path: pkgsrc/cad/MyHDL-iverilog/PLIST pathrev: pkgsrc/cad/MyHDL-iverilog/PLIST@1.2 type: modified - new: '0' old: '1.5' path: pkgsrc/cad/MyHDL-iverilog/distinfo pathrev: pkgsrc/cad/MyHDL-iverilog/distinfo@0 type: deleted - new: '1.24' old: '1.23' path: pkgsrc/cad/py-MyHDL/Makefile pathrev: pkgsrc/cad/py-MyHDL/Makefile@1.24 type: modified - new: '1.1' old: '0' path: pkgsrc/cad/py-MyHDL/Makefile.common pathrev: pkgsrc/cad/py-MyHDL/Makefile.common@1.1 type: added - new: '1.10' old: '1.9' path: pkgsrc/cad/py-MyHDL/PLIST pathrev: pkgsrc/cad/py-MyHDL/PLIST@1.10 type: modified - new: '1.9' old: '1.8' path: pkgsrc/cad/py-MyHDL/distinfo pathrev: pkgsrc/cad/py-MyHDL/distinfo@1.9 type: modified id: 20161009T031558Z.ed061183af18570d9040bf91fa63bb479feef028 log: "Update MyHDL from 0.8.1 to 0.9.0\n\npkgsrc packages altered:\n - cad/MyHDL-gplcver\n - cad/MyHDL-iverilog\n - cad/py-MyHDL\n\npkgsrc changes:\n - Add common Makefile.common for MyHDL packages\n - 0.9.0 supports now Python 3.x\n - update LICENSE to gnu-lgpl-v2.1\n - replace local patch in MyHDL-gplcver and use MAKE_FLAGS to enforce INCS\n - set CC in MyHDL-gplcver\n - setup test target in cad/py-MyHDL\n - share common distinfo\n - replace AUTO_MKDIRS with INSTALLATION_DIRS\n - switch MASTER_SITES to GitHub\n\nupstream changelog\n==================\nWhatâ\x80\x99s new in MyHDL 0.9\nPython 3 support\n\nExperimental Python 3 support has been added to MyHDL 0.9. This was a major effort to modernize the code. As a result, Python 2 and 3 are supported from a single codebase.\n\nSee Python 3 Support for more info.\nInterfaces (Conversion of attribute accesses)\nRationale\n\nComplex designs often have many signals that are passed to different levels of hierarchy. Typically, many signals logically belong together. This can be modelled by an interface: an object that has a number of Signal objects as its attributes. Grouping signals into an interface simplifies the code, improves efficiency, and reduces errors.\n\nThe following is an example of an interface definition:\n\nclass Complex:\n def __init__(self, min=-2, max=2):\n self.real = Signal(intbv(0, min=min, max=max))\n self.imag = Signal(intbv(0, min=min, max=max))\n\nAlthough previous versions supported interfaces for modeling, they were not convertible. MyHDL 0.9 now supports conversion of designs that use interfaces.\n\nThe following is an example using the above Complex interface definition:\n\na,b = Complex(-8,8), Complex(-8,8)\nc = Complex(-128,128)\n\ndef complex_multiply(clock, reset, a, b, c):\n\n @always_seq(clock.posedge, reset=reset)\n \ def cmult():\n c.real.next = (a.real*b.real) - (a.imag*b.imag)\n c.imag.next = (a.real*b.imag) + (a.imag*b.real)\n\n return cmult\n\nSolution\n\nThe proposed solution is to create unique names for attributes which are used by MyHDL generators. The converter will create a unique name by using the name of the parent and the name of the attribute along with the name of the MyHDL module instance. The converter will essentially replace the â\x80\x9D.â\x80\x9D with an â\x80\x9C_â\x80\x9D for each interface element. In essence, interfaces are supported using hierarchical name expansion and name mangling.\n\nNote that the MyHDL convertor supports interfaces, even though the target HDLs do not. This is another great example where the convertor supports a high-level feature that is not available in the target HDLs.\nSee also\n\nFor additional information see the original proposal mep-107.\nOther noteworthy improvements\nConcatSignal interface\n\nThe interface of ConcatSignal was enhanced. In addition to signals, you can now also use constant values in the concatenation.\nstd_logic type ports\n\ntoVHDL() has a new attibute std_logic_ports. When set, only std_logic type ports are used in the interface of the top-level VHDL module.\nDevelopment flow\n\nThe MyHDL development flow has been modernized by moving to git and github for version control. In addition, travis has set up so that all pull requests are tested automatically, enabling continuous intergration.\nAcknowledgments\n\nThe Python 3 support effort was coordinated by Keerthan Jaic, who also implemented most of if. Convertible interfaces were championed by Chris Felton, and implemented by Keerthan Jaic.\n\nMyHDL development is a collaborative effort, as can be seen on github. Thanks to all who contributed with suggestions, issues and pull requests.\n" module: pkgsrc subject: 'CVS commit: pkgsrc/cad' unixtime: '1475982958' user: kamil