---
- branch: MAIN
  date: Thu Oct 13 04:10:16 UTC 2016
  files:
  - new: '1.92'
    old: '1.91'
    path: pkgsrc/cad/Makefile
    pathrev: pkgsrc/cad/Makefile@1.92
    type: modified
  id: 20161013T041016Z.6fbd084ab30d73afd5ab382ac019f9b9042f9140
  log: "verilog is no longer\n"
  module: pkgsrc
  subject: 'CVS commit: pkgsrc/cad'
  unixtime: '1476331816'
  user: jnemeth