---
- branch: MAIN
  date: Sun Dec 16 09:05:13 UTC 2018
  files:
  - new: '1.1'
    old: '0'
    path: pkgsrc/cad/verilator/DESCR
    pathrev: pkgsrc/cad/verilator/DESCR@1.1
    type: added
  - new: '1.1'
    old: '0'
    path: pkgsrc/cad/verilator/Makefile
    pathrev: pkgsrc/cad/verilator/Makefile@1.1
    type: added
  - new: '1.1'
    old: '0'
    path: pkgsrc/cad/verilator/PLIST
    pathrev: pkgsrc/cad/verilator/PLIST@1.1
    type: added
  - new: '1.1'
    old: '0'
    path: pkgsrc/cad/verilator/distinfo
    pathrev: pkgsrc/cad/verilator/distinfo@1.1
    type: added
  - new: '1.1'
    old: '0'
    path: pkgsrc/cad/verilator/patches/patch-Makefile.in
    pathrev: pkgsrc/cad/verilator/patches/patch-Makefile.in@1.1
    type: added
  id: 20181216T090513Z.fbd0d1012cba0c7e0f9f2cb0185c51b1eab440c4
  log: |
    cad/verilator: import verilator-4.006

    Verilator is the fastest free Verilog HDL simulator, and outperforms
    most commercial simulators. Verilator compiles synthesizable
    SystemVerilog (generally not test-bench code), plus some SystemVerilog
    and Synthesis assertions into single- or multithreaded C++ or
    SystemC code. Verilator is designed for large projects where fast
    simulation performance is of primary concern, and is especially
    well suited to generate executable models of CPUs for embedded
    software design teams.
  module: pkgsrc
  subject: 'CVS commit: pkgsrc/cad/verilator'
  unixtime: '1544951113'
  user: ryoon